High Speed Super Low Power SRAM CS16LV40973 256k Word x 16 Bit Revision History Rev. No. History Issue Date 1.0 Initial issue Jan.18, 2005 1.1 Add in 48 mini_BGA - 6x7mm Apr. 08, 2005 1.2 Revise 48 mini_BGA 6x7mm to 6x8mm Oct. 25, 2005 1.3 Revise AC/DC Char. Mar. 11, 2008 1.4 Add in 48 mini_BGA - 6x7mm Jun. 25, 2008 1 Remark Rev. 1.4 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV40973 256k Word x 16 Bit n GENERAL DESCRIPTION The CS16LV40973 is a high performance; high speed and super low power CMOS Static Random Access Memory organized as 262,144 words by 16bits and operates from a wide range of 2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed, super low power features and maximum access time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip enable inputs (/CE1, CE2) and active LOW output enable (/OE). The CS16LV40973 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The CS16LV40973 is available in JEDEC standard 44-pin TSOP 2 package and 48 ball Mini_BGA - 6x7mm. n FEATURES O Wide operation voltage : 2.7 ~ 3.6V O Ultra low power consumption : 3mA1MHz (Typ.) , Vcc=3.0V. 0.5 uA (Typ.) CMOS standby current O High speed access time : 55/70ns. O Automatic power down when chip is deselected. O Three state outputs and TTL compatible. O Data retention supply voltage as low as 1.5V. O Easy expansion with (/CE1, CE2) and /OE options. n Product Family Part No. Operating Temp Vcc. Range Speed (ns) 0~70oC CS16LV40973 55/ 70 Standby (Typ.) Package Type 0.5uA (Vcc = 3.0V) 2.7~3.6 44 TSOP 2 48 BGA_6x7mm -40~85oC 55/ 70 2 1.0uA Dice (Vcc= 3.0V) Rev. 1.4 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV40973 256k Word x 16 Bit n PIN CONFIGURATION n FUNCTIONAL BLOCK DIAGRAM 3 Rev. 1.4 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV40973 256k Word x 16 Bit n PIN DESCRIPTIONS Name A0 - A17 Type Input Function Address inputs for selecting one of the 262,144 x 16 bit words in the RAM /CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active /CE1, CE2 Input when data read from or write to the device. If either chip enable is not active, the device is deselected and in a standby power down mode. The DQ pins will be in high impedance state when the device is deselected. The Write enable input is active LOW. It controls read and write operations. With /WE Input the chip selected, when /WE is HIGH and /OE is LOW, output data will be present on the DQ pins, when /WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip /OE Input is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when /OE is inactive. /LB, /UB Input Lower byte and upper byte data input/output control pins. DQ0~DQ15 I/O Vcc Power Power Supply Gnd Power Ground These 16 bi-directional ports are used to read data from or write data into the RAM. n TRUTH TABLE MODE Standby Output Disabled Read Write /CE1 CE2 /WE /OE /LB /UB X L X X X X H X X X X X L H H H X X X X H H L L L H H H L L X DQ0~7 DQ8~15 Vcc Current High Z High Z ICCSB, ICCSB1 High Z High Z ICC L DOUT DOUT ICC H L High Z DOUT ICC L H DOUT High Z ICC L L DIN DIN ICC H L X DIN ICC L H DIN X ICC 4 Rev. 1.4 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV40973 256k Word x 16 Bit n ABSOLUTE MAXIMUM RATINGS Symbol VTERM (1) Parameter Rating Terminal Voltage with Respect to GND Unit -0.5 to Vcc+0.5 V TBIAS Temperature Under Bias -40 to +125 O T STG Storage Temperature -60 to +150 O PT Power Dissipation 1.0 W IOUT DC Output Current 30 mA C C 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. n OPERATING RANGE Range Ambient Temperature o Vcc Commercial 0~70 C 2.7V ~3.6V Industrial -40~85oC 2.7V ~ 3.6V 1. Overshoot : Vcc +2.0V in case of pulse width 20ns. 2. Undershoot : - 2.0V in case of pulse width 20ns. 3. Overshoot and undershoot are sampled, not 100% tested. n CAPACITANCE (1) (TA = 25oC, f =1.0 MHz) Symbol Parameter Conditions MAX. Unit CIN Input Capacitance VIN=0V 6 pF CDQ Input/Output Capacitance VI/O=0V 8 pF 1. This parameter is guaranteed, and not 100% tested. 5 Rev. 1.4 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV40973 256k Word x 16 Bit n DC ELECTRICAL CHARACTERISTICS Name Parameter Test Condition Guaranteed Input Low VIL Voltage (2) Guaranteed Input High VIH Voltage (2) IIL o Input Leakage Current o (TA = 0 ~70 C, Vcc = 3.0V ) MIN TYP(1) MAX Unit Vcc=3.0V -0.5 0.8 V Vcc=3.0V 2.0 Vcc+0.5 V VCC=MAX, VIN=0 to VCC -1 1 uA -1 1 uA 0.4 V VCC=MAX, /CE1=VIh, or IOL Output Leakage Current /OE=VIh ,or /WE= VIL VIO=0V to VCC VOL Output Low Voltage VCC=MAX, IOL =2.1mA VOH Output High Voltage VCC=MIN, IOH = -1.0mA Operating Power Supply /CE1=VIL, IDQ=0mA, Current F=FMAX =1/ tRC ICCSB TTL Standby Supply /CE1=VIH, IDQ=0mA, ICCSB1 CMOS Standby Current ICC 2.4 /CE1VCC-0.2V, VIN V 30 mA 1 mA 5 uA 0.5 VCC-0.2V or VIN0.2V, o 1. Typical characteristics are at TA = 25 C. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC. DATA RETENTION CHARACTERISTICS (TA = 0o ~70oC) n Name VDR ICCDR TCDR tR Parameter Test Condition VCC for Data Retention /CE1VCC-0.2V, VINVCC-0.2V MIN or VIN0.2V Unit V 0.3 VINVCC-0.2V or VIN0.2V Retention Time Operation Recovery Time MAX 1.5 Data Retention Current /CE1VCC-0.2V, VCC=1.5V Chip Deselect to Data (1) TYP 2 uA 0 ns tRC (2) ns Refer to Retention Waveform o 1.TA = 25 C 2. tRC(2)=Read Cycle Time 6 Rev. 1.4 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV40973 256k Word x 16 Bit n AC TEST CONDITIONS Input Pulse Levels Vcc/0V Input Rise and Fall Times Input and Output Timing Reference Level Output Load n KEY TO SWITCHING WAVEFORMS WAVEFORMS 5ns INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY 0.5Vcc See FIGURE 1A MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H DON'T CARE ANY CHANGE PERMITTED CHANGE STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE OFF STATE and 1B n LOW Vcc DATA RETENTION WAVEFORM(1) ( /CE1 Controlled ) n LOW Vcc DATA RETENTION WAVEFORM(2) ( CE2 Controlled ) 7 Rev. 1.4 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV40973 256k Word x 16 Bit n AC TEST LOADS AND WAVEFORMS TERMINAL EQUIVALENT 667 OUTPUT 1.73V ALL INPUT PULSES VCC GND FIGURE 1A n 90% FIGURE 2 FIGURE 1B 90% 10% 10% 5ns 5ns AC ELECTRICAL CHARACTERISTICS (TA = 0o ~70oCVcc=3.0V ) < READ CYCLE > JEDEC Parameter Name Name -55 -70 MIN MAX MIN MAX Description 55 Unit tAVAX tRC Read Cycle Time tAVQV tAA Address Access Time 55 70 ns tELQV tCO Chip Select Access Time (/CE1) 55 70 ns tBA tBA Data Byte Control Access Time (/LB, /UB) 25 35 ns tGLQV tOE Output Enable to Output Valid 25 35 ns tELQX tLZ tBE tBLZ tGLQX ChiChip Select to Output Low Z (/CE1) 70 ns 10 10 ns Data Byte Control to Output Low Z (/LB, /UB) 5 5 ns tOLZ Output Enable to Output in Low Z 5 5 ns tEHQZ tHZ Chip Deselect to Output in High Z (/CE1) 0 20 0 25 ns tBDO tBHZ Data Byte Control to Output High Z (/LB, /UB) 0 20 0 25 ns tGHQZ tOHZ Output Disable to Output in High Z 0 20 0 25 ns tAXOX tOH Out Disable to Address Change 10 8 10 ns Rev. 1.4 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV40973 256k Word x 16 Bit n SWITCHING WAVEFORMS (READ CYCLE) NOTES: 1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 9 Rev. 1.4 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV40973 256k Word x 16 Bit n AC ELECTRICAL CHARACTERISTICS (TA = 0o ~70oCVcc=3.0V ) < WRITE CYCLE > JEDEC Parameter Name Name -55 Description -70 MIN MAX MIN Unit MAX tAVAX tWC Write Cycle Time 55 70 ns tE1LWH tCW Chip Select to End of Write 45 60 ns tAVWL tAS Address Setup Time 0 0 ns tAVWH tAW Address Valid to End of Write 45 60 ns tWLWH tWP Write Pulse Width 40 50 ns tWHAX tWR1 Write Recovery Time (/CE, /WE) 0 0 ns tBW tBW Data Byte Control to End of Write(/LB, /UB) 45 60 ns tWLQZ tWHZ Write to Output in High Z tDVWH tDW Data to Write Time Overlap 25 30 ns tWHDX tDH Data Hold from Write Time 0 0 ns tWHOX tOW End of Write to Output Active 5 5 ns n 25 30 ns SWITCHING WAVEFORMS (WRITE CYCLE) 10 Rev. 1.4 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV40973 256k Word x 16 Bit 11 Rev. 1.4 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 256k Word x 16 Bit CS16LV40973 NOTES: 1. A write occurs during the overlap(tWP) of low /CE1, high CE2 and low /WE. A write begins when /CE1 goes low and /WE goes low with asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CE1 goes high, CE2 goes low and /WE goes high. The tWP is measured from the beginning of the write to the end of write. 2. tCW is measured from the /CE1 going low or CE2 going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. TWR applied in case a write ends as /CE1 or /WE going high or CE2 going low. n ORDER INFORMATION Note: Package material code "P" & "R" meets RoHS 12 Rev. 1.4 Chiplus reserves the right to change product or specification without notice.