High Speed Super Low Power SRAM
256k Word x 16 Bit CS16LV40973
1 Rev. 1.4
Chiplus reserves the right to change product or specification without notice.
Revision History
Rev. No. History Issue Date Remark
1.0
1.1
1.2
Initial issue
Add in 48 mini_BGA - 6x7mm
Revise 48 mini_BGA 6x7mm to 6x8mm
Jan.18, 2005
Apr. 08, 2005
Oct. 25, 2005
1.3 Revise AC/DC Char. Mar. 11, 2008
1.4 Add in 48 mini_BGA - 6x7mm Jun. 25, 2008
High Speed Super Low Power SRAM
256k Word x 16 Bit CS16LV40973
2 Rev. 1.4
Chiplus reserves the right to change product or specification without notice.
n GENERAL DESCRIPTION
The CS16LV40973 is a high performance; high speed and super low power CMOS Static
Random Access Memory organized as 262,144 words by 16bits and operates from a wide range of
2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high
speed, super low power features and maximum access time of 55/70ns in 3.0V operation. Easy
memory expansion is provided by an active LOW chip enable inputs (/CE1, CE2) and active LOW
output enable (/OE).
The CS16LV40973 has an automatic power down feature, reducing the power consumption
significantly when chip is deselected. The CS16LV40973 is available in JEDEC standard 44-pin
TSOP 2 package and 48 ball Mini_BGA – 6x7mm.
n FEATURES
Ø Wide operation voltage : 2.7 ~ 3.6V
Ø Ultra low power consumption : 3mA＠1MHz (Typ.) , Vcc=3.0V.
0.5 uA (Typ.) CMOS standby current
Ø High speed access time : 55/70ns.
Ø Automatic power down when chip is deselected.
Ø Three state outputs and TTL compatible.
Ø Data retention supply voltage as low as 1.5V.
Ø Easy expansion with (/CE1, CE2) and /OE options.
n Product Family
Part No. Operating Temp
Vcc. Range
Speed (ns)
Standby (Typ.)
Package Type
0~70oC 55/ 70 0.5uA
(Vcc = 3.0V)
CS16LV40973
-40~85oC
2.7~3.6
55/ 70 1.0uA
(Vcc= 3.0V)
44 TSOP 2
48 BGA_6x7mm
Dice
High Speed Super Low Power SRAM
256k Word x 16 Bit CS16LV40973
3 Rev. 1.4
Chiplus reserves the right to change product or specification without notice.
n PIN CONFIGURATION
n FUNCTIONAL BLOCK DIAGRAM
High Speed Super Low Power SRAM
256k Word x 16 Bit CS16LV40973
4 Rev. 1.4
Chiplus reserves the right to change product or specification without notice.
n PIN DESCRIPTIONS
Name Type Function
A0 – A17 Input Address inputs for selecting one of the 262,144 x 16 bit words in the RAM
/CE1, CE2
Input
/CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active
when data read from or write to the device. If either chip enable is not active, the
device is deselected and in a standby power down mode. The DQ pins will be in
high impedance state when the device is deselected.
/WE Input
The Write enable input is active LOW. It controls read and write operations. With
the chip selected, when /WE is HIGH and /OE is LOW, output data will be present
on the DQ pins, when /WE is LOW, the data present on the DQ pins will be written
into the selected memory location.
/OE Input
The output enable input is active LOW. If the output enable is active while the chip
is selected and the write enable is inactive, data will be present on the DQ pins and
they will be enabled. The DQ pins will be in the high impedance state when /OE is
inactive.
/LB, /UB Input Lower byte and upper byte data input/output control pins.
DQ0~DQ15
I/O These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc Power
Power Supply
Gnd Power
Ground
n TRUTH TABLE
MODE /CE1
CE2
/WE
/OE
/LB /UB
DQ0~7 DQ8~15 Vcc Current
X L X X X X
Standby H X X X X X High Z High Z I
CCSB, ICCSB1
H H X X
Output Disabled
L H X X H H High Z High Z I
CC
L L D
OUT D
OUT I
CC
H L High Z D
OUT I
CC
Read L H H L
L H D
OUT High Z I
CC
L L D
IN D
IN I
CC
H L X D
IN I
CC
Write L H L X
L H D
IN X I
CC
High Speed Super Low Power SRAM
256k Word x 16 Bit CS16LV40973
5 Rev. 1.4
Chiplus reserves the right to change product or specification without notice.
n ABSOLUTE MAXIMUM RATINGS (1)
Symbol Parameter Rating Unit
VTERM Terminal Voltage with Respect to GND -0.5 to Vcc+0.5 V
TBIAS Temperature Under Bias -40 to +125 OC
TSTG Storage Temperature -60 to +150 OC
PT Power Dissipation 1.0 W
IOUT
DC Output Current
30 mA
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
n OPERATING RANGE
Range Ambient Temperature Vcc
Commercial 0~70oC 2.7V ~3.6V
Industrial -40~85oC 2.7V ~ 3.6V
1. Overshoot : Vcc +2.0V in case of pulse width ≦20ns.
2. Undershoot : - 2.0V in case of pulse width ≦20ns.
3. Overshoot and undershoot are sampled, not 100% tested.
n CAPACITANCE (1) (TA = 25oC, f =1.0 MHz)
Symbol Parameter Conditions MAX. Unit
CIN Input Capacitance V
IN=0V 6 pF
CDQ Input/Output Capacitance V
I/O=0V 8 pF
1. This parameter is guaranteed, and not 100% tested.
High Speed Super Low Power SRAM
256k Word x 16 Bit CS16LV40973
6 Rev. 1.4
Chiplus reserves the right to change product or specification without notice.
n DC ELECTRICAL CHARACTERISTICS (TA = 0o ~70oC, Vcc = 3.0V )
Name Parameter Test Condition MIN
TYP(1) MAX Unit
VIL Guaranteed Input Low
Voltage (2) Vcc=3.0V -0.5 0.8 V
VIH Guaranteed Input High
Voltage (2) Vcc=3.0V 2.0 Vcc+0.5
V
IIL Input Leakage Current V
CC=MAX, VIN=0 to VCC -1 1 uA
IOL Output Leakage Current
VCC=MAX, /CE1=VIh, or
/OE=VIh ,or /WE= VIL
VIO=0V to VCC
-1 1 uA
VOL Output Low Voltage V
CC=MAX, IOL =2.1mA 0.4 V
VOH Output High Voltage V
CC=MIN, IOH = -1.0mA 2.4 V
ICC Operating Power Supply
Current
/CE1=VIL, IDQ=0mA,
F=FMAX =1/ tRC 30 mA
ICCSB TTL Standby Supply /CE1=VIH, IDQ=0mA, 1 mA
ICCSB1 CMOS Standby Current /CE1≧VCC-0.2V, VIN≧
VCC-0.2V or VIN≦0.2V, 0.5 5 uA
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester
notice are included.
3. Fmax = 1/tRC.
n DATA RETENTION CHARACTERISTICS (TA = 0o ~70oC)
Name
Parameter Test Condition MIN
TYP(1)
MAX
Unit
VDR V
CC for Data Retention
/CE1≧VCC-0.2V, VIN≧VCC-0.2V or VIN≦0.2V
1.5 V
ICCDR
Data Retention Current
/CE1≧VCC-0.2V, VCC=1.5V
V
IN≧VCC-0.2V or VIN≦0.2V 0.3 2 uA
TCDR
Chip Deselect to Data
Retention Time 0 ns
tR Operation Recovery
Time
Refer to Retention Waveform
t
RC (2)
ns
1.TA = 25oC
2. tRC(2)=Read Cycle Time
High Speed Super Low Power SRAM
256k Word x 16 Bit CS16LV40973
7 Rev. 1.4
Chiplus reserves the right to change product or specification without notice.
n LOW Vcc DATA RETENTION WAVEFORM(1) ( /CE1 Controlled )
n LOW Vcc DATA RETENTION WAVEFORM(2) ( CE2 Controlled )
n AC TEST CONDITIONS n KEY TO SWITCHING WAVEFORMS
Input Pulse Levels Vcc/0V
WAVEFORMS INPUTS OUTPUTS
Input Rise and Fall Times
5ns
MUST BE STEADY
MUST BE STEADY
Input and Output Timing
Reference Level 0.5Vcc
Output Load See FIGURE 1A
and 1B
MAY CHANGE
FROM H TO L WILL BE CHANGE FROM
H TO L
MAY CHANGE
FROM L TO H WILL BE CHANGE FROM L
TO H
DON’T CARE ANY
CHANGE
PERMITTED
CHANGE STATE
UNKNOWN
DOES NOT APPLY
CENTER LINE IS HIGH
IMPEDANCE OFF STATE
High Speed Super Low Power SRAM
256k Word x 16 Bit CS16LV40973
8 Rev. 1.4
Chiplus reserves the right to change product or specification without notice.
n AC TEST LOADS AND WAVEFORMS
FIGURE 1A
FIGURE 1B
667
Ω
TERMINAL EQUIVALENT
OUTPUT1.73V
GND
V
CC
5ns5ns
10% 90%90% 10%
ALL INPUT PULSES
FIGURE 2
n AC ELECTRICAL CHARACTERISTICS (TA = 0o ~70oC；Vcc=3.0V )
< READ CYCLE > -55 -70 JEDEC
Name
Parameter
Name Description MIN
MAX
MIN
MAX
Unit
tAVAX
tRC Read Cycle Time 55 70 ns
tAVQV
tAA Address Access Time 55 70 ns
tELQV
tCO Chip Select Access Time (/CE1) 55 70 ns
tBA t
BA Data Byte Control Access Time (/LB, /UB) 25 35 ns
tGLQV
tOE Output Enable to Output Valid 25 35 ns
tELQX
tLZ
Chi
Chip Select to Output Low Z (/CE1) 10 10 ns
tBE t
BLZ Data Byte Control to Output Low Z (/LB, /UB) 5 5 ns
tGLQX
tOLZ Output Enable to Output in Low Z 5 5 ns
tEHQZ
tHZ Chip Deselect to Output in High Z (/CE1) 0 20 0 25 ns
tBDO t
BHZ Data Byte Control to Output High Z (/LB, /UB) 0 20 0 25 ns
tGHQZ
tOHZ Output Disable to Output in High Z 0 20 0 25 ns
tAXOX
tOH Out Disable to Address Change 10 10 ns
High Speed Super Low Power SRAM
256k Word x 16 Bit CS16LV40973
9 Rev. 1.4
Chiplus reserves the right to change product or specification without notice.
n SWITCHING WAVEFORMS (READ CYCLE)
NOTES:
1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to
output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device
and from device to device interconnection.
High Speed Super Low Power SRAM
256k Word x 16 Bit CS16LV40973
10 Rev. 1.4
Chiplus reserves the right to change product or specification without notice.
n AC ELECTRICAL CHARACTERISTICS (TA = 0o ~70oC；Vcc=3.0V )
< WRITE CYCLE >
-55 -70 JEDEC
Name
Parameter
Name Description MIN
MAX
MIN
MAX
Unit
tAVAX t
WC Write Cycle Time 55 70 ns
tE1LWH t
CW Chip Select to End of Write 45 60 ns
tAVWL t
AS Address Setup Time 0 0 ns
tAVWH t
AW Address Valid to End of Write 45 60 ns
tWLWH t
WP Write Pulse Width 40 50 ns
tWHAX t
WR1 Write Recovery Time (/CE, /WE) 0 0 ns
tBW t
BW Data Byte Control to End of Write(/LB, /UB) 45 60 ns
tWLQZ t
WHZ Write to Output in High Z 25
30 ns
tDVWH t
DW Data to Write Time Overlap 25 30 ns
tWHDX t
DH Data Hold from Write Time 0 0 ns
tWHOX t
OW End of Write to Output Active 5 5 ns
n SWITCHING WAVEFORMS (WRITE CYCLE)
High Speed Super Low Power SRAM
256k Word x 16 Bit CS16LV40973
11 Rev. 1.4
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
256k Word x 16 Bit CS16LV40973
12 Rev. 1.4
Chiplus reserves the right to change product or specification without notice.
NOTES:
1. A write occurs during the overlap(tWP) of low /CE1, high CE2 and low /WE. A write begins when /CE1
goes low and /WE goes low with asserting /UB and /LB for double byte operation. A write ends at the
earliest transition when /CE1 goes high, CE2 goes low and /WE goes high. The tWP is measured from the
beginning of the write to the end of write.
2. t
CW is measured from the /CE1 going low or CE2 going low to end of write.
3. t
AS is measured from the address valid to the beginning of write.
4. t
WR is measured from the end or write to the address change. TWR applied in case a write ends as /CE1 or
/WE going high or CE2 going low.
n ORDER INFORMATION
Note: Package material code “P” & “R” meets RoHS
