Copyright Cirrus Logic, Inc. 2010
(All Rights Reserved)
http://www.cirrus.com MARCH '10
DS792F2
Low Power, Stereo DAC w/Headphone & Speaker Amps
FEATURES
98 dB Dynamic Range (A-wtd)
88 dB THD+N
Headphone Amplifier - GND Centered
– No DC-Blocking Capacitors Required
– Integrated Negative Voltage Regulator
– 2 x 23 mW into Stereo 16 Ω @ 1.8 V
– 2 x 44 mW into Stereo 16 Ω @ 2.5V
Stereo Analog Input Passthrough Architecture
– Analog Input Mixing
– Analog Passthrough with Volume Control
Digital Signal Processing Engine
– Bass & Treble Tone Control, De- E mphasis
– PCM Input w/Independent Vol Control
– Master Digital Volume Control and Limiter
– Soft-Ramp & Zero-Cross Transitions
Programmable Peak-Detect and Limiter
Beep Generator w/Full Tone Control
– Tone Selections Across Two Octaves
– Separate Volume Control
– Programmable On and Off Time Intervals
– Continuous, Periodic, One-Shot Beep
Selections
Class D Stereo/Mono Speaker Amplifier
No External Filter Required
High Stereo Output Power at 10% THD+N
– 2 x 1.00 W into 8 Ω @ 5.0 V
– 2 x 550 mW into 8 Ω @ 3.7 V
– 2 x 230 mW into 8 Ω @ 2.5 V
High Mono Output Power at 10% THD+N
– 1 x 1.90 W into 4 Ω @ 5.0 V
– 1 x 1.00 W into 4 Ω @ 3.7 V
– 1 x 350 mW into 4 Ω @ 2.5 V
Direct Battery Powered Operation
– Battery Level Monitoring & Compensation
81% Efficiency at 800 mW
Phase-Aligned PWM Output Reduces Idle
Channel Current
Spread Spectrum Modulation
Low Quiescent Current
+1.60 V to +5.25 V
Battery
+1.65 V to +2.63 V
Digital Supply
Pulse-Width
Modulator
Battery Level Monitoring & Compensation
Multi-bit
ΔΣ DAC
Level Shifter
+1.65 V to +3.47 V
Interface Supply
Control Port Serial Audio Port
Beep
Generator
Digital Volume,
Mono Mix,
Limiter, Bass,
Treble Adjust
Left
Inputs
Σ
4321
Summing
Amplifiers
Left HP/Line
Output
Ground-Centered
Amps
Right HP/Line
Output
+1.65 V to +2.63 V
Headphone Supply
Speaker/HP
Switch
Charge Pump
+VHP
-VHP
+1.65 V to +2.63 V
Analog Supply
Stereo/Mono
Full-Bridge
Speaker
Outputs
Class D Amps
+
-
+
-
I²C
Control
Reset
Serial
Audio
Input
Right
Inputs
Σ
4321
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System Features
12, 24, and 27 MHz Master Clock Support in
Addition to Typical Audio Clock Rates
High Performance 24-bit Converters
– Multi-bit Delta–Sigma Architecture
– Very Low 64Fs Oversampling Clock Reduces
Power Consumption
Low Power Oper ation
– Stereo Analog Passthrough: 10 mW @ 1.8 V
– Stereo Playback: 14 mW @ 1.8 V
Variable Power Supplies
– 1.8 V to 2.5 V Digital & Analog
– 1.6 V to 5 V Class D Amplifier
– 1.8 V to 2.5 V Headphone Amplifier
– 1.8 V to 3.3 V Interface Logic
Power Down Management
– DAC, Passthrough Amplifier, Headphone
Amplifier, Speaker Amplifier
Flexible Clocking Options
– Master or Slave Operation
– Quarter-Speed Mode - (i.e. allows 8 kHz Fs
while maintaining a flat noise floor up to 16 kHz)
– 4 kHz to 96 kHz Sample Rates
I²CTM Control Port Operation
Headphone/Speaker Detection Input
Pop and Click Suppression
Pin-Compatible w/CS42L52
Applications
PDA’s
Personal Media Players
Portable Game Consoles
General Description
The CS43L22 is a highly integrated, low power stereo DAC
with headphone and Class D speaker amplifiers. The
CS43L22 offers many features su itable for low power, porta-
ble system applications.
The DAC output path includes a digital signal processing en-
gine with various fixed function controls. Tone Control
provides bass and treble adjustment of four selectable corner
frequencies. Digital Volume controls may be configured to
change on soft ramp transitions while the analog controls can
be configured to occur on every zero crossing. T he DAC also
includes de-emphasis, limiting functions and a BEEP genera-
tor delivering tones selectable across a range of two full
octaves.
The stere o headphone ampl ifier is powered from a separate
positive supply and the integrated charge pump provides a
negative supply. This allows a ground-centered analog output
with a wide signa l swing and elimina tes the need for external
DC-blocking capacitors.
The Class D stereo speaker amplifier does not require an
external filter and provides the high efficiency amplification re-
quired by power sensitive portable appl ications. The speaker
amplifier may be powered directly from a battery while the in-
ternal DC supply monitoring and compensation provides a
constant gain level as the battery’s voltage decays.
The CS43L22 accommodates analog routing of the analog in-
put signal directl y to the headphone amplifier. This featu re is
useful in applications that ut ili ze an FM tuner where a udio re-
covered over-the-air must be transmitted to the headphone
amplifier directly.
In addition to its many features, the CS43L22 operates from a
low voltage analog and digital core making it ideal for portable
systems that require extremely low power consumption in a
minimal amount of space.
The CS43L22 i s available in a 40-pin QFN package in Com-
mercial (-40 to +85 °C) grade. The CS43L22 Customer
Demonstration board is also available for device evaluation
and implementation suggestions. Please refer to “Ordering In-
formation” on page 66 for complete ordering information.
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TABLE OF CONTENTS
1. PIN DESCRIPTIONS .............................................................................................................................. 7
1.1 I/O Pin Characteristics ..................................................................................................................... 8
2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 9
3. CHARACTERISTIC AND SPECIFICATIONS ...................................................................................... 10
RECOMMENDED OPERATING CONDITIONS .................................................................................. 10
ABSOLUTE MAXIMUM RATINGS ...................................................................................................... 10
ANALOG OUTPUT CHARACTERISTICS .......................................................................................... 11
ANALOG PASSTHROUGH CHARACTERISTICS .............................................................................. 12
PWM OUTPUT CHARACTERISTICS ................................................................................................. 13
HEADPHONE OUTPUT POWER CHARACTERISTICS ..................................................................... 14
LINE OUTPUT VOLTAGE LEVEL CHARACTERISTICS .................................................................... 15
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ............................. 15
SWITCHING SPECIFICATIONS - SERIAL PORT .............................................................................. 16
SWITCHING SPECIFICATIONS - I²C CONTROL PORT .................................................................... 17
DC ELECTRICAL CHARACTERISTICS ....... .... ... ... ... .... ... ................ ... ... .... ... ... ... .... ... ................ ... ... ... 18
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS .................................................... 18
POWER CONSUMPTION ................................................................................................................... 19
4. APPLICATIONS ................................................................................................................................... 20
4.1 Overview ........................ ... ... ... .... ................ ... ... ................ .... ... ................ ... ... ................................ 20
4.1.1 Basic Architecture ................................................................................................................. 20
4.1.2 Line Inputs ............................................................................................................................. 20
4.1.3 Line & Headphone Outputs ................................................................................................... 20
4.1.4 Speaker Driver Outputs ......................................................................................................... 20
4.1.5 Fixed Function DSP Engine .................................................................................................. 20
4.1.6 Beep Generator ..................................................................................................................... 20
4.1.7 Power Management .............................................................................................................. 20
4.2 DSP Engine .................................................................................................................................. 21
4.2.1 Beep Generator ..................................................................................................................... 22
4.2.2 Limiter .................................................................................................................................... 22
4.3 Analog Passthrough ............. ... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... ................ ................ 24
4.4 Analog Outputs .......... .... ... ... ................ ... .... ... ................ ... .... ... ................ ... ... .... ... ......................... 25
4.5 PWM Outputs .......................... .... ... ... ................ ... .... ... ................ ... ... .... ... ................ ... ................... 26
4.5.1 Mono Speaker Output Configuration ..................................................................................... 27
4.5.2 VP Battery Compensation ........... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ................ ...... 27
4.5.2.1 Maintaining a Desired Output Level ........................................................................... 27
4.6 Serial Port Clocking ............. ................ ... .... ... ................ ... .... ... ... ................ ... .... ... ......................... 29
4.7 Digital Interface Formats ................ ................ ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ... ................... 30
4.7.1 DSP Mode ............................................................................................................................. 31
4.8 Initialization .......... ................ ... .... ... ................ ... ... .... ................ ... ... ... ................. ... ......................... 31
4.9 Recommended Power-Up Sequence ............................................................................................ 31
4.10 Recommended Power-Down Sequence ...................................................................................... 31
4.11 Required Initialization Settings ..................................................................................................... 32
5. CONTROL PORT OPERATION ........................................................................................................... 33
5.1 I²C Control ............ ... ................ .... ... ................ ... ... ................. ... ... ................ ... .... ............................ 33
5.1.1 Memory Address Pointer (MAP) .. .......... .......... ......... .......... .......... ......... .......... .......... ...... ...... 34
5.1.1.1 Map Increment (I NCR) .. ...... ....... ...... ....... ...... ....... ...... ....... ...... ... ....... ...... ....... ...... ...... 34
6. REGISTER QUICK REFERENCE ........................................................................................................ 35
7. REGISTER DESCRIPTION .................................................................................................................. 37
7.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 37
7.1.1 Chip I.D. (Read Only) ............................................................................................................ 37
7.1.2 Chip Revision (Read Only) .................................................................................................... 37
7.2 Power Control 1 (Address 02h) ...................................................................................................... 37
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7.2.1 Power Down .......... ................ ... ... ... ................. ... ... ... ................ .... ... ... ................ ... ................ 37
7.3 Power Control 2 (Address 04h) ...................................................................................................... 38
7.3.1 Headphone Power Control ....... ... ... .... ................ ... ... .... ... ... ... ... ................. ... ... ... ... .... ... ... ... ... 38
7.3.2 Speaker Power Control .................. .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ... ...... 38
7.4 Clocking Control (Address 05h) ..................................................................................................... 38
7.4.1 Auto-Detect .... ... .... ... ... ... ................ .... ... ... ................ .... ... ... ... ................ .... ... ... ...................... 38
7.4.2 Speed Mode .......... ................ ... ... ... ................. ... ... ... ................ .... ... ... ................ ... ................ 39
7.4.3 32kHz Sample Rate Group ................................................................................................... 39
7.4.4 27 MHz Video Clock .............................................................................................................. 39
7.4.5 Internal MCLK/LRCK Ratio ................................................................................................... 39
7.4.6 MCLK Divide By 2 .............................. ... ... ... ................. ... ... ... ................ .... ... ... ...................... 40
7.5 Interface Control 1 (Address 06h) .................................................................................................. 40
7.5.1 Master/Slave Mode ........ .... ... ... ... ... .... ... ... ............................................................................. 40
7.5.2 SCLK Polarity ........... ................ ... ... .... ................ ... ... .... ................ ... ... ... .... ............................ 40
7.5.3 DSP Mode ............. ................ ... ... ... ................. ... ... ... ................ .... ... ... ... ................ ................ 40
7.5.4 DAC Interface Format ........ ... ... ... ... .... ... ... ... ................. ... ... ... ... .... ... ... ................ ... .... ... ......... 40
7.5.5 Audio Word Length ................................................................................................................ 41
7.6 Interface Control 2 (Address 07h) .................................................................................................. 41
7.6.1 SCLK equals MCLK .............................................................................................................. 41
7.6.2 Speaker/Headphone Switch Invert .............. .... ... ... ... .... ... ... ... ... .... ... ................ ... ... .... ... ... ... ... 41
7.7 Passthrough x Select: PassA (Address 08h), PassB (Address 09h) ............................................. 42
7.7.1 Passthrough Input Channel Mapping .................................................................................... 42
7.8 Analog ZC and SR Settings (Address 0Ah) ................................................................................... 42
7.8.1 Ch. x Analog Soft Ramp ........ ... ................ ... .... ... ... ... ................ .... ... ... ... .... ................ ... ......... 42
7.8.2 Ch. x Analog Zero Cross .......... ... ................ .... ... ... ... .... ................ ... ... ... .... ... ................ ......... 42
7.9 Passthrough Gang Control (Address 0Ch) .................................................................................... 42
7.9.1 Passthrough Channel B=A gang Control .... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 42
7.10 Playback Control 1 (Address 0Dh) ..... ... .... ... ... ... .... ................ ... ... ................ .... ... ................ ......... 43
7.10.1 Headphone Analog Gain ........... ... .... ... ... ................ .... ... ... ... ... .... ... ................ ... ... .... ... ... ... ... 43
7.10.2 Playback Volume Setting B=A ............................................................................................ 43
7.10.3 Invert PCM Signal Polarity .................................................................................................. 43
7.10.4 Master Playback Mute ......................................................................................................... 43
7.11 Miscellaneous Controls (Address 0Eh) ........................................................................................ 44
7.11.1 Passthrough Analog ............................................................................................................ 44
7.11.2 Passthrough Mute ............................................................................................................... 44
7.11.3 Freeze Registers ................................................................................................................. 44
7.11.4 HP/Speaker De-Emphasis ..................................................................................................44
7.11.5 Digital Soft Ramp ................................................................................................................ 44
7.11.6 Digital Zero Cros s ...... ....... ...... ...... ....... ...... .... ...... ....... ...... ...... ....... ...... ....... ... ...... ................ 45
7.12 Playback Control 2 (Address 0Fh) ..................... .... ... ... ... ................ .... ... ... ... ................ .... ... ......... 45
7.12.1 Headphone Mute ................................................................................................................. 45
7.12.2 Speaker Mute ...................................................................................................................... 45
7.12.3 Speaker Volume Setting B=A ..............................................................................................45
7.12.4 Speaker Channel Swap ....................................................................................................... 45
7.12.5 Speaker MONO Control ...................................................................................................... 46
7.12.6 Speaker Mute 50/50 Control ............................................................................................... 46
7.13 Passthrough x Volume: PASSAVOL (Address 14h) & PASSBVOL (Address 15h) .................... 46
7.13.1 Passthrough x Volume ........................................................................................................ 46
7.14 PCMx Volume: PCMA (Address 1Ah) & PCMB (Address 1Bh) ................................................... 47
7.14.1 PCM Channel x Mute .......................................................................................................... 47
7.14.2 PCM Channel x Volume ...................................................................................................... 47
7.15 Beep Frequency & On Time (Address 1Ch) ................................................................................ 47
7.15.1 Beep Frequency .................................................................................................................. 47
7.15.2 Beep On Time ..................................................................................................................... 48
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7.16 Beep Volume & Off Time (Address 1Dh) ..................... ... ................ .... ... ... ... ................ .... ... ... ...... 48
7.16.1 Beep Off Time ........... ................ ... .... ... ... ... .... ... ................ ... ... .... ... ... ... .... ................ ............ 48
7.16.2 Beep Volume ................ .... ... ... ... ................ .... ... ... ... .... ... ... ... ... .... ... ................ ... ... .... ............ 49
7.17 Beep & Tone Configuration (Address 1Eh) .................................................................................. 49
7.17.1 Beep Configuration ................. ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ................ ... ... .... ............ 49
7.17.2 Beep Mix Disable ................................................................................................................ 49
7.17.3 Treble Corner Frequency ....... ................ ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... ................ 50
7.17.4 Bass Corner Frequency ...... ... ... ... ................. ... ... ... .... ... ... ... ................ .... ... ... ... ... .... ... ... ...... 50
7.17.5 Tone Control Enable ........... ... ... ... .... ... ... ... ................. ... ... ... ... .... ... ... ... ................ .... ... ......... 50
7.18 Tone Control (Address 1Fh) ........................................................................................................ 50
7.18.1 Treble Gain ............. ... ... .... ... ... ... ... .... ................ ... ... .... ... ... ... ... ................. ... ... ... ... ................ 50
7.18.2 Bass Gain .................. ... .... ... ................ ... ... .... ................ ... ... ... ................. ... ... ... ... ................ 51
7.19 Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h) ....................................... 51
7.19.1 Master Volume Control ........................................................................................................ 51
7.20 Headphone Volume Control: HPA (Address 22h) & HPB (Address 23h) ........... ... ... ... .... ... ... ... ... 51
7.20.1 Headphone Volume Control ................................................................................................51
7.21 Speaker Volume Control: SPKA (Address 24h) & SPKB (Address 25h) ..................................... 52
7.21.1 Speaker Volume Control ..................................................................................................... 52
7.22 PCM Channel Swap (Address 26h) ............................................................................................. 52
7.22.1 PCM Channel Swap ............................................................................................................ 52
7.23 Limiter Control 1, Min/Max Thresholds (Address 27h) ........ ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 53
7.23.1 Limiter Maximum Threshold ............. ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 53
7.23.2 Limiter Cushion Threshold .................................................................................................. 53
7.23.3 Limiter Soft Ramp Disable ......... ... .... ... ... ... .... ................ ... ... ... .... ... ... ... .... ... ... ... ................... 53
7.23.4 Limiter Zero Cross Disable ........ ................ .... ... ... ... .... ... ... ... ... .... ... ................ ... ... .... ... ... ...... 54
7.24 Limiter Control 2, Release Rate (Address 28h) ........................................................................... 54
7.24.1 Peak Detect and Limiter ............... .... ... ... ... .... ................ ... ... ... .... ... ... ... .... ... ... ... ... ................ 54
7.24.2 Peak Signal Limit All Channels ........................................................................................... 54
7.24.3 Limiter Release Rate .............. ... ... .... ... ................ ... .... ... ... ... ... .... ... ... ... .... ................ ... ......... 54
7.25 Limiter Attack Rate (Address 29h) ............................................................................................... 55
7.25.1 Limiter Attack Rate ........... ... ... ... ... .... ................ ... ... .... ... ... ... ... .... ................ ... ... ... .... ............ 55
7.26 Status (Address 2Eh) (Read Only) .............. ... ... .... ... ... ... .... ... ... ... ... .... ... ... ................ ... .... ... ... ...... 55
7.26.1 Serial Port Clock Error (Read Only) ....................................................................................55
7.26.2 DSP Engine Overflow (Read Only) ..................................................................................... 55
7.26.3 PCMx Overflow (Read Only) ...............................................................................................56
7.27 Battery Compensation (Address 2Fh) .......................................................................................... 56
7.27.1 Battery Compensation .. .... ................ ... ... ... .... ... ... ... ................ .... ... ... ... .... ... ... ...................... 56
7.27.2 VP Monitor .............. ... ... .... ... ... ... ... .... ... ................ ... .... ... ... ... ... .... ................ ... ... ... ................ 56
7.27.3 VP Reference ............... .... ... ... ... ................ .... ... ... ... .... ... ... ................ ... .... ... ... ... ... .... ............ 57
7.28 VP Battery Level (Address 30h) (Read Only) .............................................................................. 57
7.28.1 VP Voltage Level (Read Only) ............................................................................................57
7.29 Speaker Status (Address 31h) (Read Only) ................................................................................ 57
7.29.1 Speaker Current Load Status (Read Only) ......................................................................... 57
7.29.2 SPKR/HP Pin Status (Read Only) ....................................................................................... 58
7.30 Charge Pump Frequency (Address 34h) ..................................................................................... 58
7.30.1 Charge Pump Frequency ....... ... ... .... ... ... ............................................................................. 58
8. ANALOG PERFORMANCE PLOTS ....................................................................................................59
8.1 Headphone THD+N versus Output Power Plots ............................................................................ 59
9. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 61
9.1 Auto Detect Enabled ... ... ... ... ................ .... ... ... ................ .... ... ... ... ................ .... ... ... ...................... 61
9.2 Auto Detect Disabled ......... ................ ... .... ... ................ ... .... ... ................ ... ... .... ............................ 61
10. PCB LAYOUT CONSID ERATIO NS ... ... ... ... .... ... ... ... ................. ... ... ... ... ................. ... ... ... ... .... ............ 62
10.1 Power Supply, Grounding ............................................................................................................ 62
10.2 QFN Thermal Pad ........................................................................................................................ 62
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11. DIGITAL FILTER PLOTS ................................................................................................................... 63
12. PARAMETER DEFINITIONS .............................................................................................................. 64
13. PACKAGE DIMENSIONS .................................................................................................................. 65
THERMAL CHARACTERISTICS ......................................................................................................... 65
14. ORDERING INFORMATION .............................................................................................................. 66
15. REFERENCES .................................................................................................................................... 66
16. REVISION HISTORY .......................................................................................................................... 66
LIST OF FIGURES
Figure 1. Typical Connection Diagram ... ... ... ............................................................................................... 9
Figure 2. Headphone Output Test Load .................................................................................................... 14
Figure 3. Serial Audio Interface Timing ..................................................................................................... 16
Figure 4. Control Port Timing - I²C ............................................................................................................ 17
Figure 5. DSP Engine Signal Flow ..... .... ................ ... ... ... .... ... ... ... .... ... ... ... ................ .... ... ... ... ... ................ 21
Figure 6. Beep Configuration Options ....................................................................................................... 22
Figure 7. Peak Detect & Limiter ................................................................................................................ 23
Figure 8. Analog Passthrough Signal Flow ............................................................................................... 24
Figure 9. Analog Outputs ... ... .... ... ... ... .... ... ... ... ... .... ... ................ ... .... ... ... ... ... .... ... ................ ...................... 25
Figure 10. PWM Output Stage .................................................................................................................. 26
Figure 11. Battery Compensation ...... .... ... ... ... .......................................................................................... 28
Figure 12. I²S Format ......... ... .... ... ... ... ................ .... ... ... ... .... ... ... ................ ... .... ... ... ... .... ... ......................... 30
Figure 13. Left-Justified Format ................................................................................................................ 30
Figure 14. Right-Justified Format\ ............................................................................................................. 30
Figure 15. DSP Mode Format) .................................................................................................................. 31
Figure 16. Control Port Timing, I²C Write ........ ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... ................ 33
Figure 17. Control Port Timing, I²C Read ..... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ................ ... ... ... ................ 33
Figure 18. THD+N vs. Output Power per Channe l at 1. 8 V (16 Ω load) ................................................... 59
Figure 19. THD+N vs. Output Power per Channe l at 2. 5 V (16 Ω load) ................................................... 59
Figure 20. THD+N vs. Output Power per Channe l at 1. 8 V (32 Ω load) ................................................... 60
Figure 21. THD+N vs. Output Power per Channe l at 2. 5 V (32 Ω load) ................................................... 60
Figure 22. Passband Ripple .. .... ... ... ... .... ... ... ... ... .... ................ ... ... .... ... ... ... ... ................. ... ... ... ................... 63
Figure 23. Stopband ........................ ... .... ... ... ... ... .... ................ ... ... .... ... ... ... ... .... ................ ......................... 63
Figure 24. DAC Transition Band ............................................................................................................... 63
Figure 25. Transition Band (Detail) ........................................................................................................... 63
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1. PIN DESCRIPTIONS
Pin Name # Pin Description
SDA 1 Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode.
SCL 2 Serial Control Port Clock (Input) - Serial clock for the serial control port.
AD0 3Address Bit 0 (I²C) (Input) - AD0 is a chip address pin in I²C Mode.
SPKR_OUTA+
SPKR_OUTA-
SPKR_OUTB+
SPKR_OUTB-
4
6
7
9
PWM Speaker Output (Output) - Full-bridge amplified PWM speaker outputs.
VP 5
8Power for PWM Drivers (Input) - Power supply for the PWM output driver stages.
-VHPFILT 10 Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge
pump that provides the negative rail for the headphone/line amplifiers.
FLYN 11 Charge Pump Cap Negative Node (Output) - Negative node for the inverting charge pump’s fly-
ing capacitor.
FLYP 12 Charge Pump Cap Positive Node (Output) - Positive node for the inverting charge pump’s flying
capacitor.
+VHP 13 Positive Analog Power for Headphone (Input) - Positive voltage rail and power for the internal
headphone amplifiers and inverting charge pump.
HP/LINE_OUTB, A 14,15 Headphone/Line Audio Output (Output) - Stereo headphone or lin e level analog outputs.
VA 16 Analog Power (Input) - Positive power for the internal analog section.
12
11
13
14
15
16
17
18
19
20
29
30
28
27
26
25
24
23
22
21
39
40
38
37
36
35
34
33
32
31
2
1
3
4
5
6
7
8
9
10
GND/Therma l Pad
TSTO
MCLK
SCLK
SDIN
SDA
LRCK
FLYN
+VHP
HP/LINE_OUTB
HP/LINE_OUTA
VQ
TSTO
AIN4A
AIN2A
AD0
SPKR_OUTA+
VP
VP
VD
SPKR_OUTB-
-VHPFILT AIN4B
AIN1B
AIN2B
AFILTB
AIN3B
AFILTA
AIN1A
AIN3A
SPKR_OUTB+
SCL
DGND
SPKR_OUTA-
FLYP
VA
AGND
FILT+
RESET
VL
SPKR/HP
Top-Down (Through-Package) View
40-Pin QFN Package
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1.1 I/O Pin Characteristics
Input and output levels and associated power supply voltage are shown in the table below. Logic levels
should not exceed the corresponding power supply voltage.
AGND 17 Analog Grou nd (Input) - Ground reference for the internal analog se ction.
FILT+ 18 Positive Voltage Reference (Output) - Filter connection for the internal sampling circuits.
VQ 19 Quiescent Voltage (Output) - Filter connection for the internal quiescent voltage.
TSTO 20,36 Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no
connection external to the pin).
AIN4A,B
AIN3A,B
AIN2A,B
AIN1A,B
21,22
23,24
25,26
29,30
Line-Leve l Analog Inpu ts (Input) - Single-ended stereo line-level analog inputs.
AFILTA,AFILTB 27,28 Anti-alias Filter Conne ct ion (Output) - Anti-alias filter connection fo r analog passthrough mode.
SPKR/HP 31 Speaker/Headphone Switch (Input) - Powers down the left and/or right channel of the speaker
and/or headphone outputs.
RESET 32 Reset (Input) - The device enters a low power mode when this pin is driven low .
VL 33 Digital Interface Power (Input) - Determines the required signal level for the serial audio inter-
face and host control port.
VD 34 Digital Power (Input) - Positive power for the internal digital section.
DGND 35 Digital Ground (Input) - Ground reference for the internal digital section.
MCLK 37 Master Clock (Input) - Clock source for the delta-sigma modulators.
SCLK 38 Serial Clock (Input/Output) - Serial clock for the serial audio interface.
SDIN 39 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
LRCK 40 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on
the serial audio data line.
GND/Thermal Pad - Ground reference for PWM power FETs and charge pump; thermal relief pad for optimized heat
dissipation.
Power
Supply Pin Name I/O Internal
Connections Driver Receiver
VL
RESET Input - - 1.65 V - 3. 47 V, with Hysteresis
AD0 Input - - 1.65 V - 3.47 V, with Hysteresis
SCL Input - - 1.65 V - 3.47 V, with Hysteresis
SDA Input/
Output - 1.65 V - 3.47 V, CMOS/Open
Drain 1.65 V - 3.47 V, with Hysteresis
MCLK Input - - 1.65 V - 3.47 V
LRCK Input/
Output Weak Pull-up
(~1 MΩ)1.65 V - 3.47 V, CMOS 1.65 V - 3.47 V
SCLK Input/
Output Weak Pull-up
(~1 MΩ)1.65 V - 3.47 V, CMOS 1.65 V - 3.47 V
SDIN Input - - 1.65 V - 3.47 V
VA SPKR/HP Input - - 1.65 V - 2.63 V
VP
SPKR_OUTA+ Output - 1.6 V - 5.25 V Power MOSFET -
SPKR_OUTA- Output - 1.6 V - 5.25 V Power MOSFET -
SPKR_OUTB+ Output - 1.6 V - 5.25 V Power MOSFET -
SPKR_OUTB- Output - 1.6 V - 5.25 V Power MOSFET -
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2. TYPICAL CONNECTION DIAGRAM
Note 3
Note 2
Note 1
1 µF
+1.8 V to +2.5 V 0.1 µF
1 µF
DGND
VL
0.1 µF
+1.8 V to +3.3 V
SCL
SDA
RESET
2 kΩ
LRCK
Digital Audio
Processor
MCLK
SCLK
VD
SDIN
CS43L22
2 kΩ
+1.8 V to +2.5 V
HP/LINE_OUTB
HP/LINE_OUTA
AIN1A Left 1
100 kΩ
100 Ω
AIN1B Right 1
0.1 µF
VA
Headphone Out
Left & Right
Line Level Out
Left & Right
FLYP
FLYN
-VHPFILT
51.1 Ω
0.022 µF
100 kΩ
100 Ω
SPKR_OUTA+
SPKR_OUTA-
SPKR/HP
51.1 Ω
0.022 µF
1 µF
1 µF
0.1 µF
+VHP
1 µF
VQ
AGND
* Capacitors must be C0G or equivalent
1 µF
**
**
See Note 4
SPKR_OUTB+
SPKR_OUTB-
1 µF VP
VP
+1.6 V to
+5 V Stereo Speakers
AIN2A Left 2
100 kΩ
100 Ω
AIN2B Right 2
100 kΩ
100 Ω
1 µF
1 µF
0.1 µF
0.1 µF
Analog
Input 1
Analog
Input 2
10 µF
47 kΩ
Notes:
1. Recommended values for the default charge pump switching
frequency. The required capacitance follows an inverse
relationship with the charge pump’s switching frequency. When
increasing the switching frequency, the capacitance may
decrease; when lowering the switching frequency, the
capacitance must increase.
2. Larger capacitance reduces the ripple on the internal
amplifier’s supply. This may reduce the distortion at higher
output power levels.
3. Additional bulk capacitance may be added to improve PSRR
at low frequencies.
4. Series resistance in the path of the power supplies must be
avoided. Any voltage drop on VHP will directly impact the
negative charge pump supply (-VHPFILT) and clip the audio
output.
AIN3A Left 3
100 kΩ
100 Ω
AIN3B Right 3
100 kΩ
100 Ω
1 µF
1 µF Analog
Input 3
AIN4A Left 4
100 kΩ
100 Ω
AIN4B Right 4
100 kΩ
100 Ω
1 µF
1 µF Analog
Input 4
FILT+
10 µF
150 pF
150 pF
AFILTA
AFILTB
** Low ESR, X7R/X5R dielectric capacitors.
**
**
**
**
**
**
**
**
**
TSTO
TSTO
AD0
Figure 1. Typical Connection Dia gram
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3. CHARACTERISTIC AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
AGND=DGND=0 V, all voltages with respe c t to ground.
ABSOLUTE MAXIMUM RATINGS
AGND = DGND = 0 V; all voltages with respect to ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
Notes: 1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
2. The maximum over/under voltage is limited by the inp ut curr ent.
Parameters Symbol Min Max Units
DC Power Supply
Analog VA 1.65 2.63 V
Headphone Amplifier +VHP 1.65 2.63 V
Sp eaker Amplifier VP 1.60 5.25 V
Digital VD 1.65 2.63 V
Serial/Control Port Interface VL 1.65 3.47 V
Ambient Temperature Commercial TA-40 +85 °C
Parameters Symbol Min Max Units
DC Power Supply Analog
Speaker
Digital
Serial/Control Port Interface
VA, VHP
VP
VD
VL
-0.3
-0.3
-0.3
-0.3
3.0
5.5
3.0
4.0
V
V
V
V
Input Current (Note 1) Iin -±10mA
Analog Input Voltage (Note 2) VIN AGND-0.7 VA+0.7 V
External Vo ltage Applied to Analo g Input (Note 2) VIN AGND-0.3 VA+0.3 V
External Voltage Applied to Analo g Output VIN -VHP - 0.3 +VHP + 0.3 V
External Vo ltage Applied to Digi tal Input (Note 2) VIND -0.3 VL+ 0.3 V
Ambient Operating Temperature (p ower applied) TA-50 +115 °C
Storage Temperature Tstg -65 +150 °C
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ANALOG OUTPUT CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; All Supplies = VA; TA = +25°C;
Sample Frequency = 48 kHz; Measurement bandwidth is 20 Hz to 20 kHz; Test load RL = 10 kΩ, CL = 10 pF for the line output
(see Figure 2); Test load RL = 16 Ω, CL = 10 pF (see Figure 2) for the headphone output; HP_GAIN[2:0] = 011.
3. One (least-significant bit) LSB of triang ular PDF dither is added to data.
4. Full-scale output voltage and power is determined by the gain setting, G, in register “Headphone Analog
Gain” on pa ge 43. High gain settings at certain VA and VHP supply levels may cause clipping when the
audio signal approaches full-scale, maximum power output, as shown in Figures 18 - 21 on page 60.
VA = 2.5 V VA = 1.8 V
Parameters (Note 3) Min Typ Max Min Typ Max Unit
RL = 10 k
Ω
Dynamic Range
18 to 24-Bit A-weighted
unweighted
16-Bit A-weighted
unweighted
92
89
-
-
98
95
96
93
-
-
-
-
89
86
-
-
95
92
93
90
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-86
-75
-35
-86
-73
-33
-80
-
-29
-
-
-
-
-
-
-
-
-
-88
-72
-32
-88
-70
-30
-82
-
-26
-
-
-
dB
dB
dB
dB
dB
dB
RL = 16
Ω
Dynamic Range
18 to 24-Bit A-weighted
unweighted
16-Bit A-weighted
unweighted
92
89
-
-
98
95
96
93
-
-
-
-
89
86
-
-
95
92
93
90
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-75
-75
-35
-75
-73
-33
-69
-
-29
-
-
-
-
-
-
-
-
-
-75
-72
-32
-75
-70
-30
-69
-
-26
-
-
-
dB
dB
dB
dB
dB
dB
Other Characteristics for RL = 16
Ω
or 10 k
Ω
Output Parameters Modulation Index (MI)
(Note 4) Analog Gain Multiplier (G) -
-0.6787
0.6047 -
--
-0.6787
0.6047 -
-V/V
V/V
Full-scale Output Voltage (2•G•MI•VA) (Note 4) Refer to Table “Headphone Output Power Characteris-
tics” on page 14 Vpp
Full-scale Output Power (Note 4) Refer to Table “Headphone Output Power Characteristics” on
page 14
Interchannel Isolation (1 kHz) 16 Ω
10 kΩ
-
-80
95 -
--
-80
93 -
-dB
dB
Sp eaker Amp to HP Amp Isolation - 80 - - 80 - dB
Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB
Gain Drift - ±100 - - ±100 - ppm/°C
AC-Load Resistance (RL)(Note 5) 16 - - 16 - - Ω
Load Capacitance (CL)(Note 5) - - 150 - - 150 pF
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5. See Figure 2. RL and CL reflect the recommended minimum resistance and maximum capacitance re-
quired for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively
move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recom-
mended 150 pF can cause the internal op-amp to become unstable.
ANALOG PASSTHROUGH CHARACTERISTICS
Test Conditions (unless otherwise specified): Input sine wave (relative to full-scale): 1 kHz through passive input filter;
Passthrough Amplifier and HP/Line Gain = 0 dB; Al l Supplies = VA; TA = +25°C; Sample Frequency = 48 kHz; Measurement
Bandwidth is 20 Hz to 20 kHz. VA = 2.5 V VA = 1.8 V
Parameters Min Typ Max Min Typ Max Unit
Analog In to HP/Line Amp
RL = 10 k
Ω
Dynamic Range A-weighted
unweighted -
--96
-93 -
--
--94
-91 -
-dB
dB
Total Harmonic Distortion + Noise -1 dBFS
-20 dBFS
-60 dBFS
-
-
-
-70
-73
-33
-
-
-
-
-
-
-70
-71
-31
-
-
-
dB
dB
dB
Full-scale Input Voltage - 0.91•VA - - 0.91•VA - Vpp
Full-scale Output Voltage - 0.84•VA - - 0.84•VA - Vpp
Passband Ripple - 0/-0.3 - - 0/-0.3 - dB
RL = 16
Ω
Dynamic Range A-weighted
unweighted -
--96
-93 -
--
--94
-91 -
-dB
dB
Total Harmonic Distortion + Noise -1 dBFS
-20 dBFS
-60 dBFS
-
-
-
-70
-73
-33
-
-
-
-
-
-
-70
-71
-31
-
-
-
dB
dB
dB
Full-scale Input Voltage - 0.91•VA - - 0.91•VA - Vpp
Full-scale Output Voltage - 0.84•VA - - 0.84•VA - Vpp
Output Power - 32 - - 17 - mW
Passband Ripple - 0/-0.3 - - 0/-0.3 - dB
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PWM OUTPUT CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full scale 997 Hz signal; MCLK = 12.2880 MHz; Measurement
Bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz; Test load RL = 8 Ω for stereo full-bridge, RL = 4 Ω for mono parallel
full-bridge; VD = VL = VA = VHP = 1.8V; PWM Modulation Index of 0.85; PWM Switch Rate = 384 kHz.
Parameters (Note 7) Symbol Conditions Min Typ Max Units
VP = 5.0 V
Power Output per Channel PO
Stereo Full-Bridge THD+N < 10%
THD+N < 1% -
-1.00
0.80 -
-Wrms
Wrms
Mono Parallel Full-Bridge THD+N < 10%
THD+N < 1% -
-1.90
1.50 -
-Wrms
Wrms
Total Harmonic Distortion + Noise THD+N
Stereo Full-Bridge PO = 0 dBFS = 0.8W - 0.52 - %
Mono Parallel Full-Bridge PO = -3 dBFS = 0.75 W
PO = 0 dBFS = 1.5 W -
-0.10
0.50 -
-%
%
Dynamic Range DR
Stereo Full-Bridge PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted -
-91
88 -
-dB
dB
Mono Parallel Full-Bridge PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted -
-91
88 -
-dB
dB
VP = 3.7 V
Power Output per Channel PO
Stereo Full-Bridge THD+N < 10%
THD+N < 1% -
-0.55
0.45 -
-Wrms
Wrms
Mono Parallel Full-Bridge THD+N < 10%
THD+N < 1% -
-1.00
0.84 -
-Wrms
Wrms
Total Harmonic Distortion + Noise THD+N
Stereo Full-Bridge PO = 0 dBFS = 0.43 W - 0.54 - %
Mono Parallel Full-Bridge PO = -3 dBFS = 0.41 W
PO = 0 dBFS = 0.81 W -
-0.09
0.45 -
-%
%
Dynamic Range DR
Stereo Full-Bridge PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted -
-91
88 -
-dB
dB
Mono Parallel Full-Bridge PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted -
-95
92 -
-dB
dB
VP =2.5 V
Power Output per Channel PO
Stereo Full-Bridge THD+N < 10%
THD+N < 1% -
-0.23
0.19 -
-Wrms
Wrms
Mono Parallel Full-Bridge THD+N < 10%
THD+N < 1% -
-0.44
0.35 -
-Wrms
Wrms
Total Harmonic Distortion + Noise THD+N
Stereo Full-Bridge PO = 0 dBFS = 0.18 W - 0.50 - %
Mono Parallel Full-Bridge PO = -3 dBFS = 0.17 W
PO = 0 dBFS = 0.35 W -
-0.08
0.43 -
-%
%
Dynamic Range DR
Stereo Full-Bridge PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted -
-91
88 -
-dB
dB
Mono Parallel Full-Bridge PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted -
-94
91 -
-dB
dB
MOSFET On Resistance RDS(ON) VP = 5.0V, Id = 0.5 A - 600 - mΩ
MOSFET On Resistance RDS(ON) VP = 3.7V, Id = 0.5 A - 640 - mΩ
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6. The PWM driver should be used in captive speaker systems only.
7. Optimal PWM performance is achieved when MCLK > 12 MHz.
HEADPHONE OUTPUT POWER CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; Sample Frequency = 48 kHz;
Measurement Bandwidth is 20 Hz to 20 kHz; Test load RL = 16 Ω, CL = 10 pF (see Figure 2); “Required Initialization Settings”
on page 32 written on power up.
8. VHP settings lower than VA reduces the headroom of the headphone amplifier. As a result, the DAC
may not achieve the full THD+N performance at full-scale output voltage and power.
MOSFET On Resistance RDS(ON) VP = 2.5V, Id = 0.5 A - 760 - mΩ
Efficiency ηVP = 5.0 V, PO = 2 x 0.8 W, RL =
8Ω
-81-%
Output Operating Peak Current IPC --1.5A
VP Input Current During Reset IVP RESET, pin 32, is held low -0.85.0µA
Parameters VA = 2.5V
Min Typ Max VA = 1.8V
Min Typ Max Unit
AOUTx Power Into RL = 16
Ω
HP_GAIN[2:0] Analog
Gain (G) VHP
000 0.3959 1.8 V - 14 - - 7 - mWrms
2.5 V - 14 - - 7 - mWrms
001 0.4571 1.8 V - 1 9 - - 10 - mWrms
2.5 V - 19 - - 10 - mWrms
010 0.5111 1.8 V - 23 - - 12 - mWrms
2.5 V - 23 - - 12 - mWrms
011 (default) 0.6047 1.8 V (Note 8) - 17 - mWrms
2.5 V - 32 - - 17 - mWrms
100 0.7099 1.8 V (Note 8) - 23 - mWrms
2.5 V - 44 - - 23 - mWrms
101 0.8399 1.8 V (Note 4) See Figure 18 on
page 59 mWrms
2.5 V - 32 - mWrms
110 1.0 000 1.8 V (Note 4, 8) See Figures 18 and 19 on page 59 mWrms
2.5 V mWrms
111 1.1430 1.8 V mWrms
2.5 V mWrms
Parameters (Note 7) Symbol Conditions Min Typ Max Units
AOUTx
AGND
RL
CL
0.022 μF
51 Ω
Figure 2. Headphone Output Tes t Loa d
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LINE OUTPUT VOLTAGE LEVEL CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 20 Hz
to 20 kHz; Sample Frequency = 48 kHz; Test load RL = 10 kΩ, CL = 10 pF (see Figure 2); “Require d Initialization Settings” on
page 32 written on power up.
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
9. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 22 and 25 on
page 63) have b een normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
10. Measurement Bandwidth is from Stopband to 3 Fs.
Parameters VA = 2.5V
Min Typ Max VA = 1.8V
Min Typ Max Unit
AOUTx Voltage Into RL = 10 k
Ω
HP_GAIN[2:0] Analog
Gain (G) VHP
000 0.3959 1.8 V - 1.34 - - 0.97 - Vpp
2.5 V - 1.34 - - 0.97 - Vpp
001 0.4571 1.8 V - 1.55 - - 1.12 - Vpp
2.5 V - 1.55 - - 1.12 - Vpp
010 0.5111 1.8 V - 1.73 - - 1.25 - Vpp
2.5 V - 1.73 - - 1.25 - Vpp
011 (default) 0.6047 1.8 V - 2.05 - 1.41 1.48 1.55 V pp
2.5 V 1.95 2.05 2.15 - 1.48 - Vpp
100 0.7099 1.8 V - 2.41 - - 1.73 - Vpp
2.5 V - 2.41 - - 1.73 - Vpp
101 0.8399 1.8 V - 2.85 - 2.05 Vpp
2.5 V - 2.85 - - 2.05 - Vpp
110 1.0000 1.8 V - 3.39 - - 2.44 - Vpp
2.5 V - 3.39 - - 2.44 - Vpp
111 1.1430 1.8 V (See (Note 8) 2.79 Vpp
2.5 V - 3.88 - - 2.79 - Vpp
Parameters (Note 9) Min Typ Max Unit
Frequency Response 10 Hz to 20 kHz -0.01 - +0.08 dB
Passband to -0.05 dB corner
to -3 dB corner 0
0-
-0.4780
0.4996 Fs
Fs
StopBand 0.5465 - - Fs
StopBand Attenuation (Note 10) 50 - - dB
Group Delay - 9/Fs - s
De-emphasis Error Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
+1.5/+0
+0.05/-0.25
-0.2/-0.4
dB
dB
dB
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SWITCHING SPECIFICATIONS - SERIAL PORT
Inputs: Logic 0 = DGND; Logic 1 = VL.
11. After powering up the CS43L22, RESET should be held low after the power supplies and clocks are
settled.
12. See “Example System Clock Frequencies” on page 61 for typical MC LK fr eq uen cie s.
Parameters Symbol Min Max Units
RESET pin Low Pulse Width (Note 11) 1-ms
MCLK Frequency (Note 12) (See “Serial Port Clock-
ing” on page 29)MHz
MCLK Duty Cycle 45 55 %
Slave Mode
Sample Rate (LRCK) Fs(See “Serial Port Clock-
ing” on page 29)kHz
LRCK Duty Cycle 45 55 %
SCLK Frequency 1/tP-64•F
sHz
SCLK Duty Cycle 45 55 %
LRCK Setup Time Before SCLK Rising Edge ts(LK-SK) 40 - ns
SDIN Setup Time Before SCLK Rising Edge ts(SD-SK) 20 - ns
SDIN Hold Time After SCLK Rising Edge th20 - ns
Master Mode
Sample Rate (LRCK) Fs(See “Serial Port Clock-
ing” on page 29)Hz
LRCK Duty Cycle 45 55 %
SCLK Frequency SCLK=MCLK mode 1/tP- 12.0000 MHz
MCLK=12.0000 MHz 1/tP-68•F
sHz
all other modes 1/tP-64•F
sHz
SCLK Duty Cycle 45 55 %
SDIN Setup Time Before SCLK Rising Edge ts(SD-SK) 20 - ns
SDIN Hold Time After SCLK Rising Edge th20 - ns
//
//
//
//
//
//
ts(SD-SK)
MSB MSB-1
LRCK
SCLK
SDIN
ts(LK-SK) tP
th
Figure 3. Serial Audio Interface Timing
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SWITCHING SPECIFICATIONS - I²C CONTROL PORT
Inputs: Logic 0 = DGND; Logic 1 = V; SDA CL=30pF.
13. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
Parameters Symbol Min Max Unit
SCL Clock Frequency fscl - 100 kHz
RESET Rising Edge to Start tirs 550 - ns
Bus Free Time Between Transmissions tbuf 4.7 - µs
Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs
Clock Low time tlow 4.7 - µs
Clock High Time thigh 4.0 - µs
Setup Time for Repeated Start Condition tsust 4.7 - µs
SDA Hold Time from SCL Falling (Note 13) thdd 0-µs
SDA Setup time to SCL Rising tsud 250 - ns
Rise T ime of SCL and SDA trc -1µs
Fall Time SCL and SDA tfc - 300 ns
Setup Time for Stop Co ndition tsusp 4.7 - µs
Acknowledge Delay from SCL Falling tack 300 1000 ns
tbuf thdst thdst
tlow tr
tf
thdd
thigh
tsud tsust
tsusp
Stop Start Start Stop
Repeated
SDA
SCL
tirs
RESET
Figure 4. Control Port Timing - I²C
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DC ELECTRICAL CHARACTERISTICS
AGND = 0 V; all voltages with respect to ground.
14. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also
increase the PSRR.
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS
15. See “I/O Pin Characteristics” on page 8 for serial and control port power rails.
Parameters Min Typ Max Units
VQ Characteristics
Nominal Voltage
Output Impedance
DC Current Source/Sink
-
-
-
0.5•VA
23
-
-
-
1
V
kΩ
μA
Power Supply Rejection Ratio Characteristics
PSRR @ 1 kHz (Not e 14) DAC (HP & Line Amps) - 60 - dB
PSRR @ 60 Hz (Note 14) DAC (HP & Line Amps) - 60 - dB
PSRR @ 217 Hz Full-Bridge PWM Outputs - 56 - dB
Parameters (Note 15) Symbol Min Max Units
Input Leakage Current Iin -±10μA
Input Capacitance -10pF
1.8 V - 3.3 V Logic
High-Level Output Voltage (IOH = -100 μA) VOH VL - 0.2 - V
Low-Level Output Voltage (IOL = 100 μA) VOL -0.2V
High-Level Input Voltage VL = 1.65 V
VL = 1.8 V
VL = 2.0 V
VL > 2.0 V
VIH 0.85•VL
0.77•VL
0.68•VL
0.65•VL
-
-
-
-
V
V
V
V
Low-Level Input Voltage VIL - 0.30•VL V
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POWER CONSUMPTION See (Note 16)
16. Unless otherwise noted, test conditions are as follows: All zeros input, Slave Mode, sample
rate = 48 k Hz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode
and master/slave operation.“Required Initialization Settings” on page 32 written on power up.
17. RESET pin 25 held LO, all clocks and data lines are held LO.
18. RESET pin 25 held HI, all clocks and data lines are held HI.
19. VL current will slightly increase in Master Mode.
Register Settings Typical Current (mA)
Operation 02h 04h
PDN[7:0]
PDN_HPB[1:0]
PDN_HPA[1:0]
PDN_SPKB[1:0]
PDN_SPKA[1:0]
V
iVHP iVA iVD iVL
VL=3.3V
(Note 19)
iVP
VP=3.7V Total
Power
(mWrms)
1Off (Note 17) x x x x x 1.8 0.00 0.00 0.00 0.00 0.00 0.00
2.5 0.00 0.00 0.00 0.00
2Standby (Note 18) 0x9F x x x x 1.8 0.00 0.00 0.01 0.00 0.00 0.02
2.5 0.00 0.00 0.02 0.05
3Stereo Passthrough to Headphone 0x9E 10 10 11 11 1.8 2.79 1.91 1.06 0.01 0.00 10.39
2.5 3.18 2.14 1.81 17.85
4Mono Playback to Headphone 0x9E 10 11 11 11 1.8 1.59 1.99 2.72 0.01 0.00 11.36
2.5 2.07 2.62 4.27 22.43
5Stereo Playback to Headphone 0x9E 10 10 11 11 1.8 2.77 2.00 2.91 0.01 0.00 13.84
2.5 3.27 2.63 4.28 25.48
6Mono Playback to Speaker 0x9E 11 11 10 10 1.8 0.00 0.20 4.42 0.01 1.00 12.05
2.5 0.00 0.22 6.77 21.21
7Stereo Playback to Speaker 0x9E 11 11 10 10 1.8 0.00 0.20 4.38 0.01 1.00 11.98
2.5 0.00 0.22 6.80 21.28
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4. APPLICATIONS
4.1 Overview
4.1.1 Basic Architecture
The CS43L22 is a highly integrated, low power, 24-bit audio DAC comprised of a Digital Signal Processing
Engine, headphone amp lifiers, a digital PWM modula tor and two full-b ridge powe r back- ends. Other fea-
tures include battery level monitoring and compensation and temperature monitoring. The DAC is de-
signed using multi-bit delta-sigma techniques and operates at an oversampling ratio of 128Fs, where Fs
is equal to the system sample rate.
The PWM modulator operates at a fixed frequency of 384 kHz. The power MOSFETs are configured for
either stereo full-bridge or mono parallel full bridge output. The DAC operates in one of four sample rate
speed modes: Quarter, Half, Single and Double. It ac cepts and is capable of generating serial port clocks
(SCLK, LRCK) derived from an input Master Clock (MCLK).
4.1.2 Line Inputs
4 pairs of stereo analog inputs are provided for applications that require analog passthrough directly to
the HP/Line amplifiers. This analog input portion allows selection fro m and config uration of multiple com-
binations of these stereo sources.
4.1.3 Line & Headphone Outputs
The analog outpu t portion o f the CS43L22 includes a h eadphone amplifier capable o f drivin g headpho ne
and line-level loads. An on-chip charge pump creates a negative headphone supply allowing a full-scale
output swing ce nt er ed ar ou n d gro un d. Th is elim in at es the need for large DC-Blocking capacitors and al-
lows the amplifier to deliver more power to headphone loads at lower supply voltages.
4.1.4 Speaker Driver Outputs
The Class D power amplifiers drive 8 Ω (stereo) and 4 Ω (mono) speakers directly, without the need for
an external filter. The power MOSFETS ar e powered directly from a battery eliminating the efficiency loss
associated with an external regulator. Battery level monitoring and compensation maintains a stead y out-
put as battery levels fall. A temperature monitor continually measures the die temperature and registers
when predefined thresh olds are exceeded . NOTE: The CS43L22 sh ould only be used in captive speaker
systems where the outputs are permanently tied to the speaker terminals.
4.1.5 Fixed Function DSP Engine
The fixed-function digital signal processing engine processes the PCM serial input data. Indep endent vol-
ume control, left/right channel swaps, mono mixes, tone control and limiting functions also comprise the
DSP engine.
4.1.6 Beep Generator
The beep generator delivers tones at select frequencies across approximately two octave major scales.
With independent volume contro l, beeps ma y be configured to occur co ntinuously , pe riodically, or at sin-
gle time intervals.
4.1.7 Power Management
Two control registers provide indepe ndent power-down control of the DAC, Headphone and Speaker out-
put blocks in the CS43L22 allowing operation in select applications with minimal power consumption.
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4.2 DSP Engine
Referenced Control Register Location
DSP
DEEMPH.............................
PCMxMUTE ........................
PCMxVOL[6:0] ....................
INV_PCMx...........................
PCMxSWAP[1:0].................
MSTxVOL[7:0].....................
MSTxMUTE.........................
DIGSFT...............................
DIGZC.................................
PLYBCKB=A........................
TC_EN.................................
BASS_CF[1:0].....................
TREB_CF[1:0].....................
BASS[3:0]............................
TREB[3:0]............................
LIMIT...................................
LIMSRDIS ...........................
LIMZCDIS............................
LMAX[2:0]............................
CUSH[2:0]...........................
LIMARATE[7:0]....................
LIMRRATE[7:0] ...................
“HP/Speaker De-Emphasis” on page 44
“PCM Channel x Mute” on page 47
“PCM Channel x Volume” on page 47
“Invert PCM Signal Polarity” on page 43
“PCM Channel Swap” on page 52
“Master Volume Control” on page 51
“Master Playback Mute” on page 43
“Digital Soft Ramp” on page 44
“Digital Zero Cross” on page 45
“Playback Volume Setting B=A” on page 43
“Tone Control Enable” on page 50
“Bass Corner Frequency” on page 50
“Treble Corner Frequency” on page 50
“Bass Gain” on page 51
“Treble Gain” on page 50
“Peak Detect and Limiter” on page 54
“Limiter Soft Ramp Disable” on page 53
“Limiter Zero Cross Disable” on page 54
“Limiter Maximum Threshold” on page 53
“Limiter Cushion Threshold” on page 5 3
“Limiter Attack Rate” on page 55
“Limiter Release Rate” on page 54
Beep
Generator
Bass/
Treble/
Control
ΣVOL
Peak
Detect
Limiter
Chnl Vol.
Settings
Demph VOL
VOL
+12dB/-102dB
0.5dB steps
MSTAVOL[7:0]
MSTBVOL[7:0]
+12dB/-51.5dB
0.5dB steps
PCMAMUTE
PCMBMUTE
PCMAVOL[6:0]
PCMBVOL[6:0]
0dB/-50dB
2.0dB steps
BPVOL[4:0]
DEEMPH TC_EN
BASS_CF[1:0]
TREB_CF[1:0]
BASS[3:0]
TREB[3:0]
+12.0dB/-10.5dB
1.5dB steps
Fixed Function DSP
MSTAMUTE
MSTBMUTE
DIGSFT
DIGZC
PLYBCKB=A
LIMARATE[7:0]
LIMRRATE[7:0]
LMAX[2:0]
CUSH[2:0]
LIMSRDIS
LIMZCDIS
LIMIT
PCMASWAP[1:0]
PCMBSWAP[1:0]
PCM Serial Interface
OFFTIME[2:0]
ONTIME[3:0]
FREQ[3:0]
BEEP[1:0]
BEEPMIXDIS
Channel
Swap
INV_PCMA
INV_PCMB
PWM
Modulator
DAC
Figure 5. DSP Engine Signal Flow
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4.2.1 Beep Generator
The Beep Generato r generates audio frequencie s across approximately two octave major scales. It offers
three modes of operation: Continuous, multiple and single (one-shot) beeps. Sixteen on and eight off
times are available.
Note: The Beep is generated before the limiter and may affect desired limiting performance. If the lim-
iter function is used, it may be re quired to set the b eep volume sufficiently b elow the thr eshold to prevent
the peak detect from triggering. Since the master volume control, MSTxVOL[7:0], will affect the beep vol-
ume, DAC volume may alternatively be controlled usin g the PCMxVOL[6:0] bits.
4.2.2 Limiter
When enabled, the limiter m onitors the d igital input signal b efore the DAC and PWM modulator s, detects
when levels exce ed the maximum thresho ld settings and lowers th e master volume at a prog rammable
attack rate below the maximu m threshold. When the input signal level falls below the maximum threshold,
the AOUT volume returns to its original level set in the Master Volume Control register at a programmable
release rate. Attack and rel ease rates a re affected b y th e DAC soft r amp /zero cross settin gs an d sample
rate, Fs. Limiter soft ramp and zero cross dependency may be independently enabled/disabled.
Notes:
1. Recommended settings: Best limiting performance may be realized with the fastest attack and
slowest release settin g with soft ramp e nabled in the control register s. The MIN bits allow the user to
set a thresh old slightly below the maximum threshold for hysteresis contro l - this cushions the sound
as the limiter attacks and releases.
2. The Limiter ma intains the output signal between the CUSH and MAX thresholds. As the dig ital input
signal level changes, the level-controlled output may not always be the same but will always fall within
Referenced Con t rol Register Location
MSTxVOL[7:0].....................
PCMxVOL[6:0]....................
OFFTIME[2:0] .....................
ONTIME[3:0].......................
FREQ[3:0]...........................
BEEP[1:0]............................
BEEPMIXDIS......................
BPVOL[4:0].........................
“Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h)” on page 51
“PCMx Volume: PCMA (Address 1Ah) & PCMB (Address 1Bh)” on page 47
“Beep Off Time” on page 48
“Beep On Time” on page 48
“Beep Frequency” on page 47
“Beep Configuration” on page 49
“Beep Mix Disable” on page 49
“Beep Volume” on page 49
FREQ[3:0]
...
BPVOL[4:0]
ONTIME[3:0] OFFTIME[2:0]
BEE P [1:0] =
'01'
BEE P [1:0] =
'10'
BEE P [1:0] =
'11'
SINGLE-BEEP: Beep turns on at a
configurable frequency (FREQ) and
volume (BPVOL) for the duration of
ONTIME. BEEP must be cleared
and set for additional beeps.
MULTI-BEEP: Beep turns on at a configurable frequency (FREQ)
and volume (BPVOL) for the duration of ONTIME and turns off for
the duration of OFFTIME. On and off cycles are repeated until
BEEP is cleared.
CONTINUOUS BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) and remains on
until BEEP is cleared.
Figure 6. Beep Configuration Options
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the thresholds.
Referenced Control Register Location
Limiter Controls........ ...........
Master Volume Control........ “Limiter Control 2, Release Rate (Address 28h)” on page 54, “Limiter Attack Rate (Addr ess 29h)” on page 55
“Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h)” on page 51
MAX[2:0]
Output
(after Limiter)
Input
RRATE[5:0]ARATE[5:0]
Volume
Limiter
CUSH[2:0]
ATTACK/RELEASE SOUND
CUSHION
MAX[2:0]
Figure 7. Peak Detect & Limiter
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4.3 Analog Passthrough
The CS43L22 accommodates an alog routing of the analog input signal directly to the headphone amplifiers
by using the PASSTHRUx mux. This feature is useful in applications that utilize an FM tuner where audio
recovered over-the-air must be transmitted to the headphone amplifier directly. This analog passthrough
path reduces power consumption and is immune to modulator switching noise that could interfere with some
tuners.
Four analog input channels can be chosen or summed by using the PASSxSEL bits as shown in Figure 8
to provide input to the CS43L22 when in analog passthrough mode. A pair of passthro ugh amplifiers can be
used to mute and apply gain to the input signals.
Referenced Control Register Location
Analog Front End
PASSB=A ............................
ANLGSFTx ..........................
ANLGZCx ............................
PASSxSEL4,3,2,1................
PASSxMUTE .......................
PASSxVOL[7:0] ...................
PASSTHRUx........................
“Passthrough Channel B=A Gang Control” on page 42
“Ch. x Analog Soft Ramp” on page 42
“Ch. x Analog Zero Cross” on page 42
“Passthrough Input Channel Mapping” on page 42
“Passthrough Mute” on page 44
“Passthrough x Volume” on page 46
“Passthrough Analog” on page 44
AIN4B
AIN1B
AIN2B
AIN3B
ANALOG PASS
THRU TO
HEADPHONE
AMPLIFIER MUX
Σ
AIN4A
AIN1A
AIN2A
AIN3A Σ
Analog Passthru
Amplifiers
ANLGSFTB
ANLGGZCB
PASSB=A
PASSBMUTE
PASSBVOL[7:0]
+12dB/-60dB
0.5 dB steps
ANLGSFTA
ANLGGZCA
PASSB=A
PASSAMUTE
PASSAVOL[7:0]
+12dB/-60dB
0.5 dB steps
PASSASEL[4:1]
PASSBSEL[4:1]
DAC A
Output
DAC B
Output
PASSTHRUA
PASSTHRUB
Figure 8. Analog Passthrough Signal Flow
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4.4 Analog Outputs
Referenced Control Register Location
Analog Output
HPxMUTE ...........................
HPxVOL[7:0] .......................
PDN_HPx[1:0].....................
HPGAIN[2:0]........................
PASSTHRUx .......................
PASSxMUTE.......................
PASSxVOL[7:0]...................
CHGFREQ ..........................
“Headphone Mute” on page 45
“Headphone Volume Control” on page 51
“Headphone Power Control” on page 38
“Headphone Analog Gain” on page 43
“Passthrough Analog” on page 44
“Passthrough Mute” on page 44
“Passthrough x Volume” on page 46
“Charge Pump Frequency” on page 58
DAC
CHGFREQ[3:0]
HPGAIN[2:0]
VOL
VOL
Analog Passthru Input
Signal
HPAMUTE
HPBMUTE
HPA_VOL[7:0]
HPB_VOL[7:0]
+0dB/-102dB
0.5dB steps
PASSAMUTE
PASSBMUTE
PASSAVOL[7:0]
PASSBVOL[70]
+12dB/-60dB
0.5dB steps
PASSTHRUA
PASSTHRUB
PDN_HPA[1:0]
PDN_HPB[1:0]
A
B
from D S P
Engine HP/Line
Outputs
Charge
Pump
Figure 9. Analog Outputs
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4.5 PWM Outputs
Note: The PWM speaker amplifiers should not be used in the 384x MCLK modes (18.4320 and
16.9344 MHz).
Referenced Control Register Location
PWM Control
SPKxMUTE.........................
MUTE50/50.........................
SPKMONO..........................
SPKxVOL[7:0].....................
SPKSWAP...........................
SPKB=A ..............................
BATTCMP ...........................
VPREF[3:0] .........................
VPLVL[7:0] ..........................
PDN_SPKx[1:0]...................
SPKxSHRT..........................
“Speaker Mute” on page 45
“Speaker Mute 50/50 Control” on page 46
“Speaker MONO Control” on page 46
“Speaker Volume Control” on page 52
“Speaker Channel Swap” on page 45
“Speaker Volume Setting B=A” on page 45
“Battery Compensation” on page 56
“VP Reference” on page 57
“VP Voltage Level (Read Only)” on page 57
“Speaker Power Control” on page 38
“Speaker Current Load Status (Read Only)” on page 57
VOL PWM
Modulator
A
SPKAMUTE
SPKBMUTE
MUTE50/50
SPKMONO
SPKSWAP
SPKB=A
SPKAVOL[7:0]
SPKBVOL[7:0]
+0dB/-102dB
0.5dB steps
PDN_SPKA[1:0]
PDN_SPKB[1:0]
Short
Circuit
SPKASHRT
Battery
Compensation
BATTCMP
VPREF[3:0]
VPLVL[7:0]
SPKBSHRT
+
-
+
-
Gate
Drive
from DSP
Engine
Speaker
Outputs
B
Figure 10. PWM Output Stage
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4.5.1 Mono Speaker Output Configuration
The CS43L22 accommodates a stereo as well as a mono speaker output configuration. In mono mode
the output d rivers of each cha nnel are conne cted in parallel to deliver maximum power to a 4 ohm speak-
er. Refer to the table below for pin mapping in mono configuration.
4.5.2 VP Battery Compensation
The CS43L22 provides the op tion to maintain a desired power output le vel, independent of the VP supply.
When enabled, this feature works by monitoring the voltage on the VP supply and reducing the attenu a-
tion on the speaker outputs when VP voltage levels fall.
Note: The interna l ADC that monitors the VP supply operates from the VA supply. Calculations are based
on typical VA levels of 1.8 V and 2.5 V using the VPREF bits.
4.5.2.1 Maintaining a Desired Output Level
Using SPKxVOL, the speaker output level must first be attenuated by the decibel equivalent of the expect-
ed VP supply range (MAX relative to MIN). The CS43L22 then gradually reduces the attenuation a s the
VP supply drops from its maximum level, maintaining a nearly constant power output.
Compensation Example 1 (VP Battery supply ranges from 4.5 V to 3.0 V)
1. Set speaker attenuation (SPKxVOL) to -3.5 dB. The VP supply changes ~3.5 dB.
2. Set the reference VP supply (VPREF) to 4.5 V.
3. Enable ba tt er y com p en sa tio n (BATT CM P ).
The CS43L22 automatically adjusts the output level as the battery discharges.
Compensation Example 2 (VP Battery supply ranges from 5.0 V to 1.6 V)
1. Set speaker attenuation (SPKxVOL) to -10 dB. The VP supply changes ~9.9 dB.
2. Set the reference VP supply (VPREF) to 5.0 V.
3. Enable ba tt er y com p en sa tio n (BATT CM P ).
The CS43L22 automatically adjusts the output level as the battery discharges. Refer to Figure 11 on
page 28. In this example, the VP supply changes over a wide range, illustrating the accuracy of the
CS43L22’s battery compensation.
Pin Speaker Output
SPKMONO=0 SPKMONO=1
SPKSWAP=0 SPKSWAP=1 SPKSWAP=0 SPKSWAP=1
4 SPKOUTA+ SPKOUTB+ SPKOUTA+ SPKOUTB+
6 SPKOUTA- SPKOUTB- SPKOUTA+ SPKOUTB+
7 SPKOUTB+ SPKOUTA+ SPKOUTA- SPKOUTB-
9 SPKOUTB- SPKOUTA- SPKOUTA- SPKOUTB-
Referenced Control Register Location
SPKMONO..........................
SPKSWAP........................... “Speaker MONO Control” on page 46
“Speaker Channel Swap” on page 45
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Referenced Cont ro l Regis te r Loc ation
VPREF................................
SPKxVOL............................ “VP Reference” on page 57
“Speaker Volume Contro l” on page 52
-24
-22
-20
-18
-16
-14
-12
-10
-8
-6
1.61.92.22.52.83.13.43.744.34.64.9
Uncompensated
PWM Output
Level
Battery Compensated
PWM O utput Level
VP Supply (V)
PWM Output Level (dB)
Figure 11. Battery Compensation
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4.6 Serial Port Clocking
The CS43L22 serial au dio in te rface p ort oper ates either as a slave or ma ster, deter mined by the M/S bit. It
accepts externally generated clocks in Slave Mode and will generate synchronous clocks derived from an
input master clock (MCLK) in Master Mode. Refer to the tables below for the requir ed setting in register 05h
and 06h associated with a given MCLK and sample rate.
Referenced Control Register Location
M/S...................................
Register 05h......................
Register 06h......................
“Master/Slave Mode” on page 40
“Clocking Control (Address 05h)” on page 38
“Interface Control 1 (Address 06h)” on page 40
MCLK
(MHz) Sample Rate,
Fs (kHz) SPEED[1:0]
(AUTO=’0’b) 32kGROUP VIDEOCLK RATIO[1:0] MCLKDIV2
12.2880
8.0000 11 1 0 00 0
12.0000 11 0 0 00 0
16.0000 10 1 0 00 0
24.0000 10 0 0 00 0
32.0000 01 1 0 00 0
48.0000 01 0 0 00 0
96.0000 00 0 0 00 0
11.2896
11.0250 11 0 0 00 0
22.0500 10 0 0 00 0
44.1000 01 0 0 00 0
88.2000 00 0 0 00 0
18.4320
(Slave
Mode
ONLY)
8.0000 11 1 0 00 0
12.0000 11 0 0 00 0
16.0000 10 1 0 00 0
24.0000 10 0 0 00 0
32.0000 01 1 0 00 0
48.0000 01 0 0 00 0
96.0000 00 0 0 00 0
16.9344
(Slave
Mode
ONLY)
*8.0182... 11 0 0 10 0
11.0250 11 0 0 00 0
22.0500 10 0 0 00 0
44.1000 01 0 0 00 0
88.2000 00 0 0 00 0
12.0000
8.0000 11 1 0 01 0
*11.0294... 11 0 0 11 0
12.0000 11 0 0 01 0
16.0000 10 1 0 01 0
*22.0588...10 0 0110
24.0000 10 0 0 01 0
32.0000 01 1 0 01 0
*44.1176...01 0 0110
48.0000 01 0 0 01 0
*88.2353...00 0 0110
96.0000 00 0 0 01 0
24.0000
8.0000 11 1 0 01 1
*11.0294... 11 0 0 11 1
12.0000 11 0 0 01 1
16.0000 10 1 0 01 1
*22.0588...10 0 0111
24.0000 10 0 0 01 1
32.0000 01 1 0 01 1
*44.1176...01 0 0111
48.0000 01 0 0 01 1
*88.2353...00 0 0111
96.0000 00 0 0 01 1
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Note: *The marked sample rate values are n ot exact representations of the actu al frame clock frequency
They have been truncated to 4 decimal places. The exact va lue c an be calcula ted by d ividing the
MCLK being used by the desired MCLK/LRCK ratio.
Table 1. Serial Port Clocking
4.7 Digital Interface Formats
The serial port operates in standard I²S, Left-Justified, Right-Justified, or DSP Mode digital interface formats
with varying bit depths from 16 to 24. Data is clocked into the DAC on the rising edge of SCLK.
27.0000
8.0000 11 1 1 01 0
12.0000 11 0 1 01 0
24.0000 10 0 1 01 0
32.0000 01 1 1 01 0
*44.1176... 01 0 1 11 0
48.0000 01 0 1 01 0
*11.0294... 11 0 1 11 0
*22.0588... 10 0 1 11 0
16.0000 10 1 1 01 0
MCLK
(MHz) Sample Rate,
Fs (kHz) SPEED[1:0]
(AUTO=’0’b) 32kGROUP VIDEOCLK RATIO[1:0] MCLKDIV2
LRCK
SCLK
MSB LSB MSB LSB
AOUTA
Left Channel Righ t Channel
SDIN AOUTB
MSB
Figure 12. I²S Format
LRCK
SCLK
MSB LSB MSB LSB
Lef t Channel R igh t Channel
SDIN MSB
AOUTA AOUTB
Figure 13. Left-Justified Format
LRCK
SCLK
MSB LSB MSB LSB
Left Channel Right Chan nel
SDIN
AOUTA AOUTB
Audio W ord Length (AWL)
Figure 14. Right-Justified Format\
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4.7.1 DSP Mode
In DSP Mode, the LR CK acts as a frame sync for 2 data -packed words (left an d right channel) input on
SDIN. The MSB is input on the first SCLK rising edge after the frame sync rising edge. The right channel
immediately follows the left channel.
4.8 Initialization
The CS43L22 enters a Power-Down state upon initial power-up. The interpolation and decimation filters,
delta-sigma and PWM modulators and control port registers are reset. The internal voltage reference, and
switched-capacitor low-pass filters are po we re d down .
The device will remain in the Power-Down state until the RESET pin is brought high. The contr ol port is ac-
cessible once RESET is high and the desi red reg ister se ttings can be loaded per the inter face descriptio ns
in the “Register Description” on page 37.
Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage referenc e, FILT+, will begin power-
ing up to no rma l ope ratio n. Th e cha rge pum p s lowly po wers up and ch arge s t he capa cit ors. Power is then
applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a mut-
ed state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the
MCLK/LRCK frequency ratio and normal operation begins.
4.9 Recommended Power-Up Sequence
1. Hold RESET low until the power supplies are stable.
2. Bring RESET high.
3. The default state of the “Power Ctl. 1” register (0x02) is 0x01. Load the desired register settings while
keeping the “Power Ctl 1” register set to 0x01.
4. Load the required initialization settings listed in Section 4.11.
5. Apply MCLK at the appropriate frequency, as discussed in Section 4.6. SCLK may be applied or set to
master at any time; LRCK may only be applied or set to master while the PDN bit is set to 1.
6. Set the “Power Ctl 1” register (0x02) to 0x9E.
7. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to
prevent power glitch related issues.
4.10 Recommended Power-Down Sequence
To minimize audible pops when turning off or placing the DAC in standby,
1. Mute the DAC’s and PWM outputs.
2. Disable soft ramp and zero cross volume transitions.
3. Set the “Power Ctl 1” register (0x02) to 0x9F.
LRCK
SCLK
MSB LSB
SDIN
HP/LINE OUTB
LSB Le ft Channe l R ight Channe l
MSB LSB MSB
Audio Word Lengt h (AWL)
1/fs
HP/LINE OUTA
Figure 15. DSP Mode Format)
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4. Wait at least 100 µs.
The device will be fully powered down after this 100 µs delay. Prior to the removal of the master clock
(MCLK), this delay of at least 100 µs must be implemented after step 3 to avoid premature disruption
of the DAC’s power down sequence.
A disruption in the device’s power down sequence (i.e. removing the MCLK signal before this 100 µs
delay) has consequences on both the headphone and PWM speaker amplifiers : The charge pump may
stop abruptly, causing the headphone amplifiers to drive the outputs up to the +VHP supply. Also, the
last state of each ‘+’ and ‘-’ PWM output terminal before the premature removal of MCLK could randomly
be held at either VP or AGND. When this event occurs, it is possible for each PWM terminal to output
opposing potentials, creating a DC source into the speaker voice coil.
The disruption of the device’s power down sequence may also cause clicks and pops on the output of
the DAC’s as the modulator holds the last outpu t level before the MCLK signal was removed.
5. MCLK may be removed at this time.
6. To achieve the lowest operating quiescent current, bring RESET low. All control port registers will be
reset to their default state.
4.11 Required Initialization Settings
Various sections in the device must be adjusted by implementing the initialization settings shown below after
power-up sequence step 3. All performance and power consumption measurements were taken with the
following settings:
1. Write 0x99 to register 0x00.
2. Write 0x80 to register 0x47.
3. Write ‘1’b to bit 7 in register 0x32.
4. Write ‘0’b to bit 7 in register 0x32.
5. Write 0x00 to register 0x00.
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5. CONTROL PORT OPERATION
The control port is used to access the registers allowing the CS43L22 to be configured for the desired op-
erational modes and formats. The operation of the control port may be completely asynchronous with re-
spect to the audio sample rates. However, to avoid potential interference problems, the control port pins
should remain static if no operation is re quired.
The control port operates using an I²C interface with the CS43L22 acting as a slave device.
5.1 I²C Control
SDA is a bidirectional data line. Data is clocked into and out of the device by the clock, SCL. The AD0 pin
sets the LSB of the chip a ddress; ‘0’ whe n conn ected to DGND, ‘1’ when connec ted to VL. This pin may be
driven by a host controller or directly connected to VL or DGND. The AD0 pin state is sensed and the LSB
of the chip address is set upon the release of the RESET signal (a low-to-high transition).
The signal timings for a rea d and wr ite cycle are sh own in Figure 16 and Figure 17. A Start condition is de-
fined as a falling transition of SDA while the clock is high. A Stop condition is defined as a rising transition
of SDA while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent
to the CS43L22 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read,
low for a write).
The upper 6 bits of the address field are fixed at 100101. To communicate with the CS43L22, the chip ad-
dress field, which is the first byte sent to the CS43L22, should match 100101 followed by the setting of the
AD0 pin. The eighth bit of th e address is the R/W bit. If the operation is a wr ite, the next byte is the Memory
Address Pointer (MAP), which selects the register to be read or written. If the operation is a read, the con-
tents of the register pointed to by the MAP will be output. Setting the auto-increment bit in MAP allows suc-
cessive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK
bit is output from the CS43L22 a fter each input byte is read and is input to the CS43 L22 from the microcon-
troller after each transmitted byte.
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 17, the write op eration is aborted after the ackno wledge for the MAP byte by sending a stop con-
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
4 5 6 7 24 25
SCL
CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1
START
ACK STOP
ACKACKACK
1 0 0 1 0 1 AD0 0
SDA INCR 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0
0 1 2 3 8 9 12 16 17 18 19 10 11 13 1 4 15 27 28
26
DATA +n
Figure 16. Control Port Timing, I²C Write
SCL
CHIP ADDRESS (WRITE) MAP BY TE DATA DATA +1
START ACK
STOP
ACK
ACK
ACK
1 0 0 1 0 1 AD0 0
SDA 1 0 0 1 0 1 AD0 1
CHIP ADDRESS (READ)
START
INCR 6 5 4 3 2 1 0 7 0 7 0 7 0
NO
16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28
2 3 10 11 17 18 19 25
ACK
DATA + n
STOP
Figure 17. Control Port Timing, I²C Read
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Send start condition.
Send 10010100 (chip add ress & write operation).
Receive acknowledge bit.
Send MAP byte, auto-increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10010101 (chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
5.1.1 Memory Address Pointer (MAP)
The MAP byte comes after the address byte and selects the register to be read or written. Refer to the
pseudo code above for implementation details.
5.1.1.1 Map Increment (INCR)
The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is
set to 0, MAP will stay constant for successiv e I²C writes or reads. If INCR is set to 1, MAP w ill auto-in-
crement after each byte is read or written, allowing block reads or writes of successive registers.
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6. REGISTER QUICK REFERENCE
Default values ar e shown below the bit names. Unless ot herwise spec ified, all “R eserved” bits mu st maintain the ir
default value.
Adr. Function 7 6 5 4 3 2 1 0
01h ID CHIPID4 CHIPID3 CHIPID2 CHIPID1 CHIPID0 REVID2 REVID1 REVID0
p37 11100xxx
02h Power Ctl 1 PDN7 PDN6 PDN5 PDN4 PDN3 PDN2 PDN1 PDN0
p37 000 00001
03h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
000 00111
04h Power Ctl 2 PDN_HPB1 PDN_HPB0 PDN_HPA1 PDN_HPA0 PDN_SPKB1 PDN_SPKB0 PDN_SPKA1 PDN_SPKA0
p38 000 00101
05h Clocking Ctl AUTO SPEED1 SPEED0 32kGROUP VIDEOCLK RATIO1 RATIO0 MCLKDIV2
p38 101 00000
06h Interface Ctl 1 M/S INV_SCLK Reserved DSP DACDIF1 DACDIF0 AWL1 AWL0
p40 000 00000
07h Interface Ctl 2 Reserved SCLK=MCLK Reserved Reserved INV_SWCH Reserved Rese rved Reserved
p41 000 00000
08h Passthrough A
Select Reserved Reserved Reserved Reserved PASSASEL4 PASSASEL3 PASSASEL2 PASSASEL1
p42 100 00001
09h Passthrough B
Select Reserved Reserved Reserved Reserved PASSBSEL4 PASSBSEL3 PASSBSEL2 PASSBSEL1
p42 100 00001
0Ah Analog ZC and
SR Settings Reserved Reserved Reserved Reserved ANLGSFTB ANLGZCB ANLGSFTA ANLGZCA
p42 101 00101
0Bh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
000 00000
0Ch Passthrough
Gang Control PASSB=A Reserved Reserved Reserved Reserved Reserved Reserved Reserved
p42 000 00000
0Dh Playback Ctl 1 HPGAIN2 HPGAIN1 HPGAIN0 PLYBCKB=A INV_PCMB INV_PCMA MSTBMUTE MSTAMUTE
p43 011 00000
0Eh Misc. Ctl PASSTHRUB PASSTHRUA PASSBMUTE PASSAMUTE FREEZE DEEMPH DIGSFT DIGZC
p44 000 00010
0Fh Playback Ctl 2 HPBMUTE HPAMUTE SPKBMUTE SPKAMUTE SPKB=A SPKSWAP SPKMONO MUTE50/50
p45 00000 00
10h- Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
13h 0 0 0 0 0 0 0 0
14h Passthrough A
Vol PASSAVOL7 PASSAVOL6 PASSAVOL5 PASSAVOL4 PASSAVOL3 PASSAVOL2 PASSAVOL1 PASSAVOL0
p46 000 00000
15h Passthrough B
Vol PASSBVOL7 PASSBVOL6 PASSBVOL5 PASSBVOL4 PASSBVOL3 PASSBVOL2 PASSBVOL1 PASSBVOL0
p46 000 00000
16h- Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
17h 0 0 0 0 0 0 0 0
18h- Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
19h 1 0 0 0 0 0 0 0
1Ah PCMA Vol PCMAMUTE PCMAVOL6 PCMAVOL5 PCMAVOL4 PCMAVOL3 PCMAVOL2 PCMAVOL1 PCMAVOL0
p47 000 00000
1Bh PCMB Vol PCMBMUTE PCMBVOL6 PCMBVOL5 PCMBVOL4 PCMBVOL3 PCMBVOL2 PCMBVOL1 PCMBVOL0
p47 000 00000
1Ch BEEP Freq,
On Time FREQ3 FREQ2 FREQ1 FREQ0 ONTIME3 ONTIME2 ONTIME1 ONTIME0
p47 000 00000
1Dh BEEP Vol,
Off Time OFFTIME2 OFFTIME1 OFFTIME0 BPVOL4 BPVOL3 BPVOL2 BPVOL1 BPVOL0
p48 000 00000
1Eh BEEP,
Tone Cfg. BEEP1 BEEP0 BEEPMIXDIS TREB_CF1 TREB_CF0 BASS_CF1 BASS_CF0 TC_EN
p49 000 00000
1Fh Tone Ctl TREB3 TREB2 TREB1 TREB0 BASS3 BASS2 BASS1 BASS0
p50 100 01000
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20h Master A Vol MSTAVOL7 MSTAVOL6 MSTAVOL5 MSTAVOL4 MSTAVOL3 MSTAVOL2 MSTAVOL1 MSTAVOL0
p51 00000000
21h Master B Vol MSTBVOL7 MSTBVOL6 MSTBVOL5 MSTBVOL4 MSTBVOL3 MSTBVOL2 MSTBVOL1 MSTBVOL0
p51 00000000
22h Headphone A
Volume HPAVOL7 HPAVOL6 HPAVOL5 HPAVOL4 HPAVOL3 HPAVOL2 HPAVOL1 HPAVOL0
p51 00000000
23h Headphone B
Volume HPBVOL7 HPBVOL6 HPBVOL5 HPBVOL4 HPBVOL3 HPBVOL2 HPBVOL1 HPBVOL0
p51 00000000
24h Speaker A
Volume SPKAVOL7 SPKAVOL6 SPKAVOL5 SPKAVOL4 SPKAVOL3 SPKAVOL2 SPKAVOL1 SPKAVOL0
p52 00000000
25h Speaker B
Volume SPKBVOL7 SPKBVOL6 SPKBVOL5 SPKBVOL4 SPKBVOL3 SPKBVOL2 SPKBVOL1 SPKBVOL0
p52 00000000
26h Channel Mixer
& Swap PCMASWP1 PCMASWP0 PCMBSWP1 PCMBSWP0 Reserved Reserved Reserved Reserved
p52 00000000
27h Limit Ctl 1,
Thresholds LMAX2 LMAX1 LMAX0 CUSH2 CUSH1 CUSH0 LIMSRDIS LIMZCDIS
p53 00000000
28h Limit Ctl 2,
Release Rate LIMIT LIMIT_ALL LIMRRATE5 LIMRRATE4 LIMRRATE3 LIMRRATE2 LIMRRATE1 LIMRRATE0
p54 01111111
29h Limiter Attack
Rate Reserved Reserved LIMARATE5 LIMARATE4 LIMARATE3 LIMARATE2 LIMARATE1 LIMARATE0
p55 00000000
2Ah Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
00000000
2Bh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
00111111
2Ch- Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
2Dh 0 0 0 0 0 0 0 0
2Eh Overflow &
Clock Status Reserved SPCLKERR DSPBOVFL DSPAOVFL PCMAOVFL PCMBOVFL Reserved Reserved
p55 00000000
2Fh Battery Com-
pensation BATTCMP VPMONITOR Reserved Reserved VPREF3 VPREF2 VPREF1 VPREF0
p56 00000000
30h VP Battery
Level VPLVL7 VPLVL6 VPLVL5 VPLVL4 VPLVL3 VPLVL2 VPLVL1 VPLVL0
p57 00000000
31h Speaker Status Reserved Reserved SPKASHRT SPKBSHRT SPKR/HP Reserved Reserved Reserved
p57 00000000
32h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
00111011
33h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
00000000
34h Charge Pump
Frequency CHGFREQ3 CHGFREQ2 CHGFREQ1 CHGFREQ0 Reserved Reserved Reserved Reserved
p58 01011111
Adr. Function 7 6 5 4 3 2 1 0
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7. REGISTER DESCRIPTION
All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are
read only. See the following bit definition tables for bit assignment information. The default state of each bit after a
power-up sequence or reset is shown as shaded in the table. Unless otherwise specified, all “Reserved” bits must
maintain their default value.
7.1 Chip I.D. and Revision Register (Address 01h) (Read Only)
7.1.1 Chip I.D. (Read Only)
I.D. code for the CS43L22.
7.1.2 Chip Revision (Read Only)
CS43L22 revision level.
7.2 Power Control 1 (Address 02h)
7.2.1 Power Down
Configures the power state of the CS43L22.
Note:
1. All states of PDN[7:0] not shown in the table are reserved.
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CHIPID4 CHIPID3 CHIPID2 CHIPID1 CHIPID0 REVID2 REVID1 REVID0
CHIPID[4:0] Device
11100 CS43L22
REVID[2:0] Revision Level
000 A0
001 A1
010 B0
011 B1
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PDN7 PDN6 PDN5 PDN4 PDN3 PDN2 PDN1 PDN0
PDN[7:0] Status
0000 0001 Powered Down - same as setting 1001 1111
1001 1110 Powered Up
1001 1111 Powered Down - same as setting 0000 0001
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7.3 Power Control 2 (Address 04h)
7.3.1 Headphone Power Control
Configures how the SPK/HP_SW pin, 6, controls the power for the headphone amplifier.
7.3.2 Speaker Power Control
Configures how the SPK/HP_SW pin, 6, controls the power for the speaker amplifier.
7.4 Clocking Control (Address 05h)
7.4.1 Auto-Detect
Configures the auto-detect circuitry for detecting the speed mode of the CS43L22 when operating as a
slave.
Notes:
1. The SPEED[1:0] bits are ignored and speed is determined by the MCLK/LRCK ratio.
2. When AUTO is disabled and the CS43L22 operates in Master Mode, the MCLKDIV2 bit is ignored.
3. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit
(“32kHz Sample Rate Group” on page 39) and/or the VIDEOCLK bit (“27 MHz Video Clock” on
page 39) and RATIO[1:0] bits (“Internal MCLK/LRCK Ratio” on page 39). Low sample rates may also
affect dynamic range performance in the typical audio band. Refer to the referenced application for
more information.
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PDN_HPB1 PDN_HPB0 PDN_HPA1 PDN_HPA0 PDN_SPKB1 PDN_SPKB0 PDN_SPKA1 PDN_SPKA0
PDN_HPx[1:0] Headphone Status
00 Headphone channel is ON when the SPK/HP_SW pin, 6, is LO.
Headphone channel is OFF when the SPK/HP_SW pin, 6, is HI.
01 Headphone channel is ON when the SPK/HP_SW pin, 6, is HI.
Headphone channel is OFF when the SPK/HP_SW pin, 6, is LO.
10 Headphone channel is always ON.
11 Headphone channel is always OFF.
PDN_SPKx[1:0] Speaker Status
00 Speaker channel is ON when the SPK/HP_SW pin, 6, is LO.
Speaker channel is OFF when the SPK/HP_SW pin, 6, is HI.
01 Speaker channel is ON when the SPK/HP_SW pin, 6, is HI.
Speaker channel is OFF when the SPK/HP_SW pin, 6, is LO.
10 Speaker channel is always ON.
11 Speaker channel is always OFF.
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AUTO SPEED1 SPEED0 32k_GROUP VIDEOCLK RATIO1 RATIO0 MCLKDIV2
AUTO Auto-detection of Speed Mode
0 Disabled
1Enabled
Application: “Serial Port Clocking” on page 29
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7.4.2 Speed Mode
Configures the speed mode of the DAC in Slave Mode and sets the appropriate MCLK divide ratio for
LRCK and SCLK in Master Mode.
Notes:
1. Slave/Master Mode is determined by the M/S bit in “Master/Slave Mode” on page 40.
2. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit
(“32kHz Sample Rate Group” on page 39) and/or the VIDEOCLK bit (“27 MHz Video Clock” on
page 39) and RATIO[1:0] bits ( “Internal MCLK/LRCK Ratio” on page 39). Low sample rates may also
affect dynamic range performance in the typical audio band. Refer to the referenced application for
more information.
3. These bits are ignored when the AUTO bit (“Auto-Detect” on page 38) is enabled.
7.4.3 32kHz Sample Rate Group
Specifies whether or not the input/output sample rate is 8 kHz, 16 kHz or 32 kHz.
7.4.4 27 MHz Video Clock
Specifies whether or not the external MCLK frequency is 27 MHz
7.4.5 Internal MCLK/LRCK Ratio
Configures the internal MCLK/LRCK ratio.
SPEED[1:0] Slave Mode Master Mode
Serial Port Speed MCLK/LRCK Ratio SCLK/LRCK Ratio
00 Double-Speed Mode (DSM - 50 kHz -100 kHz Fs) 512 64
01 Single-Speed Mode (SSM - 4 kHz -50 kHz Fs) 256 64
10 Half-Speed Mode (HSM - 12.5kHz -25 kHz Fs) 128 64
11 Quarter-Speed Mode (QSM - 4 kHz -12.5 kHz Fs) 128 64
Application: “Serial Port Clocking” on page 29
32kGROUP 8 kHz, 16 kHz or 32 kHz sample rate?
0No
1Yes
Application: “Serial Port Clocking” on page 29
VIDEOCLK 27 MHz MCLK?
0No
1Yes
Application: “Serial Port Clocking” on page 29
RATIO[1:0] Internal MCLK Cycles per LRCK SCLK/LRCK Ratio in Master Mode
00 128 64
01 125 62
10 132 66
11 136 68
Application: “Serial Port Clocking” on page 29
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7.4.6 MCLK Divide By 2
Divides the input MCLK by 2 prior to all internal circuitry.
Note: In Slave Mode, this bit is ignored when the AUTO bit (“Auto-Detect” on page 38) is disabled.
7.5 Interface Control 1 (Address 06h)
7.5.1 Master/Slave Mode
Configures the serial port I/O clocking.
7.5.2 SCLK Polarity
Configures the polarity of the SCLK signal.
7.5.3 DSP Mode
Configures a data-packed interface format for the DAC.
Notes:
1. Select the audio word length using the AWL[1:0] bits (“Audio Word Length” on pa ge 41).
2. The interface format for the DAC must be set to “Left-Justified” when DSP Mode is enabled.
7.5.4 DAC Interface Format
Configures the digital interface format for data on SDIN.
Note: Select the audio word length for Right Justified using th e AWL[1:0] bits (“Audio Word Length” on
page 41).
MCLKDIV2 MCLK signal into DAC
0No divide
1 Divided by 2
Application: “Serial Port Clocking” on page 29
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M/S INV_SCLK Reserved DSP DACDIF1 DACDIF0 AWL1 AWL0
M/S Serial Port Clocks
0Slave (input ONLY)
1 Master (output ONLY)
INV_SCLK SCLK Polarity
0Not Inverted
1 Inverted
DSP DSP Mode
0Disabled
1 Enabled
Application: “DSP Mode” on page 31
DACDIF[1:0] DAC Interf ace Format
00 Left Justified, up to 24-bit data
01 I²S, up to 24-bit data
10 Right Justified
11 Reserved
Application: “Digital Interface Formats” on page 30
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7.5.5 Audio Word Length
Configures the audio sample word length used for the data into SDIN.
Note: When the internal MCLK/LRCK ratio is set to 125 in Master Mode, the 32-bit data width option
for DSP Mode is not valid unless SCLK=MCLK.
7.6 Interface Control 2 (Address 07h)
7.6.1 SCLK equals MCLK
Configures the SCLK signal source for Master Mode.
Note: This bit is only valid for MCLK = 12.0000 MHz.
7.6.2 Speaker/Headphone Switch Invert
Determines the control signal polarity of the SPK/HP_SW pin.
AWL[1:0] Audio Word Length
DSP Mode Right Justified
00 32-bit data 24-bit data
01 24-bit data 20-bit data
10 20-bit data 18-bit data
11 16-bit data 16-bit data
Application: “DSP Mode” on page 31
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Reserved SCLK=MCLK Reserved Reserved INV_SWCH Reserved Reserved Reserved
SCLK=MCLK Output SCLK
0Re-timed signal, synchronously derived from MCLK
1 Non-retimed, MCLK signal
INV_SWCH SPK/HP_SW pin 6 Control
0Not inverted
1 Inverted
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7.7 Passthrough x Select: PassA (Address 08h), PassB (Address 09h)
7.7.1 Passthrough Input Channel Mapping
Selects one or sums/mixes the analog input signal into the passthrough Amplifier. Each bit of the
PASSx_SEL[4:1] word corresponds to individual channels (i.e. PASSx_SEL1 selects AIN1x,
PASSx_SEL2 selects AIN2x, etc.).
7.8 Analog ZC and SR Settings (Address 0Ah)
7.8.1 Ch. x Analog Soft Ramp
Configures an incremental volume ramp from the current level to the new level at the specified rate.
7.8.2 Ch. x Analog Zero Cross
Configures when the signal level changes occur for the analog volume controls.
Note: If the signal does not encounter a zero crossing, the requested volume change will occur after a
timeout period of 1024 sample periods (approximately 10.7 ms at 48 kHz sample rate).
7.9 Passthrough Gang Control (Address 0Ch)
7.9.1 Passthrough Channel B=A Gang Control
Configures independent or ganged control of the passthrough channel settings. Mute is not affected.
7 6 5 4 3210
Reserved Reserved Reserved Reserved PASSASEL4 PASSASEL3 PASSASEL2 PASSASEL1
PASSxSEL[4:1] Selected Input to Passthrough Channel x
00000 No inputs selected
00001 AIN1x
00010 AIN2x
00100 AIN3x
01000 AIN4x
Application: “Analog Passthrough” on page 24
Note: Table does not show all possible combinations.
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Reserved Reserved Reserved Reserved ANLGSFTB ANLGZCB ANLGSFTA ANLGZCA
ANLGSFTx Volume Changes Affected Analog Volume Controls
0Do not occur with a soft ramp PASSxVOL[7:0] (“Passthrough x Volume” on page 46)
1 Occur with a soft ramp
Ramp Rate: 1/2 dB every 16 LRCK cycles
ANLGZCx Volume Changes Affected Analog Volume Controls
0Do not occur on a zero cross-
ing PASSxVOL[7:0] (“Passthrough x Volume” on page 46)
1Occur on a zero crossing
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PASSB=A Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PASSB=A Single Volume Control
0Disabled
1 Enabled
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7.10 Playback Control 1 (Address 0Dh)
7.10.1 Headphone Analog Gain
Selects the gain multiplier for the headphone/lin e outputs.
Note: Refer to “Headphone Outpu t Power Chara cteristics” o n page 14 and “Headphone Output Power
Characteristics” on page 14.
7.10.2 Playback Volume Setting B=A
Configures independent or ganged volume control of all playback channels. Mute is not affected.
7.10.3 Invert PCM Signal Polarity
Configures the polarity of the digital input signal.
7.10.4 Master Playback Mu te
Configures a digital mute on th e master volume control for channel x.
Note: The muting function is affected by the DIGSFT (“Digital Soft Ramp” on page 44) and DIGZC
(“Digital Zero Cross” on page 45) bits.
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HPGAIN2 HPGAIN1 HPGAIN0 PLYBCKB=A INV_PCMB INV_PCMA MSTBMUTE MSTAMUTE
HPGAIN[2:0] Headphone/Line Gain Setting (G)
000 0.3959
001 0.4571
010 0.5111
011 0.6047
100 0.7099
101 0.8399
110 1.000
111 1.1430
PLYBCKB=A Single Volume Control for all Playback Channels
0Disabled
1 Enabled
INV_PCMx PCM Signal Polarity
0Not Inverted
1 Inverted
MSTxMUTE Master Mute
0Not Inverted
1 Inverted
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7.11 Miscellaneous Controls (Address 0Eh)
7.11.1 Passthro ugh Analog
Configures an analog passthrough from the analog inputs to the headphone/line outputs.
7.11.2 Passthro ugh Mute
Configures an analog mute on the ch annel x analog in to analog out passthrough.
7.11.3 Freeze Registers
Configures a hold on all register settings.
7.11.4 HP/Speaker De-Emphasis
Configures a 15μs/50μs digital de-empha sis filter response on the headphone/line and speaker outputs.
7.11.5 Digital Soft Ramp
Configures an incremental volume ramp from the current level to the new level at the specified rate.
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PASSTHRUB PASSTHRUA PASSBMUTE PASSAMUTE FREEZE DEEMPH DIGSFT DIGZC
PASSTHRUx Analog In Routed to HP/Line Output
0Disabled
1 Enabled
PASSxMUTE Passthrough Mute
0Disabled
1 Enabled
FREEZE Control Port Status
0Register changes take effect immediately
1Modifications may be made to all control port registers without the changes taking effect until after the
FREEZE is disabled.
DEEMPHASIS Control Port Status
0Disabled
1 Enabled
DIGSFT Volume Changes Affected Digital Volume Controls
0 Does not occur with a soft ramp MSTxMUTE (“Master Playback Mute” on page 43),
HPxMUTE, SPKxMUTE (“Playback Control 2 (Address 0Fh)” on page 45),
PCMxMUTE, PCMxVOL[7:0] (“PCM Channel x Volume” on page 47),
MSTxVOL[7:0] (“Master Volume Control” on page 51),
HPxVOL[7:0] (“Headphone Volume Control” on page 51),
SPKxVOL[7:0] (“Speaker Volume Control” on page 52),
1Occurs with a soft ramp
Ramp Rate: 1/8 dB every LRCK cycle
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7.11.6 Digital Zero Cross
Configures when the signal level changes occur for the digital volume controls.
Notes:
1. If the signal does not encounter a zero crossing, the requested volume change will occur after a
timeout period be tween 1 024 and 2048 sample pe riods (21.3 ms to 42.7 ms at 48 kHz samp le rate).
2. The zero cross function is independently monitored and imple mented for each channel.
3. The DIS_LIMSFT bit (“Limiter Soft Ramp Disab le” on page 53) is ignored when zero cross is enabl ed.
7.12 Playback Control 2 (Address 0Fh)
7.12.1 Headphone Mute
Configures a digital mute on headphone channel x.
7.12.2 Speaker Mute
Configures a digital mute on speaker channel x.
7.12.3 Speaker V olume Setting B=A
Configures independent or ganged volume control of the speaker volu me. Mute is not affected.
7.12.4 Speaker Channel Swap
Configures a channel swap on the speaker channels.
DIGZC Volume Changes Affected Digital Volume Controls
0Do not occur on a zero cross-
ing MSTxMUTE (“Master Playback Mute” on page 43),
HPxMUTE, SPKxMUTE (“Playback Control 2 (Address 0Fh)” on page 45),
PCMxMUTE, PCMxVOL[7:0] (“PCM Channel x Volume” on page 47),
MSTxVOL[7:0] (“Master Volume Control” on page 51),
HPxVOL[7:0] (“Headphone Volume Control” on page 51),
SPKxVOL[7:0] (“Speaker Volume Control” on page 52),
1 Occur on a zero crossing
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HPBMUTE HPAMUTE SPKBMUTE SPKAMUTE SPKB=A SPKSWAP SPKMONO MUTE50/50
HPxMUTE Headphone Mute
0Disabled
1 Enabled
SPKxMUTE Speaker Mute
0Disabled
1 Enabled
SPKB=A Single Volume Control for the Speaker Channel
0Disabled
1 Enabled
SPKSWAP Speaker Output
0Channel A
1 Channel B
Application: “Mono Speaker Output Configuration” on page 27
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7.12.5 Speaker MONO Control
Configures a parallel full bridge output for the speaker channels.
7.12.6 Speaker Mute 50/50 Control
Configures how the speaker channels mute.
7.13 Passthrough x Volume: PASSAVOL (Address 14h) & PASSBVOL (Address 15h)
7.13.1 Passthrough x Volume
Sets the volume/gain of the analog input signal routed to the headphone/line output.
Notes:
1. This register is ignored when the PASSTHRUx bit (“Passthrough Analog” on page 44) is disabled.
2. The step size may deviate from 0.5 dB at settings below -40 dB. Code settings 0x95, 0xA1, 0xAD and
0xB9 are not guaranteed to be monotonic.
SPKMONO Parallel Full Bridge Output
0Disabled
1 Enabled
Application: “Mono Speaker Output Configuration” on page 27
MUTE50/50 Speaker Mute 50/50
0Disabled; The PWM amplifiers outputs modulated silence when SPKxMUTE is enabled.
1Enabled; The PWM amplifiers switch at an exact 50%-duty-cycle signal (not modulated) when SPKxMUTE is
enabled.
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PASSxVOL7 PASSxVOL6 PASSxVOL5 PASSxVOL4 PASSxVOL3 PASSxVOL2 PASSxVOL1 PASSxVOL0
PASSxVOL[7:0] Gain
0111 1111 12 dB
... ...
0001 1000 12 dB
... ...
0000 0001 +0.5 dB
0000 0000 0 dB
11111 1111 -0.5 dB
... ...
1000 1000 -60.0 dB
... ...
1000 0000 -60.0 dB
Step Size: 0.5 dB (approximate)
Application: “Passthrough Analog” on page 44
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7.14 PCMx Volume: PCMA (Address 1Ah) & PCMB (Address 1Bh)
7.14.1 PCM Channel x Mute
Configures a digital mute on the PCM data from the serial data input (SDIN) to the DSP.
7.14.2 PCM Channel x V olume
Sets the volume/gain of the PCM data from the serial data input (SDIN) to the DSP.
7.15 Beep Frequency & On Time (Address 1Ch)
7.15.1 Beep Frequency
Sets the freque n cy of th e be ep sign a l.
76543210
PCMxMUTE PCMxVOL6 PCMxVOL5 PCMxVOL4 PCMxVOL3 PCMxVOL2 PCMxVOL1 PCMxVOL0
PCMxMUTE PCM Mute
0Disabled
1 Enabled
PCMxVOL[6:0] Volume
001 1000 +12.0 dB
... ...
000 0001 +0.5 dB
000 0000 0 dB
111 1111 -0.5 dB
... ...
001 1001 -51.5 dB
Step Size: 0.5 dB
76543210
FREQ3 FREQ2 FREQ1 FREQ0 ONTIME3 ONTIME2 ONTIME1 ONTIME0
FREQ[3:0] Frequency (Fs = 12, 24, 48 or 96 kHz) Pitch
0000 260.87 Hz C4
0001 521.74 Hz C5
0010 585.37 Hz D5
0011 666.67 Hz E5
0100 705.88 Hz F5
0101 774.19 Hz G5
0110 888.89 Hz A5
0111 1000.00 Hz B5
1000 1043.48 Hz C6
1001 1200.00 Hz D6
1010 1333.33 Hz E6
1011 1411.76 Hz F6
1100 1600.00 Hz G6
1101 1714.29 Hz A6
1110 2000.00 Hz B6
1111 2181.82 Hz C7
Application: “Beep Generator” on page 22
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Notes:
1. This setting must not change when BEEP is enabled.
2. Beep frequency will scale directly with sample rate, Fs, but is fixed at the nominal Fs within each
speed mode.
7.15.2 Beep On Time
Sets the on duration of the beep signal.
Notes:
1. This setting must not change when BEEP is enabled.
2. Beep on time will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed
mode.
7.16 Beep Volume & Off Time (Address 1Dh)
7.16.1 Beep Off T ime
Sets the off duration of the beep signal.
ONTIME[3:0] On Time (Fs = 12, 24, 48 or 96 kHz)
0000 ~86 ms
0001 ~430 ms
0010 ~780 ms
0011 ~1.20 s
0100 ~1.50 s
0101 ~1.80 s
0110 ~2.20 s
0111 ~2.50 s
1000 ~2.80 s
1001 ~3.20 s
1010 ~3.50 s
1011 ~3.80 s
1100 ~4.20 s
1101 ~4.50 s
1110 ~4.80 s
1111 ~5.20 s
Application: “Beep Generator” on page 22
76543210
OFFTIME2 OFFTIME1 OFFTIME0 BPVOL4 BPVOL3 BPVOL2 BPVOL1 BPVOL0
OFFTIME[2:0] Off Time (Fs = 48 or 96 kHz)
000 ~1.23 s
001 ~2.58 s
010 ~3.90 s
011 ~5.20 s
100 ~6.60 s
101 ~8.05 s
110 ~9.35 s
111 ~10.80 s
Application: “Beep Generator” on page 22
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Notes:
1. This setting must not change when BEEP is enabled.
2. Beep off time will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed
mode.
7.16.2 Beep Volume
Sets the volume of the beep signal.
Note: This setting must not change when BEEP is enabled.
7.17 Beep & Tone Configuration (Address 1Eh)
7.17.1 Beep Configuration
Configures a beep mixed with the HP/Line and SPK output.
Notes:
1. When used in analog pass through mode, the output alternates between the signal from the
Passthrough Amplifier and the b eep signal. The beep signal does not mix with the analog signal from
the Passthrough Amplifier.
2. Re-engaging the beep before it has completed its initial cycle will cause the beep signal to remain ON
for the maximum ONTIME duration.
7.17.2 Beep Mix Disable
Configures how the beep mixes with the serial data input.
Note: This setting must not change when BEEP is enabled.
BEEPVOL[4:0] Gain
00110 +6.0 dB
··· ···
00000 -6 dB
11111 -8 dB
11110 -10 dB
··· ···
00111 -56 dB
Step Size: 2 dB
Application: “Beep Generator” on page 22
76543210
BEEP1 BEEP0 BEEPMIXDIS TREBCF1 TREBCF0 BASSCF1 BASSCF0 TCEN
BEEP[1:0] Beep Occurrence
00 Off
01 Single
10 Multiple
11 Continuous
Application: “Beep Generator” on page 22
BEEPMIXDIS Beep Output to HP/Line and Speaker
0Mix Enabled; The beep signal mixes with the digital signal from the serial data input.
1Mix Disabled; The output alternates between the signal from the serial data input and the beep signal. The
beep signal does not mix with the digital signal from the serial data input.
Application: “Beep Generator” on page 22
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7.17.3 Treble Corner Frequency
Sets the corner frequency (-3 dB point) for the treble shelving filter.
7.17.4 Bass Corner Frequency
Sets the corner frequency (-3 dB point) for the bass she lving filter.
7.17.5 Tone Control Enable
Configures the treble and bass activation.
7.18 Tone Control (Address 1Fh)
7.18.1 Treble Gain
Sets the gain of the treble shelving filter.
TREBCF[1:0] Treble Corner Frequency Setting
00 5 kHz
01 7 kHz
10 10 kHz
11 15 kHz
BASSCF[1:0] Bass Corner Frequency Setting
00 50 Hz
01 100 Hz
10 200 Hz
11 250 Hz
TCEN Bass and Treble Control
0Disabled
1 Enabled
Application: “Beep Generator” on page 22
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TREB3 TREB2 TREB1 TREB0 BASS3 BASS2 BASS1 BASS0
TREB[3:0] Gain Setting
0000 +12.0 dB
··· ···
0111 +1.5 dB
1000 0 dB
1001 -1.5 dB
··· ···
1111 -10.5 dB
Step Size: 1.5 dB
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7.18.2 Bass Gain
Sets the gain of the bass shelving filter.
7.19 Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h)
7.19.1 Master Volume Control
Sets the volume of the signal out the DSP.
7.20 Headphone Volume Control: HPA (Address 22h) & HPB (Address 23h)
7.20.1 Headphone Volume Control
Sets the volume of the signal out the DAC.
TREB[3:0] Gain Setting
0000 +12.0 dB
··· ···
0111 +1.5 dB
1000 0 dB
1001 -1.5 dB
··· ···
1111 -10.5 dB
Step Size: 1.5 dB
76543210
MSTxVOL7 MSTxVOL6 MSTxVOL5 MSTxVOL4 MSTxVOL3 MSTxVOL2 MSTxVOL1 MSTxVOL0
MSTxVOL[7:0] Master Volume
0001 1000 +12.0 dB
··· ···
0000 0000 0 dB
1111 1111 -0.5 dB
1111 1110 -1.0 dB
··· ···
0011 0100 -102 dB
··· ···
0001 1001 -102 dB
Step Size: 0.5 dB
76543210
HPxVOL7 HPxVOL6 HPxVOL5 HPxVOL4 HPxVOL3 HPxVOL2 HPxVOL1 HPxVOL0
HPxVOL[7:0] Headphone Volume
0000 0000 0 dB
1111 1111 -0.5 dB
1111 1110 -1.0 dB
··· ···
0011 0100 -96.0 dB
··· ···
0000 0001 Muted
Step Size: 0.5 dB
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7.21 Speaker Volume Control: SPKA (Address 24h) & SPKB (Address 25h)
7.21.1 Speaker Volume Control
Sets the volume of the signal out the PWM modulator.
Note: The maximum step size err or is +/-0.15 dB.
7.22 PCM Channel Swap (Address 26h)
7.22.1 PCM Channel Swap
Configures a mix/swap of the PCM data to the headphone/line or speaker outputs.
76543210
SPKxVOL7 SPKxVOL6 SPKxVOL5 SPKxVOL4 SPKxVOL3 SPKxVOL2 SPKxVOL1 SPKxVOL0
SPKxVOL[7:0] Speaker Volume
0000 0000 0 dB
1111 1111 -0.5 dB
1111 1110 -1.0 dB
··· ···
0100 0000 -96.0 dB
··· ···
0000 0001 Muted
Step Size: 0.5 dB
76543210
PCMASWP1 PCMASWP0 PCMBSWP1 PCMBSWP0 Reserved Reserved Reserved Reserved
PCMxSWP[1:0] PCM to HP/LINEOUTA PCM to HP/LINEOUTB
00 Left Right
01 (Left + Right)/2 (Left + Right)/2
10
11 Right Left
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7.23 Limiter Control 1, Min/Max Thresholds (Address 27h)
7.23.1 Limiter Maximum Threshold
Sets the maximum level, below full scale, at which to limit and attenuate the output signal at the attack
rate (LIMARATE - “Limiter Release Rate” on page 54).
Note: Bass, Treble and digital gain settings that boost the signal beyond the maximum threshold may
trigger an attack.
7.23.2 Limiter Cushion Threshold
Sets the minimum level at which to disengage the Limiter’s attenuation at the release rate (LIMRRATE -
“Limiter Release Rate” on page 54) until levels lie between th e LM AX an d CUSH thre sh o lds.
Note: This setting is usually set slightly be low the LM AX th re shold .
7.23.3 Limiter Soft Ramp Disable
Configures an over rid e of th e dig ita l soft ram p settin g.
Note: This bit is ignored when the DIGZC (“Digital Zero Cross” on page 45) is enabled.
76543210
LMAX2 LMAX1 LMAX0 CUSH2 CUSH1 CUSH0 LIMSRDIS LIMZCDIS
LMAX[2:0] Threshold Setting
000 0 dB
001 -3 dB
010 -6 dB
011 -9 dB
100 -12 dB
101 -18 dB
110 -24 dB
111 -30 dB
Application: “Limiter” on page 22
CUSH[2:0] Threshold Settin g
000 0 dB
001 -3 dB
010 -6 dB
011 -9 dB
100 -12 dB
101 -18 dB
110 -24 dB
111 -30 dB
Application: “Limiter” on page 22
LIMSRDIS Limiter Soft Ramp Disable
0OFF; Limiter Attack Rate is dictated by the DIGSFT (“Digital Soft Ramp” on page 44) setting
1 ON; Limiter volume changes take effect in one step, regardless of the DIGSFT setting.
Application: “Limiter” on page 22
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7.23.4 Limiter Zero Cross Disable
Configures an override of the digital zero cross setting.
7.24 Limiter Control 2, Release Rate (Address 28h)
7.24.1 Peak Detect and Limiter
Configures the peak detect and limiter circuitry.
7.24.2 Peak Signal Limit All Channels
Sets how channels are attenuated when the limiter is enabled.
7.24.3 Limiter Release Rate
Sets the rate at which the limiter relea ses the dig ita l attenuation from leve ls below the CUSH[2:0 ] thresh-
old (“Limiter Cushion Threshold” on page 53) and return s the analog output leve l to the MSTxVOL[7:0]
(“Master Volume Control” on pag e 51) setting.
Note: The limiter release rate is user-selectable but is also a function of the sampling frequency, Fs,
and the DIGSFT (“Digital Soft Ramp” on page 44) and DIGZC (“Digital Zero Cross” on page 45) s et tin g.
LIMZCDIS Limiter Zero Cross Disable
0OFF; Limiter Attack Rate is dictated by the DIGZC (“Digital Zero Cross” on page 45) setting
1 ON; Limiter volume changes take effect in one step, regardless of the DIGZC setting.
Application: “Limiter” on page 22
76543210
LIMIT LIMIT_ALL LIMRRATE5 LIMRRATE4 LIMRRATE3 LIMRRATE2 LIMRRATE1 LIMRRATE0
LIMIT Limiter Status
0Disabled
1 Enabled
Application: “Limiter” on page 22
LIMIT_ALL Limiter action:
0
Apply the necessary attenuation on a specific channel only when the signal amplitude on that specific chan-
nel rises above LMAX.
Remove attenuation on a specific channel only when the signal amplitude on that specific channel falls below
CUSH.
1Apply the necessary attenuation on BOTH channels when the signal amplitude on any ONE channel rises
above LMAX.
Remove attenuation on BOTH channels only when the signal amplitude on BOTH channels fall below CUSH.
Application: “Limiter” on page 22
LIMRRATE[5:0] Release Time
00 0000 Fastest Release
··· ···
11 1111 Slowest Release
Application: “Limiter” on page 22
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7.25 Limiter Attack Rate (Address 29h)
7.25.1 Limiter Attack Rate
Sets the rate at which the limiter applies digital attenuation from levels above the MAX[2:0] threshold
(“Limiter Maximum Threshold” on page 53).
Note: The limiter attack rate is user-selectable b ut is also a function of the sampling frequency, Fs, and
the DIGSFT (“Digital Soft Ramp” on page 44) and DIGZC (“Digital Zero Cross” on page 45) setting unless
the respective disable bit (“Limiter Soft Ramp Disable” on page 53 or “Limiter Zero Cross Disable” on
page 54) is enabled.
7.26 Status (Address 2Eh) (Read Only)
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT oc cu rr ed sin ce t he last re ad ing
of the register. Reading the register resets all bits to 0.
7.26.1 Serial Port Clock Error (Read Only)
Indicates the status of the MCLK to LRCK ratio.
Note: On initial power up and application of clocks, this bit will report ‘1’b as the serial port re-synchro-
nizes.
7.26.2 DSP Engine Overflow (Read Only)
Indicates the over-range status in the DSP data path.
76543210
Reserved Reserved LIMARATE5 LIMARATE4 LIMARATE3 LIMARATE2 LIMARATE1 LIMARATE0
LIMARATE[5:0] Attack Time
00 0000 F astest Attack
··· ···
11 1111 Slowest Attack
Application: “Limiter” on page 22
76543210
Reserved SPCLKERR DSPAOVFL DSPBOVFL PCMAOVFL PCMBOVFL Reserved Reserved
SPCLKERR Serial Port Clock Status:
0 MCLK/LRCK ratio is valid.
1 MCLK/LRCK ratio is not valid.
Application: “Serial Port Clocking” on page 29
DSPxOVFL DSP Overflow Status:
0 No digital clipping has occurred in the data path after the DSP.
1 Digital clipping has occurred in the data path after the DSP.
Application: “DSP Engine” on page 21
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7.26.3 PCMx Overflow (Read Only)
Indicates the over-range status in the PCM data path.
7.27 Battery Compensation (Address 2Fh)
7.27.1 Battery Compensation
Configures automatic adjustment of the speaker volume when VP deviates from VPREF[3:0].
7.27.2 VP Monitor
Configures the internal ADC that monitors the VP voltage level.
Notes:
1. The internal ADC that monitors the VP supply is enabled automatically when BATTCMP is enabled, re-
gardless of the VPMONITOR setting. Conversely, when BATTCMP is disabled, the ADC may be en-
abled by enabling VPMONITOR; this provides a convenient battery monitor without enabling battery
compensation.
2. When enabled, VPMONITOR remains enabled regardless of the PDN bit setting.
PCMxOVFL PCM Overflow Status:
0No digital clipping has occurred in the data path of the PCM (“PCM Channel x Volume” on page 47) of the
DSP.
1 Digital clipping has occurred in the data path of the PCM of the DSP.
Application: “DSP Engine” on page 21
76543210
BATTCMP VPMONITOR Reserved Reserved VPREF3 VPREF2 VPREF1 VPREF0
BATTCMP Automatic Battery Compensation
0Disabled
1 Enabled
Application: “Maintaining a Desired Output Level” on page 27
VPMONITOR VP ADC Status
0Disabled
1 Enabled
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7.27.3 VP Reference
Sets the desired VP reference used for battery compensation.
7.28 VP Battery Level (Address 30h) (Read Only)
7.28.1 VP Voltage Level (Read Only)
Indicates the unsigned VP voltage level.
7.29 Speaker Status (Address 31h) (Read Only)
7.29.1 Speaker Current Load Status (Read Only)
Indicates whether or not any of the speaker outputs is shorted to ground.
VPREF[3:0] Desired VP used to calculate the required attenuation on the speaker output:
(for VA = 1.8 V)
0000 1.5 V
0001 2.0 V
0010 2.5 V
0011 3.0 V
0100 3.5 V
0101 4.0 V
0110 4.5 V
0111 5.0 V (for VA = 2.5 V)
1000 1.5 V
1001 2.0 V
1010 2.5 V
1011 3.0 V
1100 3.5 V
1101 4.0 V
1110 4.5 V
1111 5.0 V
Application: “VP Battery Compensation” on page 27
76543210
VPLVL7 VPLVL6 VPLVL5 VPLVL4 VPLVL3 VPLVL2 VPLVL1 VPLVL0
VPLVL[7:0] VP Voltage
...
0101 1110 3.0 V (for VA = 2.0 V); apply formula using actual VA voltage to calculate VP voltage.
...
0111 0010 3.7 V (for VA = 2.0 V); apply formula using actual VA voltage to calculate VP voltage.
...
Formula: VP Voltage = (Binary representation of VPLVL[7:0]) * VA / 63.3
76543210
Reserved Reserved SPKASHRT SPKBSHRT SPKR/HP Reserved Reserved Reserved
SPKxSHRT Speaker Output Load
0 No overload detected
1 Overload detected
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7.29.2 SPKR/HP Pin Status (Read Only)
Indicates the status of the SPKR/HP pin.
7.30 Charge Pump Frequency (Address 34h)
7.30.1 Charge Pump Frequency
Sets the charge pump frequency on FLYN and FLYP.
Note: The headphone ou tput THD+N performance may be affected.
SPKR/HP Pin State
0 Pulled Low
1 Pulled High
76543210
CHGFREQ3 CHGFREQ2 CHGFREQ1 CHGFREQ0 Reserved Reserved Reserved Reserved
CHGFREQ[3:0] N
0000 0
...
0101 5
...
1111 15
Formula: Frequency = (64xFs)/(N+2)
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8. ANALOG PERFORMANCE PLOTS
8.1 Headphone THD+N versus Output Power Plots
Test conditions (unless otherwise sp ecified): Input test sign al is a 997 H z sine wave; measureme nt band-
width is 10 Hz to 20 kHz; Fs = 48 kHz.
G = 0.6047
G = 0.7099
G = 0.8399
G = 1.0000
G = 1.1430
Legend
-100
-10
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
d
B
r
A
080m10m 20m 30m 40m 50m 60m 70m
W
Figure 18. THD+N vs. Output Power per Channel at 1.8 V (16 Ω load)
VHP = VA = 1.8 V
NOTE: Graph shows the out-
put power per channel (i.e.
Output Power = 23 mW into
single 16 Ω and 46 mW into
stereo 16 Ω with THD+N = -
75 dB).
G = 0.6047
G = 0.7099
G = 0.8399
G = 1.0000
G = 1.1430
Legend
-100
-10
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
d
B
r
A
080m10m 20m 30m 40m 50m 60m 70m
W
Figure 19. THD+N vs. Output Power per Channel at 2.5 V (16 Ω load)
VHP = VA = 2.5 V
NOTE: Graph shows the out-
put power per channel (i.e.
Output Power = 44 mW into
single 16 Ω and 88 mW into
stereo 16 Ω with THD+N = -
75 dB).
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G = 0.6047
G = 0.7099
G = 0.8399
G = 1.0000
G = 1.1430
Legend
-100
-20
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
d
B
r
A
060m6m 12m 18m 24m 30m 36m 42m 48m 54m
W
Figure 20. THD+N vs. Output Power per Channel at 1.8 V (32 Ω load)
VHP = VA = 1.8 V
NOTE: Graph shows the out-
put power per channel (i.e.
Output Power = 22 mW into
single 32 Ω and 44 mW into
stereo 32 Ω with THD+N = -
75 dB).
G = 0.6047
G = 0.7099
G = 0.8399
G = 1.0000
G = 1.1430
Legend
-100
-20
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
d
B
r
A
060m5m 10m 15m 20m 25m 30m 35m 40m 45m 50m 55m
W
Figure 21. THD+N vs. Output Power per Channel at 2.5 V (32 Ω load)
VHP = VA = 2.5 V
NOTE: Graph shows the out-
put power per channel (i.e.
Output Power = 42 mW into
single 32 Ω and 84 mW into
stereo 32 Ω with THD+N = -
75 dB).
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9. EXAMPLE SYSTEM CLOCK FREQUENCIES *The”MCLKDIV2” bit must be enabled.
9.1 Auto Detect Enabled
9.2 Auto Detect Disabled
Sample Rate
LRCK (kHz) MCLK (MHz)
1024x 1536x 2048x* 3072x*
8 8.1920 12.2880 16.3840 24.5760
11.025 11.2896 16.9344 22.5792 33.8688
12 12.2880 18.4320 24.5760 36.8640
Sample Rate
LRCK (kHz) MCLK (MHz)
512x 768x 1024x* 1536x*
16 8.1920 12.2880 16.3840 24.5760
22.05 11.2896 16.9344 22.5792 33.8688
24 12.2880 18.4320 24.5760 36.8640
Sample Rate
LRCK (kHz) MCLK (MHz)
256x 384x 512x* 768x*
32 8.1920 12.2880 16.3840 24.5760
44.1 11.2896 16.9344 22.5792 33.8688
48 12.2880 18.4320 24.5760 36.8640
Sample Rate
LRCK (kHz) MCLK (MHz)
128x 192x 256x* 384x*
64 8.1920 12.2880 16.3840 24.5760
88.2 11.2896 16.9344 22.5792 33.8688
96 12.2880 18.4320 24.5760 36.8640
Sample Rate
LRCK (kHz) MCLK (MHz)
512x 768x 1024x 1536x 2048x 3072x
8 - 6.1440 8.1920 12.2880 16.3840 24.5760
11.025 - 8.4672 11.2896 16.9344 22.5792 33.8688
12 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640
Sample Rate
LRCK (kHz) MCLK (MHz)
256x 384x 512x 768x 1024x 1536x
16 - 6.1440 8.1920 12.2880 16.3840 24.5760
22.05 - 8.4672 11.2896 16.9344 22.5792 33.8688
24 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640
Sample Rate
LRCK (kHz) MCLK (MHz)
256x 384x 512x 768x
32 8.1920 12.2880 16.3840 24.5760
44.1 11.2896 16.9344 22.5792 33.8688
48 12.2880 18.4320 24.5760 36.8640
Sample Rate
LRCK (kHz) MCLK (MHz)
128x 192x 256x 384x
64 8.1920 12.2880 16.3840 24.5760
88.2 11.2896 16.9344 22.5792 33.8688
96 12.2880 18.4320 24.5760 36.8640
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10.PCB LAYOUT CONSIDERATIONS
10.1 Power Supply, Grounding
As with any high-resolution conve rter, the CS43L2 2 require s careful attention to po wer supply and ground-
ing arrangements if its p otential performance is to be realized. Figure 1 on page 9 shows the recommended
power arrangements, with VA and VHP connected to clean supplies VD, which powers the digital circuitry,
may be run from the system logic supply. Alternatively, VD may be powered from the analog supply via a
ferrite bead. In this case, no additional devices should be powered from VD.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are r ecommended. Decoupling ca pacitors should be as close to the pins of the CS43L22 as pos-
sible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same
side of the board as the CS43L22 to minimize inductance effects.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted
coupling into the modulators. The VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to
minimize the electrical path from AGND. The CDB43L22 evaluation board demonstrates the optimum layout
and power supply arrangements.
10.2 QFN Thermal Pad
The CS43L22 is available in a compact QFN package. The underside of the QFN package reveals a large
metal pad th at serves as a thermal r elief to provide for ma ximum hea t dissipation. This pad mu st mate with
an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of
vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers.
In split ground systems, it is recommended that this thermal pad be connected to AGND for best perfor-
mance. The CS43L22 evaluation board demonstrates the optimum thermal pad and via configuration.
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12.PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms va lue of the signa l to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Ran ge is a signal-to-noise ra tio measurement over the specified b and width made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This
technique ensures that the distortion components are below the noise level and do not affect the measur e-
ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms va lue of the signa l to the rms sum of all other spectral components over the specified
band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of th e am p litu de r es po ns e varia tio n f ro m 1 0 H z t o 20 kH z r ela tiv e to th e am p litu de r es po ns e at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channel pairs. Measured for each channel at the convert-
er's output with no signal to the input under test and a full-scale signal ap plied to the other channel. Units in
decibels.
Interchannel Gain Mism atch
The gain difference between left and right channel pairs. Units in decibels.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
DS792F2 65
CS43L22
Confidential Draft
3/4/10
13.PACKAGE DIMENSIONS
1. Dimensioning and tolerance per ASME Y 14.5M-1995.
2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm
from the terminal tip.
THERMAL CHARACTERISTICS
INCHES MILLIMETERS NOTE
DIM MIN NOM MAX MIN NOM MAX
A -- -- 0.0394 -- -- 1.00 1
A1 0.0000 -- 0.0020 0.00 -- 0.05 1
b 0.0071 0.0091 0.0110 0.18 0.23 0.28 1,2
D 0.2362 BSC 6.00 BSC 1
D2 0.1594 0.1614 0.1634 4.05 4.10 4.15 1
E 0.2362 BSC 6.00 BSC 1
E2 0.1594 0.1614 0.1634 4.05 4.10 4.15 1
e 0.0197 BSC 0.50 BSC 1
L 0.0118 0.0157 0.0197 0.30 0.40 0.50 1
JEDEC #: MO-220
Controlling Dimension is Millimeters.
Parameter Symbol Min Typ Max Units
Junction to Ambient Thermal Impedance 2 Layer Board
4 Layer Board θJA
θJA
-
-44
19 -
-°C/Watt
°C/Watt
40L QFN (6 X 6 mm BODY) PACKAGE DRAWING
eb
A
A1
PIN #1 IDENTIFIER
∅0.50±0.10
LASER MARKING
E
2.00 REF
D2
L
PIN #1 CORNER
2.00 REF
E2
D
66 DS792F2
CS43L22
Confidential Draft
3/4/10
14.ORDERING INFORMATION
15.REFERENCES
1. Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000.
http://www.semiconductors.philips.com
16.REVISION HISTORY
Product Description Package Pb-Free Grade Temp Range Container Order #
CS43L22 Low-Power Stereo DAC
w/HP and S peaker Amp s
for Portable Apps 40L-QFN Yes Commercial -40 to +85° C Rail CS43L22-CNZ
Tape & Reel CS43L22-CNZR
CDB43L22 CS43L22 Eva l uation
Board - No - - - CDB43L22
Revision Changes
F2 Added AD0 characteristics to “I/O Pin Characteristics” on page 8.
Added a description of the AD0 pin to “I²C Control” on page 33.
Added AD0 detail to Figure 16. Control Port Timing, I²C Write on page 33 and Figure 17. Control Port Timing, I²C
Read on page 33.
Updated the first paragraph in “Register Quick Reference” on page 35 and “Register Description” on page 37 to
allow for data sheet-specified control-writes to reserved registers.
Updated Note 3 on page 11.
Removed I²C address heading row from “Register Quick Reference” on page 35.
Contacting Cirrus Logic Support
For all product questions and inq uiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidi aries (“Cirrus”) believe that t he information conta ined in this documen t is accu rate and r eliable. However, the information is subject
to change without notice a nd is prov ided “AS IS” without war ranty of any kind (express or implie d). Cust omers are ad vised to o btain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms a nd co nditio ns of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of paten ts or other r ights of third
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POT ENTIAL RI SKS OF DEAT H, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS AR E NOT DESIGNED, AU THORIZED OR WARRANTED FOR USE
IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT-
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ER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY
INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DI STRI BUT ORS AN D OT HE R AGE NTS FRO M ANY AND AL L LI ABI L I TY, I NCL UDING AT-
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Cirrus Logic, Cirrus, an d the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other bra nd an d product names in this document may be trademarks
or service marks of their respective owners.
I²C is a trademark of Philips Semiconductor.
