935277841518 - NXP SEMICONDUCTORS

1. General description

The P89LPC933/934/935/936 is a single-chip microcontroller, available in low cost

packages, based on a high performance pr ocessor arch itecture that executes instr uctions

in two to four clocks, six times the rate of standard 80C51 devices. Many system-level

functions have been incorpora ted into the P89LPC933/934/935/936 in order to reduce

component count, board space, and system cost.

2. Features and benefits

2.1 Principal features

4 kB/8 kB/16 kB byte-erasa ble flash code memory organized into 1 kB/2 kB sectors

and 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile

data storage.

256-byte RAM data memory. Both the P89LPC935 and P89LPC936 also include a

512-byte auxiliary on-chip RAM.

512-byte customer data EEPROM on chip allows serialization of devices, storage of

setup parameters , etc. (P89LPC935/936).

Dual 4-input multiplexed 8-bit A/D converters/DAC ou tputs (P89LPC935/936, single

A/D on P89LPC933/934).Two analog comparators with selectable inputs and

reference source.

Two 16-bit counter/timers (each may be configured to toggle a port output upon timer

overflow or to become a PWM output) and a 23-b it system timer that can also be used

as an RTC.

Enhanced UART with fractional baud rate generator, break detect, framing error

detection, and automatic address detection; 400 kHz byte-wide I2C-bus

communication port and SPI communication port.

Capture/Compare Unit (CCU) provides PWM, input capture, and output compare

functions (P89LPC9 35/936).

High-accuracy internal RC oscillator option allows operation without external oscillator

components. The RC oscillator option is selectable and fine tunable.

2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or

driven to 5.5 V).

28-pin TSSOP, PLCC, and HVQFN packages with 23 I/O pins minimum and up to 26

I/O pins while using on-chip oscillator and reset options.

P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs

Rev. 8 — 12 January 2011 Product data sheet

Product data sheet Rev. 8 — 12 January 2011 2 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

2.2 Additional features

A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns

for all instructions except multiply and divide when executing at 18 MHz. This is six

times the performance of the standard 80C51 running at the same clock frequen cy. A

lower clock frequen cy for the same performance re sults in power savings and reduced

EMI.

Serial flash In-Circuit Programming (ICP) allows simple production coding with

commercial EPRO M pr ogr am m er s. Fla sh secu r ity bits preven t re ad ing of sensit ive

application programs.

Serial flash In-System Programming (ISP) allows coding while the device is mounted

in the end applica tion .

In-Application Programming (IAP) of the fl ash code memo ry. Th is allows cha ng ing the

code in a running application.

Watchdog timer with separate on-chip oscillator, requiring no external components.

The watchdog prescaler is selectab le from eight values.

Low voltage reset (brown out detect) allows a graceful system shutdown when power

fails. May optionally be configured as an interrupt.

Idle and two different power-down reduced power modes. Improved wake-up from

Power-down mode (a LOW interr upt input starts execution). Typical power-down

current is 1 μA (total power-down with voltage comparat or s disa b led ).

Active-LOW reset. On-chip power-on reset allows operation without external reset

components. A reset counter and reset glitch suppression circuitry prevent spurious

and incomplete resets. A software reset function is also available.

Configurable on-chip oscillator with frequency range options selected by user

programmed flash configuration bits. Oscillator options support frequencies from

20 kHz to the maximum operating frequency of 18 MHz.

Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator

allowing it to perform an oscillator fail detect function.

Programmable port output configuration options: quasi-bidirectional, open drain,

push-pull, input-only.

Port ‘input patte rn match’ detect. Port 0 may generate an interrupt when the value of

the pins match or do not match a programmable pattern.

LED drive capability (20 mA) on all port pins. A maximum limit is specified for the

entire chip.

Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns

minimum ramp times.

Only power and gr ou n d conn ections are req uir ed to oper at e th e

P89LPC933/934/935/936 when internal reset option is selected.

Four interrupt priority levels.

Eight keypad in terrupt inputs , plus two additional external interrupt inputs.

Schmitt trigger port inputs.

Second data pointer.

Emulation suppo rt.

Product data sheet Rev. 8 — 12 January 2011 3 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

3. Product comparison overview

Table 1 highlights the differences between the four devices. For a complete list of device

features please see Section 2 “Features and benefits”.

4. Ordering information

4.1 Ordering options

Table 1. Product comparison overview

Device Flash memory Sector size ADC1 ADC0 CCU Data EEPROM

P89LPC933 4 kB 1 kB X - - -

P89LPC934 8 kB 1 kB X - - -

P89LPC935 8 kB 1 kB X X X X

P89LPC936 16 kB 2 kB X X X X

Table 2. Ordering information

Type number Package

Name Description Version

P89LPC935FA PLCC28 plastic leaded chip carrier; 28 leads SOT261-2

P89LPC933HDH TSSOP28 plastic thin shrink small outline

package; 28 leads; body width 4.4 mm SOT361-1

P89LPC933FDH

P89LPC934FDH

P89LPC935FDH

P89LPC936FDH

P89LPC935FHN HVQFN28 plastic thermal enhanced very thin

quad flat package; no leads;

28 terminals; body 6 ×6×0.85 mm

SOT788-1

Table 3. Orderin g options

Type number Flash memory Temperature range Frequency

P89LPC933HDH 4 kB −40 °Cto+125°C 0 MHzto18MHz

P89LPC933FDH 4 kB −40 °Cto+85°C

P89LPC935FA 8 kB

P89LPC934FDH

P89LPC935FDH

P89LPC935FHN

P89LPC936FDH 16 kB

Product data sheet Rev. 8 — 12 January 2011 4 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

5. Block diagram

Fig 1. Block diagram

ACCELERATED 2-CLOCK 80C51 CPU

4 kb/8 kB/16 kB

CODE FLASH

256-BYTE

DATA RAM

PORT 2

CONFIGURABLE I/Os

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

PROGRAMMABLE

OSCILLATOR DIVIDER

CPU

clock

CONFIGURABLE

OSCILLATOR

ON-CHIP

OSCILLATOR

internal bus

CRYSTAL

RESONATOR

POWER MONITOR

(POWER-ON RESET,

BROWNOUT RESET)

002aab070

UART

ANALOG

COMPARATORS

512-BYTE

AUXILIARY RAM

I2C-BUS

512-BYTE

DATA EEPROM

(P89LPC935/936)

PORT 3

CONFIGURABLE I/Os

CCU (CAPTURE/

COMPARE UNIT)

(P89LPC935/936)

P89LPC933/934/935/936

WATCHDOG TIMER

AND OSCILLATOR

TIMER 0

TIMER 1

REAL-TIME CLOCK/

SYSTEM TIMER

SPI

ADC1/DAC1

ADC0/DAC0

(P89LPC935/936)

P3[1:0]

P2[7:0]

P1[7:0]

P0[7:0]

TXD

RXD

SCL

SDA

CMP2

CIN2B

CIN2A

CMP1

CIN1A

CIN1B

OCA

OCB

OCC

OCD

ICA

AD10

AD11

AD12

AD13

DAC1

AD00

AD01

AD02

AD03

DAC1

ICB

SPICLK

MOSI

MISO

Product data sheet Rev. 8 — 12 January 2011 5 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

6. Pinning information

6.1 Pinning

Fig 2. P89LPC933/934 TSSOP28 pin configuration

Fig 3. P89LPC935/936 TSSOP28 pin configuration

P89LPC933HDH

P89LPC933FDH

P89LPC934FDH

002aab071

P2.7

P2.6

P0.1/CIN2B/KBI1/AD10

P0.2/CIN2A/KBI2/AD11

P0.3/CIN1B/KBI3/AD12

P0.4/CIN1A/KBI4/DAC1/AD13

P0.5/CMPREF/KBI5

VDD

P0.6/CMP1/KBI6

P0.7/T1/KBI7

P1.0/TXD

P1.1/RXD

P2.5/SPICLK

P2.4/SS

P2.0/DAC0

P2.1

P0.0/CMP2/KBI0

P1.7

P1.6

P1.5/RST

VSS

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1

P1.3/INT0/SDA

P1.2/T0/SCL

P2.2/MOSI

P2.3/MISO

P89LPC935FDH

P89LPC936FDH

002aab072

P2.0/ICB/DAC0/AD03

P2.1/OCD/AD02

P0.0/CMP2/KBI0/AD01

P1.7/OCC/AD00

P1.6/OCB

P1.5/RST

VSS

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1

P1.3/INT0/SDA

P1.2/T0/SCL

P2.2/MOSI

P2.3/MISO

P2.7/ICA

P2.6/OCA

P0.1/CIN2B/KBI1/AD10

P0.2/CIN2A/KBI2/AD11

P0.3/CIN1B/KBI3/AD12

P0.4/CIN1A/KBI4/DAC1/AD13

P0.5/CMPREF/KBI5

VDD

P0.6/CMP1/KBI6

P0.7/T1/KBI7

P1.0/TXD

P1.1/RXD

P2.5/SPICLK

P2.4/SS

Product data sheet Rev. 8 — 12 January 2011 6 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

Fig 4. P89LPC935 PLCC28 pin configuration

Fig 5. P89LPC935 HVQFN28 pin configuration

P89LPC935FA

002aab074

P1.6/OCB

P1.5/RST

VSS

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1

P1.3/INT0/SDA

P1.7/OCC/AD00

P0.0/CMP2/KBI0/AD01

P2.1/OCD/AD02

P2.0/ICB/DAC0/AD03

P2.7/ICA

P2.6/OCA

P0.1/CIN2B/KBI1/AD10

P0.2/CIN2A/KBI2/AD11

P0.3/CIN1B/KBI3/AD12

P0.4/CIN1A/KBI4/DAC1/AD13

P0.5/CMPREF/KBI5

VDD

P0.6/CMP1/KBI6

P0.7/T1/KBI7

P1.2/T0/SCL

P2.2/MOSI

P2.3/MISO

P2.4/SS

P2.5/SPICLK

P1.1/RXD

P1.0/TXD

002aab076

P89LPC935FHN

Transparent top view

7 15

6 16

5 17

4 18

319

2 20

1 21

terminal 1

index area

P1.7/OCC/AD00

P2.7/ICA

P2.1/OCD/AD02

P2.0/ICB/DAC0/AD03

P0.0/CMP2/KBI0/AD01

P2.6/OCA

P0.1/CIN2B/KBI1/AD10

P2.4/SS

P2.2/MOSI

P2.3/MISO

P1.2/T0/SCL

P2.5/SPICLK

P1.0/TXD

P1.1/RXD

P1.4/INT1

P1.3/INT0/SDA

P3.0/XTAL2/CLKOUT

P3.1/XTAL1

VSS

P1.5/RST

P1.6/OCB

P0.6/CMP1/KBI6

P0.7/T1/KBI7

P0.5/CMPREF/KBI5

VDD

P0.4/CIN1A/KBI4/DAC1/AD13

P0.3/CIN1B/KBI3/AD12

P0.2/CIN2A/KBI2/AD11

Product data sheet Rev. 8 — 12 January 2011 7 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

6.2 Pin description

Table 4. Pin description

Symbol Pin Type Description

TSSOP28,

PLCC28 HVQFN28

P0.0 to P0.7 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type.

During reset Port 0 latches are configured in the input only mode with the

internal pull-up disabled. The operation of Port 0 pins as inputs and

outputs depends upon the port configuration selected. Each port pin is

configured independently. Refer to Section 8.13.1 “Port configurations”

and Table 11 “Static characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt trigger inputs.

Port 0 also provides various special functions as described below:

P0.0/CMP2/

KBI0/AD01 327I/OP0.0 — Port 0 bit 0.

OCMP2 — Comparator 2 output.

IKBI0 — Keyboard input 0.

IAD01 — ADC0 channel 1 analog input. (P89L PC935/936)

P0.1/CIN2B/

KBI1/AD10 26 22 I/O P0.1 — Port 0 bit 1.

ICIN2B — Comparator 2 positive input B.

IKBI1 — Keyboard input 1.

IAD10 — ADC1 channel 0 analog input.

P0.2/CIN2A/

KBI2/AD11 25 21 I/O P0.2 — Port 0 bit 2.

ICIN2A — Comparator 2 positive input A.

IKBI2 — Keyboard input 2.

IAD11 — ADC1 channel 1 analog input.

P0.3/CIN1B/

KBI3/AD12 24 20 I/O P0.3 — Port 0 bit 3.

ICIN1B — Comparator 1 positive input B.

IKBI3 — Keyboard input 3.

IAD12 — ADC1 channel 2 analog input.

P0.4/CIN1A/

KBI4/DAC1/

AD13

23 19 I/O P0.4 — Port 0 bit 4.

ICIN1A — Comparator 1 positive input A.

IKBI4 — Keyboard input 4.

ODAC1 — Digital-to-analog converter output 1.

IAD13 — ADC1 channel 3 analog input.

P0.5/

CMPREF/

KBI5

22 18 I/O P0.5 — Port 0 bit 5.

ICMPREF — Comparator reference (negative) input.

IKBI5 — Keyboard input 5.

P0.6/CMP1/

KBI6 20 16 I/O P0.6 — Port 0 bit 6.

OCMP1 — Comparator 1 output.

IKBI6 — Keyboard input 6.

P0.7/T1/

KBI7 19 15 I/O P0.7 — Port 0 bit 7.

I/O T1 — Timer/counter 1 external count input or overflow output.

IKBI7 — Keyboard input 7.

Product data sheet Rev. 8 — 12 January 2011 8 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

P1.0 to P1.7 I/O, I [1] Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type,

except for three pins as noted below. During reset Port 1 latches are

configured in the input only mode with the internal pull-up disabled. The

operation of the configurable Port 1 pins as inputs and outputs depends

upon the port configuration selected. Ea ch of the configurable port pins

are programmed independently. Refer to Section 8.13.1 “Port

configurations” and Table 11 “Static characteristics” for details. P1.2 and

P1.3 are open drain when used as outputs. P1.5 is input only.

All pins have Schmitt trigger inputs.

Port 1 also provides various special functions as described below:

P1.0/TXD 18 14 I/O P1.0 — Port 1 bit 0.

OTXD — T ransmitter output for the serial port.

P1.1/RXD 17 13 I/O P1.1 — Port 1 bit 1.

IRXD — Receiver input for the serial port.

P1.2/T0/SCL 12 8 I/O P1.2 — Port 1 bit 2 (open-drain when used as outpu t).

I/O T0 — Timer/counter 0 external count input or overflow output (open-drain

when used as output).

I/O SCL — I2C serial clock input/output.

P1.3/INT0/

SDA 11 7 I/O P1.3 — Port 1 bit 3 (o pen-drain when used as output).

IINT0 — External interrupt 0 input.

I/O SDA — I2C serial data input/output.

P1.4/INT1 10 6 I P1.4 — Port 1 bit 4.

IINT1 — External interrupt 1 input.

P1.5/RST 62IP1.5 — Port 1 bit 5 (input only).

IRST — External reset input du ring power-on or if selected via UCFG1.

When functioning as a reset input, a LOW on this pin resets the

microcontroller, causing I/O ports and peripherals to take on their default

states, and the processor begins execution at address 0. Also used during

a power-on sequence to force ISP mode. When using an oscillator

frequency above 12 MHz, the re set input function of P1.5 must be

enabled. An external circuit is required to hold the device in reset at

power-up until VDD has reached its specified level. When system

power is removed VDD will fall below the minimum specified

operating voltage. When using an oscillator frequency above

12 MHz, in some applications, an external brownout detect circuit

may be required to hold the device in reset when VDD falls below the

minimum specified opera ting voltage.

P1.6/OCB 5 1 I/O P1.6 — Port 1 bit 6.

OOCB — Output Compare B. (P89LPC935/936)

P1.7/OCC/

AD00 428I/OP1.7 — Port 1 bit 7.

OOCC — Output Compare C. (P89LPC935/936)

IAD00 — ADC0 channel 0 analog input. (P89L PC935/936)

Table 4. Pin description …continued

Symbol Pin Type Description

TSSOP28,

PLCC28 HVQFN28

Product data sheet Rev. 8 — 12 January 2011 9 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

P2.0 to P2.7 I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type.

During reset Port 2 latches are configured in the input only mode with the

internal pull-up disabled. The operation of Port 2 pins as inputs and

outputs depends upon the port configuration selected. Each port pin is

configured independently. Refer to Section 8.13.1 “Port configurations”

and Table 11 “Static characteristics” for details.

All pins have Schmitt trigger inputs.

Port 2 also provides various special functions as described below:

P2.0/ICB/

DAC0/AD03 125I/OP2.0 — Port 2 bit 0.

IICB — Input Capture B. (P89LPC935/936)

IDAC0 — Digital-to-analog converter output.

IAD03 — ADC0 channel 3 analog input. (P89L PC935/936)

P2.1/OCD/

AD02 226I/OP2.1 — Port 2 bit 1.

OOCD — Output Compare D. (P89LPC935/936)

IAD02 — ADC0 channel 2 analog input. (P89L PC935/936)

P2.2/MOSI 13 9 I/O P2.2 — Port 2 bit 2.

I/O MOSI — SPI master out slave in. When configured as master, this pin is

output; when configured as slave, this pin is input.

P2.3/MISO 14 10 I/O P2.3 — Port 2 bit 3.

I/O MISO — When configured as master , this pin is input, when configured as

slave, this pin is output.

P2.4/SS 15 11 I/O P2.4 — Port 2 bit 4.

ISS — SPI Slave select.

P2.5/

SPICLK 16 12 I/O P2.5 — Port 2 bit 5.

I/O SPICLK — SPI clock. When configured as master , this pin is output; when

configured as slave, this pin is input.

P2.6/OCA 27 23 I/O P2.6 — Port 2 bit 6.

OOCA — Output Compare A. (P89LPC935/936)

P2.7/ICA 28 24 I/O P2.7 — Port 2 bit 7.

IICA — Input Capture A. (P89LPC935/936)

Table 4. Pin description …continued

Symbol Pin Type Description

TSSOP28,

PLCC28 HVQFN28

Product data sheet Rev. 8 — 12 Ja nuary 2011 10 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

[1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.

P3.0 to P3.1 I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type.

During reset Port 3 latches are configured in the input only mode with the

internal pull-up disabled. The operation of Port 3 pins as inputs and

outputs depends upon the port configuration selected. Each port pin is

configured independently. Refer to Section 8.13.1 “Port configurations”

and Table 11 “Static characteristics” for details.

All pins have Schmitt trigger inputs.

Port 3 also provides various special functions as described below:

P3.0/XTAL2/

CLKOUT 95I/OP3.0 — Port 3 bit 0.

OXTAL2 — Output from the oscillator amplifier (when a crystal oscillator

option is selected via the flash configuration.

OCLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -

TRIM.6). It can be used if the CPU clock is the internal RC oscillator,

watchdog oscillator or external clock input, except when XTAL1/XTAL2

are used to generate clock source for the RTC/system timer.

P3.1/XTAL1 8 4 I/O P3.1 — Port 3 bit 1.

IXTAL1 — Input to the oscillator circuit and internal clock generator circuits

(when selected via the flash configuration). It can be a port pin if internal

RC oscillator or watchdog oscillator is used as the CPU clock source, and

if XTAL1/XTAL2 are not used to generate the clock for the RTC/system

timer.

VSS 73IGround: 0 V reference.

VDD 21 17 I Power supply: This is the power supply voltage for normal operatio n as

well as Idle and Power-down modes.

Table 4. Pin description …continued

Symbol Pin Type Description

TSSOP28,

PLCC28 HVQFN28

Product data sheet Rev. 8 — 12 January 2011 11 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

7. Logic symbols

Fig 6. P89LPC933/934 logic symbol

VDD VSS

PORT 0

PORT 3

TXD

RXD

INT0

INT1

RST

SCL

SDA

002aab077

CMP2

CIN2B

CIN2A

CIN1B

CIN1A

CMPREF

CMP1

XTAL2

XTAL1

KBI0

KBI1

KBI2

KBI3

KBI4

KBI5

KBI6

KBI7

DAC1

DAC0

MOSI

MISO

SPICLK

AD10

AD11

AD12

AD13 PORT 1

PORT 2

P89LPC933

P89LPC934

CLKOUT

Fig 7. P89LPC935/936 logic symbol

VDD VSS

PORT 0

PORT 3

TXD

RXD

INT0

INT1

RST

SCL

SDA

002aab078

CMP2

CIN2B

CIN2A

CIN1B

CIN1A

CMPREF

CMP1

XTAL2

XTAL1

KBI0

KBI1

KBI2

KBI3

KBI4

KBI5

KBI6

KBI7

DAC1

MOSI

MISO

SPICLK

AD10

AD11

AD12

AD13

AD01

PORT 1

PORT 2

P89LPC935

P89LPC936

OCB

OCC

ICB

OCD

OCA

ICA

AD00

AD03

AD02

DAC0

CLKOUT

Product data sheet Rev. 8 — 12 Ja nuary 2011 12 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8. Functional description

Remark: Please refer to the P89LPC933/934/935/936 User manual for a more detailed

functional description.

8.1 Special function registers

Remark: SFR accesses are restricted in the following ways:

•User must not attempt to access any SFR locations not defined.

•Accesses to any define d SFR locations m ust be strictly for th e functions for the SFRs.

•SFR bits labeled ‘-’, logic 0 or logic 1 can only be written and read as follows:

–‘-’ Unless otherwise specified, must be written with logic 0, but can return any

value when read ( even if it was written with logic 0). It is a reserved bit and may be

used in future derivatives.

–Logic 0 must be written with logic 0, and will return a logic 0 when read.

–Logic 1 must be written with logic 1, and will return a logic 1 when read.

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Product data sheet Rev. 8 — 12 January 2011 13 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

Table 5. Special function registers - P89LPC933/934

* indicates SFRs that are bit addressable.

Name Description SFR

addr. Bit functions and addresses Reset value

MSB LSB Hex Binary

Bit addressE7E6E5E4E3E2E1E0

ACC* Accumulator E0H 00 0000 0000

ADCON0A/D control register0 8EH-----ENADC0--0000000000

ADCON1 A/D control register 1 97H ENBI1 ENADCI

1TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10 00 0000 0000

ADINSA/D input select A3HADI13ADI12ADI11ADI10----0000000000

ADMODAA/D mode registerA C0HBNDI1BURST1SCC1SCAN1----0000000000

ADMODB A/D mode register B A1H CLK2 CLK1 CLK0 - ENDAC1 ENDAC0 BSA1 - 00 000x 0000

AD0DAT3 A/D_0 data register 3 F 4H 00 0000 0000

AD1BH A/D_1 boundary high register C4H FF 1111 1111

AD1BL A/D_1 boundary low register BCH 00 0000 0000

AD1DAT0 A/D_1 data register 0 D5H 00 0000 0000

AD1DAT1 A/D_1 data register 1 D6H 00 0000 0000

AD1DAT2 A/D_1 data register 2 D7H 00 0000 0000

AD1DAT3 A/D_1 data register 3 F 5H 00 0000 0000

AUXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENT0 SRST 0 - DPS 00[1] 0000 00x0

Bit addressF7F6F5F4F3F2F1F0

B* B register F0H 00 0000 0000

BRGR0 Baud rate generator rate low BEH 00[2] 0000 0000

BRGR1 Baud rate generator rate high BFH 00[1][2] 0000 0000

BRGCONBaud rate generator controlBDH------SBRGSBRGEN00

[2] xxxx xx00

CMP1 Comparator 1 control register ACH - - CE1 CP1 CN1 OE1 CO1 CMF1 00[1] xx00 0000

CMP2 Comparator 2 control register ADH - - CE2 CP2 CN2 OE2 CO2 CMF2 00[1] xx00 0000

DIVM CPU clock divide-by-M

control 95H 00 0000 0000

DPTR Data pointer (2 bytes)

DPH Data pointe r hi gh 8 3H 00 0000 0000

DPL Data poin te r lo w 82H 00 0000 0000

FMADRH Program flash address high E7H 00 0000 0000

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Product data sheet Rev. 8 — 12 January 2011 14 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

FMADRL Program flash address low E6H 00 0000 0000

FMCON Program flash control (Read) E4H BUSY - - - HVA HVE SV OI 70 0111 0000

Program flash control (Write) E4H FMCMD.

7FMCMD.

6FMCMD.

5FMCMD.

4FMCMD.

3FMCMD.

2FMCMD.

1FMCMD.

FMDATA Program flash data E5H 00 0000 0000

I2ADR I2C slave address register DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC 00 0000 0000

Bit addressDFDEDDDCDBDAD9D8

I2CON* I2C control register D8H - I2EN STA STO SI AA - CRSEL 00 x000 00x0

I2DAT I2C data register DAH

I2SCLH Serial clock generator/SCL

duty cycle register high DDH 00 0000 0000

I2SCLL Serial clock generator/SCL

duty cycle register low DCH 00 0000 0000

I2STAT I2C status register D9H STA.4 STA.3 STA.2 STA.1 STA.0 0 0 0 F8 1111 1000

ICRAH Input capture A register high ABH 00 0000 0000

ICRAL Inpu t capture A register low AAH 00 0000 0000

ICRBH Input capture B register high AF H 00 0000 0000

ICRBL Inpu t capture B register low AEH 00 0000 0000

Bit addressAFAEADACABAAA9A8

IEN0* Interrupt enable 0 A8H EA EWD RT EBO ES/ESR ET1 EX1 ET0 EX0 00 0000 0000

Bit addressEFEEEDECEBEAE9E8

IEN1* Interrupt enable 1 E8H EAD EST - - ESPI EC EKBI EI2C 00[3] 00x0 0000

Bit addressBFBEBDBCBBBAB9B8

IP0* Interrupt priority 0 B8H - PWDRT PBO PS/PSR PT1 PX1 PT0 PX0 00[3] x000 0000

IP0H Interrupt priority 0 high B7H - PWD RT

HPBOH PSH/

PSRH PT1H PX1H PT0H PX0H 00[3] x000 0000

Bit address FF FE FD FC FB FA F9 F8

IP1* Interrupt priority 1 F8H PAD PST - - PSPI PC PKBI PI2C 00[3] 00x0 0000

IP1H Interrupt priority 1 high F7H PADH PSTH - - PSPIH PCH PKBIH PI2CH 00[3] 00x0 0000

Table 5. Special function registers - P89LPC933/934 …continued

* indicates SFRs that are bit addressable.

Name Description SFR

addr. Bit functions and addresses Reset value

MSB LSB Hex Binary

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Product data sheet Rev. 8 — 12 January 2011 15 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

KBCONKeypad control register94H------PATN

_SEL KBIF 00[3] xxxx xx00

KBMASK Keypad interrupt mask

KBPATN Keypad pattern register 93H FF 1111 1111

Bit address8786858483828180

P0* Port 0 80H T1/KB7 CMP1

/KB6 CMPREF

/KB5 CIN1A

/KB4 CIN1B

/KB3 CIN2A

/KB2 CIN2B

/KB1 CMP2

/KB0 [3]

Bit address9796959493929190

P1* Port 1 90H - - RST INT1 INT0/

SDA T0/SCL RXD TXD [3]

Bit addressA7A6A5A4A3A2A1A0

P2* Port 2 A0H - - SPICLK SS MISO MOSI - - [3]

Bit addressB7B6B5B4B3B2B1B0

P3*Port3 B0H------XTAL1XTAL2 [3]

P0M1 Port 0 output mode 1 84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF[3] 1111 1111

P0M2 Port 0 output mode 2 85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00[3] 0000 0000

P1M1 Port 1 output mode 1 91H (P1M1.7) (P1M1.6) - (P1M1.4) (P1M1.3) (P1M1.2)(P1M1.1)(P1M1.0)D3

[3] 11x1 xx11

P1M2 Port 1 output mode 2 92H (P1M2.7) (P1M2.6) - (P1M2.4) (P1M2.3) (P1M2.2)(P1M2.1)(P1M2.0)00

[3] 00x0 xx00

P2M1 Port 2 output mode 1 A4H (P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0) FF[3] 1111 1111

P2M2 Port 2 output mode 2 A5H (P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0) 00[3] 0000 0000

P3M1Port3 output mode1 B1H------(P3M1.1)(P3M1.0)03

[3] xxxx xx11

P3M2Port3 output mode2 B2H------(P3M2.1)(P3M2.0)00

[3] xxxx xx00

PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 0000 0000

PCONA Power control register A B5H RTCPD - VCPD ADPD I2PD SPPD SPD - 00[3] 0000 0000

Bit addressD7D6D5D4D3D2D1D0

PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 0000 0000

PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 xx00 000x

RSTSRC Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX [4]

RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60[3][5] 011x xx00

Table 5. Special function registers - P89LPC933/934 …continued

* indicates SFRs that are bit addressable.

Name Description SFR

addr. Bit functions and addresses Reset value

MSB LSB Hex Binary

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Product data sheet Rev. 8 — 12 January 2011 16 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

RTCH Real-time clock register high D2H 00[5] 0000 0000

RTCL Real-time clock register low D3H 00[5] 0000 0000

SADDR Serial port address register A9H 00 0000 0000

SADEN Serial port addre ss enable B9H 00 0000 0000

SBUF Serial Port data buf f er regist er 99H xx xxxx xxxx

Bit address9F9E9D9C9B9A9998

SCON* Seri al port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000

SSTAT Serial port extende d status

SP Stack poi n te r 81H 07 0000 0111

SPCTL SPI control register E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 04 0000 0100

SPSTAT SPI status register E1H SPIF WCOL - - ----0000xxxxxx

SPDAT SPI data register E3H 00 0000 0000

TAMOD Timer 0 and 1 auxiliary mode 8FH - - - T1M2 - - - T0M2 00 xxx0 xxx0

Bit address8F8E8D8C8B8A8988

TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 0000 0000

TH0 Timer 0 high 8CH 00 0000 0000

TH1 Timer 1 high 8DH 00 0000 0000

TL0 Timer 0 low 8AH 00 0000 0000

TL1 Timer 1 low 8BH 00 0000 0000

TMOD Timer 0 and 1 mode 89H T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 0 000 0000

TRIM Internal oscillator trim register 96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 [6] [5]

WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK [7] [5]

Table 5. Special function registers - P89LPC933/934 …continued

* indicates SFRs that are bit addressable.

Name Description SFR

addr. Bit functions and addresses Reset value

MSB LSB Hex Binary

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Product data sheet Rev. 8 — 12 January 2011 17 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

[1] Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other

purposes in future derivatives. The reset values shown for these bits are logic 0s although they are unknown when read.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[3] All ports are in input only (high-impedance) state after power-up.

[4] The RSTSRC register reflects the cause of the P89LPC933/934/935/936 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset

value is xx11 0000.

[5] The only reset source that affects these SFRs is power-on reset.

[6] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[7] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

Other resets will not affect WDTOF.

WDL Watchdog load C1H FF 1111 1111

WFEED1 Watchdog feed 1 C2H

WFEED2 Watchdog feed 2 C3H

Table 5. Special function registers - P89LPC933/934 …continued

* indicates SFRs that are bit addressable.

Name Description SFR

addr. Bit functions and addresses Reset value

MSB LSB Hex Binary

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Product data sheet Rev. 8 — 12 January 2011 18 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

Table 6. Special function registers - P89LPC935/936

* indicates SFRs that are bit addressable.

Name Description SFR

addr. Bit functions and addresses Reset value

MSB LSB Hex Binary

Bit addressE7E6E5E4E3E2E1E0

ACC* Accumulator E0H 00 0000 0000

ADCON0 A/D control register 0 8EH ENBI0 ENADCI

0TMM0 EDGE0 ADCI0 ENADC0 ADCS01 ADCS00 00 0000 0000

ADCON1 A/D control register 1 97H ENBI1 ENADCI

1TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10 00 0000 0000

ADINS A/D inpu t select A3H ADI13 ADI12 ADI11 ADI10 ADI03 ADI02 ADI01 ADI00 00 0000 0000

ADMODA A/D mode regi ster A C0H BNDI1 BURST1 SCC1 SCAN1 BNDI0 BURST0 SCC0 SCAN0 00 0000 0000

ADMODB A/D mode register B A1H CLK2 CLK1 CLK0 - END AC1 ENDAC0 BSA1 BSA0 00 000x 0000

AD0BH A/D_0 boundary high register BBH FF 1111 1111

AD0BL A/D_0 boundary low register A6H 00 0000 0000

AD0DAT0 A/D_0 data register 0 C5H 00 0000 0000

AD0DAT1 A/D_0 data register 1 C6H 00 0000 0000

AD0DAT2 A/D_0 data register 2 C7H 00 0000 0000

AD0DAT3 A/D_0 data register 3 F 4H 00 0000 0000

AD1BH A/D_1 boundary high register C4H FF 1111 1111

AD1BL A/D_1 boundary low register BCH 00 0000 0000

AD1DAT0 A/D_1 data register 0 D5H 00 0000 0000

AD1DAT1 A/D_1 data register 1 D6H 00 0000 0000

AD1DAT2 A/D_1 data register 2 D7H 00 0000 0000

AD1DAT3 A/D_1 data register 3 F 5H 00 0000 0000

AUXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENT0 SRST 0 - DPS 00 0000 00x0

Bit addressF7F6F5F4F3F2F1F0

B* B register F0H 00 0000 0000

BRGR0[2] Baud rate generator rate low BEH 00 0000 0000

BRGR1[2] Baud rate generator rate high BFH 00 0000 0000

BRGCONBaud rate generator controlBDH------SBRGSBRGEN00

[2] xxxx xx00

CCCRA Capture compare A control

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Product data sheet Rev. 8 — 12 January 2011 19 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

CCCRB Capture compare B control

CCCRC Capture compare C control

CCCRD Capture compare D control

CMP1 Comparator 1 control register ACH - - CE1 CP1 CN1 OE1 CO1 CMF1 00[3] xx00 0000

CMP2 Comparator 2 control register ADH - - CE2 CP2 CN2 OE2 CO2 CMF2 00[3] xx00 0000

DEECON Data EEPROM control

DEEDAT Data EEPROM data register F2H 00 0000 0000

DEEADR Data EEPROM address

DIVM CPU clock divide-by-M

control 95H 00 0000 0000

DPTR Data pointer (2 bytes)

DPH Data pointe r hi gh 8 3H 00 0000 0000

DPL Data poin te r lo w 82H 00 0000 0000

FMADRH Program flash address high E7H 00 0000 0000

FMADRL Program flash address low E6H 00 0000 0000

FMCON Program flash control (Read) E4H BUSY - - - HVA HVE SV OI 70 0111 0000

Program flash control (Write) E4H FMCMD.

7FMCMD.

6FMCMD.

5FMCMD.

4FMCMD.

3FMCMD.

2FMCMD.

1FMCMD.

FMDATA Program flash data E5H 00 0000 0000

I2ADR I2C slave address register DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC 00 0000 0000

Bit addressDFDEDDDCDBDAD9D8

I2CON* I2C control register D8H - I2EN STA STO SI AA - CRSEL 00 x000 00x0

I2DAT I2C data register DAH

I2SCLH Serial clock generator/SCL

duty cycle register high DDH 00 0000 0000

Table 6. Special function registers - P89LPC935/936 …continued

* indicates SFRs that are bit addressable.

Name Description SFR

addr. Bit functions and addresses Reset value

MSB LSB Hex Binary

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Product data sheet Rev. 8 — 12 January 2011 20 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

I2SCLL Serial clock generator/SCL

duty cycle register low DCH 00 0000 0000

I2STAT I2C status register D9H STA.4 STA.3 STA.2 STA.1 STA.0 0 0 0 F8 1111 1000

ICRAH Input capture A register high ABH 00 0000 0000

ICRAL Inpu t capture A register low AAH 00 0000 0000

ICRBH Input capture B register high AF H 00 0000 0000

ICRBL Inpu t capture B register low AEH 00 0000 0000

Bit addressAFAEADACABAAA9A8

IEN0* Interrupt enable 0 A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0 EX0 00 0000 00 00

Bit addressEFEEEDECEBEAE9E8

IEN1* Interrupt enable 1 E8H EADEE EST - ECCU ESPI EC EKBI EI2C 00[3] 00x0 0000

Bit addressBFBEBDBCBBBAB9B8

IP0* Interrupt priority 0 B8H - PWDRT PBO PS/PSR PT1 PX1 PT0 PX0 00[3] x000 0000

IP0H Interrupt priority 0 high B7H - PWD RT

HPBOH PSH/

PSRH PT1H PX1H PT0H PX0H 00[3] x000 0000

Bit address FF FE FD FC FB FA F9 F8

IP1* Interrupt priority 1 F8H PADEE PST - PCCU PSPI PC PKBI PI2C 00[3] 00x0 0000

IP1H Interrupt priority 1 high F7H PAEEH PSTH - PCCUH PSPIH PCH PKBIH PI2CH 00[3] 00x0 0000

KBCONKeypad control register94H------PATN

_SEL KBIF 00[3] xxxx xx00

KBMASK Keypad interrupt mask

KBPATN Keypad pattern register 93H FF 1111 1111

OCRAH Output compare A register

high EFH 00 0000 0000

OCRAL Output compare A register

low EEH 00 0000 0000

OCRBH Output compare B register

high FBH 00 0000 0000

OCRBL Output compare B register

low FAH 00 0000 0000

Table 6. Special function registers - P89LPC935/936 …continued

* indicates SFRs that are bit addressable.

Name Description SFR

addr. Bit functions and addresses Reset value

MSB LSB Hex Binary

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Product data sheet Rev. 8 — 12 January 2011 21 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

OCRCH Output compare C register

high FDH 00 0000 0000

OCRCL Output compare C register

low FCH 00 0000 0000

OCRDH Output compare D register

high FFH 00 0000 0000

OCRDL Output compare D register

low FEH 00 0000 0000

Bit address8786858483828180

P0* Port 0 80H T1/KB7 CMP1

/KB6 CMPREF

/KB5 CIN1A

/KB4 CIN1B

/KB3 CIN2A

/KB2 CIN2B

/KB1 CMP2

/KB0 [3]

Bit address9796959493929190

P1* Port 1 90H OCC OCB RST INT1 INT0/

SDA T0/SCL RXD TXD [3]

Bit addressA7A6A5A4A3A2A1A0

P2* Port 2 A0H ICA OCA SPICLK SS MISO MOSI OCD ICB [3]

Bit addressB7B6B5B4B3B2B1B0

P3*Port3 B0H------XTAL1XTAL2 [3]

P0M1 Port 0 output mode 1 84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF[3] 1111 1111

P0M2 Port 0 output mode 2 85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00[3] 0000 0000

P1M1 Port 1 output mode 1 91H (P1M1.7) (P1M1.6) - (P1M1.4) (P1M1.3) (P1M1.2)(P1M1.1)(P1M1.0)D3

[3] 11x1 xx11

P1M2 Port 1 output mode 2 92H (P1M2.7) (P1M2.6) - (P1M2.4) (P1M2.3) (P1M2.2)(P1M2.1)(P1M2.0)00

[3] 00x0 xx00

P2M1 Port 2 output mode 1 A4H (P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0) FF[3] 1111 1111

P2M2 Port 2 output mode 2 A5H (P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0) 00[3] 0000 0000

P3M1Port3 output mode1 B1H------(P3M1.1)(P3M1.0)03

[3] xxxx xx11

P3M2Port3 output mode2 B2H------(P3M2.1)(P3M2.0)00

[3] xxxx xx00

PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 0000 0000

PCONA Power control register A B 5H RTCPD DEEPD VCPD ADPD I2PD SPPD SPD CCUPD 00[3] 0000 0000

Bit addressD7D6D5D4D3D2D1D0

PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 0000 0000

PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 xx00 000x

Table 6. Special function registers - P89LPC935/936 …continued

* indicates SFRs that are bit addressable.

Name Description SFR

addr. Bit functions and addresses Reset value

MSB LSB Hex Binary

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Product data sheet Rev. 8 — 12 January 2011 22 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

RSTSRC Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX [4]

RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60[3][5] 011x xx00

RTCH Real-time clock register high D2H 00[5] 0000 0000

RTCL Real-time clock register low D3H 00[5] 0000 0000

SADDR Serial port address register A9H 00 0000 0000

SADEN Serial port addre ss enable B9H 00 0000 0000

SBUF Serial Port data buf f er regist er 99H xx xxxx xxxx

Bit address9F9E9D9C9B9A9998

SCON* Seri al port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000

SSTAT Serial port extende d status

SP Stack poi n te r 81H 07 0000 0111

SPCTL SPI control register E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 04 0000 0100

SPSTAT SPI status register E1H SPIF WCOL - - ----0000xxxxxx

SPDAT SPI data register E3H 00 0000 0000

TAMOD Timer 0 and 1 auxiliary mode 8FH - - - T1M2 - - - T0M2 00 xxx0 xxx0

Bit address8F8E8D8C8B8A8988

TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 0000 0000

TCR20* CCU control register 0 C8H PLEEN HLTRN HLTEN ALTCD ALTAB TDIR2 TMOD21 TMOD20 00 0000 0000

TCR21 CCU control register 1 F9H TCOU2 - - - PLLDV.3 PLLDV.2 PLL DV.1 PLLDV.0 00 0xxx 0000

TH0 Timer 0 high 8CH 00 0000 0000

TH1 Timer 1 high 8DH 00 0000 0000

TH2 CCU timer high CDH 00 0000 0000

TICR2 CCU interrupt control register C9H TOIE2 TOCIE2

DTOCIE2

CTOCIE2B TOCIE2A - TICIE2B TICIE2A 00 0000 0x00

TIFR2 CCU interrupt flag register E9H T OIF2 TOCF2D TOCF2C TOCF2B TOCF2A - TICF2B TICF2A 00 0000 0x00

TISE2 CCU interrupt status encode

2ENCINT.

1ENCINT.

000 xxxx x000

TL0 Timer 0 low 8AH 00 0000 0000

TL1 Timer 1 low 8BH 00 0000 0000

Table 6. Special function registers - P89LPC935/936 …continued

* indicates SFRs that are bit addressable.

Name Description SFR

addr. Bit functions and addresses Reset value

MSB LSB Hex Binary

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 8 — 12 January 2011 23 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

[1] Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other

purposes in future derivatives. The reset values shown for these bits are logic 0s although they are unknown when read.

[2] All ports are in input only (high-impedance) state after power-up.

[3] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[4] The RSTSRC register reflects the cause of the P89LPC933/934/935/936 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset

value is xx11 0000.

[5] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

Other resets will not affect WDTOF.

[6] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[7] The only reset source that affects these SFRs is power-on reset.

TL2 CCU timer low CCH 00 0000 0000

TMOD Timer 0 and 1 mode 89H T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 0 000 0000

TOR2H CCU reload register high CFH 00 0000 0000

TOR2L CCU reload register low CEH 00 0000 0000

TPCR2HPrescaler control register highCBH------TPCR2H.

1TPCR2H.

000 xxxx xx00

TPCR2L Prescal er contro l register low CAH TPCR2L.

7TPCR2L.

6TPCR2L.

5TPCR2L.

4TPCR2L.

3TPCR2L.

2TPCR2L.

1TPCR2L.

000 0000 0000

TRIM Internal oscillator trim register 96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 [6] [5]

WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK [7] [5]

WDL Watchdog load C1H FF 1111 1111

WFEED1 Watchdog feed 1 C2H

WFEED2 Watchdog feed 2 C3H

Table 6. Special function registers - P89LPC935/936 …continued

* indicates SFRs that are bit addressable.

Name Description SFR

addr. Bit functions and addresses Reset value

MSB LSB Hex Binary

Product data sheet Rev. 8 — 12 Ja nuary 2011 24 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.2 Enhanced CPU

The P89LPC933/934/935/936 uses an enhanced 80C51 CPU which runs at six times the

speed of st andard 80C51 de vices. A machine cycle consist s of two CPU clock cycles, and

most instructions execute in one or two machine cycles.

8.3 Clocks

8.3.1 Clock definitions

The P89LPC933/934/935/936 device has several internal clocks as defined below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock

sources (see Figure 8) and can also be o ptionally divided to a slower frequency (see

Section 8.8 “CCLK modification: DIVM register”).

Remark: fosc is defined as the OSCCLK frequency.

CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per ma ch ine

cycle, and most instr uctions are executed in one to two machine cycles (two o r four CCLK

cycles).

RCCLK — The internal 7.373 MHz RC oscillator output.

PCLK — Clock for the various peripheral devices and is CCLK⁄2.

8.3.2 CPU clock (OSCCLK)

The P89LPC933/934/935/936 provides several user-selectable oscillator options in

generating the CPU clock. This allo ws optimization for a range of needs fr om high

precision to lowest possible cost. These options are co nfigured when the flash is

programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an

oscillator using an external crystal, or an external clock source. The crystal oscillator can

be optimized for low, medium, or hig h frequ ency crystals covering a ra nge from 2 0 kHz to

18 MHz.

8.3.3 Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic

resonators are also supported in this configuration.

8.3.4 Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic

resonators are also supported in this configuration.

8.3.5 High speed oscillator option

This option supports an external cryst al in the range of 4 MHz to 18 MHz. Ceramic

resonators are also supported in this configuration.

8.3.6 Clock output

The P89LPC933/934/935/936 supports a user-selectable clock output function on the

XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if

another clock source has been selected (on-chip RC oscillator, watchdog oscillator,

Product data sheet Rev. 8 — 12 Ja nuary 2011 25 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

external clock input on X1) and if the RTC is not using the crystal oscillator as its clock

source. This allows external devices to synchronize to the P89LPC933/934 /935/936. Th is

output is enabled by the ENCLK bit in the TRIM register.

The frequency of this clock output is 1⁄2 that of the CCLK. If the clock output is not needed

in Idle mode, it may be turned off prior to entering Idle, saving additional power.

8.4 On-chip RC oscillator option

The P89LPC933/934/935/936 has a 6-bit TRIM register that can be used to tune the

frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory

preprogrammed value to adjust the oscillator frequency to 7.373 MHz ±1 % at room

temperature. End-user applications can write to the TRIM register to adjust the on-chip

RC oscillator to other frequencies.

8.5 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator

can be used to save power when a high clock frequency is not needed.

8.6 External clock input option

In this configuration, the processor clock is derived from an external source driving the

P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XTAL2 pin may be

used as a standard port pin or a clock output. When using an oscillator frequency

above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit

is required to hold the device in reset at power-up until VDD has reached its

specified level. When system power is removed VDD will fall below the minimum

specified operating voltage. When using an oscillator frequency above 12 MHz, in

some applications, an external brownout detect circuit may be required to hold the

device in reset when VDD falls below the minimum specified operating voltage.

Product data sheet Rev. 8 — 12 Ja nuary 2011 26 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

Fig 8. Block diagram of oscillator control

÷2

002aab079

RTC

ADC1

ADC0

(P89LPC935/936)

CPU

WDT

DIVM CCLK

UART

OSCCLK

I2C-BUS

PCLK

TIMER 0 AND

TIMER 1

HIGH FREQUENCY

MEDIUM FREQUENCY

LOW FREQUENCY

XTAL1

XTAL2

OSCILLATOR

WATCHDOG

OSCILLATOR

(7.3728 MHz ±1 %) PCLK

RCCLK

SPI

CCU

(P89LPC935/936)

32 × PLL

(400 kHz +30 % −20 %)

Product data sheet Rev. 8 — 12 Ja nuary 2011 27 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.7 CCLK wake-up delay

The P89LPC933/934/935/936 has an internal wake-up timer that delays the clock until it

stabilizes depending on the clock source used. If the clock source is any of the three

crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles

plus 60 μsto100μs. If the clock source is either the internal RC oscillator, watchdog

oscillator, or external clock, the delay is 224 OSCCLK cycles plus 60 μs to 100 μs.

8.8 CCLK modification: DIVM register

The OSCCLK frequency can be divided down up to 510 times by configuring a dividing

CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can

retain the ability to respond to events that would not exit Idle mode by executing its normal

program at a lower rate. This can also allow bypassing the oscillator start-up time in cases

where Power-down mode would otherwise be used. The value of DIVM may be changed

by the program at any time without interrupting code execution.

8.9 Low power select

The P89LPC933/934/935/936 is designed to run at 18 MHz (CCLK) maximum. However,

if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower

the power consumption further. On any reset, CLKLP is logic 0 allowing highest

performance access. This bit can then be set in software if CCLK is running at 8 MHz or

slower.

8.10 Memory organization

The various P89LPC933/934/935/936 memory spaces are as follows:

•DATA

128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect

addressing, using instructions other than MOVX and MOVC. All or part of the Stack

may be in this area.

•IDATA

Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via

indirect addressing using instructions other th an MOVX and MOVC. All or part of the

Stack may be in this area. This area includes the DATA area and the 128 bytes

immediately ab o ve it.

•SFR

Selected CPU registers and peripheral control and status registers, accessible only

via direct addressing.

•XDATA (P89LPC935/936)

‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space

addressed via the MOVX instruction using the SPTR, R0, or R1. All or part of this

space could be implemented on-chip. The P89LPC935/936 has 512 bytes of on-chip

XDATA memory.

Product data sheet Rev. 8 — 12 Ja nuary 2011 28 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

•CODE

64 kB of code memory space, accessed as part of program execution an d via the

MOVC instruction. The P89LPC933/934/935/936 have 4 KB/8 kB/16 kB of on-chip

Code memory.

The P89LPC935/936 also has 512 bytes of on-chip data EEPROM that is accessed via

SFRs (see Section 8.27 “Data EEPROM (P89LPC935/936)”).

8.11 Data RAM arrangement

The 768 bytes of on-chip RAM are organized as shown in Table 7.

8.12 Interrupts

The P89LPC933/934/935/936 uses a four priority level interrupt structure. This allows

great flexibility in controlling the handling of the many interrupt sources. The

P89LPC933/934/935/936 supports 15 interrupt sources: external inter rupts 0 and 1,

timers 0 and 1, seri al port T x, serial po rt Rx, combined seria l port Rx/Tx, brownout detect,

watchdog/Real-Time clock, I2C-bus, keyboard, comparators 1 and 2, SPI, CCU, data

EEPROM write/ADC completion.

Each interrupt source can be individually enable d or disabled by setting or clearing a bit in

the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global

disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by

setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An

interrupt service routine in progress can be interrupted by a higher priority interrupt, but

not by another interrupt of the same or lower prior ity. The highest priority interrupt service

cannot be interrupted by any other interrupt source. If two requests of different priority

levels are pending at the start of an in struction, the request of hig he r pr ior ity level is

serviced.

If requests of the same priority level are pending at the start of an instruction, an internal

polling sequence determines which request is serviced. This is called the arbitration

ranking.

Remark: The arbitration ranking is on ly used to resolve pending requests of the same

priority level.

8.12.1 External interrupt inputs

The P89LPC933/934/935/936 has two external interrupt inputs as well as the Keypad

Interrupt function. The two interrupt inputs are identical to those present on the standard

80C51 microcontrollers.

Table 7. On-chip data memory usages

Type Data RAM Size (bytes)

DATA Memory that can be addressed directly and indire ctly 128

IDATA M emory that can be addressed indirectly 256

XDATA Auxiliary (‘External Data’) on-chip memory that is accessed

using the MOVX instructions (P89LPC935/936) 512

Product data sheet Rev. 8 — 12 Ja nuary 2011 29 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

These external interrupts can be programmed to be level-triggered or edge-triggered by

setting or clearing bit IT1 or IT0 in register TCON.

In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle

and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an

interrupt reque st.

If an external interrupt is enabled when the P89LPC933/934/935/936 is put into

Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume

operation. Refer to Section 8.15 “Power reduction modes” for details.

(1) See Section 8.19 “CCU (P89LPC935/936)”

(2) P89LPC935/936

Fig 9. Interrupt sources, interrupt enables, and po wer-down wake-up sources

002aab081

IE0

EX0

IE1

EX1

BOF

EBO

KBIF

EKBI

interrupt

to CPU

wake-up

(if in power-down)

EWDRT

CMF2

CMF1

EA (IE0.7)

TF1

ET1

TI & RI/RI

ES/ESR

EST

EI2C

SPIF

ESPI

RTCF

ERTC

(RTCCON.1)

WDOVF

TF0

ET0

any CCU interrupt(1)

ECCU

ENADCI0(2)

ADCI0(2)

ENADCI1

ADCI1

ENBI0(2)

BNDI0(2)

ENBI1

BNDI1

EEIF(2)

EADEE (P89LPC935)

EAD (P89LPC933/934)

Product data sheet Rev. 8 — 12 Ja nuary 2011 30 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.13 I/O ports

The P89LPC933/934/935/936 has four I/O ports: Port 0, Port 1, Port 2, and Port 3.

Ports 0, 1 and 2 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins

available depends upon the clock and reset options chosen, as shown in Table 8.

[1] Required for operation above 12 MHz.

8.13.1 Port configurations

All but three I/O port pins on the P89 LPC933/934/9 35/936 ma y be configured by sof twa re

to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51

port outputs), push-pull, open drain, and input-only. Two configuration registers for each

port select the output type for each port pin.

1. P1.5 (RST) can only be an input and cannot be configur ed.

2. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or

open-drain.

8.13.1.1 Quasi-bidirectional output configuration

Quasi-bidirectional output type can be used as both an input and output without the need

to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is

weakly driven, allowing an external device to pull the pin LOW. When the pin is driven

LOW, it is driven strongly and able to sink a fairly large current. These features are

somewhat similar to an open-dra in output except that ther e are three pull-up transistors in

the quasi-bid i re ctio nal ou tp ut th at serve different purpose s.

The P89LPC933/934/935/936 is a 3 V device, but the pins are 5 V-tolerant. In

quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current flowing

from the pin to VDD, causing extra power consumption. Therefore, applying 5 V in

quasi-bidirectional mode is discouraged.

A quasi-bidirectional port pin has a Schmitt trigger input that also has a glitch suppression

circuit.

8.13.1.2 Open-drain output configuration

The open-drain output configuratio n turns off all pull-ups and only drives the pull-down

transistor of the port driver when the port latch contains a logic 0. To be used as a logic

output, a port configured in this manner must have an external pull-up, typically a resistor

tied to VDD.

Table 8. Number of I/O pins available

Clock source Reset option Number of I/O pins

(28-pin package)

On-chip oscillator or watchdog

oscillator No external reset (except during

power-up) 26

External RST pin supported 25

External clock input No external reset (except during

power-up) 25

External RST pin supported[1] 24

Low/medium/high speed oscillator

(external crystal or resonator) No external reset (except during

power-up) 24

External RST pin supported[1] 23

Product data sheet Rev. 8 — 12 Ja nuary 2011 31 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

An open-drain port pin has a Schmitt trigger input that also has a glitch suppression

circuit.

8.13.1.3 Input-only configuration

The input-only port configuration has no output drivers. It is a Schmitt trigger input that

also has a glitch suppression circuit.

8.13.1.4 Push-p ull output configuration

The push-pull output configuration has the same pull-down structure as both the

open-drain and the quasi-bidirectional output modes, but provides a continuous strong

pull-up when the port latch contains a logic 1. The push-pull mode may be used when

more source current is needed from a port output. A push -pull port pin has a Schmitt

trigger input that also has a glitch suppression circuit.

8.13.2 Port 0 analog functions

The P89LPC933/934/9 35/936 incorporates two Analog Comparators. In order to give the

best analog function p erformance and to minimize power consumption, pins that are being

used for analog functions must have the digital outputs and digital inputs disabled.

Digital outputs are disabled by putting the port output into the Input-Only

(high-impedance) mode.

Digital inputs on Port 0 ma y be disab le d thro ug h th e use of th e PT0AD registe r, bits 1: 5.

On any reset, PT0AD[1:5] defaults to logic 0s to enable digital functions.

8.13.3 Additional port features

After power-up, all pins are in Input-Only mode.

Remark: Please note that this is different from the LPC76x series of devices.

•After power-up, all I/O pins except P1.5, may be configured by software.

•Pin P1.5 is input only. Pins P1.2 and P1.3 and are con figurable for eithe r input-on ly or

open-drain.

Every output on the P89LPC933/934/935/936 has been designed to sink typical LED

drive current. However, there is a maximum tot al output current for all ports which must

not be exceeded. Please refer to Table 11 “Static characteristics” for detailed

specifications.

All ports pins that can function a s an output ha ve slew rate controlled outputs to limit noise

generated by quickly switching output signals. The slew rate is factory-set to

approximately 10 ns rise and fall times.

8.14 Power monitoring functions

The P89LPC933/934/935/936 incorporates power monitoring functions designed to

prevent incorrect operation during initial power-up and power loss or reduction during

operation. This is accomplished with two hardware functions: Power-on detect and

brownout detect.

Product data sheet Rev. 8 — 12 Ja nuary 2011 32 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.14.1 Brownout detection

The brownout detect function determines if the power supply voltage drops below a

certain level. The default operation is for a brownout detection to cause a proc essor reset,

however it may alternatively be configured to gener ate an interrupt.

Brownout detection may be enabled or disabled in software.

If brownout detection is enabled the brownout condition occurs when VDD falls below the

brownout trip volt age, Vbo (see Table 11 “S tatic characteristics”), and is negated when VDD

rises above Vbo. If the P89LPC933/934/935/936 device is to operate with a power supply

that can be below 2.7 V, BOE should be lef t in the unprog rammed st at e so that the de vice

can operate at 2.4 V, otherwise continuous brownout r eset may prevent the device from

operating.

For correct activation of brownout detect, the VDD rise and fall times must be observed.

Please see Table 11 “Static characteristics” for specifications.

8.14.2 Power-on detection

The power-on dete ct has a function similar to the browno ut detect, but is designed to work

as power comes up initially, before the power supply voltage reaches a level where

brownout detect can work. The POF flag in the RST SRC register is set to indicate an

initial power-up condition. The POF flag will remain set until cleared by software.

8.15 Power reduction modes

The P89LPC933/934/935/936 supports three different power reduction modes. These

modes are Idle mode, Power-down mode, and total Po wer-down mode.

8.15.1 Idle mode

Idle mode leaves peripherals running in order to allow them to activate the proces sor

when an interrupt is generated. Any enabled in terrupt source or reset may terminate Idle

mode.

8.15.2 Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption. The

P89LPC933/934/935/936 exits Power-down mode via any reset, or certain interrupts. In

Power-down mode, the po wer supply voltage may be reduced to the RAM keep-alive

voltage VRAM. This retains the RAM co ntents at the point wh ere Power-down mode wa s

entered. SFR content s are no t guar anteed a f ter V DD has been lowe red to VDDR, therefore

it is highly recommended to wake-up the processor via reset in this case. VDD must be

raised to within the operating range before the Power-down mode is exited.

Some chip functions continue to operate and draw power during Power-down mode,

increasing the total power used during power-down. These include: brownout detect,

watchdog timer, Comparators (note that Comparators can be powered-down sep arately),

and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator

has been selected as the system clock and the RTC is enabled.

Product data sheet Rev. 8 — 12 Ja nuary 2011 33 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.15.3 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry an d

the voltage comparators are also disabled to conserve additional power. The internal RC

oscillator is disabled unless both the RC oscillator has been selected as the system clock

and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during

power-down, there will be high power consumption. Please use an external low frequency

clock to achieve low power with the RTC running during power-down.

8.16 Reset

The P1.5/RST pin can function as either a LOW-active reset input or as a digital input,

P1.5. The Reset Pin Enable (RPE) bit in UCFG1, when set to logic 1, ena bles the external

reset input function on P1.5. When cleared, P1.5 may be used as an input pin.

Remark: During a power-up sequence, the RPE selection is overridden and this pin will

always functions as a reset input. An external circuit connected to this pin should not

hold this pin LOW during a power-on se quence as this will keep the dev ice in reset.

After power-up this input will function either as an external reset input or as a digital input

as defined by the RPE bit. Only a power-up reset will temporarily override the selection

defined by RPE bit. Other sources of reset will not override the RPE bit. When this pin

functions as a reset input, an inte rnal pull-up resist ance is connected (see Table 11 “Static

characteristics”).

Reset can be triggered from the following sources:

•External reset pin (during power-up or if user configured via UCFG1).

•Power-on detect.

•Brownout detect.

•Watchdog timer.

•Software reset.

•UART break character detect reset.

For every reset source, there is a flag in the reset register, RSTSRC. The user can read

this register to determine the most recent reset source. These flag bits can be cleared in

software by writing a logic 0 to the corresponding bit. More than one flag bit may be set:

•During a power- on res et , bot h POF an d BOF ar e set but the ot he r fla g bits are

cleared.

•For any other reset, previously set flag bits that have no t been cleared will remain set.

8.16.1 Reset vector

Following reset, the P89LPC933/934/935/936 will fetch instructions from either address

0000H or the boot address. The boot address is formed by using the boot vector as the

high byte of the addres s and the low byte of the address = 00H.

The boot address will be used if a UART break reset occurs, or the non-volatile boot

status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see

P89LPC933/934/935/936 User manual). Otherwise, instructions will be fetched from

address 0000H.

Product data sheet Rev. 8 — 12 Ja nuary 2011 34 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.17 Timers/counters 0 and 1

The P89LPC933/934/935/936 has two general purpose counter/timers which are upward

compatible with the standard 80C5 1 Timer 0 an d Timer 1. Both can be configur ed to

operate either as timer s or event counter. An option to automatically toggle the T0 and/or

T1 pins upon timer overflow has been added.

In the ‘timer’ function, the register is incremented every machine cycle.

In the ‘counter’ function, the register is incremented in response to a 1-to-0 transition at its

corresponding external input pin, T0 or T1. In this function, the external input is sampled

once during every machine cycle.

Timer 0 and Timer 1 have five operating modes (modes 0, 1, 2, 3 and 6). Modes 0, 1, 2

and 6 are the same for both timers/counters. Mode 3 is different.

8.17.1 Mode 0

Putting either timer into Mode 0 makes it look like an 8048 timer, which is an 8-bit counter

with a divide-by-32 prescaler. In this mode, the timer register is configured as a 13-bit

8.17.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register ar e used.

8.17.3 Mode 2

Mode 2 configures the timer register as an 8-bit counter with automatic reload. Mode 2

operation is the same for Timer 0 and Timer 1.

8.17.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit

counters and is provided for applications that r equire an extra 8-bit time r. When Timer 1 is

in Mode 3 it can still be used by the serial port as a baud rate generator.

8.17.5 Mode 6

In this mode, the corresponding timer can be changed to a PWM with a full period of

256 timer clocks.

8.17.6 Timer overflow toggle output

Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer

overflow occurs. The same device pins that are used for the T0 and T1 count inputs are

also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first

timer overflow when this mode is turn ed on.

8.18 RTC/system timer

The P89LPC933/934 /935/936 has a simple R TC that allows a user to co ntinue running an

accurate timer while the rest of the device is powered-down. The RTC can be a wake-up

or an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler

and a 16-bit loadable down counter. When it reaches all logic 0s, the counter will be

reloaded again and the RTCF flag will be set. The clock source for this counter can be

either the CPU clock (CCLK) or the XTAL oscillator, provided that the XTAL oscillator is

Product data sheet Rev. 8 — 12 Ja nuary 2011 35 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

not being used as the CPU clock. If the XTAL oscillator is used as the CPU clock, then the

RTC will use CCLK as its clock source. Only power-on reset will reset the RTC and its

associated SFRs to the default state.

8.19 CCU (P89LPC935/936)

This unit features:

•A 16-bit timer with 16-bit reload on ove rflow.

•Selectable clock, with prescaler to divide clock source by any integral number

between 1 and 1024.

•Four compare/PWM outputs with selectable polarity.

•Symmetrical/asymmetrical PWM selection.

•Two capture inputs with event counter and digital noise rejection filter.

•Seven interrupts with common interrupt vector (one overflow, two capture,

four compare).

•Safe 16-bit read/write via shadow registers.

8.19.1 CCU clock

The CCU runs on the CCUCLK, which is either PCLK in basic timer mode, or the output of

a Phase-Locked Loop (PLL). The PLL is designed to use a clock source between 0 .5 MHz

to 1 MHz that is multiplied by 32 to produce a CCUCLK between 16 MHz and 32 MHz in

PWM mode (asymmetrical or symmetrica l). The PLL cont ains a 4-bit divider to help divide

PCLK into a frequency between 0.5 MHz and 1 MHz.

8.19.2 CCUCLK prescaling

This CCUCLK can further be divided down by a prescaler. The prescaler is implemented

as a 10-bit free-running counter with programmable reload at overflow.

8.19.3 Basic timer operation

The timer is a free-running up/do wn counter with a direction control bit. If the timer

counting direction is changed while the counter is running, the count sequence will be

reversed. The timer can be written or read at any time.

When a reload occurs, the CCU T imer Overflow Interrupt Flag will be set, and an interrupt

generated if enabled. The 16-bit CCU timer may also be used as an 8-bit up/down timer.

8.19.4 Output compare

There are four output compare channels A, B, C and D. Each output compare channel

needs to be enabled in order to operate and the user will have to set the associated I/O

pin to the desired output mode to connect the pin. When the co ntents of the timer matches

that of a capture compare control register, the Timer Output Compare Interrupt Flag

(TOCFx) becomes set. An interrupt will occur if enabled.

8.19.5 Input capture

Input capture is always enab led. Each time a capture e vent occurs on one of the two input

capture pins, the contents of the timer is transferred to the corresponding 16-bit input

capture register. The capture event can be programmed to be either rising or falling edge

triggered. A simple noise filter can be enabled on the input capture by enabling the Input

Product data sheet Rev. 8 — 12 Ja nuary 2011 36 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

Capture Noise Filter bit. If set, the capture logic needs to see four consecutive samples of

the same value in or der to recognize an edge as a capture event. An event counter can be

set to delay a capture by a number of capture events.

8.19.6 PWM operation

PWM operation has two main modes, symmetrical and asymmetrical.

In asymmetrical PWM operation the CCU timer operates in down-counting mode

regardless of the direction control bit.

In symmetrical mode, the timer counts up/down alterna tely. The main difference from

basic timer operation is the operation of the compare module, which in PWM mode is

used for PWM waveform genera tion.

As with basic timer operation, when the PWM (compare) pins are connected to the

compare logic, their logic state remains unchanged. However, since bit FCO is used to

hold the halt value, only a compare event can change the state of the pin.

Fig 10. Asymmetrical PWM, down-coun ting mode

Fig 11. Symmetrical PWM

TOR2

compare value

timer value

non-inverted

inverted

0x0000

002aaa89

TOR2

compare value

timer value

non-inverted

inverted

002aaa89

Product data sheet Rev. 8 — 12 Ja nuary 2011 37 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.19.7 Alternating output mode

In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating

pairs for bridge drive control. In this mode the output of these PWM channels are

alternately ga te d on eve ry counte r cycle.

8.19.8 PLL operation

The PWM module features a PLL that can be used to generate a CCUCLK frequency

between 16 MHz and 32 MHz. At this frequency the PWM module pr ov ide s ultr as on ic

PWM frequency with 10-bit resolution provided that the crystal frequency is 1 MHz or

higher. The PLL is fed an input signal from 0.5 MHz to 1 MHz and generates an output

signal of 32 times the input frequency. This signal is used to clock the timer. The user will

have to set a divider that scales PCLK by a factor from 1 to 16. This divider is found in the

SFR register TCR21. The PLL frequency can be expressed as shown in Equation 1.

(1)

Where: N is the value of PLLDV.3 to PLLDV.0.

Since N ranges from 0 to 15, the CCLK frequency can be in the range of PCLK to PCLK⁄16.

Fig 12. Alternate output mode

TIMER VALUE

002aaa895

TOR2

COMPARE VALUE A (or C)

COMPARE VALUE B (or D)

PWM OUTPUT (OCA or OCC)

PWM OUTPUT (OCB or OCD)

PLL frequency PCLK

N1+()

------------------

Product data sheet Rev. 8 — 12 Ja nuary 2011 38 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.19.9 CCU interrupts

There are seven interrupt sources on the CCU which share a common interrupt vector.

8.20 UART

The P89LPC933/934/935/936 has an enhanced UART that is compatible with the

conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate

source. The P89LPC933/934/935/936 does include an independent baud rate generator.

The baud rate can be selected from the oscillator (divided by a constant), Timer 1

overflow, or the independent baud rate generator. In addition to the baud rate generation,

enhancements over the standard 80C51 UART include Framing Error detection,

automatic address recognition, selectable double buffering and seve ral interrupt options.

The UART can be operated in four modes: shift register, 8-bit UART, 9-bit UART, and CPU

clock⁄32 or CPU clock⁄16.

8.20.1 Mode 0

Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are

transmitted or received, LSB first. The baud rate is fixed at 1⁄16 of the CPU clock

frequency.

Fig 13. Capture/compare unit interrupts

002aaa896

interrupt to

CPU

TOIE2 (TICR2.7)

TOIF2 (TIFR2.7)

TICIE2A (TICR2.0)

TICF2A (TIFR2.0)

TICIE2B (TICR2.1)

TICF2B (TIFR2.1)

TOCIE2A (TICR2.3)

TOCF2A (TIFR2.3)

TOCIE2B (TICR2.4)

TOCF2B (TIFR2.4)

TOCIE2C (TICR2.5)

TOCF2C (TIFR2.5)

TOCIE2D (TICR2.6)

TOCF2D (TIFR2.6)

EA (IEN0.7)

ECCU (IEN1.4)

PRIORITY

ENCODER

other

interrupt

sources

ENCINT.0

ENCINT.1

ENCINT.2

Product data sheet Rev. 8 — 12 Ja nuary 2011 39 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.20.2 Mode 1

10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0),

8 data bit s ( LSB first), and a stop bit (logic 1). When dat a is received, the stop bit is stored

in RB8 in special function register SCON. The baud rate is variable and is determined by

the Timer 1 overflow rate or the baud rate generator (described in Section 8.20.5 “Baud

rate generator and selection”).

8.20.3 Mode 2

11 bits are tra nsmitted (t hro ugh TXD) or r eceived (thr ough RXD): start bit (logic 0), 8 data

bits (L SB first) , a programmable 9th data bit, and a stop bit (logic 1). When data is

transmitted, the 9th data bit (TB8 in SCON) can be assigned th e value of logic 0 or logic 1.

Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is

received, the 9th data bit goes into RB8 in special function register SCON, while the stop

bit is not saved. The baud rate is programmable to either 1⁄16 or 1⁄32 of the CPU clock

frequency, as determined by the SMOD1 bit in PCON.

8.20.4 Mode 3

11 bits are transmitted (through TXD) or received (through RXD) : a start bit (logic 0), 8

data bit s (LSB first), a programmable 9th dat a bit, and a stop bit (logic 1). In fact, Mode 3 is

the same as Mode 2 in all respects except baud ra te . The baud r ate in Mo de 3 is variable

and is determined by the Timer 1 overflow rate or the baud rate generator (described in

Section 8.20.5 “Baud rate generator and selection”).

8.20.5 Baud rate generator and selection

The P89LPC933/934/935/936 enhanced UART has an independent baud rate gen erator.

The baud rate is dete rmined by a baud-ra te preprogram med into the BRGR1 and BRGR0

SFRs which together form a 16-bit baud rate divisor value that works in a similar manner

as Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be

used for other timing functions.

The UAR T can use eith er Timer 1 or the baud rate ge nerator o utput (see Figure 14). Note

that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The

independent baud rate generator uses CCLK.

8.20.6 Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)

is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is

logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up

when SMOD0 is logic 0.

Fig 14. Baud rate sources for UART (Modes 1, 3)

baud rate modes 1 and 3

SBRGS = 1

SBRGS = 0

SMOD1 = 0

SMOD1 = 1

timer 1 overflow

(PCLK-based)

baud rate generator

(CCLK-based) 002aaa89

÷2

Product data sheet Rev. 8 — 12 Ja nuary 2011 40 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.20.7 Break detect

Break detect is reported in the status register (SSTAT). A break is detected when

11 consecutive bits are sensed LOW. The break detect can be used to reset the device

and force the device into ISP mode.

8.20.8 Double buffering

The UART ha s a transmit double buffer that allows buffering of the next character to be

written to SBUF while the first character is being transmitted. Double buffering allows

transmission of a string of characters with only one stop bit between any two characters,

as long as the next character is written between the start bit and the stop bit of the

previous char acter.

Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is

compatible with the conven tio nal 80C51 UART. If enabled, the UART allows writing to

SnBUF while the previous data is being shifted out. Double buffering is only allowed in

Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled

(DBMOD = 0).

8.20.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated

when the double buffer is ready to receive new data.

8.20.10 The 9th bit (bit 8) in double buffering (modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as long

as TB8 is updated some time befo re that bit is shifted out. TB8 must not be change d until

the bit is shifted out, as indicated by the Tx interrupt.

If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will

be double-buffered together with SBUF dat a.

Product data sheet Rev. 8 — 12 Ja nuary 2011 41 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.21 I2C-bus serial interface

The I2C-bus uses two wires (SDA and SCL) to tra n sfe r info r matio n be tw ee n de vices

connected to the bus, and it has the following features:

•Bidirectional data transfer between masters and slaves

•Multi master bus (no central master)

•Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus

•Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus

•Serial clock synchronization can be used as a handshake me chanism to suspend and

resume serial transfer

•The I2C-bus may be used for test and diagnostic purposes.

A typical I2C-bus configuration is shown in Figure 15. The P89LPC933/934/935/936

device provides a byte-oriented I2C-bus interface that supports data transfers up to

400 kHz.

Fig 15. I2C-bus configuration

OTHER DEVICE

WITH I

C-BUS

INTERFACE

SDA

SCL

OTHER DEVICE

WITH I

C-BUS

INTERFACE

P1.3/SDA P1.2/SCL

P89LPC935

C-bus

002aab082

Product data sheet Rev. 8 — 12 Ja nuary 2011 42 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

Fig 16. I2C-bus serial interface b lo ck diagram

INTERNAL BUS

002aaa89

ADDRESS REGISTER

COMPARATOR

SHIFT REGISTER

I2ADR

ACK

BIT COUNTER /

ARBITRATION

AND SYNC LOGIC

I2DAT

TIMING

AND

CONTROL

LOGIC

SERIAL CLOCK

GENERATOR

CCLK

interrupt

INPUT

FILTER

OUTPUT

STAGE

INPUT

FILTER

OUTPUT

STAGE

P1.3

P1.3/SDA

P1.2/SCL

P1.2

timer 1

overflow

CONTROL REGISTERS AND

SCL DUTY CYCLE REGISTERS

I2CON

I2SCLH

I2SCLL

STATUS

DECODER

status bus

STATUS REGISTER

I2STAT

Product data sheet Rev. 8 — 12 Ja nuary 2011 43 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.22 SPI

The P89LPC933/934/935/936 provides another high-speed serial communication

interface—the SPI interface. SPI is a full-duplex, high-speed, synchronous

communication bus with two operation modes: Master mode and Slave mode. Up to

3 Mbit/s can be supported in Master mode or up to 2 Mbit/s in Slave mode. It has a

Transfer Completion Flag and Write Collision Flag Protection.

The SPI interface has four pins: SPICLK, MOSI, MISO and SS:

•SPICLK, MOSI and MISO are typically tied together between two or more SPI

devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows

from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output

in the master mode and is input in the slave mode. If the SPI system is disabled, i.e.,

SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.

•SS is the optional slave select pin. In a typical configuration, an SPI master asserts

one of it s port p ins to select one SPI devi ce as the curr ent sla ve. An SPI slave device

uses its SS pin to determine whether it is selected.

Ty pic al con n ec tio ns ar e sh own in Figure 18 through Figure 20.

Fig 17. SPI block diagram

002aaa900

CPU clock

DIVIDER

BY 4, 16, 64, 128

SELECT CLOCK LOGIC

SPI CONTROL REGISTER

READ DATA BUFFER

8-BIT SHIFT REGISTER

SPI CONTROL

SPI STATUS REGISTER

SPR1

SPIF

WCOL

SPR0

SPI clock (master)

CONTROL

LOGIC

MISO

P2.3

MOSI

P2.2

SPICLK

P2.5

P2.4

SPI

interrupt

request

internal

data

bus

SSIG

SPEN

MSTR

DORD

MSTR

CPHA

CPOL

SPR1

SPR0

MSTR

SPEN

clock

Product data sheet Rev. 8 — 12 Ja nuary 2011 44 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.22.1 Typical SPI configurations

Fig 18. SPI single master single slave configuration

Fig 19. SPI dual device configur ation, where either can be a master or a sla ve

002aaa90

master slave

8-BIT SHIFT

SPI CLOCK

GENERATOR

8-BIT SHIFT

MISO

MOSI

SPICLK

PORT

MISO

MOSI

SPICLK

002aaa90

master slave

8-BIT SHIFT

SPI CLOCK

GENERATOR

SPI CLOCK

GENERATOR

8-BIT SHIFT

MISO

MOSI

SPICLK

MISO

MOSI

SPICLK

Product data sheet Rev. 8 — 12 Ja nuary 2011 45 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

Fig 20. SPI single master multiple slaves configuration

002aaa90

master slave

8-BIT SHIFT

SPI CLOCK

GENERATOR

8-BIT SHIFT

MISO

MOSI

SPICLK

port

MISO

MOSI

SPICLK

slave

8-BIT SHIFT

MISO

MOSI

SPICLK

Product data sheet Rev. 8 — 12 Ja nuary 2011 46 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.23 Analog comparators

Two analog comparators are provided on the P89LPC933/934/935/936. Input and output

options allow use of the comparators in a number of different configurations. Comparator

operation is such that th e output is a logic 1 (which may be read in a register and/or routed

to a pin) when the positive input (one of two selectable pins) is greater than the negative

input (selectable from a pin or an internal reference voltage). Otherwise the output is a

zero. Each comparator may be configured to cause an interrupt when the output value

changes.

The overall connections to both comparators are shown in Figure 21. The comparators

function to VDD =2.4V.

When each comparat or is first en ab led, the comparator output and inter rupt flag are not

guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt

should not be enabled during that time, an d the comparator inter rupt flag mu st be cl eared

before the interrupt is enabled in order to prevent an immediate interrupt service.

When a comparator is disabled the comparator’s output, COn, goes HIGH. If the

comparato r output was LOW and then is disabled, the resulting transition of the

comparator output from a LOW to HIGH state will set the comparator flag, CMFn. This will

cause an interrupt if the compar ator interrupt is enabled. The user should therefore

disable the comparator interrupt prior to disabling the comparator. Additionally, the user

should clear the comparator flag, CMFn, after disabling the comparator.

8.23.1 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single

comparator inp ut pin is used. The value of the internal reference voltage, referred to as

Vref(bg), is 1.23 V ±10 %.

Fig 21. Compara tor inp ut an d ou tput connections

comparator 1

CP1

CN1

(P0.4) CIN1A

(P0.3) CIN1B

(P0.5) CMPREF

Vref(bg)

OE1

change detect

CO1

CMF1

interrupt

002aaa904

CMP1 (P0.6)

change detect

CMF2

comparator 2

OE2

CO2

CMP2 (P0.0)

CP2

CN2

(P0.2) CIN2A

(P0.1) CIN2B

Product data sheet Rev. 8 — 12 Ja nuary 2011 47 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.23.2 Comparator interrupt

Each comparator has an interrupt flag contained in its configuration register. This flag is

set whenever the comp arator output changes st ate. The flag may be polled by sof tware or

may be used to generate an interrupt. The two comp arators use one common interrupt

vector. If both comparators enable interrupts, after entering the interrupt service routine,

the user needs to read the flags to determine which comparator caused the interrupt.

8.23.3 Comparators and power reduction modes

Either or both comparators may remain enabled when Power-down or Idle mode is

activated, but both comparators are disab led automatically in Total Power-down mode.

If a comparator interrupt is enabled (except in Total Power-down mode), a change of the

comparator output state will generate an interrupt and wake-up the processor. If the

comparato r output to a pin is enabled, the p in shou ld be conf igu red in the push-pull m ode

in order to obtain fast switching times while in Power-down mode. The reason is that with

the oscillator stopped, the temporary strong pull-up that normally occurs during switching

on a quasi-bidirectional port pin does not take place.

Comparators consume power in Power-down and Idle modes, as well as in the normal

operating mode. This fact should be taken into account when system power consumption

is an issue. To minimize power consumption, the user can disable the comparators via

PCONA.5, or put the device in Total Power-down mode.

8.24 Keypad interrupt

The Keypad Interrupt (KBI) function is intended primarily to allow a single interrupt to be

generated when Port 0 is equal to or not equal to a certain pattern. This function can be

used for bus address recognition or keypad recognition. The user can configure the port

via SFRs for different tasks.

The Keypad Interrupt Mask register (KBMASK) is used to define which input pins

connected to Port 0 can trigger the interrupt. The Keypad Pattern register (KBPATN) is

used to define a p attern that is compa red to the value of Por t 0. The Keypad Interr upt Flag

(KBIF) in the Keypad Interrupt Control register (KBCON) is set when the condition is

matched while the Keypad Interrupt function is active. An interrupt will be generated if

enabled. The PATN_SEL bit in the Keypad Interrupt Control register (KBCON) is used to

define equal or not-equal for the comparison.

In order to use the Keypad Interrupt as an original KBI function like in 87 LPC76x series,

the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key

connected to Port 0 which is enabled by the KBMASK register will cause the hardware to

set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to

wake-up the CPU from Idle or Power-down modes. This feature is particularly useful in

handheld, ba tt er y- po we re d sys tem s that nee d to care fu lly ma n ag e po wer co nsu m ption

yet also need to be convenient to use.

In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer

than six CCLKs.

Product data sheet Rev. 8 — 12 Ja nuary 2011 48 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.25 Watchdog timer

The watchdog timer causes a system reset wh en it underflows as a result of a failure to

feed the timer prior to th e timer reaching its terminal count. It consists of a programmable

12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap

take n from the prescaler. The clock source for the prescaler is either the PCLK or the

nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a

power-on reset. When the watchdog feature is disabled, it can be used as an interval

timer and may generate an interrupt. Figure 22 shows the watchdog timer in Watchdog

mode. Feeding the watch dog requires a two-byte sequence. If PCLK is selected as the

watchdog clock and the CPU is powered-down, the watchdog is disabled. The watchdog

timer has a time-out period that r anges from a few μs to a few se conds. Please refer to the

P89LPC933/934/935/936 User manual for more details.

8.26 Additional features

8.26.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,

as if an exte rnal reset or watchd og reset had occur red. Care should b e take n when writing

to AUXR1 to avoid accidental software resets.

8.26.2 Dual data pointers

The dual Data Pointers (DP TR) provides two different Data Pointers to specify the

address used with certain instructions. The DPS bit in the AUXR1 register selects one of

the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS

bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed

sequence.

Fig 22. Watchdog timer in Watchdog mode (WDTE = 1)

PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK

WDCON (A7H)

SHADOW REGISTER

PRESCALER

002aaa90

8-BIT DOWN

COUNTER

WDL (C1H)

watchdog

oscillator

PCLK ÷32

MOV WFEED1, #0A5H

MOV WFEED2, #05AH

reset

(1)

Product data sheet Rev. 8 — 12 Ja nuary 2011 49 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.27 Data EEPROM (P89LPC935/936)

The P89LPC935/936 has 512 bytes of on-chip Data EEPROM. The Data EEPROM is

SFR based, byte readable, byte writable, and erasable (via row fill and sector fill). The

user can read, write and fill the memory via SFRs and one interrupt. This Data EEPROM

provides 100,000 minimum erase/program cycles for each byte.

•Byte mode: In this mode, data can be read and written one byte at a time.

•Row fill: In this mode, the addressed row (64 bytes) is filled with a single value. The

entire row can be erased by writing 00H.

•Sector fill: In this mode, all 512 bytes are filled with a single value. The entire sector

can be erased by writin g 00 H.

After the operation finishes, the hardware will set the EEIF bit, which if enabled will

generate an interrupt. The flag is cleared by software.

8.28 Flash program memory

8.28.1 General description

The P89LPC933/934/935/936 flash memory provides in-circuit electrical erasure and

programming. The flash can be erased, read, and written as bytes. The Sector and Page

Erase functions can erase an y flash sector (1 kB or 2 kB depending on the device) or

page (64 bytes). The Chip Erase operation will erase the entire program memory. ICP

using standard commercial programmers is available. In addition, IAP and byte-erase

allows code memory to be used for non-volatile data storag e. On-chip erase and write

timing generation contribute to a user-friendly programm ing interface. The

P89LPC933/934/935/9 36 flash reliab ly stores m emory conte nt s even after 100,000 erase

and program cycles. The cell is designed to optimize the erase and programming

mechanisms. The P89LPC933/934/935/936 uses VDD as the supply voltage to perform

the Program/Erase algorithms.

8.28.2 Features

•Programming and erase over the full operating voltage range.

•Byte erase allows cod e mem ory to be us ed for da ta storag e.

•Read/Programming/Erase using ISP/IAP/ICP.

•Internal fixed boot ROM, contain ing low-level IAP routines available to user code.

•Default loader providing ISP via the serial port, located in upper end of user program

memory.

•Boot vector allows user-provided flash loader code to reside anywhere in the flash

memory space, providing flexibility to the user.

•Any flash program/erase operation in 2 ms.

•Programming with industry-standard commercial programmers.

•Programmable security for the code in the flash for each sector.

•100,000 typical erase/program cycles for each byte.

•10 year minim um da ta retent ion .

Product data sheet Rev. 8 — 12 Ja nuary 2011 50 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.28.3 Flash organization

The program memory consist s of eight 2 kB sectors on the P89LPC936 device, eight 1 kB

sectors on the P89LPC934 /935 devices, and four 1 kB sectors on the P89LPC933 device.

Each sector can be fur the r divi de d into 64 -b yt e pages. In add itio n to se cto r er as e, page

erase, and byte erase, a 64-b yte page register is included which allows from 1 to 64 bytes

of a given page to be programmed at the same time, substantially reducing overall

programming time.

8.28.4 Using flash as data storage

The flash code memory arr ay of this device supports individual byte erasing and

programming. Any byte in the code memory ar ray may be read using the MOVC

instruction, pr ov ide d th at the se cto r co ntaining the by te has no t be en sec ur ed (a MO VC

instruction is not allo we d to read co de mem ory contents of a secured sec to r). Th us any

byte in a non-secured sector may be used for non-volatile data storage.

8.28.5 Flash programming and erasing

Four different methods of erasing or programming of the flash are available. The flash

may be programmed or erased in the end-user application (IAP) under control of the

application’s firmware. Another option is to use the ICP mechanism. This ICP system

provides for programmi ng through a serial clock - serial data interface. As shipped from

the factory, the upper 512 bytes of user code space contains a serial ISP routine allowing

the device to be prog ra mm e d in circ uit thr ough the serial port. The flash may also be

programmed or eras ed usin g a co mm e rcia lly av aila ble EPROM pr og ra m mer wh ich

supports this device. This device does not provide for direct verification of code memo ry

contents. Instead , this device pr ovide s a 32-b it CRC re sult on either a se ctor or the entire

user code space.

8.28.6 In-circuit programming

ICP is performed without removing the microcontroller from the system. The ICP facility

consists of internal hardware resources to facilitate remote programming of the

P89LPC933/934/935/936 through a two-wire serial interface. The Philips ICP facility has

made ICP in an embedded application—using commercially available

programm ers — po ss i ble with a min im um of ad di tional expense in components an d circuit

board area. The ICP fu nction uses five pins. Only a small conn ector needs to be available

to interface your applica tion to a commercial programmer in order to use this feature.

Additional details may be found in the P89LPC933/934/935/936 User manual.

8.28.7 In-application programming

IAP is performed in the application und er the control of the microcontroller’s firmware. The

IAP facility consists of internal hardware resources to facilit ate programming and erasing.

The Philips IAP has made IAP in an embedded application possible without additional

components. Two methods are available to accomplish IAP. A set of predefined IAP

functions are provided in a boot ROM and can be called through a common interface,

PGM_MTP. Several IAP calls are available for use by an application program to permit

selective erasing and programming of flash sectors, pages, security bits, configuration

bytes, and device ID. These functions are selected by setting up the microcontroller’s

registers before making a call to PGM_MTP at FF03H. The boot ROM occupies the

program memory space at the top of the address space from FF00H to FFEFH, thereby

not conflicting with the user program memory space.

Product data sheet Rev. 8 — 12 Ja nuary 2011 51 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

In addition, IAP operations can be accomplished through the use of four SFRs consisting

of a control/status register, a data register, and two address registers. Additional details

may be found in the P89LPC933/934/935/936 User manual.

8.28.8 ISP

ISP is performed without removing the microcontroller from the system. The ISP facility

consists of a series of intern al hardware resources coupled with internal firmware to

facilitate remote programming of the P89LPC933/934/935/936 through the serial port.

This firmware is provided by Philips and embedded within each P89LPC933/934/935/936

device. The Philips ISP facility has made ISP in an embedded application possible with a

minimum of additional expense in components and circuit board area. The ISP function

uses five pins (VDD, VSS, TXD, RXD, and RST). Only a small connector needs to be

available to interface your application to an external circuit in order to use this feature.

8.28.9 Power-on reset code execution

The P89LPC933/934/935/936 contains two special flash elements: the boot vector and

the boot status bit. Following reset, the P89LPC933/934/935/936 examines the contents

of the boot sta tus bit. If the boot status bit is set to zero, power-up execution st arts at

location 0000H, which is the normal start address of the user’s application code. When

the boot status bit is set to a value other than zero, the contents of the boot vector are

used as the high byte of the execution address and the low byte is set to 00H.

Table 9 shows the factory default boot vector settings for these devices.

Remark: These settings are different than the original P89LPC932 . Tools designed to

support the P89LPC933/934/935/936 should be used to program this device, such as

Flash Magic version 1.98, or later.

A factory-provided boot loader is preprogrammed into the address space indicated and

uses the indicated boot loader entry point to perform ISP functions. This code can be

erased by the user.

Remark: Users who wish to use this loader should take precautions to avoid erasing the

sector that contains this boot loader. Instead, the page erase function can be used to

erase the pages located in th is sect or which are not used by th e bo ot load e r.

A custom boot loader can be written with the boot vector set to the custom boot loader, if

desired.

Table 9. Default boot vector values an d ISP en try points

Device Default

boot vector Default

boot loader

entry point

Default boot loader

code range Boot sector

range

P89LPC933 0F H 0F00H 0E00H to 0FFFH 0C00H to 0FFFH

P89LPC934 1F H 1F00H 1E00H to 1FFFH 1C00H to 1FFFH

P89LPC935 1F H 1F00H 1E00H to 1FFFH 1C00H to 1FFFH

P89LPC936 3F H 3F00H 3E00H to 3FFFH 3C00H to 3FFFH

Product data sheet Rev. 8 — 12 Ja nuary 2011 52 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.28.10 Hardware activation of the boot loader

The boot loader can also be executed by forcing the device into ISP mode during a

power-on sequence (see the P89LPC933/934/935/936 User manual for specific

information). This h as the same effect as having a non-zero status byte. This allows an

application to be built that will normally execute user code but can be manually forced into

ISP operation. If the factory default setting for the boot vector is changed, it will no longer

point to the factory preprogrammed ISP boot loader code. After progra mming the flash,

the status byte should be programmed to zero in order to allow execution of the user’s

application code beginning at address 0000H.

8.29 User configuration bytes

Some user-configurable features of the P89LPC933/934/935/936 must be defined at

power-up and therefore cannot be set by the program after start of execution. These

features are configured through the use of the flash byte UCFG1. Please see the

P89LPC933/934/935/936 User manual for additional details.

8.30 User sector security bytes

There are eight User Secto r Security Bytes on the P89L PC933/934/935/936 d evice. Each

byte corresponds to one se ctor . Please see the P89LPC933/934/9 35/936 User manual for

additional details.

9. A/D converter

9.1 General description

The P89LPC935/936 have two 8 -bit, 4-channel multiplexed successive approximation

analog-to-digital converter modules sharing common control logic. The P89L PC933/934

have a single 8-bit, 4-channel multiplexed analog-to-digital converter and an additional

DAC module. A block diagram of the A/D converter is shown in Figure 23. Each A/D

consists of a 4-input multip le xe r wh ich feeds a sa mp le- a nd -h o l d circu it pr oviding an input

signal to one of two comparator inputs. The control logic in combination with the SAR

drives a digital-to-analog converter which pr ovides the other input to the comparator. The

output of the comparator is fed to the SAR.

9.2 Features and benefits

Two (P89LPC935/936) 8-bit, 4-channe l multiplexed input, successive approximation

A/D converters with common control logic (one A/D on the P89LPC933/934).

Four result registers for each A/D.

Six operating mode s:

Fixed channel, single conversion mode.

Fixed channel, continuous conversion mode.

Auto scan, single conversion mode.

Auto scan, continuous conversion mode.

Dual channel, co nt in u ou s con ve rs i on mode .

Single step mode.

Four conversion start modes:

Timer triggered start.

Product data sheet Rev. 8 — 12 Ja nuary 2011 53 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

Start immediately.

Edge triggered.

Dual start immediately (P89LPC935/936).

8-bit conversion time of ≥3.9 μs at an A/D clock of 3.3 MHz.

Interrupt or polled op e ra tio n.

Boundary limits interrupt.

DAC output to a port pin with high output impedance.

Clock divider.

Power-down mode.

9.3 Block diagram

9.4 A/D operating modes

9.4.1 Fixed channel, single conversion mode

A single input channel can be selected for conversion. A single conversion will be

performed and the result placed in the result register which corresponds to the selected

input channel. An interrupt, if enabled, will be generated after the conversion completes.

Fig 23. ADC block diagram

–

comp

DAC1

SAR

INPUT

MUX

CONTROL

LOGIC

–

comp

DAC0

SAR

INPUT

MUX

CCLK

002aab08

Product data sheet Rev. 8 — 12 Ja nuary 2011 54 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

9.4.2 Fixed channel, continuous conversion mode

A single input channel can be selected for continuous conversion. The results of the

conversions will be sequentially placed in the four result registers. An interrupt, if enabled,

will be generated after every four conversions. Additional conversion results will again

cycle through the four result registers, overwriting the previous results. Continuous

conversions continue until terminated by the user.

9.4.3 Auto scan, single conversion mode

Any combination of the fo ur inpu t cha nne ls can be selected for conversion. A single

conversion of each selected input will be performed and the result placed in the result

generated after all selected channels have been converted. If only a single channel is

selected this is equivalent to single channel, single co nversion mode.

9.4.4 Auto scan, continuous conversion mode

Any combination of the four input channels can be selected for conversion. A conversion

of each selected input will be performed and the result placed in the result register which

corresponds to the selected input channel. An interrupt, if enabled, will be generated after

all selected channels have been converted. The process will repeat starting with the first

selected channel. Additional conversion results will again cycle through the four result

registers, overwriting the previous results. Continuous conversions continue until

terminated by the user.

9.4.5 Dual channel, continuous conversion mode

This is a variation of the auto scan contin uous conversion mode whe re conversio n occurs

on two user-selecta ble input s. The result of the conversion of the first cha nnel is placed in

result register, ADxDAT0. The result of the conversion of the second channel is placed in

result register, ADxDAT1. The first channel is again converted and its result stored in

ADxDAT2. The second channel is again converted and its result placed in ADxDAT3. An

interrupt is genera ted, if enabled, af ter every se t of fo ur conver sions ( two conversions p er

channel).

9.4.6 Single step mode

This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any

combination of the four input cha nnels can be selected for conversion. Af ter each ch annel

is converted, an interrupt is generated, if enabled, and th e A/D wa its for the next start

condition. May be us ed with an y of th e start modes.

9.5 Conversion start modes

9.5.1 Timer triggered start

An A/D conversion is started by the overflow of Timer 0. Once a conversion has started,

additional Timer 0 triggers are ignored until the conversion has completed. The Timer

triggered start mode is available in all A/D operating modes.

9.5.2 Start immediately

Programming th is mode immediately start s a conversion. This st art mode is available in all

A/D operating modes.

Product data sheet Rev. 8 — 12 Ja nuary 2011 55 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

9.5.3 Edge triggered

An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has

starte d, additional edge triggers are ignored until th e conversion has completed. The edge

triggered start mode is available in all A/D operating modes.

9.5.4 Dual start immediately (P89LPC935/936)

Programming this mode starts a synchronized conversion of both A/D converters. This

start mode is available in all A/D operating modes. Both A/D converters must be in the

same operating mode. In the continuous conversion modes, both A/D converters must

select an identical number of channels. Any trigger of either A/D will start a simultaneous

conversion of both A/Ds.

9.6 Boundary limits interrupt

Each of the A/D converters has both a high and low boundary limit register. After the four

MSBs have been conv er te d, th es e fou r bits are compared with the four MSBs of the

boundary high and low registers. If the four MSBs of the conversion are outside the limit

an interrupt will be generated, if enabled. If the conversion result is within the limits, the

boundary limits will again be compared after all 8 bits have been converted. An interrupt

will be generated, if enabled, if the result is outside the boundary limits. The boundary limit

may be disabled by clearing the boundary limit interrupt enable.

9.7 DAC output to a port pin with high output impedance

Each A/D converter’s DAC block can be output to a port pin. In this mode, the ADxDAT3

DAC (written to ADxDAT3), the DAC output will appear on the channel 3 pin.

9.8 Clock divider

The A/D converter requires that its internal clock source be in the range of 500 kHz to

3.3 MHz to maint ain accuracy. A programmable clock divider that divides the clock

from 1 to 8 is provided for this purpose.

9.9 Power-down and Idle mode

In Idle mode the A/C converter, if enabled, will continue to function and can cause the

device to exit Idle mode when the conversion is completed if the A/D interrupt is enabled.

In Power-down mode or Total Power-down mode, the A/D does not function. If the A/D is

enabled, it will consume power. Power can be reduced by disabling the A/D.

Product data sheet Rev. 8 — 12 Ja nuary 2011 56 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

10. Limiting values

[1] The following applies to Table 10:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over ambient temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

Table 10. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

Tamb(bias) bias ambient temperature −55 +125 °C

Tstg storage temperature −65 +150 °C

IOH(I/O) HIGH-level output current per

input/output pin -20mA

IOL(I/O) LOW-level output current per

input/output pin -20mA

II/Otot(max) maximum total input/ ou tp ut current - 100 mA

Vxtal crystal voltage on XTAL1, XTAL2 pin to VSS -V

DD + 0.5 V

Vnvoltage on any other pin except XTAL1, XTAL2 to VSS −0.5 +5.5 V

Ptot(pack) total power dissipation (per package) based on package heat

transfer, not device power

consumption

-1.5W

Product data sheet Rev. 8 — 12 Ja nuary 2011 57 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

11. Static characteristics

Table 11. Static characteristics

VDD = 2.4 V to 3.6 V unless otherwise specified.

Tamb =−40 °Cto+85°C for industrial, −40 °Cto+125°C for extended, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

IDD(oper) operating supp ly current V DD = 3.6 V; fosc =12MHz [2] -1118mA

VDD = 3.6 V; fosc =18MHz [2] -1423mA

IDD(idle) Idle mode supply current VDD = 3.6 V; fosc =12MHz [2] -3.255mA

VDD = 3.6 V; fosc =18MHz [2] -57mA

IDD(pd) Power-down mode supply

current VDD = 3.6 V; voltage

comparators powered

down

[2] -5580μA

IDD(tpd) total Power-down mode supply

current all devices except

P89LPC933HDH;

VDD =3.6V

[3] -15μA

P89LPC933HDH only;

VDD =3.6V [3] --25μA

(dV/dt)rrise rate of VDD --2mV/μs

(dV/dt)ffall rate of VDD --50mV/μs

VPOR power-on reset voltage - - 0.5 V

VDDR data retention supply voltage 1.5 - - V

Vth(HL) HIGH-LOW threshold voltage excep t SCL, SDA 0.22VDD 0.4VDD -V

VIL LOW-level input voltage SCL, SDA only −0.5 - 0.3VDD V

Vth(LH) LOW-HIGH threshold voltage except SCL, SDA - 0.6VDD 0.7VDD V

VIH HIGH-level input voltage SCL, SD A only 0.7VDD -5.5V

Vhys hysteresis voltage port 1 - 0.2VDD -V

VOL LOW-level output voltage IOL =20mA;

VDD = 2.4 V to 3.6 V

all ports, all modes except

high-Z

[4] -0.61.0V

IOL = 3.2 mA; VDD =2.4V

to 3.6 V all ports, all modes

except high-Z

-0.20.3V

VOH HIGH-level output voltage IOH =−20 μA;

VDD = 2.4 V to 3.6 V;

all ports,

quasi-bidirectional mode

VDD −0.3 VDD −0.2 - V

IOH =−3.2 mA;

VDD = 2.4 V to 3.6 V;

all ports, push-pull mode

VDD −0.7 VDD −0.4 - V

IOH =−10 mA; VDD =3.6V;

all ports, push-pull mode -3.2-V

Vxtal cryst al volt age on XTAL1, XTAL2 pins;

with respect to VSS

−0.5 - +4.0 V

Vnvoltage on any other pin except XTAL1, XTAL2,

VDD; with respect to VSS

[5] −0.5 - +5.5 V

Ciss input capacitance [6] --15pF

Product data sheet Rev. 8 — 12 Ja nuary 2011 58 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.

[2] The IDD(oper), IDD(idle), and IDD(pd) specifications are measured using an external clock with the following functions disabled: comparators,

real-time clock, and watchdog timer.

[3] The IDD(tpd) specification is measured using an external clock with the following functions disabled: comparators, real-time clock,

brownout detect, and watchdog timer.

[4] See Section 10 “Limiting values” for steady state (non-transient) limits on IOL or IOH. If IOL/IOH exceeds the test condition, VOL/VOH may

exceed the related specification.

[5] This specification can be applied to pins which have A/D input or analog comparator input functions when the pin is not being used for

those analog functions. When the pin is being used as an analog input pin, the maximum voltage on the pin must be limited to 4.0 V with

respect to VSS.

[6] Pin capacitance is characterized but not tested.

[7] Measured with port in quasi-bidirectional mode.

[8] Measured with port in high-impedance mode.

[9] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is

highest when VI is approximately 2 V.

IIL LOW-level input current V I=0.4V [7] --−80 μA

ILI input leakage current VI=V

IL,V

IH or Vth(HL) [8] --±10 μA

ITHL HIGH-LOW transition current all ports; VI=1.5V at

VDD =3.6V [9] −30 - −450 μA

RRST_N(int) internal pull-up resistance on

pin RST 10 - 30 kΩ

Vbo brownout trip voltage 2.4 V < VDD < 3.6 V; with

BOV = 1, BOPD = 0 2.40 - 2.70 V

Vref(bg) band gap reference voltage 1.11 1.23 1.34 V

TCbg band gap temperature

coefficient -1020ppm/

°C

Table 11. Static characteristics …continued

VDD = 2.4 V to 3.6 V unless otherwise specified.

Tamb =−40 °Cto+85°C for industrial, −40 °Cto+125°C for extended, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 8 — 12 Ja nuary 2011 59 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

11.1 IOH as a function of VOH

a. Tamb = 25 °C; VDD = 3.6 V; push-pull mode b. Tamb = 25 °C; VDD = 2.6 V; push-pull mode

Fig 24. IOH as a function of VOH (typical values)

002aab098

01234

VOH

IOH

002aab099

0123

VOH

IOH

Product data sheet Rev. 8 — 12 Ja nuary 2011 60 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

12. Dynamic characteristics

Table 12. Dynamic characteristics (12 MHz)

VDD = 2.4 V to 3.6 V unless otherwise specified.

Tamb =−40 °Cto+85°C for industrial, −40 °Cto+125°C for extended, unless otherwise specified.[1][2]

Symbol Parameter Conditions Variable clock fosc =12MHz Unit

Min Max Min Max

fosc(RC) internal RC oscillator frequency 7.189 7.557 7.189 7.557 MHz

fosc(WD) internal watchdog oscillator

frequency 320 520 320 520 kHz

fosc oscillator frequency 0 12 - - MHz

Tcy(clk) clock cycle time see Figure 27 83 - - - ns

fCLKLP low-power select clock

frequency 08--MHz

Glitch filter

tgr glitch rejection time P1.5/RST pin - 50 - 50 ns

any pin except

P1.5/RST - 15 - 15 ns

tsa signal acceptance time P1.5/RST pin 125 - 125 - ns

any pin except

P1.5/RST 50 - 50 - ns

External clock

tCHCX clock HIGH time see Figure 27 33 Tcy(CLK) −tCLCX 33 - ns

tCLCX clock LOW time see Figure 27 33 Tcy(CLK) −tCHCX 33 - ns

tCLCH clock rise time see Figure 27 -8-8ns

tCHCL clock fall time see Figure 27 -8-8ns

Shift register (UART mode 0)

TXLXL serial port clock cycle time see Figure 25 16Tcy(CLK) - 1333 - ns

tQVXH output data set-up to clock rising

edge time see Figure 25 13Tcy(CLK) - 1083 - ns

tXHQX output data hold after clock

rising edge time see Figure 25 -T

cy(CLK) +20 - 103 ns

tXHDX input data hold after clock rising

edge time see Figure 25 -0-0ns

tXHDV input data valid to clock rising

edge time see Figure 25 150 - 150 - ns

SPI interface

fSPI SPI operating frequency

slave 0 CCLK⁄602.0MHz

master - CCLK⁄4-3.0MHz

TSPICYC SPI cycle time see Figure 26, 28,

29, 30

slave 6⁄CCLK -500-ns

master 4⁄CCLK -333-ns

tSPILEAD SPI enable lead time see Figure 29, 30

slave 250 - 250 - ns

Product data sheet Rev. 8 — 12 Ja nuary 2011 61 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

[1] Parameters are valid over ambient temperature range unless otherwise specified.

[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

tSPILAG SPI enable lag time see Figure 29, 30

slave 250 - 250 - ns

tSPICLKH SPICLK HIGH time see Figure 26, 28,

29, 30

master 2⁄CCLK -165-ns

slave 3⁄CCLK -250-ns

tSPICLKL SPICLK LOW time see Figure 26, 28,

29, 30

master 2⁄CCLK -165-ns

slave 3⁄CCLK -250-ns

tSPIDSU SPI data set-up time see Figure 26, 28,

29, 30

master or slave 100 - 100 - ns

tSPIDH SPI data hold time see Figure 26, 28,

29, 30

master or slave 100 - 100 - ns

tSPIA SPI access time see Figure 29, 30

slave 0 120 0 120 ns

tSPIDIS SPI disable time see Figure 29, 30

slave 0 240 - 240 ns

tSPIDV SPI enable to output data valid

time see Figure 26, 28,

29, 30

slave - 240 - 240 ns

master - 167 - 167 ns

tSPIOH SPI output data hold time see Figure 26, 28,

29, 30 0-0-ns

tSPIR SPI rise time see Figure 26, 28,

29, 30

SPI outputs

(SPICLK, MOSI, MISO) - 100 - 100 ns

SPI inputs

(SPICLK, MOSI, MISO, SS)- 2000 - 2000 ns

tSPIF SPI fall time see Figure 26, 28,

29, 30

SPI outputs

(SPICLK, MOSI, MISO) - 100 - 100 ns

SPI inputs

(SPICLK, MOSI, MISO, SS)- 2000 - 2000 ns

Table 12. Dynamic characteristics (12 MHz) …continued

VDD = 2.4 V to 3.6 V unless otherwise specified.

Tamb =−40 °Cto+85°C for industrial, −40 °Cto+125°C for extended, unless otherwise specified.[1][2]

Symbol Parameter Conditions Variable clock fosc =12MHz Unit

Min Max Min Max

Product data sheet Rev. 8 — 12 Ja nuary 2011 62 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

Table 13. Dynamic characteristics (18 MHz)

VDD = 3.0 V to 3.6 V unless otherwise specified.

Tamb =−40 °Cto+85°C for industrial, −40 °Cto+125°C for extended, unless otherwise specified.[1][2]

Symbol Parameter Conditions Variable clock fosc =18MHz Unit

Min Max Min Max

fosc(RC) internal RC oscillator frequency 7.189 7.557 7.189 7.557 MHz

fosc(WD) internal watchdog oscillator

frequency 320 520 320 520 kHz

fosc oscillator frequency 0 18 - - MHz

Tcy(CLK) clock cycle see Figure 27 55 - - - ns

fCLKLP low-power select clock

frequency 08--MHz

Glitch filter

tgr glitch rejection time P1.5/RST pin - 50 - 50 ns

any pin except

P1.5/RST - 15 - 15 ns

tsa signal acceptance time P1.5/RST pin 125 - 125 - ns

any pin except

P1.5/RST 50 - 50 - ns

External clock

tCHCX clock HIGH time see Figure 27 22 Tcy(CLK) −tCLCX 22 - ns

tCLCX clock LOW time see Figure 27 22 Tcy(CLK) −tCHCX 22 - ns

tCLCH clock rise time see Figure 27 -5-5ns

tCHCL clock fall time see Figure 27 -5-5ns

Shift register (UART mode 0)

TXLXL serial port clock cycle time see Figure 25 16Tcy(CLK) -888-ns

tQVXH output data set-up to clock

rising edge time see Figure 25 13Tcy(CLK) -722-ns

tXHQX output data hold after clock

rising edge time see Figure 25 -T

cy(CLK) + 20 - 75 ns

tXHDX input data hold after clock rising

edge time see Figure 25 -0-0ns

tXHDV input data valid to clock rising

edge time see Figure 25 150 - 150 - ns

SPI interface

fSPI SPI operating frequency

slave 0 CCLK⁄603.0MHz

master - CCLK⁄4-4.5MHz

TSPICYC SPI cycle time see Figure 26, 28,

29, 30

slave 6⁄CCLK -333-ns

master 4⁄CCLK -222-ns

tSPILEAD SPI enable lead time see Figure 29, 30

slave 250 - 250 - ns

tSPILAG SPI enable lag time see Figure 29, 30

slave 250 - 250 - ns

Product data sheet Rev. 8 — 12 Ja nuary 2011 63 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

[1] Parameters are valid over ambient temperature range unless otherwise specified.

[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

tSPICLKH SPICLK HIGH time see Figure 26, 28,

29, 30

master 2⁄CCLK -111-ns

slave 3⁄CCLK -167-ns

tSPICLKL SPICLK LOW time see Figure 26, 28,

29, 30

master 2⁄CCLK -111-ns

slave 3⁄CCLK -167-ns

tSPIDSU SPI data set-up time see Figure 26, 28,

29, 30

master or slave 100 - 100 - ns

tSPIDH SPI data hold time see Figure 26, 28,

29, 30

master or slave 100 - 100 - ns

tSPIA SPI access time see Figure 29, 30

slave 0 80 0 80 ns

tSPIDIS SPI disable time see Figure 29, 30

slave 0 160 - 160 ns

tSPIDV SPI enable to output data valid

time see Figure 26, 28,

29, 30

slave - 160 - 160 ns

master - 111 - 111 ns

tSPIOH SPI output data hold time see Figure 26, 28,

29, 30 0-0-ns

tSPIR SPI rise time see Figure 26, 28,

29, 30

SPI outputs

(SPICLK, MOSI, MISO) - 100 - 100 ns

SPI inputs

(SPICLK, MOSI, MISO, SS)- 2000 - 2000 ns

tSPIF SPI fall time see Figure 26, 28,

29, 30

SPI outputs

(SPICLK, MOSI, MISO) - 100 - 100 ns

SPI inputs

(SPICLK, MOSI, MISO, SS)- 2000 - 2000 ns

Table 13. Dynamic characteristics (18 MHz) …continued

VDD = 3.0 V to 3.6 V unless otherwise specified.

Tamb =−40 °Cto+85°C for industrial, −40 °Cto+125°C for extended, unless otherwise specified.[1][2]

Symbol Parameter Conditions Variable clock fosc =18MHz Unit

Min Max Min Max

Product data sheet Rev. 8 — 12 Ja nuary 2011 64 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

12.1 Waveforms

Fig 25. Shif t re gi s t er mode timing

0 1234567

valid valid valid valid valid valid valid valid

TXLXL

002aaa90

set TI

set RI

tXHQX

tQVXH

tXHDV

tXHDX

clock

output data

write to SBUF

input data

clear RI

Fig 26. SPI master timing (CPHA = 0)

TSPICYC

tSPICLKH

tSPICLKL

master LSB/MSB outmaster MSB/LSB out

tSPIDH

tSPIDSU

tSPIF

tSPIOH tSPIDV

tSPIR

tSPIDV

tSPIF tSPIR

SPICLK

(CPOL = 0)

(output)

002aaa908

SPICLK

(CPOL = 1)

(output)

MISO

(input)

MOSI

(output)

LSB/MSB in

MSB/LSB in

Fig 27. E xternal clock timing (with an amplitude of at least Vi(RMS) = 200 mV)

CHCL

CLCX

CHCX

cy(clk)

CLCH

002aaa90

Product data sheet Rev. 8 — 12 Ja nuary 2011 65 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

Fig 28. SPI master timing (CPHA = 1)

TSPICYC

tSPICLKL

tSPICLKH

master LSB/MSB outmaster MSB/LSB out

tSPIDH

tSPIDSU

tSPIF

tSPIOH tSPIDV

tSPIR

tSPIDV

tSPIF

tSPIR

SPICLK

(CPOL = 0)

(output)

002aaa909

SPICLK

(CPOL = 1)

(output)

MISO

(input)

MOSI

(output)

LSB/MSB in

MSB/LSB in

Fig 29. SPI slave timing (CPHA = 0)

TSPICYC

tSPICLKH

tSPICLKL

tSPILEAD tSPILAG

tSPIDSU tSPIDH tSPIDH

tSPIDSU tSPIDSU

tSPIF

tSPIA tSPIOH tSPIDIS

tSPIR

slave MSB/LSB out

MSB/LSB in LSB/MSB in

slave LSB/MSB out

tSPIDV

tSPIOH tSPIOH

tSPIDV

tSPIR

tSPIF

SPICLK

(CPOL = 0)

(input)

002aaa910

SPICLK

(CPOL = 1)

(input)

MISO

(output)

MOSI

(input)

not defined

Product data sheet Rev. 8 — 12 Ja nuary 2011 66 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

12.2 ISP entry mode

Fig 30. SPI slave timing (CPHA = 1)

002aaa911

TSPICYC

tSPICLKH

tSPICLKL

tSPILEAD

tSPICLKL

tSPILAG

tSPIDSU tSPIDSU

tSPIDH tSPIDH

tSPIF tSPIR

tSPIR

tSPIA

tSPIOH tSPIOH tSPIOH

tSPIDIS

slave MSB/LSB out

not defined

MSB/LSB in LSB/MSB in

slave LSB/MSB out

tSPIDV tSPIDV tSPIDV

tSPIR

tSPIF

SPICLK

(CPOL = 0)

(input)

SPICLK

(CPOL = 1)

(input)

MISO

(output)

MOSI

(input)

Table 14. Dynamic characteristics , ISP entry mode

VDD = 2.4 V to 3.6 V, unless otherwise specified.

Tamb =−40 °Cto+85°C for industrial, −40 °Cto+125°C for extended, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

tVR RST delay from VDD active time 50 - - μs

tRH RST HIGH time 1 - 32 μs

tRL RST LOW time 1 - - μs

Fig 31. ISP entry timing

002aaa91

RST

Product data sheet Rev. 8 — 12 Ja nuary 2011 67 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

13. Other characteristics

13.1 Comparator electrical characteristics

[1] This parameter is characterized, but not tested in production.

Table 15. Comparator electrical characteristics

VDD = 2.4 V to 3.6 V, unless otherwise specified.

Tamb =−40 °Cto+85°C for industrial, −40 °Cto+125°C for extended, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

VIO input offset volt age - - ±20 mV

VIC common-mode input voltage 0 - VDD −0.3 V

CMRR common-mode rejection ratio [1] --−50 dB

tres(tot) total response time - 250 500 ns

t(CE-OV) chip enable to output valid ti me - - 10 μs

ILI input leakage current 0 < VI<V

DD --±10 μA

Product data sheet Rev. 8 — 12 Ja nuary 2011 68 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

13.2 ADC electrical characteristics

Table 16. ADC electrical characteristics

VDD = 2.4 V to 3.6 V, unless otherwise specified.

Tamb =−40 °Cto+85°C for industrial, −40 °Cto+125°C for extended, unless otherwise specified.

All limits valid for an external source impedance of less than 10 kΩ.

Symbol Parameter Conditions Min Typ Max Unit

VIA analog input voltage VSS −0.2 - VDD +0.2 V

Ciss input capacitance - - 15 pF

EDdifferential linearity error - - ±1LSB

EL(adj) integral non-linearity - - ±1LSB

EOoffset error - - ±2LSB

EGgain error - - ±1%

Eu(tot) tot al unadjusted error - - ±2LSB

MCTC channel-to-channel matching - - ±1LSB

αct(port) cro sstalk betwe e n p ort inpu ts 0 kHz to 100 kHz - - −60 dB

SRin input slew rat e - - 100 V/ms

Tcy(ADC) ADC clock cycle time 111 - 2000 ns

tADC ADC conversion time A/D enabled - - 13Tcy(ADC) ns

Product data sheet Rev. 8 — 12 Ja nuary 2011 69 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

14. Package outline

Fig 32. Package outline SOT261-2 (PLCC28)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

SOT261-2 112E08 MS-018 EDR-7319

511

detail X

(A )

vMB

vMA

0 5 10 mm

scale

99-12-27

01-11-15

pin 1 index

PLCC28: plastic leaded chip carrier; 28 leads SOT261-

UNIT β

mm 4.57

4.19 0.51 3.05 0.53

0.33

0.021

0.013

1.27 2.16

45o

0.18 0.10.18

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

11.58

11.43

12.57

12.32 2.16

0.81

0.66

1.22

1.07

0.180

0.165 0.02 0.12

0.25

0.01 0.05 0.085

0.007 0.0040.007

1.44

1.02

0.057

0.040

0.456

0.450

11.58

11.43

0.456

0.450

0.495

0.485

12.57

12.32

0.495

0.485

10.92

9.91

0.43

0.39

10.92

9.91

0.43

0.39 0.085

0.032

0.026

0.048

0.042

inches

AA1

min.

max. bpeywvD(1) E(1) HDHEZD(1)

max. ZE(1)

max.

b1kA3Lp

eDeE

Product data sheet Rev. 8 — 12 Ja nuary 2011 70 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

Fig 33. Package outline SOT361-1 (TSSOP28)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

9.8

9.6

4.5

4.3 0.65 6.6

6.2

0.4

0.3

0.8

0.5

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT361-1 MO-153 99-12-27

03-02-19

0.25

114

28 15

pin 1 index

detail X

(A )

vMA

0 2.5 5 mm

scale

SSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361

-1

max.

1.1

Product data sheet Rev. 8 — 12 Ja nuary 2011 71 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

Fig 34. Package outline SOT788-1 (HVQFN28)

0.651

A1Eh

UNIT ye

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 6.1

5.9

6.1

5.9

4.25

3.95

4.25

3.95

3.9

0.35

0.25

0.05

0.00 0.2 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT788-1 MO-220- - - - - -

0.75

0.50

0.1

0.05

0 2.5 5 mm

scale

SOT788

-1

VQFN28: plastic thermal enhanced very thin quad flat package; no leads;

8 terminals; body 6 x 6 x 0.85 mm

A(1)

max.

AA1

detail X

y1C

814

28 22

02-10-22

terminal 1

index area

terminal 1

index area

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1) E(1)

Product data sheet Rev. 8 — 12 Ja nuary 2011 72 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

15. Abbreviations

Table 17. Acronym list

Acronym Description

A/D Analog to Digital

CPU Central Processing Unit

DAC Digital to Analog Converter

EPROM Erasable Programmable Read-Only Memory

EEPROM Electrically Erasable Programmable Read-Only Memory

EMI Electro-Magnetic Interference

LED L ight Emitting Diode

PWM Pulse Width Modulator

RAM Random Access Memory

RC Resistance-Capacitance

RTC Re al-Time Clock

SAR Successive Approximation Register

SFR Special Function Register

SPI Serial Peripheral Interface

UART Universal Asynchronous Receiver/Transmitter

Product data sheet Rev. 8 — 12 Ja nuary 2011 73 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

16. Revision history

Table 18. Revision history

Document ID Release

date Data sheet status Change notice Supersedes

P89LPC933_934_ 935_936 v.8 20110112 Product data sheet - P89LPC933_934_ 935_936 v.7

Modifications: •Table 10 “Limiting values”: Changed Vn max to 5.5 V.

•Table 11 “Static characteristics”: Added VPOR.

•Table 16 “ADC electrical characteristics”: Corrected VIA max.

•Section 8.16 “Reset”: Added sentence “When this pin functions as a reset input....”

P89LPC933_934_ 935_936 v.7 20081126 Product data sheet - P89LPC933_934_ 935_936 v.6

P89LPC933_934_ 935_936 v.6 20050620 Product data sheet - P89LPC933_934_ 935_936 v.5

P89LPC933_934_ 935_9 36 v.5 20041103 Product data sheet - P89LPC933_934_ 935 v.4

P89LPC933_934_ 935 v.4 20040209 Objective data - P89LPC933_934_ 935 v.3

Product data sheet Rev. 8 — 12 Ja nuary 2011 74 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

17.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict wit h the short data sheet, th e

full data sheet shall pre va il.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agr eed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

17.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability t owards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suit able for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applicati ons or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo m er(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semic onductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by cust omer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains dat a from the objective specificati on for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.

Product [short] data sheet Production This document contains the prod uct specification.

Product data sheet Rev. 8 — 12 Ja nuary 2011 75 of 77

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for aut omotive use. It i s neither qua lified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in au tomotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims resulting f rom customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

17.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

I2C-bus — logo is a trademark of NXP B.V.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 8 — 12 Ja nuary 2011 76 of 77

continued >>

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

19. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1

2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 2

3 Product comparison overview . . . . . . . . . . . . . 3

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

7 Logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . 11

8 Functional description . . . . . . . . . . . . . . . . . . 12

8.1 Special function registers . . . . . . . . . . . . . . . . 12

8.2 Enhanced CPU. . . . . . . . . . . . . . . . . . . . . . . . 24

8.3 Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.3.1 Clock definitions . . . . . . . . . . . . . . . . . . . . . . . 24

8.3.2 CPU clock (OSCCLK). . . . . . . . . . . . . . . . . . . 24

8.3.3 Low speed oscillator option . . . . . . . . . . . . . . 24

8.3.4 Medium speed oscillator option . . . . . . . . . . . 24

8.3.5 High speed oscillator option . . . . . . . . . . . . . . 24

8.3.6 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.4 On-chip RC oscillator option. . . . . . . . . . . . . . 25

8.5 Watchdog oscillator option . . . . . . . . . . . . . . . 25

8.6 External clock input option . . . . . . . . . . . . . . . 25

8.7 CCLK wake-up delay . . . . . . . . . . . . . . . . . . . 27

8.8 CCLK modification: DIVM register . . . . . . . . . 27

8.9 Low power select . . . . . . . . . . . . . . . . . . . . . . 27

8.10 Memory organization . . . . . . . . . . . . . . . . . . . 27

8.11 Da ta RAM arrangement . . . . . . . . . . . . . . . . . 28

8.12 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.12.1 External interrupt inputs . . . . . . . . . . . . . . . . . 28

8.13 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.13.1 Port configurations . . . . . . . . . . . . . . . . . . . . . 30

8.13.1.1 Quasi-bidirectional output configuration . . . . . 30

8.13.1.2 Open-drain output confi guration. . . . . . . . . . . 30

8.13.1.3 Input-only configuration . . . . . . . . . . . . . . . . . 31

8.13.1.4 Push-pull output configuration . . . . . . . . . . . . 31

8.13.2 Port 0 analog functions. . . . . . . . . . . . . . . . . . 31

8.13.3 Additional port features. . . . . . . . . . . . . . . . . . 31

8.14 Power monitoring functions . . . . . . . . . . . . . . 31

8.14.1 Brownout detection. . . . . . . . . . . . . . . . . . . . . 32

8.14.2 Power-on detection. . . . . . . . . . . . . . . . . . . . . 32

8.15 Power reduction modes . . . . . . . . . . . . . . . . . 32

8.15.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.15.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . 32

8.15.3 Total Po we r-d o w n mode . . . . . . . . . . . . . . . . 33

8.16 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.16.1 Reset vector. . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.17 Timers/counters 0 and 1 . . . . . . . . . . . . . . . . 34

8.17.1 Mode 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.17.2 Mode 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.17.3 Mode 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.17.4 Mode 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.17.5 Mode 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.17.6 Timer overflow toggle output . . . . . . . . . . . . . 34

8.18 RTC/system timer . . . . . . . . . . . . . . . . . . . . . 34

8.19 CCU (P89LPC935/936) . . . . . . . . . . . . . . . . . 35

8.19.1 CCU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.19.2 CCUCLK prescaling. . . . . . . . . . . . . . . . . . . . 35

8.19.3 Basic timer operation. . . . . . . . . . . . . . . . . . . 35

8.19.4 Output compare. . . . . . . . . . . . . . . . . . . . . . . 35

8.19.5 Input capture . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.19.6 PWM operation . . . . . . . . . . . . . . . . . . . . . . . 36

8.19.7 Alternating output mode. . . . . . . . . . . . . . . . . 37

8.19.8 PLL operation. . . . . . . . . . . . . . . . . . . . . . . . . 37

8.19.9 CCU interrupts. . . . . . . . . . . . . . . . . . . . . . . . 38

8.20 UART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.20.1 Mode 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.20.2 Mode 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.20.3 Mode 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.20.4 Mode 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.20.5 Baud rate generator and selection. . . . . . . . . 39

8.20.6 Framing error. . . . . . . . . . . . . . . . . . . . . . . . . 39

8.20.7 Break detect. . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.20.8 Double buffering. . . . . . . . . . . . . . . . . . . . . . . 40

8.20.9 Transmit interrupts with double

buffering enabled (modes 1, 2 and 3) . . . . . . 40

8.20.10 The 9th bit (bit 8 ) in double

buffering (modes 1, 2 and 3) . . . . . . . . . . . . . 40

8.21 I2C-bus serial interface. . . . . . . . . . . . . . . . . . 41

8.22 SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.22.1 Typical SPI configurations . . . . . . . . . . . . . . . 44

8.23 Analog comparators. . . . . . . . . . . . . . . . . . . . 46

8.23.1 Internal reference voltage . . . . . . . . . . . . . . . 46

8.23.2 Comparator interrupt . . . . . . . . . . . . . . . . . . . 47

8.23.3 Co mparators and power reduction modes. . . 47

8.24 Keypad interrupt. . . . . . . . . . . . . . . . . . . . . . . 47

8.25 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 48

8.26 Additional features. . . . . . . . . . . . . . . . . . . . . 48

8.26.1 Software reset . . . . . . . . . . . . . . . . . . . . . . . . 48

8.26.2 Dual data pointers . . . . . . . . . . . . . . . . . . . . . 48

8.27 Data EEPROM (P89LPC935/936). . . . . . . . . 49

8.28 Flash program memory . . . . . . . . . . . . . . . . . 49

NXP Semiconductors P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 12 January 2011

Document identifier: P89LPC933_934_935_936

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

8.28.1 General description . . . . . . . . . . . . . . . . . . . . 49

8.28.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.28.3 Flash organization . . . . . . . . . . . . . . . . . . . . . 50

8.28.4 Using flash as data storage . . . . . . . . . . . . . . 50

8.28.5 Flash programming and erasing. . . . . . . . . . . 50

8.28.6 In-circuit programming . . . . . . . . . . . . . . . . . . 50

8.28.7 In-application programming . . . . . . . . . . . . . . 50

8.28.8 ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8.28.9 Power-on reset code execution . . . . . . . . . . . 51

8.28.10 Hard ware activation of the boot loader. . . . . . 52

8.29 User configuration bytes. . . . . . . . . . . . . . . . . 52

8.30 User sector security bytes . . . . . . . . . . . . . . . 52

9 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9.1 General description . . . . . . . . . . . . . . . . . . . . 52

9.2 Features and benefits. . . . . . . . . . . . . . . . . . . 52

9.3 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . 53

9.4 A/D operating modes . . . . . . . . . . . . . . . . . . . 53

9.4.1 Fixed channel, single conversion mode . . . . . 53

9.4.2 Fixed channel, continuous conversi on mode . 54

9.4.3 Auto scan, single conversion mode . . . . . . . . 54

9.4.4 Auto scan, continuous conversion mode . . . . 54

9.4.5 Dual channel, continuous conversion mode. . 54

9.4.6 Single step mode . . . . . . . . . . . . . . . . . . . . . . 54

9.5 Conversion start modes . . . . . . . . . . . . . . . . . 54

9.5.1 Timer triggered start . . . . . . . . . . . . . . . . . . . . 54

9.5.2 Start immediately . . . . . . . . . . . . . . . . . . . . . . 54

9.5.3 Edge triggered . . . . . . . . . . . . . . . . . . . . . . . . 55

9.5.4 Dual start immediately (P89LPC935/936) . . . 55

9.6 Boundary limits interrupt. . . . . . . . . . . . . . . . . 55

9.7 DAC output to a port pin with high output

impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9.8 Clock divider. . . . . . . . . . . . . . . . . . . . . . . . . . 55

9.9 Power-down and Idle mode . . . . . . . . . . . . . . 55

10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 56

11 Static characteristics. . . . . . . . . . . . . . . . . . . . 57

11.1 IOH as a function of VOH . . . . . . . . . . . . . . . . . 59

12 Dynamic characteristics . . . . . . . . . . . . . . . . . 60

12.1 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

12.2 ISP entry mode. . . . . . . . . . . . . . . . . . . . . . . . 66

13 Other characteristics. . . . . . . . . . . . . . . . . . . . 67

13.1 Comparator electrical characteri stics . . . . . . . 67

13.2 ADC electrical characteristics. . . . . . . . . . . . . 68

14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 69

15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 72

16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 73

17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 74

17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 74

17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 74

17.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 75

18 Contact information . . . . . . . . . . . . . . . . . . . . 75

19 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76