Application Report SPRA063A - January 2002 How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs Victor J. Gallardo C6000 DSP Software Solutions ABSTRACT Development is available for systems using the Texas Instruments TMS320C6202, C6203B, and the latest additions -- the TMS320C6202C, 03C and C6204. Due to the compatibility between TMS320C6000 generation devices, current C6000 tools are used to develop code for these and other future devices. This allows for systems functional when silicon becomes available. This document briefly describes the similarities and differences between the C6202/02C/03B/03C/04 Digital Signal Processors and serves as a reference for designers migrating between the C6202/02C/03B/03C/04, either for performance improvement or improved feature set. Contents 1 Development With the TMS320C6202 and TMS320C6202C DSPs . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 C6202 and C6201 DSP Similarities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 C6202 and C6201 DSP Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Development With the TMS320C6203 DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 C6203B and C6202 DSP Similarities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 C6203B and C6202 DSP Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 C6203B and C6203C DSP Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Development With the TMS320C6204 DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 C6204 and C6202 DSP Similarities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 C6204 and C6202 DSP Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 TMS320C6000 Code Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 Writing Code for the C6202/02C/03B/03C/04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 Designing C6203 Software for Memory Map Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 Designing C6204 Software for Memory Map Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 TMS320C6202/03/04 Hardware Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 PLL Options on the TMS320C6202/02C/03B/03C/04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Designing to Achieve Performance With the C6202/02C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 6 7 7 TMS320C6000 and C6000 are trademarks of Texas Instruments Incorporated. Trademarks are the property of their respective owners. 1 SPRA063A 7 Designing to Achieve Performance With the C6203B/03C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 Designing to Achieve Performance With the C6204 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 IBIS Modeling for the 6202C, 6203B Rev. 3 and 6203C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.1 Determining Compatibility Between the 6203C DSP and MT48LC2M32B2 SDRAM . . . . . . 21 10 C6000 Tools Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11 C6000 Literature Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 TMS320C6200 Fixed-Point Roadmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 TMS320C6202 and C6202C Digital Signal Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 TMS320C6203B/03C Digital Signal Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TMS320C6204 Digital Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DSP Target Device Perception of Board Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 List of Tables Table 1 Table 2 Table 2 Table 3 Table 4 Table 5 1 TMS320C6202/02C/03B/03C/04 Comparison Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TMS320C6202/02C/03B/03C/04 PLL Multiply and Bypass (x1) Options . . . . . . . . . . . . 13 TMS320C6202/02C/03B/03C/04 PLL Multiply and Bypass (x1) Options (Continued) . . 14 TMS320C6202/02C/03B/03C/04 CLKMODE Pins Compatibility for GLS (GNY for `03C,GLW for '04) Package (18mm sq. 384-pin BGA) . . . . . . . . . . . . . . . . . . . . 14 TMS320C6202/02C/03C CLKMODE Pins Compatibility for GJL Package (27mm sq. 352-pin BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Minimum and Maximum Route Lengths and Impedance Used to Determine 6202C, 6203B and 6203C EMIF Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Development With the TMS320C6202 and TMS320C6202C DSPs The Texas Instruments TMS320C6000 platform of high-performance digital signal processors now includes the TMS320C6202C in addition to the existing C6202. The C6202 and C6202C are large-memory versions of the original C6000 device, C6201. Similar to the C6202, the C6202C is capable of achieving 2000 MIPS (million instructions per second) at 250 MHz. Introduced in February 1997, the C6000 platform is based on TI's VelociTI architecture, an advanced, long instruction word (VLIW) architecture for DSPs. Figure 1 illustrates the roadmap for the fixed-point generation of the C6000 platform. VelociTI is a trademark of Texas Instruments Incorporated. 2 How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs SPRA063A Better technology loer power High performance 1.5*PMEM 4*DMEM 4*PMEM 2*DMEM 32-bit XBUS 0.18 micron technology 2 Mbit program memory 1 Mbit data memory 32-bit expansion bus C6201 200 MHz 0.18 micron technology 512 Kbit program memory 512 Kbit data memory Low cost two-level cache enhanced DMA 1997 C6202 200-250 MHz C6211 150-167 MHz 0.18 micron technology L1/L2 memory 4 KB L1 program cache 4 KB L1 data cache 64 KB L2 cache SRAM 1998 C6203B 250-300 MHz Better technology, low power, more PLL modes 0.15 micron technology 3 Mbit program memory 4 Mbit data memory 32-bit expansion bus 0.12 micron technology 3 Mbit program memory 4 Mbit data memory 32-bit expansion bus C6202C 300 MHz 0.12 micron technology 2 Mbit program memory 1 Mbit data memory 32-bit expansion bus Better technology, lower power, C6201 memory size, more PLL modes PCI 2.2 compliant low power C6201 memory size C6203C 300 MHz C6204 200-250 MHz Better technology lower power 0.15 micron technology 512 Kbit program memory 512 Kbit data memory 32-bit expansion bus C6205 200-250 MHz 0.15 micron technology 512 Kbit program memory 512 Kbit data memory 32-bit 33 MHz PCI 2.2 1999 2000 Figure 1. TMS320C6200 Fixed-Point Roadmap The 32-bit expansion bus (XB) supports interfaces to a variety of asynchronous peripherals, asynchronous or synchronous FIFOs, PCI Bridge chips, and other external masters. Thus, the XB provides additional bandwidth by complementing the EMIF. The XB also provides either a synchronous (master and slave mode) or asynchronous (slave mode similar to the C6201) host port interface (HPI). The synchronous mode provides higher throughput in the range of 133-266 Mbps per second, an improvement of four to eight times over the C6201 HPI. The expansion bus is the lone different aspect of the C6202; while the internal memories are much larger on the C6202, their functionality is equivalent to those of the C6201. In addition to the CPU, many of the on-chip peripherals are common between C6000 devices. Figure 2 illustrates a diagram of the C6202/02C DSP's roadmap. The blocks shaded gray are common to the C6201 devices and the C6202/02C. How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs 3 SPRA063A C6202/02C Digital Signal Processor External Memory Interface (EMIF) Program Access/Cache Controller Internal Program Memory 1 Block Mapped Program 1 Block Program/Cache (128K bytes each) (256K bytes each) Interrupt Selector Timer0 C6200 B/C CPU In-Circuit Emulation Instruction Decode Data Path 1 Data Path 2 A Register File L1 Multi-Channel Buffered Serial Port 2 (McBSP2) Expansion Bus Instruction Dispatch S1 M1 D1 B Register File D2 M2 S2 Interrupt Control Multi-Channel Buffered Serial Port 1 (McBSP1) Control Registers Instruction Fetch Peripheral Control Bus Multi-Channel Buffered Serial Port 0 (McBSP0) DMA Bus Timer1 L2 Boot Configuration Direct Memory Access Controller (DMA) Power Down Logic Data Access Controller Internal Data Memory (128K bytes) 2 Blocks 4 Banks Each PLL Figure 2. TMS320C6202 and C6202C Digital Signal Processors 1.1 C6202 and C6201 DSP Similarities The C6202 is highly-compatible with the first C6000 device, the C6201. The following device components are identical between the devices: 4 * CPU: The CPU of the C6202 is identical to that of the C6201, which means that code written for the C6201 will run unmodified on the C6202. * Multi-Channel Buffered Serial Ports (McBSPs): The McBSPs are unchanged on the C6202. * Direct Memory Access (DMA) Controller: The DMA transfers data between any two locations in the memory map. * 32-Bit Timers: Two timers are on the C6202. * Interrupt Selection: There are 16 interrupt sources that may be used to interrupt the CPU or send an event to the DMA. How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs SPRA063A 1.2 C6202 and C6201 DSP Differences Several enhancements have been made to allow the C6202 greater performance capability. These include: 2 * Faster Clock Rate: The maximum clock frequency has been increased from 200 MHz to 250 MHz. This increased frequency allows the C6202 to achieve 2000 MIPS performance. * Larger Internal Memory Space: The internal data and program memories have been significantly increased in size. The internal data memory has been increased two-fold from 64Kbytes on the C6201 to 128Kbytes. Internal program memory has been quadrupled, with 256Kbytes available. A 128Kbyte block of the program memory is selectable as program cache. * External Memory Interface (EMIF): The EMIF has been modified slightly to reduce the pin count of the C6202. Synchronous DRAM (SDRAM) and Sync-Burst SRAM (SBSRAM) share control signals on the EMIF bus. The two are mutually exclusive, so only one of the two memory types is permissible in a system. * Expansion Bus (XB): The expansion bus has been added to the C6202 to replace the Host-Port Interface (HPI) of the C6201. The C6202 offers a glue-less interface to PCI bridge chips, synchronous industry-standard buses, synchronous FIFO memories, and asynchronous peripherals. Development With the TMS320C6203 DSP The Texas Instruments TMS320C6000 platform of high-performance digital signal processors now includes the TMS320C6203B and C6203C. The C6203B and C6203C provide up to 2400 MIPS (million instructions per second) at 300 MHz. The C6203B/03C is a larger-memory and faster clock speed version of it's predecessor, the C6202. Due to improved process, the higher performance C6203B DSPs operate at lower power levels than the C6202 or the C6201. The C6203B DSPs boast of a large on-chip memory for a single core and thus eliminates the need for external memory. The 0.15 m L-effective process technology delivers low power consumption of about 1.5 W (0.9 mA/MIPS); the 0.12 m L-effective process technology delivers even lower power consumption. The two 32-bit buses (one via the EMIF and the other via the XB), similar to the C6202, maximize bandwidth. All the features just described make the C6203 DSPs the right candidates for high performance, high density, and possibly a single-chip solution for most applications. In addition to the CPU, many of the on-chip peripherals are common between C6000 devices. Figure 3 illustrates a diagram of the C6203B/03C DSP's roadmap. Blocks shaded gray are common to the C6202 and C6203B DSPs. How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs 5 SPRA063A C6203/03C Digital Signal Processor External Memory Interface (EMIF) Program Access/Cache Controller Internal Program Memory 1 Block Mapped Program (256K bytes) 1 Block Program/Cache (128K bytes) Interrupt Selector Timer 0 Multi-Channel Buffered Serial Port 1 (McBSP1) Expansion Bus Instruction Dispatch In-Circuit Emulation Instruction Decode Data Path 1 Data Path 2 A Register File L1 S1 M1 D1 Multi-Channel Buffered Serial Port 2 (McBSP2) Control Registers Instruction Fetch B Register File D2 M2 S2 Interrupt Control Multi-Channel Buffered Serial Port 0 (McBSP0) DMA Bus Timer 1 Peripheral Control Bus C6200C CPU L2 Boot Configuration Direct Memory Access Controller (DMA) Power Down Logic Data Access Controller Internal Data Memory (256K bytes) 2 Blocks 4 Banks each PLL Figure 3. TMS320C6203B/03C Digital Signal Processors 2.1 C6203B and C6202 DSP Similarities The C6203B is highly compatible with the C6202. The following device components are identical between the devices: 6 * CPU: The CPU of the C6203B is identical to that of the C6202, which means that code written for the C6202 will run unmodified on the C6203B. * * Multi-Channel Buffered Serial Ports (McBSPs): The McBSPs are unchanged on the C6203B. * * 32-Bit Timers: are unchanged on the C6203B. * External Memory Interface (EMIF): The 32-bit memory interface is unchanged on the C6203B. Direct Memory Access (DMA) Controller: The DMA transfers data between any two locations in the memory map. Interrupt Selection: There are 16 interrupt sources that may be used to interrupt the CPU or send an event to the DMA. How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs SPRA063A * * * 2.2 Expansion Bus (XB): The 32-bit XB is unchanged on the C6203B. Package Options: Both C6202 and C6203B offer two package choices - 27mm sq. and 18mm sq. BGA. The pin out for both packages has been preserved (note the different voltage levels on internal power supply - see below) I/O Voltage Level: The I/O voltage remains unchanged at 3.3 V (but core voltage has changed, see below). C6203B and C6202 DSP Differences Several enhancements have been made to allow the C6203B for greater performance capability. These include: * Faster Clock Rate: The maximum clock frequency has been increased from 250 MHz to 300 MHz. This increased frequency will allow the C6203B to achieve 2400 MIPS during operation. * More PLL Multiply Options: In addition to x1 and x4 modes that already exist on the C6202, the C6203B features six additional PLL modes (x6, x7, x8, x9, x10 and x11) on the GLS 384-pin BGA package, and two additional PLL modes (x8, and x10) on the GJL 352-pin BGA package. * Lower Power Consumption: The C6203B is manufactured using an improved process resulting in a smaller die with lower power consumption, even as the internal memory has been increased from 3mb (384Kbytes) to 7mb (896 Kbytes). * Core Voltage Level: The core power supply has been reduced from 1.8 V to 1.5 V due to improved process technology. The I/O voltage remains unchanged at 3.3 V. * Larger Internal Memory Spaces: The internal data and program memories have been significantly increased in size. The internal data memory has been increased four fold from 128Kbytes on the C6202 to 512Kbytes on the C6203B. Internal program memory has increased one and one-half times from 256Kbytes to 384Kbytes. A 128Kbyte block of the program memory is still selectable as program cache. * Improved PLL: The PLL circuitry on the C6203B requires new component values for correct operation. These new components reduce the internal jitter. They can be found in table 1. * IBIS Modeling: C6203B Rev 3.x takes into account board level constants, such as signal route delays. See the IBIS modeling section near the end of this application note for further details. 2.3 C6203B and C6203C DSP Differences The C6203C is an enhanced version of the C6203B DSPs in terms of more advanced process technology. The new process technology yields improved speed with lower power consumption. The C6203C differs from the C6203B in the following features: * Process Technology: The C6203C uses the next process generation 0.12m/6-level Metal Process. This process yields a lower core voltage and lower power dissipation. * Speed: The C6203B runs at 250 MHz and 300 MHz. The C6203C is capable of core clock speeds up to 300 MHz. * Lower Core Voltage: C6203C requires only 1.2 V to power the core due to the 12C035 process technology * PLL Options: For GNZ package the PLL options are x1, x4, x8 and x12. For GNY package the options are x1, x4, x6, x8, x12. How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs 7 SPRA063A 3 * PLL External Components: The C6203C does not require external components but they are recommended for complete compatibly with C6202C and C6203B * IBIS Modeling: C6203C takes into account board level constants, such as signal route delays. See the IBIS modeling section near the end of this application note for further details. Development With the TMS320C6204 DSP The Texas Instruments TMS320C6204 is a new addition to the family of high-performance and flagship digital signal processors - the TMS320C6000. (see Figure 1). The C6204 is derived from the C6202 and delivers 1600MIPS at 200 MHz. In addition to the CPU, many of the on-chip peripherals are common between C6000 devices. The C6204 derives its peripheral set from the C6202 and the internal memory architecture from the C6201. Figure 4 illustrates a diagram of the C6204 DSP's roadmap. Those blocks shaded gray are common to the C6202 and C6204. C6204 Digital Signal Processor External Program Access/Cache Memory Controller Interface Internal Program Memory 1 Block Program/Cache (64K bytes each) Interrupt (EMIF) Selector C6200C CPU Timer 0 Control Buffered Serial Port 0 Registers Instruction Dispatch Data Path 1 Data Path 2 A Register File L1 (McBSP0) In-Circuit Emulation Instruction Decode B Register File S1 M1 D1 D2 M2 S2 Interrupt Control Multi-Channel DMA Bus Timer 1 Peripheral Control Bus Instruction Fetch L2 Multi-Channel Boot Buffered Configuration Serial Port 1 Data Internal Data Memory Power Access (64K bytes) Down Logic Controller (McBSP1) Expansion Bus Direct Memory Access Controller (DMA) 2 Blocks 4 Banks each PLL Figure 4. TMS320C6204 Digital Signal Processor 8 How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs SPRA063A 3.1 C6204 and C6202 DSP Similarities The C6204 is highly compatible with the C6202. The following device components are identical between the devices: 3.2 * CPU: The CPU of the C6204 is identical to that of the C6202, which means that code written for the C6202 will run unmodified on the C6204. * Multi-Channel Buffered Serial Ports (McBSPs): The McBSPs are unchanged on the C6204 except that there are two McBSPs in C6204 whereas the C6202 has three. * Direct Memory Access (DMA) Controller: The DMA transfers data between any two locations in the memory map. * 32-Bit Timers: are unchanged on the C6204. * Interrupt Selection: There are 16 interrupt sources that may be used to interrupt the CPU or send an event to the DMA. * External Memory Interface (EMIF): The 32-bit memory interface is unchanged on the C6204. * Expansion Bus (XB): The 32-bit XB is unchanged on the C6204. * I/O Voltage Level: The I/O voltage remains unchanged at 3.3 V (but core voltage has changed, see below). C6204 and C6202 DSP Differences The following are the differences to keep in mind when migrating between the C6202 and the C6204 devices. * Internal Memory: The internal memory of the C6204 is similar to the C6201 with 64Kbytes of program memory/cache and 64Kbytes of data memory organized as two blocks. * Multi-Channel Buffered Serial Ports (McBSPs): The McBSPs are unchanged on the C6202 except that there are two McBSPs in C6204 whereas the C6202 has three. * Package Options: The C6204 will be available in the 18mm sq. BGA package as well as a 16mm sq. BGA package. The pin-out for the 18mm package has been preserved and thus is pin-compatible with the 18mm C6202 family. Note the different voltage levels on internal power supply - see below. * Lower Power Consumption: The C6204 is manufactured using the improved 0.15 m process resulting in a smaller die with lower power consumption * Lower Core Voltage: The core voltage is reduced to 1.5 V since it uses a 0.15 m process technology - the 15C05. The I/O supply remains unchanged at 3.3 V. How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs 9 SPRA063A 4 TMS320C6000 Code Compatibility All C6000 devices are code-compatible with one another, the only exception being that there are some floating-point instructions that are only valid on the floating-point (C67x) members. All of the C6200 fixed-point devices are based on the same CPU core designed to achieve high performance through increased instruction-level parallelism. Surpassing the throughput of traditional superscalar designs, VelociTI provides eight execution units, including two multipliers and six arithmetic logic units (ALUs). These units operate in parallel and can perform up to eight instructions during a single clock cycle--up to 2400 MIPS at 300 MHz. VelociTI's advanced features include instruction packing, conditional branching, variable-width instructions, and pre-fetched branching, all of which eliminate problems that were previously associated with VLIW implementations. The architecture is highly deterministic, with few restrictions on how or when instructions are fetched, executed, or stored. This architectural flexibility is key to the breakthrough efficiency levels of the C6000 compiler. This common architecture allows designers to begin development with existing C6000 software tools for those devices currently in development. This also allows for migration from one C6000 processor to another, as design requirements necessitate. 4.1 Writing Code for the C6202/02C/03B/03C/04 The identical CPUs in the C620x devices allow for code to be written for the C6202/02C/03B/03C/04 using existing C6000 tools. C6201 code will require no modification to use on the C6202, C6202C, C6203B, C6203C, and C6204. All peripheral-specific code, with the exception of the expansion bus, will also be able to run unchanged on the C6202. Note that the C6202, C6202C, C6203B, C6203C, and the C6204 share the same peripheral set (except that the C6204 has one less McBSP) and therefore the peripheral-specific code is also compatible between these devices. This high level of compatibility between the two processors allows for system development to begin now. By taking advantage of the C6000 software tools currently available, C6202C/C6203C systems can have a running start for when silicon becomes available. The C6000 compiler may be used for all members of the C6000 device platform. Fixed-point devices are object code compatible, so code written for the C6201 may be used for the new devices. Code development for the C6000 family may begin using the fast C6000 simulator. The simulator provides a cycle-accurate accounting of device performance, assuming that all on-chip memory is used for code and data. The simulator provides a good environment to learn the C6000 VLIW architecture. The standard C6000 simulator may be used to incorporate peripheral support. C6000 designs may be worked out in detail on the simulator prior to purchasing actual silicon, with cycle-accurate accounting of peripherals performance. For a development start in hardware, the C6201 EVM may be used to understand the C6000 functionality. With the exception of the expansion bus, all of the peripherals on the C6202/C6202C/C6203B/C6203C/C6204 are identical to those of the C6201, so the EVM is a good tool to understand how to incorporate the peripherals into a real-time system. 10 How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs SPRA063A Performance will significantly improve when migrating from the C6201 to the C6202/C6202C/C6203B/C6203C/C6204, due to the combination of increase in on-chip memory locations, faster clock, more advanced process technology, and the addition of the 32-bit expansion bus (XB). For systems that have already been designed using the C6202, the same code can be used to run on the newer C6202C, C6203B, C6203C, and C6204. Note that the C6204 has an internal memory size (64KB Program and 64KB Data memory) similar to the C6201 and hence the code that may have occupied the complete memory space of the C6202 may have to be partly placed in external memory. Using these development platforms, as well as the C6000 literature currently available will enable C6202/C6202C/C6203B/C6203C/C6204 systems to be completed in a timely manner. 4.2 Designing C6203 Software for Memory Map Compatibility While the address ranges of the added program and data memory to the C6203B/03C completely overlap the corresponding smaller C6202 blocks, the block assignments within the larger memory ranges have changed. Memory locations previously located in one block on the C6202 can now end up in another block if the same s/w is executed on the C6203B/03C. To review, each internal program and data space is split between two blocks. This feature allows the CPU to be executing program from one of the blocks, while the DMA is simultaneously loading the next segment of the code into the other block, with an assurance of no memory conflicts and resulting lost cycles. Similarly, both sides of the CPU assure simultaneous access of internal data, without any conflicts provided each side uses a different memory block. Since the C6203B/03C memory map is a superset of the C6202 memory, the C6202 code will run on the C6203B/03C without modification. However, if the original code used blocking to minimize memory access conflicts, in order to preserve the original blocking intent, the logical to physical memory mapping must be changed at the linker level. Depending on the application, this may not be necessary, as any cycles lost due to increased memory conflicts may be negated by the higher operating frequency of the C6203B/03C devices. 4.3 Designing C6204 Software for Memory Map Compatibility The internal memory configuration of the C6204 is similar to the C6201 so any programs written for the C6201 do not require any changes and no special considerations are necessary. When migrating from C6202/02C/03B/03C to C6204, a revision of memory locations is required because the C6204 internal memory map size has been reduced in different sections when compared to these other members of the C6000 platform How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs 11 SPRA063A 5 TMS320C6202/03/04 Hardware Compatibility The C6202, C6202C, C6203B, C6203C, and C6204 are pin compatible devices thus making new system designs easier and providing faster time to market. As a quick reference, Table 1 lists the differences between these devices. Table 1. TMS320C6202/02C/03B/03C/04 Comparison Chart Hardware Feature Package C6202 C6202C 27mm x 27mm (352-pin BGA (GJL)) Same as C6203C 18mm x 18mm (384-pin BGA (GLS)) Peripheral C6203B C6203C C6204 18mm x 18mm (384-pin BGA (GNY)) 16mm x 16mm (288-pin BGA (GHK)) 18mm x 18mm (384-pin BGA (GLS) and GNY) 27mm x 27mm (352-pin BGA (GNZ)) 18mm x 18mm (384-pin BGA (GLW)) 3 McBSPs Same as C6202 3 McBSPs Same as C6203B 2 McBSPs 256KB Program 128KB Data Same as C6202 384KB Program 512KB Data Same as C6203B 64KB Program 64KB Data 200-250 300 250-300 300 200 Core/(I/O) Voltage 1.8 V/3.3 V 1.2 V/3.3 V 1.5 V/3.3 V 1.2 V/3.3 V 1.5 V/3.3 V PLL Options Bypass, x4 Bypass, x4, x6, x8, x12 Bypass, x4, x6, x7, x8, x9, x10, x11 Bypass, x4, x6, x8, x12 Bypass, x4 R1 60.4 C1 27 nF C2 560 pF R1 45.3 C1 47 nF C2 10 pF Same as C6202C Same as C6202 2005602F 2005602F 3005D02F 4005D02F 1005E02F 0002 0004 0003 0004 0003 On-chip Memory Speed (MHz) PLL Components JTAG ID CPU ID Same as C6202C GLS package 12 How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs SPRA063A 5.1 PLL Options on the TMS320C6202/02C/03B/03C/04 Various PLL options exist for the TMS320C6202/02C/03B/03C/04 devices depending on the packages. Table 2 shows which pins select the various PLL modes for the different packages. It is important that the crystals have sockets in your board design, so that moving to any of the 6202, 6202C, 6203B, 6203C, or the 6204 makes it easier to utilize the benefits of the different PLL multiply options. The new multiply options such as the x6, x7, x8, x9, x10, and the x11 makes the design cheaper by allowing the use of low frequency crystals. Table 2. TMS320C6202/02C/03B/03C/04 PLL Multiply and Bypass (x1) Options Device C6202 (GJL and GLS) C6202C (GNZ and GNY) C6203B (GJL and GNY) GJL or GNZ Package (27mm sq. 352-pin BGA) GLS or GNY Package (18mm sq. 384-pin BGA) CLKMODE[0] Mode CLKMODE[2:0] Mode 0 x1 XX0 x1 1 x4 XX1 x4 CLKMODE[1:0] Mode CLKMODE[2:0] Mode 0 x1 000 x1 1 x4 001 x4 10 x8 010 x8 11 x12 011 x12 100 x6 101 X8 110 X6 111 X8 CLKMODE[2:0] Mode 000 x1 001 x4 010 x8 011 x10 100 x6 101 X9 110 X7 111 X11 Not Applicable GHK Package (16mm sq. 288-pin BGA) Not Applicable Not Applicable Not Applicable How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs 13 SPRA063A Table 2. TMS320C6202/02C/03B/03C/04 PLL Multiply and Bypass (x1) Options (Continued) GJL or GNZ Package (27mm sq. 352-pin BGA) Device GLS or GNY Package (18mm sq. 384-pin BGA) GHK Package (16mm sq. 288-pin BGA) CLKMODE[1:0] Mode CLKMODE[2:0] Mode 00 x1 000 x1 01 x4 001 x4 10 x8 010 x8 11 x12 011 x12 100 x6 101 X8 110 X6 111 X8 01 x4 CLKMODE[0] Mode 10 x8 0 X1 11 x10 1 X4 C6203C (GNZ and GNY) ( (see N Notes t 1 1, 3) C6204 (GLS and GHK) (see Note 2) Not Applicable Not Applicable NOTES: 1. The C6203C comes in a GNY package. The GNY package is an 18mm plastic, molded package with the same pin configuration as the GLS package. 2. C6204 GLW package is a subset of the GLS package used on the 6202 and 6203 families. The GLW package is compatible with the GLS package, with the inner row of core supply and ground pins removed (see TMS320C6204 data sheet for more details). 3. The GNZ package is a 27mm plastic, molded package with the same pin configuration as the GJL package. The 18mm x 18mm GLS and GNY packages for the 6202/02C/03B/03C/04 are fully pin-compatible. The pins that select the new PLL modes on the C6202C, C6203B, and C6203C are unconnected (UC) or don't cares on the C6202 and C6204. This is shown in Table 3. Thus a C6202C/C6203B/C6203C will have the capability of selecting between the x1 and x4 modes if placed in a 6202-based board. The C6202C, C6203B, and C6203C have similar PLL modes for each package type as shown in Table 4. The converse is also true. An 18mm sq. GLS package C6202 can be placed in a similar package C6202C/03B/03C board for full operation. Table 3. TMS320C6202/02C/03B/03C/04 CLKMODE Pins Compatibility for GLS (GNY for `03C,GLW for '04) Package (18mm sq. 384-pin BGA) PLL Selection Pins 14 C6202 C6202C C6203B C6203C C6204 CLKMODE[0] Pin B12 CLKMODE[1] Pin A9 UC UC CLKMODE[2] Pin A14 UC UC How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs SPRA063A Table 4. TMS320C6202/02C/03C CLKMODE Pins Compatibility for GJL Package (27mm sq. 352-pin BGA) PLL Selection Pins C6202 C6202C C6203C CLKMODE[0] Pin B15 CLKMODE[1] Pin C11 GND CLKMODE[2] Does Not Exist Does Not Exist Does Not Exist For the case of 27mm sq. GJL package, the CLKMODE[1] pin that selects the additional new modes (see Table 2) on C6202C, and C6203C. It is a ground pin on the C6202 as shown in Table 4. Thus a C6202C/03C will have the capability of selecting between the x1 and x4 modes if placed in a 6202 socket. Conversely, caution should be exercised for the following case. If a C6202 is placed in a C6202C/03B/03C board with the CLKMODE[1] pin pulled to the non-default state (default is GND) there will be current drawn through the pull-up (3.3 V/20K or 165 uA). If a C6202 is placed in a C6202C/03B/03C board with the pins directly to the VCC plane for the new modes, there will be a ground/power short through the package. 5.2 Power Supply Considerations All C6000 devices require two voltage levels to power the device. They are the core voltage and I/O voltage. The I/O voltage remains the same at 3.3 V across all these devices. The core voltage reduces as better process technologies are used for fabrication. The core voltage of the C6202 is 1.8 V since it uses the 18C05 or 0.18 m process technology. Because the C6203B/04 is manufactured using a better (0.15 m) process technology (15C05), it requires a 1.5 V core voltage. The C6202C and C6203C is manufactured using a smaller process (0.12 m, 12C035) and requires a 1.2 V core voltage. An existing C6202 board can easily be migrated to the C6202C, C6203B, C6203C, or the C6204 by changing/removing (as applicable) the resistors of the power supply module used. Or if a programmable power supply module is used, the output voltage of such a module can be changed by programming the pins to a '1' or '0' as required. Some example application notes for power sequencing and power supply design can be found on the TI web at: http://www.ti.com How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs 15 SPRA063A 6 Designing to Achieve Performance With the C6202/02C The enhancements made to the design of the C6201 allow the C6202 to offer twice the system I/O and 25 percent higher performance in fixed-point MIPS. The improved performance of the CPU comes in part from the increased device clock rate of 250 MHz, allowing for 2000 MIPS, but primarily from the additional internal memory and the new expansion bus. The C6202 offers three times the internal memory space of the C6201, with 256Kbytes of program memory and 128Kbytes of data memory. By providing more on-chip memory, designers will be able to keep more critical code sections and data in fast, quick-access memories. This will allow the CPU to maintain its high performance capability of 2000 MIPS over a wide range of applications. The internal program memory of the C6202 is divided into two 128Kbyte blocks. One block is configured as either mapped RAM or as cache, with the other fixed as mapped RAM. This option allows for critical code to stay in internal memory while still having the added performance and flexibility of cache. If the program space is configured entirely as RAM, the dual-block structure allows for the DMA to transfer new sections of code into one block while the CPU is running from the other. This provides system designers with a means to easily schedule their own program-paging scheme. The internal data memory of the C6202 is configured as it is on the C6201, with two blocks of four 16-bit banks each. Each bank is accessible by either the CPU or the DMA during each cycle. The dual-bank structure of the data memory allows the CPU to operate on a set of data in one block while the DMA transfers new data into and old data out of the other block. This reduces the opportunity of contention between the CPU and DMA for data memory resource. The 32-bit expansion bus replaces the host port interface (HPI) of the C6201 and provides the C6202 with an additional interface to peripheral I/O devices. There are four separate memory spaces, as in the EMIF, each of which is independently configured using space control registers. The expansion bus has two host-interface modes: synchronous and asynchronous. The asynchronous mode is simply a 32-bit version of the C6201 HPI. The synchronous mode allows the expansion bus to interface to several industry-standard bus protocols. The expansion bus may run at speeds up to one-fourth the CPU speed (62.5 MHz, in the case of a 250 MHz-6202) when servicing a synchronous host. Possible synchronous host interfaces include: * Master/Slave Interface to PCI Bridge * Slave Interface to Industry-standard Synchronous Bus Protocols The asynchronous memory interface of the expansion bus is identical to that of the EMIF, with the exception that the addressable space is limited. The expansion bus has the advantage over the EMIF of also supporting a glueless synchronous FIFO interface. The advantage here is that slower peripheral I/O devices are decoupled from the faster memories that are typically attached to the EMIF, and by splitting the external devices between two buses, system loading is minimized. The expansion bus is independent of the EMIF, so both may be accessed simultaneously. It is possible to have the CPU making program fetches from SDRAM via the EMIF while the DMA is continuously servicing a synchronous FIFO on the expansion bus. This feature significantly increases the possible data throughput of the device. 16 How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs SPRA063A 7 Designing to Achieve Performance With the C6203B/03C The enhancements made to the successful design of the C6202 allow the C6203 to offer 20 percent higher performance in fixed-point MIPS. The improved performance by the CPU comes in part from the increased device clock rate of 300 MHz and from the additional internal program and data memory. The C6203B offers more than double the internal memory space of the C6202, with 384Kbytes of program memory and 512Kbytes of data memory. By providing more on-chip memory, designers will be able to keep more critical code sections and data in fast, quick-access memories. This will allow the CPU to maintain its high performance capability. The 384Kbyte internal program memory of the C6203B is divided into a 256Kbyte memory-mapped block and a 128Kbyte direct-mapped block. The 128Kbyte block can be configured as either RAM or cache, and the 256Kbyte block fixed as RAM. This option allows for critical code to stay in internal memory while still having the added performance and flexibility of cache. If the program space is configured entirely as RAM, the dual-block structure allows for the DMA to transfer new sections of code into one block while the CPU is running from the other. This will provide system designers with a means to easily schedule their own program-paging scheme. Note, that while the address ranges of the added program and data memory to the C6203B completely overlap the corresponding smaller C6202 blocks, the block assignments within the larger memory ranges have changed. Memory locations previously located in one block on the C6202 can now end up in another block if the same software is executed on the C6203B. To review, each internal program and data space is split between two equally sized blocks. This feature allows the CPU to be executing program from one of the blocks, while the DMA is simultaneously loading the next segment of the code into the other block, with a guarantee of no memory conflicts and resulting lost cycles. Similarly, both sides of the CPU are guaranteed to always be able to simultaneously access internal data without any conflicts as long as each side uses a different memory block. Since the C6203B memory map is a superset of the C6202 memory, the C6202 code will run on the C6203B without any modifications. However, if the original code used blocking to minimize memory access conflicts, in order to preserve the original blocking intent, the logical to physical memory mapping may have to be changed at the linker level. Depending on the application, this may not be necessary as any cycles lost due to increased memory conflicts may be negated by the higher operating frequency of the C6203B device. How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs 17 SPRA063A 8 Designing to Achieve Performance With the C6204 Enhancements and modifications to the design of the C6202 provide for a low-cost C6204. The C6204 provides performance on the order of 1600 MIPS at 200 MHz. Since the C6204 is a low cost device among the C620x family, it offers the memory architecture of the C6201, but with a better process (15C05) technology. In addition it provides a two-fold increase in bandwidth compared to the C6201 due to the 32-bit expansion bus. The internal program memory of the C6204 contains 64Kbyte of RAM which can be configured as either mapped RAM or as cache similar to the C6201. The internal data memory of the C6204 is again configured as it is on the C6201, with two blocks of four 16-bit banks. Each bank is accessible by either the CPU or the DMA during each cycle. The dual-bank structure of the data memory allows the CPU to operate on a set of data in one block while the DMA transfers new data into and old data out of the other block. This reduces the opportunity of contention between the CPU and DMA for data memory resource. The 32-bit expansion bus replaces the Host Port Interface (HPI) of the C6201 and provides the C6204 with an additional interface to peripheral I/O devices. There are four separate memory spaces, as in the EMIF, each of which is independently configured using space control registers. The expansion bus has two host-interface modes: synchronous and asynchronous. The asynchronous mode is simply a 32-bit version of the C6201 HPI. The synchronous mode allows the expansion bus to interface to several industry-standard bus protocols. The expansion bus may run at speeds up to one-fourth the CPU speed (in the case of the C6204, 50 MHz) when servicing a synchronous host. Possible synchronous host interfaces include: * Master/Slave Interface to PCI Bridge * Slave Interface to Industry-standard Synchronous Bus Protocols The asynchronous memory interface of the expansion bus is identical to that of the EMIF, with the exception that the addressable space is limited. The expansion bus has the advantage over the EMIF of also supporting a glue-less synchronous FIFO interface. The advantage here is that slower peripheral I/O devices are de-coupled from the faster memories that are typically attached to the EMIF, and by splitting the external devices between two buses, system loading is minimized. The expansion bus is independent of the EMIF, so both may be accessed simultaneously. It is possible to have the CPU making program fetches from SDRAM via the EMIF while the DMA is continuously servicing a synchronous FIFO on the expansion bus. This feature significantly increases the possible data throughput of the device. 18 How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs SPRA063A 9 IBIS Modeling for the 6202C, 6203B Rev. 3 and 6203C Care must be taken when routing clock, control, and data lines between high-speed interfaces on the DSP. IBIS models should be used to account for board topology. In order to meet the requirements of the latest high-speed memories and other I/O devices, 6202C, 6203B Rev 3 and 6203C timings were designed to account for these board level constants. Constraints are placed on the distance that trace lengths can be. This constraint on trace length results in an increased window between set-up and hold times. Figure 5 shows how to determine the required set-up and hold times based on board route delays. CLKOUT2 (Output from DSP) Clock Route Delay CLKOUT2 (Input to Ext. Device) Minimum DSP Hold Time Minimum DSP Set-Up Time Control Signals (Output from DSP) Ext. Device Hold Time Requirement Ext. Device Set-Up Time Requirement Control Signal Route Delay Control Signals (Input to Ext. Device) Ext. Device Hold Time Ext. Device Access Time Data (Output from Ext. Device) DSP Hold Time Requirement DSP Set-Up Time Requirement Data Route Delay Data (Input to DSP) Figure 5. DSP Target Device Perception of Board Delays Route Delays are caused by a combination of trace impedance and trace length. Higher impedance traces will slow the buffer rise times. Signals, depending on medium, have typical propagation times on the order of 180 pS/inch. Other factors, such as driver characteristics and loading also impact the route delays seen at the EMIF interface. Typical loading for a single SDRAM is on the order of 5pF. Lighter loading results in faster rise/fall times; conversely, heavier loading produces slower rise/fall times. The more devices on the EMIF bus, the higher the loading. How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs 19 SPRA063A To assist in the design of 6202C, 6203B Rev 3 and 6203C based systems, board level issues were taken into account when specifying EMIF timing parameters. By using typical board impedances and trace lengths, critical timing windows (the period from set-up to hold) more accurately reflect real operating conditions. The trace length and impedance used for these measurements are given in table 5. Window placement (where the timing window sits with respect to a rising clock edge) is determined by the silicon manufacturing process, as well as route delays. DSPs manufactured in a Fast-Strong environment will have increased set-up times and decreased hold times. Slow-Weak environments produce shorter set-up times and longer hold times. The trace lengths given in Table 5 take into account minimum and maximum values based on typical board routes. Trace lengths should be matched for all signals and clocks. Variation in signal trace lengths decreases the marginality given to the system. The 6202C, 6203B Rev 3 and 6203C were designed such that they fit to the parameters specified in the data sheets based on the trace lengths and length variations given in Table 1. Table 5. Minimum and Maximum Route Lengths and Impedance Used to Determine 6202C, 6203B and 6203C EMIF Parameters Minimum Distance Maximum Distance Delay Path Impedance () in. cm. in. cm. Clock Route 50 1.90 4.83 2.30 5.84 Data Route 50 0.54 1.37 0.97 2.46 Control Route 50 2.78 7.06 4.10 10.41 Using the information given in Figure 5, the following equations can be derived; DSP Controls to SDRAM Control Set-Up Time: Control Hold Time: tisu(SDRAM) tosu(DSP) + ClockRoute Delay - ControlRoute Delay(Slowest) tih(SDRAM) toh(DSP) - ClockRoute Delay + ControlRoute Delay(Fastest) DSP Reads from SDRAM Data Set-Up Time: Data Hold Time: tisu(DSP) ClockPeriod - ClockRoute Delay - DataRoute Delay (Slowest) - tAcc tih(DSP) toh(SDRAM) + DataRoute Delay (Fastest) + ClockRoute Delay DSP Writes to SDRAM Data Set-Up Time: Data Hold Time: tisu(SDRAM) tosu(DSP) + ClockRoute Delay - DataRoute Delay(Slowest) tih(SDRAM) toh(DSP) - ClockRoute Delay + DataRoute Delay(Fastest) Using these equations, in conjunction with the timing parameters given in the 6203B and 6203C data sheets, a board can be laid out such that most standard SDRAM devices can be used to interface with the DSP. 9.1 shows how the 6203C and a Micron SDRAM easily interface. 20 How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs SPRA063A 9.1 Determining Compatibility Between the 6203C DSP and MT48LC2M32B2 SDRAM This example shows how the 6203C DSP and a Micront MT48LC2M32B2 SDRAM can be checked for compatibility. * * 6203C: - CPUT Frequency: P 300 MHz - EMIF Frequency: 2P 150 MHz - Control tosu: P - 1 3.33 - 1 = 2.3 ns - Control toh: P - 2.3 3.33 - 2.3 = 1 ns - Data tosu: P - 1.6 3.33 - 1.6 = 1.73 ns - Data toh: P - 2 3.33 - 2 = 1.33 ns - Data tisu: 0 ns - Data tih: 2.3 ns 64Mb x32 SDRAM : - Frequency: 166 MHz - Data tAcc: 5.5 ns - Data toh: 2 ns - Control tsu: 1.5 ns - Control th: 1 ns Using the numbers and equations given above the following is obtained: DSP Controls to SDRAM Control Set-Up Time: tisu(SDRAM) tosu(DSP) + ClockRoute Delay - ControlRoute Delay(Slowest) or 1.5 nS 1.73 ns + ClockRoute Delay - ControlRoute Delay(Slowest) or -0.23 ns ClockRoute Delay - ControlRoute Delay(Slowest) Control Hold Time: tih(SDRAM) toh(DSP) - ClockRoute Delay + ControlRoute Delay(Fastest) or 1 nS 1.33 ns - ClockRoute Delay + ControlRoute Delay(Fastest) or 0.33 ns ClockRoute Delay - ControlRoute Delay(Fastest) The maximum difference between the Clock trace length and the longest Control trace length can be calculated from the Control Set-Up Time: ControlRoute Length(Slowest) - ClockRoute Length 0.23 (ns) / 0.180 (nS/in) 1.28 inches The minimum difference between the Clock trace length and the shortest Control trace length can be calculated from the Control Hold Time: ClockRoute Length - ControlRoute Length(Fastest) 0.33 (ns) / 0.180 (nS/in) 1.83 inches How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs 21 SPRA063A These numbers are the control length differences from the clock route length. These distances must not be exceeded in order to guarantee timings according to the data sheets. DSP Writes to SDRAM Data Set-Up Time: Data Hold Time: tisu(SDRAM) tosu(DSP) + ClockRoute Delay - DataRoute Delay(Slowest) or 1.5 nS 1.73 nS + ClockRoute Delay - DataRoute Delay(Slowest) or -0.23 ClockRoute Delay - DataRoute Delay(Slowest) tih(SDRAM) toh(DSP) - ClockRoute Delay + DataRoute Delay(Fastest) or 1 nS 1.33 nS - ClockRoute Delay + DataRoute Delay(Fastest) or 0.33 nS ClockRoute Delay - DataRoute Delay(Fastest) Data writes to SDRAM are similar to control signals; therefore, the values generated for data route length difference with respect to the clock route length difference are the same. DataRoute Length(Slowest) ClockRoute Length + 1.28 inches DataRoute Length(Fastest) ClockRoute Length - 1.83 inches DSP Reads From SDRAM Data Set-Up Time: Data Hold Time: tisu(DSP) ClockPeriod - ClockRoute Delay - DataRoute Delay (Slowest) - tAcc or 0 ns 6.67 - ClockRoute Delay - DataRoute Delay (Slowest) - 5.5 ns or 1.17 ns ClockRoute Delay + DataRoute Delay (Slowest) tih(DSP) toh(SDRAM) + DataRoute Delay (Fastest) + ClockRoute Delay or 2.3 ns 2 ns + DataRoute Delay (Fastest) + ClockRoute Delay or 0.3 ns DataRoute Delay (Fastest) + ClockRoute Delay Converting the read parameters to length gives, 1.17 (ns) / 0.180 (ns/in) 6.5 in ClockRoute Length + DataRoute Length (Slowest) 0.3 (ns) / 0.180 (ns/in) 1.67 in DataRoute Length (Fastest) + ClockRoute Length Substitution with the write parameters gives the acceptable Clock Route Length parameters, 6.5 - 1.28 inches 2 x ClockRoute Length ClockRoute Length Max 2.61 inches 1.67 + 1.83 inches 2 x ClockRoute Length ClockRoute Length Min 1.75 inches In order to meet timing parameters for the DSP and SDRAM, the clock route length should be between 1.75 inches and 2.61 inches. Shorter clock routes increase control signal hold times to the SDRAM, but decrease data hold times from the SDRAM. This should be taken into consideration when designing with this type of interface. Once the clock route length is determined, control routes and data routes can be placed in accordance with the calculated minimum and max distances. This example gives an estimate of whether or not an SDRAM will work with the 6203C DSP. Other factors, such as loading, impedance, driver characteristics, etc., will need to be taken into account when doing actual board layout. IBIS models should be used to accurately determine signal integrity issues that may arise due to various trace lengths, loadings, etc. 22 How to Begin Development Today and Migrate Across the TMS320C6202/02C/03B/03C/04 DSPs SPRA063A 10 C6000 Tools Support C6000 tools are available now for use in all C6000 designs. The C6000 development tools available today are: 11 * Code Composert Studio which includes Code Composer Studio-Compile Tools and Code Composer Studio-Debug Tools * C6000 Simulator Software * C6000 Optimizing C Compiler/Assembler * TMS320C6201 Evaluation Module (EVM) * XDS510 C6000 C Source Debugger Software * XDS510 Emulator Hardware With JTAG Emulation Cable C6000 Literature Available A great deal of literature is available today for the C6000 devices. * TMS320C6000 CPU and Instruction Set Reference Guide (SPRU189) * TMS320C6000 Peripherals Reference Guide (SPRU190) * TMS320C6000 Technical Brief (SPRU197) * TMS320C6000 Programmer's Guide (SPRU198) * TMS320C6x Evaluation Module Reference Guide (SPRU308) * TMS320C2x Peripheral Support Library Programmer's Reference (SPRU273) * TMS320C6000 Assembly Language Tools User's Guide (SPRU186) * TMS320C6000 Optimizing C Compiler User's Guide (SPRU187) * TMS320C6x C Source Debugger User's Guide (SPRU188) * TMS320C6x C Source Debugger For Sparcstations (SPRU224) Code Composer and XDS510 are trademarks of Texas Instruments Incorporated. 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