Freescale Semiconductor Document Number: MPC852TEC Rev. 4, 09/2007 Technical Data MPC852T PowerQUICCTM Hardware Specifications This document contains detailed information for the MPC852T power considerations, DC/AC electrical characteristics, AC timing specifications, and pertinent electrical and physical characteristics. For information about functional characteristics of the processor, refer to the MPC866 PowerQUICCTM Family Reference Manual (MPC866UM). The MPC852T contains a PowerPCTM processor core built on Power ArchitectureTM technology. To locate published errata or updates for this document, refer to the MPC852T product summary page on our website listed on the back cover of this document or, contact your local Freescale sales office. (c) Freescale Semiconductor, Inc., 2004, 2007. All rights reserved. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 6 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 7 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal Calculation and Measurement . . . . . . . . . . . 9 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power Supply and Power Sequencing . . . . . . . . . . . 12 Mandatory Reset Configurations . . . . . . . . . . . . . . . 12 Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 14 IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 42 CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 44 FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 57 Mechanical Data and Ordering Information . . . . . . . 60 Document Revision History . . . . . . . . . . . . . . . . . . . 76 Overview 1 Overview The MPC852T is a 0.18-micron derivative of the MPC860 PowerQUICCTM family, and can operate up to 100 MHz on the MPC8xx core with a 66-MHz external bus. The MPC852T has a 1.8-V core and a 3.3-V I/O operation with 5-V TTL compatibility. The MPC852T integrated communications controller is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in Ethernet control applications, including CPE equipment, Ethernet routers and hubs, VoIP clients, and WiFi access points. The MPC852T is a PowerPC architecture-based derivative of the MPC860 Quad Integrated Communications Controller (PowerQUICC). The CPU on the MPC852T is a MPC8xx core, a 32-bit microprocessor that implements the PowerPC architecture, incorporating memory management units (MMUs) and instruction and data caches. The MPC852T is the subset of this family of devices. 2 Features The MPC852T is comprised of three modules that each use a 32-bit internal bus: an MPC8xx core, system integration unit (SIU), and communication processor module (CPM). The following list summarizes the key MPC852T features: * Embedded MPC8xx core up to 100 MHz * Maximum frequency operation of the external bus is 66 MHz -- 50/66 MHz core frequencies support both 1:1 and 2:1 modes -- 80/100 MHz core frequencies support 2:1 mode only * Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two 32-bit general-purpose registers (GPRs) -- The core performs branch prediction with conditional prefetch, without conditional execution. -- 4-Kbyte data cache and 4-Kbyte instruction cache - 4-Kbyte instruction caches is two-way, set-associative with 128 sets - 4-Kbyte data cachesis two-way, set-associative with 128 sets - Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks - Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis -- MMUs with 32-entry TLB, fully associative instruction, and data TLBs -- MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces, and 16 protection groups * Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) * 32 address lines * Memory controller (eight banks) -- Contains complete dynamic RAM (DRAM) controller -- Each bank can be a chip select or RAS to support a DRAM bank MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 2 Freescale Semiconductor Features * * * * * -- Up to 30 wait states programmable per memory bank -- Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices -- DRAM controller-programmable to support most size and speed memory interfaces -- Four CAS lines, four WE lines, and one OE line -- Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) -- Variable block sizes (32 Kbytes-256 Mbytes) -- Selectable write protection -- On-chip bus arbitration logic Fast Ethernet controller (FEC) General-purpose timers -- Two 16-bit timers or one 32-bit timer -- Gate mode can enable or disable counting -- Interrupt can be masked on reference match and event capture System integration unit (SIU) -- Bus monitor -- Software watchdog -- Periodic interrupt timer (PIT) -- Low-power stop mode -- Clock synthesizer -- Decrementer and time base -- Reset controller -- IEEE 1149.1TM standard test access port (JTAG) Interrupts -- Seven external interrupt request (IRQ) lines -- Seven port pins with interrupt capability -- Eighteen internal interrupt sources -- Programmable priority between SCCs -- Programmable highest-priority request Communications processor module (CPM) -- RISC controller -- Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and RESTART TRANSMIT) -- Supports continuous mode transmission and reception on all serial channels -- 8-Kbytes of dual-port RAM -- Eight serial DMA (SDMA) channels -- Three parallel I/O registers with open-drain capability MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 3 Features * * * * * * * * Two baud rate generators -- Independent (can be connected toany SCC3/4 or SMC1) -- Allows changes during operation -- Autobaud support option Two SCCs (serial communication controllers) -- Ethernet/IEEE 802.3(R) standard optional on SCC3 and SCC4, supporting full 10-Mbps operation -- HDLC/SDLC -- HDLC bus (implements an HDLC-based local area network (LAN)) -- Universal asynchronous receiver transmitter (UART) -- Totally transparent (bit streams) -- Totally transparent (frame-based with optional cyclic redundancy check (CRC)) One SMC (serial management channel) -- UART One SPI (serial peripheral interface) -- Supports master and slave modes -- Supports multimaster operation on the same bus PCMCIA interface -- Master (socket) interface, release 2.1 compliant -- Supports one independent PCMCIA socket; 8-memory or I/O windows supported Debug interface -- Eight comparators: four operate on instruction address, two operate on data address, and two operate on data -- Supports conditions: = < > -- Each watchpoint can generate a break point internally Normal high and normal low power modes to conserve power 1.8 V core and 3.3-V I/O operation with 5-V TTL compatibility. Refer to Table 5 for a listing of the 5-V tolerant pins. Figure 1 shows the MPC852T block diagram. MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 4 Freescale Semiconductor Features 4-Kbyte Instruction Instruction Cache Bus Embedded MPC8xx Processor Core System Interface Unit (SIU) Unified Bus Instruction MMU 32-Entry ITLB Load/Store Bus Memory Controller External Internal Bus Interface Bus Interface Unit Unit 4-Kbyte Data Cache System Functions Data MMU 32-Entry DTLB PCMCIA-ATA Interface Fast Ethernet Controller DMAs FIFOs 10/100 Base-T Media Access Control Parallel I/O 2 Baud Rate Generators 2 Interrupt 8-Kbyte Timers Controllers Dual-Port RAM 32-Bit RISC Controller and Program ROM Timers 1 Virtual IDMA and 8 Serial DMA Channels MII SCC3 SCC4 SMC1 SPI Serial Interface (NMSI) Figure 1. MPC852T Block Diagram MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 5 Maximum Tolerated Ratings 3 Maximum Tolerated Ratings This section provides the maximum tolerated voltage and temperature ranges for the MPC852T. Table 1 provides the maximum ratings and operating temperatures. Table 1. Maximum Tolerated Ratings Rating Symbol Supply voltage1 Value Unit VDDL (core voltage) - 0.3 to 3.4 V VDDH (I/O voltage) - 0.3 to 4 V - 0.3 to 3.4 V 100 mV VDDSYN Difference between VDDL to VDDSYN Input voltage2 Vin GND - 0.3 to V DDH V Storage temperature range Tstg - 55 to +150 C 1 2 The power supply of the device must start its ramp from 0.0 V. Functional operating conditions are provided with the DC electrical specifications in Table 5. Absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than V DDH. This restriction applies to power-up and normal operation (that is, if the MPC852T is unpowered, a voltage greater than 2.5 V must not be applied to its inputs). Figure 2 shows the undershoot and overshoot voltages at the interface of the MPC852T. VDDH/VDDL + 20% VDDH/VDDL + 5% VIH VDDH/VDDL GND GND - 0.3 V VIL GND - 0.7 V Not to Exceed 10% of tinterface1 Note: 1. tinterface refers to the clock period associated with the bus clock interface. Figure 2. Undershoot/Overshoot Voltage for VDDH and VDDL MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 6 Freescale Semiconductor Thermal Characteristics Table 2. Operating Temperatures Rating Symbol Value Unit TA(min) 0 C Tj(max) 95 C TA(min) - 40 C Tj(max) 100 C Temperature 1 (standard) Temperature (extended) 1 Minimum temperatures are guaranteed as ambient temperature, TA. Maximum temperatures are guaranteed as junction temperature, Tj. This device contains circuitry protecting against damage that high-static voltage or electrical fields cause; however, Freescale recommends taking normal precautions to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VDD). 4 Thermal Characteristics Table 3 shows the thermal characteristics for the MPC852T. Table 3. MPC852T Thermal Resistance Data Rating Environment Junction-to-ambient1 Symbol Value Unit Single-layer board (1s) RJA2 49 C/W Four-layer board (2s2p) RJMA3 32 Single-layer board (1s) RJMA3 41 Four-layer board (2s2p) RJMA3 29 RJB 24 RJC 13 Natural convection JT 3 Airflow (200 ft/min) JT 2 Natural convection Airflow (200 ft/min) Junction-to-board4 Junction-to-case5 Junction-to-package 1 2 3 4 5 6 top6 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal Per JEDEC JESD51-6 with the board horizontal Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed pad packages where the pad would be expected to be soldered, junction-to-case thermal resistance is a simulated value from the junction to the exposed pad without contact resistance. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2 MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 7 Power Dissipation 5 Power Dissipation Table 4 provides power dissipation information. The modes are 1:1, where CPU and bus speeds are equal, and 2:1 mode, where CPU frequency is twice bus speed. Table 4. Power Dissipation (PD) Die Revision Bus Mode Frequency (MHz) Typical1 Maximum2 Unit 50 110 140 mW 66 150 180 mW 66 140 160 mW 80 170 200 mW 100 210 250 mW 1:1 0 2:1 1 2 Typical power dissipation is measured at 1.9 V. Maximum power dissipation at VDDL and VDDSYN is at 1.9 V. and V DDH is at 3.465 V. NOTE Values in Table 4 represent VDDL-based power dissipation, and do not include I/O power dissipation over VDDH. I/O power dissipation varies widely by application that buffer current can cause, depending on external circuitry. The VDDSYN power dissipation is negligible. 6 DC Characteristics Table 5 provides the DC electrical characteristics for the MPC852T. Table 5. DC Electrical Specifications Characteristic Symbol Min Max Unit VDDH 3.135 3.465 V VDDL 1.7 1.9 V VDDSYN 1.7 1.9 V Difference between VDDL to VDDSYN -- 100 mV Input high voltage (all inputs except PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15, PD[3:15], TDI, TDO, TCK, TRST, TMS, MII_TXEN, MII_MDIO)1 VIH 2.0 3.465 V Input low voltage VIL GND 0.8 V VIHC 0.7 x VDDH VDDH V Operating voltage EXTAL, EXTCLK input high voltage MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 8 Freescale Semiconductor Thermal Calculation and Measurement Table 5. DC Electrical Specifications (continued) Characteristic Symbol Min Max Unit Input leakage current, Vin = 5.5 V (Except TMS, TRST, DSCK and DSDI pins) for 5-V tolerant pins 1 Iin -- 100 A Input leakage current, Vin = VDDH (Except TMS, TRST, DSCK, and DSDI) IIn -- 10 A Input leakage current, Vin = 0 V (Except TMS, TRST, DSCK and DSDI pins) IIn -- 10 A Input capacitance2 Cin -- 20 pF Output high voltage, IOH = -2.0 mA, VDDH = 3.0 V Except XTAL and open drain pins VOH 2.4 -- V Output low voltage IOL = 2.0 mA (CLKOUT) IOL = 3.2 mA3 IOL = 5.3 mA4 IOL = 7.0 mA (Txd1/pa14, txd2/pa12) IOL = 8.9 mA (TS, TA, TEA, BI, BB, HRESET, SRESET) VOL -- 0.5 V 1 The PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15, PD[3:15], TDI, TDO, TCK, TRST, TMS, MII_TXEN, MII_MDIO are 5-V tolerant pins. 2 Input capacitance is periodically sampled. 3 A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IWP(0:1)/VFLS(0:1), RXD3/PA11, TXD3/PA10, RXD4/PA9, TXD4/PA8, TIN3/BRGO3/CLK5/PA3, BRGCLK2/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/PA1, TOUT4/CLK8/PA0, SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29, BRGO4/SPIMISO/PB28, SMTXD1/PB25, SMRXD1/PB24, BRGO3/PB15, RTS1/DREQ0/PC15, RTS3/PC13, RTS4/PC12, CTS3/PC7, CD3/PC6, CTS4/SDACK1/PC5, CD4/PC4, MII-RXD3/PD15, MII-RXD2/PD14, MII-RXD1/PD13, MII-MDC/PD12, MII-TXERR/RXD3/PD11, MII-RX0/TXD3/PD10, MII-TXD0/RXD4/PD9, MII-RXCLK/TXD4/PD8, MII-TXD3/PD5, MII-RXDV/RTS4/PD6, MII-RXERR/RTS3/PD7, MII-TXD2/REJECT3/PD4, MII-TXD1/REJECT4/PD3, MII_CRS, MII_MDIO, MII_TXEN, and MII_COL 4 BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6), CS(7), WE0/BS_B0/IORD, WE1/BS_B1/IOWR, WE2/BS_B2/PCOE, WE3/ BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1, GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, GPL_A5, ALE_A, CE1_A, CE2_A, DSCK, OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, and BADDR(28:30) 7 Thermal Calculation and Measurement For the following discussions, PD= (VDDL x IDDL) + PI/O, where PI/O is the power dissipation of the I/O drivers. NOTE The VDDSYN power dissipation is negligible. 7.1 Estimation with Junction-to-Ambient Thermal Resistance An estimation of the chip junction temperature, TJ, in C can be obtained from the equation: TJ = TA +(RJA x PD) MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 9 Thermal Calculation and Measurement where: TA = ambient temperature (C) RJA = package junction-to-ambient thermal resistance (C/W) PD = power dissipation in package The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity TJ - TA) are possible. 7.2 Estimation with Junction-to-Case Thermal Resistance Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RJA = RJC + RCA where: RJA = junction-to-ambient thermal resistance (C/W) RJC = junction-to-case thermal resistance (C/W) RCA = case-to-ambient thermal resistance (C/W) RJC is device-related and cannot be influenced by the user. The user adjusts the thermal environment to affect the case-to-ambient thermal resistance, RCA. For instance, the user can change the airflow around the device, add a heat sink, change the mounting arrangement on the printed-circuit board, or change the thermal dissipation on the printed-circuit board surrounding the device. This thermal model is most useful for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink to the ambient environment. For most packages, a better model is required. 7.3 Estimation with Junction-to-Board Thermal Resistance A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed-circuit board. Thermal performance of most plastic packages and especially PBGA packages is strongly dependent on the board temperature. If the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation: TJ = TB +(RJB x PD) where: RJB = junction-to-board thermal resistance (C/W) TB = board temperature (C) PD = power dissipation in package MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 10 Freescale Semiconductor References If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. For this method to work, the board and board mounting must be similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground plane. 7.4 Estimation Using Simulation When the board temperature is not known, a thermal simulation of the application is needed. The simple two-resistor model can be used with the thermal simulation of the application [2], or a more accurate and complex model of the package can be used in the thermal simulation. 7.5 Experimental Determination To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) where: JT = thermal characterization parameter TT = thermocouple temperature on top of package PD = power dissipation in package The thermal characterization parameter is measured per JESD51-2 specification published by JEDEC using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors that cooling effects of the thermocouple wire cause. 8 References Semiconductor Equipment and Materials International (415) 964-5111 805 East Middlefield Rd Mountain View, CA 94043 MIL-SPEC and EIA/JESD (JEDEC) specifications 800-854-7179 or (Available from Global Engineering documents) 303-397-7956 JEDEC Specifications http://www.jedec.org 1. C.E. Triplett and B. Joiner, "An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module," Proceedings of SemiTherm, San Diego, 1998, pp. 47-54. 2. B. Joiner and V. Adams, "Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling," Proceedings of SemiTherm, San Diego, 1999, pp. 212-220. MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 11 Power Supply and Power Sequencing 9 Power Supply and Power Sequencing This section provides design considerations for the MPC852T power supply. The MPC852T has a core voltage (VDDL) and PLL voltage (VDDSYN) that operates at a lower voltage than the I/O voltage VDDH. The I/O section of the MPC852T is supplied with 3.3 V across VDDH and VSS (GND). The signals PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15] PD[3:15], TDI, TDO, TCK, TRST, TMS, MII_TXEN, MII_MDIO are 5-V tolerant. All inputs cannot be more than 2.5 V greater than VDDH. In addition, 5-V tolerant pins can not exceed 5.5 V, and the remaining input pins cannot exceed 3.465 V. This restriction applies to power-on reset or power down and normal operation. One consequence of multiple power supplies is that when power is initially applied, the voltage rails ramp up at different rates. The rates depend on the nature of the power supply, the type of load on each power supply, and the manner in which different voltages are derived. The following restrictions apply: * VDDL must not exceed VDDH during power-on reset or power down. * VDDL must not exceed 1.9 V, and VDDH must not exceed 3.465. These cautions are necessary for the long-term reliability of the part. If they are violated, the electrostatic discharge (ESD) protection diodes are forward-biased, and excessive current can flow through these diodes. If the system power supply design does not control the voltage sequencing, the circuit shown in Figure 3 can be added to meet these requirements. The MUR420 Schottky diodes control the maximum potential difference between the external bus and core power supplies on power-on reset, and the 1N5820 diodes regulate the maximum potential difference on power-down. VDDH VDDL MUR420 1N5820 Figure 3. Example Voltage Sequencing Circuit 10 Mandatory Reset Configurations The MPC852T requires a mandatory configuration during reset. If hardware reset configuration word (HRCW) is enabled, by asserting the RSTCONF during HRESET assertion, the HRCW[DBGC] value that is needed to be set to binary X1 in the hardware reset configuration word (HRCW) and the SIUMCR[DBGC] should be programmed with the same value in the boot code after reset. If hardware reset configuration word (HRCW) is disabled, by negating the RSTCONF during the HRESET assertion, the SIUMCR[DBGC] should be programmed with binary X1 in the boot code after reset. MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 12 Freescale Semiconductor Layout Practices The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR should be configured with the mandatory value in Table 6 in the boot code after the reset deasserts. Table 6. Mandatory Reset Configuration of MPC852T Register/Configuration Field Value (Binary) HRCW (Hardware reset configuration word) HRCW[DBGC] X1 SIUMCR (SIU module configuration register) SIUMCR[DBGC] X1 MBMR (Machine B mode register) MBMR[GPLB4DIS} 0 PAPAR (Port A pin assignment register) PAPAR[4-7] PAPAR[12-15] 0 PADIR (Port A data direction register) PADIR[4-7] PADIR[12-15] 1 PBPAR (Port B pin assignment register) PBPAR[14] PBPAR[16-23] PBPAR[26-27] 0 PBDIR (Port B data direction register) PBDIR[14] PBDIR[16-23] PBDIR[26-27] 1 PCPAR (Port C pin assignment register) PCPAR[8-11] PCDIR[14] 0 PCDIR (Port C data direction register) PCDIR[8-11] PCDIR[14] 1 11 Layout Practices Each VDD pin on the MPC852T should be provided with a low-impedance path to the board's supply. Each GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip. The VDD power supply should be bypassed to ground using at least four 0.1 F bypass capacitors located as close as possible to the four sides of the package. Each board designed should be characterized and additional appropriate decoupling capacitors should be used if required. The capacitor leads and associated printed-circuit traces connecting to chip VDD and GND should be kept to less than half an inch per capacitor lead. At a minimum, a four-layer board employing two inner layers as VDD and GND planes should be used. All output pins on the MPC852T have fast rise and fall times. Printed-circuit (PC) trace interconnection length should be minimized to minimize undershoot and reflections that these fast output switching times cause. This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances that the PC traces cause. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads, because these loads create higher transient currents in the VDD and GND circuits. Pull up all unused inputs or signals that are inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. For more information, please refer to the MPC866 PowerQUICCTM Family Reference Manual, Section 14.4.3, "Clock Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1)." MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 13 Bus Signal Timing 12 Bus Signal Timing The maximum bus speed that the MPC852T supports is 66 MHz. Table 7 shows the frequency ranges for standard part frequencies. Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode) 50 MHz 66 MHz Part Frequency Min Max Min Max Core 40 50 40 66.67 Bus 40 50 40 66.67 Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode) 50 MHz 66 MHz 80 MHz 100 MHz Part Frequency Min Max Min Max Min Max Min Max Core 40 50 40 66.67 40 80 40 100 Bus 2:1 20 25 20 33.33 20 40 20 50 Table 9 provides the bus operation timing for the MPC852T at 33, 40, 50, and 66 MHz. The timing for the MPC852T bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum delays. CLKOUT assumes a 100-pF load maximum delay Table 9. Bus Operation Timings 33 MHz Num 40 MHz 50 MHz 66 MHz Characteristic Unit Min Max Min Max Min Max Min Max B1 Bus period (CLKOUT) See Table 7 -- -- -- -- -- -- -- -- ns B1a EXTCLK to CLKOUT phase skew--If CLKOUT is an integer multiple of EXTCLK, then the rising edge of EXTCLK is aligned with the rising edge of CLKOUT. For a non-integer multiple of EXTCLK, this synchronization is lost, and the rising edges of EXTCLK and CLKOUT have a continuously varying phase skew. -2 +2 -2 +2 -2 +2 -2 +2 ns B1b CLKOUT frequency jitter peak-to-peak -- 1 -- 1 -- 1 -- 1 ns -- 0.50 -- 0.50 -- 0.50 -- 0.50 % EXTCLK1 B1c Frequency jitter on B1d CLKOUT phase jitter peak-to-peak for OSCLK 15 MHz -- 4 -- 4 -- 4 -- 4 ns CLKOUT phase jitter peak-to-peak for OSCLK < 15 MHz -- 5 -- 5 -- 5 -- 5 ns 12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns B2 CLKOUT pulse width low (MIN = 0.4 x B1, MAX = 0.6 x B1) MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 14 Freescale Semiconductor Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num 40 MHz 50 MHz 66 MHz Characteristic Unit Min Max Min Max Min Max Min Max 12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns B3 CLKOUT pulse width high (MIN = 0.4 x B1, MAX = 0.6 x B1) B4 CLKOUT rise time -- 4.00 -- 4.00 -- 4.00 -- 4.00 ns B5 CLKOUT fall time -- 4.00 -- 4.00 -- 4.00 -- 4.00 ns B7 CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3) output hold (MIN = 0.25 x B1) 7.60 -- 6.30 -- 5.00 -- 3.80 -- ns B7a CLKOUT to TSIZ(0:1), REG, RSV, BDIP, PTR output hold (MIN = 0.25 x B1) 7.60 -- 6.30 -- 5.00 -- 3.80 -- ns B7b CLKOUT to BR, BG, FRZ, VFLS(0:1), VF(0:2) IWP(0:2), LWP(0:1), STS output hold (MIN = 0.25 x B1) 7.60 -- 6.30 -- 5.00 -- 3.80 -- ns B8 CLKOUT to A(0:31), BADDR(28:30) RD/WR, BURST, D(0:31), DP(0:3) valid (MAX = 0.25 x B1 + 6.3) -- 13.80 -- 12.50 -- 11.30 -- 10.00 ns B8a CLKOUT to TSIZ(0:1), REG, RSV, BDIP, PTR valid (MAX = 0.25 x B1 + 6.3) -- 13.80 -- 12.50 -- 11.30 -- 10.00 ns B8b CLKOUT to BR, BG, VFLS(0:1), VF(0:2), IWP(0:2), FRZ, LWP(0:1), STS Valid3 (MAX = 0.25 x B1 + 6.3) -- 13.80 -- 12.50 -- 11.30 -- 10.00 ns B9 CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3), TSIZ(0:1), REG, RSV, PTR High-Z (MAX = 0.25 x B1 + 6.3) 7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns B11 CLKOUT to TS, BB assertion (MAX = 0.25 x B1 + 6.0) 7.60 13.60 6.30 12.30 5.00 11.00 3.80 9.80 ns B11a CLKOUT to TA, BI assertion (when driven by the memory controller or PCMCIA interface) (MAX = 0.00 x B1 + 9.302) 2.50 9.30 2.50 9.30 2.50 9.30 2.50 9.80 ns B12 CLKOUT to TS, BB negation (MAX = 0.25 x B1 + 4.8) 7.60 12.30 6.30 11.00 5.00 9.80 3.80 8.50 ns B12a CLKOUT to TA, BI negation (when driven by the memory controller or PCMCIA interface) (MAX = 0.00 x B1 + 9.00) 2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns B13 CLKOUT to TS, BB High-Z (MIN = 0.25 x B1) 7.60 21.60 6.30 20.30 5.00 19.00 3.80 14.00 ns B13a CLKOUT to TA, BI High-Z (when driven by the memory controller or PCMCIA interface) (MIN = 0.00 x B1 + 2.5) 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns B14 CLKOUT to TEA assertion (MAX = 0.00 x B1 + 9.00) 2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 15 Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num 40 MHz 50 MHz 66 MHz Characteristic Unit Min Max Min Max Min Max Min Max B15 CLKOUT to TEA High-Z (MIN = 0.00 x B1 + 2.50) 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns B16 TA, BI valid to CLKOUT (setup time) (MIN = 0.00 x B1 + 6.00) 6.00 -- 6.00 -- 6.00 -- 6.00 -- ns B16a TEA, KR, RETRY, CR valid to CLKOUT (setup time) (MIN = 0.00 x B1 + 4.5) 4.50 -- 4.50 -- 4.50 -- 4.50 -- ns B16b BB, BG, BR, valid to CLKOUT (setup time) 3 (4MIN = 0.00 x B1 +.000) 4.00 -- 4.00 -- 4.00 -- 4.00 -- ns B17 CLKOUT to TA, TEA, BI, BB, BG, BR valid (hold time) (MIN = 0.00 x B1 + 1.004) 1.00 -- 1.00 -- 1.00 -- 2.00 -- ns B17a CLKOUT to KR, RETRY, CR valid (hold time) (MIN = 0.00 x B1 + 2.00) 2.00 -- 2.00 -- 2.00 -- 2.00 -- ns B18 D(0:31), DP(0:3) valid to CLKOUT rising edge (setup time)5 (MIN = 0.00 x B1 + 6.00) 6.00 -- 6.00 -- 6.00 -- 6.00 -- ns B19 CLKOUT rising edge to D(0:31), DP(0:3) valid (hold time)5 (MIN = 0.00 x B1 + 1.006) 1.00 -- 1.00 -- 1.00 -- 2.00 -- ns B20 D(0:31), DP(0:3) valid to CLKOUT falling edge (setup time)7 (MIN = 0.00 x B1 + 4.00) 4.00 -- 4.00 -- 4.00 -- 4.00 -- ns B21 CLKOUT falling edge to D(0:31), DP(0:3) valid (hold Time)7 (MIN = 0.00 x B1 + 2.00) 2.00 -- 2.00 -- 2.00 -- 2.00 -- ns B22 CLKOUT rising edge to CS asserted GPCM ACS = 00 (MAX = 0.25 x B1 + 6.3) 7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns B22a CLKOUT falling edge to CS asserted GPCM ACS = 10, TRLX = 0 (MAX = 0.00 x B1 + 8.00) -- 8.00 -- 8.00 -- 8.00 -- 8.00 ns B22b CLKOUT falling edge to CS asserted GPCM ACS = 11, TRLX = 0, EBDF = 0 (MAX = 0.25 x B1 + 6.3) 7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns B22c CLKOUT falling edge to CS asserted GPCM ACS = 11, TRLX = 0, EBDF = 1 (MAX = 0.375 x B1 + 6.6) 10.90 18.00 10.90 16.00 7.00 14.10 5.20 12.30 ns B23 CLKOUT rising edge to CS negated GPCM read access, GPCM write access ACS = 00, TRLX = 0 & CSNT = 0 (MAX = 0.00 x B1 + 8.00) 2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns B24 A(0:31) and BADDR(28:30) to CS asserted GPCM ACS = 10, TRLX = 0 (MIN = 0.25 x B1 - 2.00) 5.60 -- 4.30 -- 3.00 -- 1.80 -- ns MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 16 Freescale Semiconductor Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num 40 MHz 50 MHz 66 MHz Characteristic Unit Min Max Min Max Min Max Min Max 13.20 -- 10.50 -- 8.00 -- 5.60 -- ns -- 9.00 9.00 ns B24a A(0:31) and BADDR(28:30) to CS asserted GPCM ACS = 11 TRLX = 0 (MIN = 0.50 x B1 - 2.00) B25 CLKOUT rising edge to OE, WE(0:3)/BS_B[0:3] asserted (MAX = 0.00 x B1 + 9.00) B26 CLKOUT rising edge to OE negated (MAX = 0.00 x B1 + 9.00) 2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns B27 A(0:31) and BADDR(28:30) to CS asserted GPCM ACS = 10, TRLX = 1 (MIN = 1.25 x B1 - 2.00) 35.90 -- 29.30 -- 23.00 -- 16.90 -- ns B27a A(0:31) and BADDR(28:30) to CS asserted GPCM ACS = 11, TRLX = 1 (MIN = 1.50 x B1 - 2.00) 43.50 -- 35.50 -- 28.00 -- 20.70 -- ns B28 CLKOUT rising edge to WE(0:3)/ BS_B[0:3] negated GPCM write access CSNT = 0 (MAX = 0.00 x B1 + 9.00) -- 9.00 -- 9.00 -- 9.00 -- 9.00 ns B28a CLKOUT falling edge to WE(0:3)/ BS_B[0:3] negated GPCM write access TRLX = 0,1 CSNT = 1, EBDF = 0 (MAX = 0.25 x B1 + 6.80) 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns B28b CLKOUT falling edge to CS negated GPCM write access TRLX = 0,1 CSNT = 1 ACS = 10 or ACS = 11, EBDF = 0 (MAX = 0.25 x B1 + 6.80) -- 14.30 -- 13.00 -- 11.80 -- 10.50 ns B28c CLKOUT falling edge to WE(0:3)/BS_B[0:3] negated GPCM write access TRLX = 0,1 CSNT = 1 write access TRLX = 0,1 CSNT = 1, EBDF = 1 (MAX = 0.375 x B1 + 6.6) 10.90 18.00 10.90 18.00 7.00 14.30 5.20 12.30 ns B28d CLKOUT falling edge to CS negated GPCM write access TRLX = 0,1 CSNT = 1, ACS = 10, or ACS = 11, EBDF = 1 (MAX = 0.375 x B1 + 6.6) -- 18.00 -- 18.00 -- 14.30 -- 12.30 ns B29 WE(0:3)/BS_B[0:3] negated to D(0:31), DP(0:3) High-Z GPCM write access, CSNT = 0, EBDF = 0 (MIN = 0.25 x B1 - 2.00) 5.60 -- 4.30 -- 3.00 -- 1.80 -- ns B29a WE(0:3)/BS_B[0:3] negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 0, CSNT = 1, EBDF = 0 (MIN = 0.50 x B1 - 2.00) 13.20 -- 10.50 -- 8.00 -- 5.60 -- ns 9.00 9.00 MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 17 Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num 40 MHz 50 MHz 66 MHz Characteristic Unit Min Max Min Max Min Max Min Max B29b CS negated to D(0:31), DP(0:3), High Z GPCM write access, ACS = 00, TRLX = 0,1 and CSNT = 0 (MIN = 0.25 x B1 - 2.00) 5.60 -- 4.30 -- 3.00 -- 1.80 -- ns B29c CS negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 0, CSNT = 1, ACS = 10, or ACS = 11 EBDF = 0 (MIN = 0.50 x B1 - 2.00) 13.20 -- 10.50 -- 8.00 -- 5.60 -- ns B29d WE(0:3)/BS_B[0:3] negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 0 (MIN = 1.50 x B1 - 2.00) 43.50 -- 35.50 -- 28.00 -- 20.70 -- ns B29e CS negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 1, CSNT = 1, ACS = 10, or ACS = 11 EBDF = 0 (MIN = 1.50 x B1 - 2.00) 43.50 -- 35.50 -- 28.00 -- 20.70 -- ns B29f WE(0:3/BS_B[0:3]) negated to D(0:31), DP(0:3) High Z GPCM write access, TRLX = 0, CSNT = 1, EBDF = 1 (MIN = 0.375 x B1 - 6.30)8 5.00 -- 3.00 -- 1.10 -- 0.00 -- ns B29g CS negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 0, CSNT = 1 ACS = 10 or ACS = 11, EBDF = 1 (MIN = 0.375 x B1 - 6.30)8 5.00 -- 3.00 -- 1.10 -- 0.00 -- ns B29h WE(0:3)/BS_B[0:3] negated to D(0:31), DP(0:3) High Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 1 (MIN = 0.375 x B1 - 3.30) 38.40 -- 31.10 -- 24.20 -- 17.50 -- ns B29i CS negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1 (MIN = 0.375 x B1 - 3.30) 38.40 -- 31.10 -- 24.20 -- 17.50 -- ns B30 CS, WE(0:3)/BS_B[0:3] negated to A(0:31), BADDR(28:30) Invalid GPCM write access 9 (MIN = 0.25 x B1 - 2.00) 5.60 -- 4.30 -- 3.00 -- 1.80 -- ns B30a WE(0:3)/BS_B[0:3] negated to A(0:31), BADDR(28:30) Invalid GPCM, write access, TRLX = 0, CSNT = 1, CS negated to A(0:31) invalid GPCM write access TRLX = 0, CSNT =1 ACS = 10, or ACS == 11, EBDF = 0 (MIN = 0.50 x B1 - 2.00) 13.20 -- 10.50 -- 8.00 -- 5.60 -- ns MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 18 Freescale Semiconductor Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num 40 MHz 50 MHz 66 MHz Characteristic Unit Min Max Min Max Min Max Min Max B30b WE(0:3)/BS_B[0:3] negated to A(0:31) Invalid GPCM BADDR(28:30) invalid GPCM write access, TRLX = 1, CSNT = 1. CS negated to A(0:31) Invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10, or ACS == 11 EBDF = 0 (MIN = 1.50 x B1 - 2.00) 43.50 -- 35.50 -- 28.00 -- 20.70 -- ns B30c WE(0:3)/BS_B[0:3] negated to A(0:31), BADDR(28:30) invalid GPCM write access, TRLX = 0, CSNT = 1. CS negated to A(0:31) invalid GPCM write access, TRLX = 0, CSNT = 1 ACS = 10, ACS == 11, EBDF = 1 (MIN = 0.375 x B1 - 3.00) 8.40 -- 6.40 -- 4.50 -- 2.70 -- ns B30d WE(0:3)/BS_B[0:3] negated to A(0:31), BADDR(28:30) invalid GPCM write access TRLX = 1, CSNT =1, CS negated to A(0:31) invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10 or 11, EBDF = 1 38.67 -- 31.38 -- 24.50 -- 17.83 -- ns B31 CLKOUT falling edge to CS valid - as requested by control bit CST4 in the corresponding word in the UPM (MAX = 0.00 x B1 + 6.00) 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns B31a CLKOUT falling edge to CS valid - as requested by control bit CST1 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.80) 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns B31b CLKOUT rising edge to CS valid - as requested by control bit CST2 in the corresponding word in the UPM (MAX = 0.00 x B1 + 8.00) 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns B31c CLKOUT rising edge to CS valid- as requested by control bit CST3 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.30) 7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns B31d CLKOUT falling edge to CS valid, as requested by control bit CST1 in the corresponding word in the UPM EBDF = 1 (MAX = 0.375 x B1 + 6.6) 13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns B32 CLKOUT falling edge to BS valid- as requested by control bit BST4 in the corresponding word in the UPM (MAX = 0.00 x B1 + 6.00) 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 19 Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num 40 MHz 50 MHz 66 MHz Characteristic Unit Min Max Min Max Min Max Min Max B32a CLKOUT falling edge to BS valid - as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 0 (MAX = 0.25 x B1 + 6.80) 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns B32b CLKOUT rising edge to BS valid - as requested by control bit BST2 in the corresponding word in the UPM (MAX = 0.00 x B1 + 8.00) 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns B32c CLKOUT rising edge to BS valid - as requested by control bit BST3 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.80) 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns B32d CLKOUT falling edge to BS valid- as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 1 (MAX = 0.375 x B1 + 6.60) 13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns B33 CLKOUT falling edge to GPL valid - as requested by control bit GxT4 in the corresponding word in the UPM (MAX = 0.00 x B1 + 6.00) 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns B33a CLKOUT rising edge to GPL Valid - as requested by control bit GxT3 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.80) 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns B34 A(0:31), BADDR(28:30), and D(0:31) to CS valid - as requested by control bit CST4 in the corresponding word in the UPM (MIN = 0.25 x B1 - 2.00) 5.60 -- 4.30 -- 3.00 -- 1.80 -- ns B34a A(0:31), BADDR(28:30), and D(0:31) to CS valid - as requested by control bit CST1 in the corresponding word in the UPM (MIN = 0.50 x B1 - 2.00) 13.20 -- 10.50 -- 8.00 -- 5.60 -- ns B34b A(0:31), BADDR(28:30), and D(0:31) to CS valid - as requested by CST2 in the corresponding word in UPM (MIN = 0.75 x B1 - 2.00) 20.70 -- 16.70 -- 13.00 -- 9.40 -- ns B35 A(0:31), BADDR(28:30) to CS valid - as requested by control bit BST4 in the corresponding word in the UPM (MIN = 0.25 x B1 - 2.00) 5.60 -- 4.30 -- 3.00 -- 1.80 -- ns B35a A(0:31), BADDR(28:30), and D(0:31) to BS valid - As Requested by BST1 in the corresponding word in the UPM (MIN = 0.50 x B1 - 2.00) 13.20 -- 10.50 -- 8.00 -- 5.60 -- ns MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 20 Freescale Semiconductor Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num 40 MHz 50 MHz 66 MHz Characteristic Unit Min Max Min Max Min Max Min Max B35b A(0:31), BADDR(28:30), and D(0:31) to BS valid - as requested by control bit BST2 in the corresponding word in the UPM (MIN = 0.75 x B1 - 2.00) 20.70 -- 16.70 -- 13.00 -- 9.40 -- ns B36 A(0:31), BADDR(28:30), and D(0:31) to GPL valid as requested by control bit GxT4 in the corresponding word in the UPM (MIN = 0.25 x B1 - 2.00) 5.60 -- 4.30 -- 3.00 -- 1.80 -- ns B37 UPWAIT valid to CLKOUT falling edge10 (MIN = 0.00 x B1 + 6.00) 6.00 -- 6.00 -- 6.00 -- 6.00 -- ns B38 CLKOUT falling edge to UPWAIT valid10 (MIN = 0.00 x B1 + 1.00) 1.00 -- 1.00 -- 1.00 -- 1.00 -- ns B39 AS valid to CLKOUT rising edge11 (MIN = 0.00 x B1 + 7.00) 7.00 -- 7.00 -- 7.00 -- 7.00 -- ns B40 A(0:31), TSIZ(0:1), RD/WR, BURST, valid to CLKOUT rising edge (MIN = 0.00 x B1 + 7.00) 7.00 -- 7.00 -- 7.00 -- 7.00 -- ns B41 TS valid to CLKOUT rising edge (setup time) (MIN = 0.00 x B1 + 7.00) 7.00 -- 7.00 -- 7.00 -- 7.00 -- ns B42 CLKOUT rising edge to TS valid (hold time) (MIN = 0.00 x B1 + 2.00) 2.00 -- 2.00 -- 2.00 -- 2.00 -- ns B43 AS negation to memory controller signals negation (MAX = TBD) -- TBD -- TBD -- TBD -- TBD ns 1 If the rate of change of the frequency of EXTAL is slow (that is, it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time), then the maximum allowed jitter on EXTAL can be up to 2%. 2 For part speeds above 50MHz, use 9.80ns for B11a. 3 The timing required for BR input is relevant when the MPC852T is selected to work with internal bus arbiter. The timing for BG input is relevant when the MPC852T is selected to work with external bus arbiter. 4 For part speeds above 50MHz, use 2ns for B17. 5 The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is asserted. 6 For part speeds above 50MHz, use 2ns for B19. 7 The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for read accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) 8 This formula applies to bus operation up to 50 MHz. 9 The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0. 10 The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 19. 11 The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified in Figure 22. MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 21 Bus Signal Timing Figure 4 is the control timing diagram. CLKOUT A B Outputs A B Outputs D C Inputs D C Inputs A Maximum output delay specification. B Minimum output hold time. C Minimum input setup time specification. D Minimum input hold time specification. Figure 4. Control Timing Figure 5 provides the timing for the external clock. CLKOUT B1 B3 B1 B4 B2 B5 Figure 5. External Clock Timing MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 22 Freescale Semiconductor Bus Signal Timing Figure 6 provides the timing for the synchronous output signals. CLKOUT B8 B7 B9 Output Signals B8a B7a B9 Output Signals B8b B7b Output Signals Figure 6. Synchronous Output Signals Timing Figure 7 provides the timing for the synchronous active pull-up and open-drain output signals. CLKOUT B13 B11 B12 TS, BB B13a B11a B12a TA, BI B14 B15 TEA Figure 7. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 23 Bus Signal Timing Figure 8 provides the timing for the synchronous input signals. CLKOUT B16 B17 TA, BI B16a B17a TEA, KR, RETRY, CR B16b B17 BB, BG, BR Figure 8. Synchronous Input Signals Timing Figure 9 provides normal case timing for input data. It also applies to normal read accesses under the control of the UPM in the memory controller. CLKOUT B16 B17 TA B18 B19 D[0:31], DP[0:3] Figure 9. Input Data Timing in Normal Case MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 24 Freescale Semiconductor Bus Signal Timing Figure 10 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) CLKOUT TA B20 B21 D[0:31], DP[0:3] Figure 10. Input Data Timing When Controlled by UPM in the Memory Controller and DLT3 = 1 Figure 11 through Figure 14 provide the timing for the external bus read that various GPCM factors control. CLKOUT B11 B12 TS B8 A[0:31] B22 B23 CSx B25 B26 OE B28 WE[0:3] B19 B18 D[0:31], DP[0:3] Figure 11. External Bus Read Timing (GPCM Controlled--ACS = 00) MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 25 Bus Signal Timing CLKOUT B11 B12 TS B8 A[0:31] B22a B23 CSx B24 B25 B26 OE B18 B19 D[0:31], DP[0:3] Figure 12. External Bus Read Timing (GPCM Controlled--TRLX = 0, ACS = 10) CLKOUT B11 B12 TS B8 B22b A[0:31] B22c B23 CSx B24a B25 B26 OE B18 B19 D[0:31], DP[0:3] Figure 13. External Bus Read Timing (GPCM Controlled--TRLX = 0, ACS = 11) MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 26 Freescale Semiconductor Bus Signal Timing CLKOUT B11 B12 TS B8 A[0:31] B22a B23 CSx B27 OE B26 B27a B22b B22c B18 B19 D[0:31], DP[0:3] Figure 14. External Bus Read Timing (GPCM Controlled--TRLX = 0 or 1, ACS = 10, ACS = 11) MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 27 Bus Signal Timing Figure 15 through Figure 17 provide the timing for the external bus write that various GPCM factors control. CLKOUT B11 B12 TS B8 B30 A[0:31] B22 B23 CSx B25 B28 WE[0:3] B29b B26 OE B29 B8 B9 D[0:31], DP[0:3] Figure 15. External Bus Write Timing (GPCM Controlled--TRLX = 0 or 1, CSNT = 0) MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 28 Freescale Semiconductor Bus Signal Timing CLKOUT B11 B12 TS B30a B30c B8 A[0:31] B28b B28d B22 B23 CSx B29c B29g B25 WE[0:3] B29a B29f B26 OE B28a B28c B8 B9 D[0:31], DP[0:3] Figure 16. External Bus Write Timing (GPCM Controlled--TRLX = 0 or 1, CSNT = 1) MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 29 Bus Signal Timing CLKOUT B11 B12 TS B8 B30b B30d A[0:31] B22 B28b B28d B23 CSx B25 B29e B29i WE[0:3] B29d B29h B26 OE B29b B8 B28a B28c B9 D[0:31], DP[0:3] Figure 17. External Bus Write Timing (GPCM Controlled--TRLX = 0 or 1, CSNT = 1) MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 30 Freescale Semiconductor Bus Signal Timing Figure 18 provides the timing for the external bus that the UPM controls. CLKOUT B8 A[0:31] B31a B31d B31c B31b B31 CSx B34 B34a B34b B32a B32d B32c B32b B32 BS_A[0:3] B35 B36 B35a B33a B35b B33 GPL_A[0:5], GPL_B[0:5] Figure 18. External Bus Timing (UPM Controlled Signals) MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 31 Bus Signal Timing Figure 19 provides the timing for the asynchronous asserted UPWAIT signal that the UPM controls. CLKOUT B37 UPWAIT B38 CSx BS_A[0:3] GPL_A[0:5], GPL_B[0:5] Figure 19. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing Figure 20 provides the timing for the asynchronous negated UPWAIT signal that the UPM controls. CLKOUT B37 UPWAIT B38 CSx BS_A[0:3] GPL_A[0:5], GPL_B[0:5] Figure 20. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 32 Freescale Semiconductor Bus Signal Timing Figure 21 provides the timing for the synchronous external master access that the GPCM controls. CLKOUT B41 B42 TS B40 A[0:31], TSIZ[0:1], R/W, BURST B22 CSx Figure 21. Synchronous External Master Access Timing (GPCM Handled ACS = 00) Figure 22 provides the timing for the asynchronous external master memory access that the GPCM controls. CLKOUT B39 AS B40 A[0:31], TSIZ[0:1], R/W B22 CSx Figure 22. Asynchronous External Master Memory Access Timing (GPCM Controlled--ACS = 00) Figure 23 provides the timing for the asynchronous external master control signals negation. AS B43 CSx, WE[0:3], OE, GPLx, BS[0:3] Figure 23. Asynchronous External Master--Control Signals Negation Timing MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 33 Bus Signal Timing Table 10 provides interrupt timing for the MPC852T. . Table 10. Interrupt Timing All Frequencies Characteristic1 Num Unit Min 1 Max I39 IRQx valid to CLKOUT rising edge (set up time) 6.00 ns I40 IRQx hold time after CLKOUT 2.00 ns I41 IRQx pulse width low 3.00 ns I42 IRQx pulse width high 3.00 ns I43 IRQx edge-to-edge time 4 x TCLOCKOUT -- The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as level-sensitive. The IRQ lines are synchronized internally and need not be asserted or negated with reference to the CLKOUT. The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and have no direct relation with the total system interrupt latency that the MPC852T is able to support. Figure 24 provides the interrupt detection timing for the external level-sensitive lines. CLKOUT I39 I40 IRQx Figure 24. Interrupt Detection Timing for External Level Sensitive Lines Figure 25 provides the interrupt detection timing for the external edge-sensitive lines. CLKOUT I41 I42 IRQx I43 I43 Figure 25. Interrupt Detection Timing for External Edge Sensitive Lines MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 34 Freescale Semiconductor Bus Signal Timing Table 11 shows the PCMCIA timing for the MPC852T. Table 11. PCMCIA Timing 33 MHz Num 50 MHz 66 MHz Unit Min Max Min Max Min Max Min Max A(0:31), REG valid to PCMCIA Strobe asserted.1 (MIN = 0.75 x B1 - 2.00) 20.70 -- 16.70 -- 13.00 -- 9.40 -- ns J83 A(0:31), REG valid to ALE negation.1 (MIN = 1.00 x B1 - 2.00) 28.30 -- 23.00 -- 18.00 -- 13.20 -- ns J84 CLKOUT to REG valid (MAX = 0.25 x B1 + 8.00) 7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns J85 CLKOUT to REG Invalid. (MIN = 0.25 x B1 + 1.00) 8.60 -- 7.30 -- 6.00 -- 4.80 -- ns J86 CLKOUT to CE1, CE2 asserted. (MAX = 0.25 x B1 + 8.00) 7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns J87 CLKOUT to CE1, CE2 negated. (MAX = 0.25 x B1 + 8.00) 7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns J88 CLKOUT to PCOE, IORD, PCWE, IOWR assert time. (MAX = 0.00 x B1 + 11.00) -- 11.00 -- 11.00 -- 11.00 -- 11.00 ns J89 CLKOUT to PCOE, IORD, PCWE, IOWR negate time. (MAX = 0.00 x B1 + 11.00) 2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00 ns J90 CLKOUT to ALE assert time (MAX = 0.25 x B1 + 6.30) 7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns J91 CLKOUT to ALE negate time (MAX = 0.25 x B1 + 8.00) -- 15.60 -- 14.30 -- 13.00 -- 11.80 ns J92 PCWE, IOWR negated to D(0:31) invalid.1 (MIN = 0.25 x B1 - 2.00) 5.60 -- 4.30 -- 3.00 -- 1.80 -- ns J93 WAITA and WAITB valid to CLKOUT rising edge.1 (MIN = 0.00 x B1 + 8.00) 8.00 -- 8.00 -- 8.00 -- 8.00 -- ns J94 CLKOUT rising edge to WAITA and WAITB invalid.1 (MIN = 0.00 x B1 + 2.00) 2.00 -- 2.00 -- 2.00 -- 2.00 -- ns J82 1 40 MHz Characteristic PSST = 1. Otherwise add PSST times cycle time. PSHT = 0. Otherwise add PSHT times cycle time. These synchronous timings define when the WAITA signals are detected in order to freeze (or relieve) the PCMCIA current cycle. The WAITA assertion is effective only if it is detected 2 cycles before the PSL timer expiration. See the PCMCIA Interface section in the MPC866 PowerQUICCTM Family Reference Manual. MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 35 Bus Signal Timing Figure 26 provides the PCMCIA access cycle timing for the external bus read. CLKOUT TS P44 A[0:31] P46 P45 P47 REG P48 P49 CE1/CE2 P50 P51 P53 P52 PCOE, IORD P52 ALE B18 B19 D[0:31] Figure 26. PCMCIA Access Cycles Timing External Bus Read MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 36 Freescale Semiconductor Bus Signal Timing Figure 27 provides the PCMCIA access cycle timing for the external bus write. CLKOUT TS P44 A[0:31] P46 P45 P47 REG P48 P49 CE1/CE2 P50 P51 P53 P52 B8 B9 P54 PCWE, IOWR P52 ALE D[0:31] Figure 27. PCMCIA Access Cycles Timing External Bus Write Figure 28 provides the PCMCIA WAIT signals detection timing. CLKOUT P55 P56 WAITA Figure 28. PCMCIA WAIT Signals Detection Timing MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 37 Bus Signal Timing Table 12 shows the PCMCIA port timing for the MPC852T. Table 12. PCMCIA Port Timing 33 MHz Num 40 MHz 50 MHz 66 MHz Characteristic Unit Min Max Min Max Min Max Min Max -- 19.00 -- 19.00 -- 19.00 -- 19.00 ns J95 CLKOUT to OPx Valid (MAX = 0.00 x B1 + 19.00) J96 HRESET negated to OPx drive1 (MIN = 0.75 x B1 + 3.00) 25.70 -- 21.70 -- 18.00 -- 14.40 -- ns J97 IP_Xx valid to CLKOUT rising edge (MIN = 0.00 x B1 + 5.00) 5.00 -- 5.00 -- 5.00 -- 5.00 -- ns J98 CLKOUT rising edge to IP_Xx invalid (MIN = 0.00 x B1 + 1.00) 1.00 -- 1.00 -- 1.00 -- 1.00 -- ns 1 OP2 and OP3 only. Figure 29 provides the PCMCIA output port timing for the MPC852T. CLKOUT P57 Output Signals HRESET P58 OP2, OP3 Figure 29. PCMCIA Output Port Timing Figure 30 provides the PCMCIA output port timing for the MPC852T. CLKOUT P59 P60 Input Signals Figure 30. PCMCIA Input Port Timing MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 38 Freescale Semiconductor Bus Signal Timing Table 13 shows the debug port timing for the MPC852T. Table 13. Debug Port Timing All Frequencies Num Characteristic Unit Min Max 3 x TCLOCKOUT -- -- J82 DSCK cycle time J83 DSCK clock pulse width 1.25 x TCLOCKOUT -- -- J84 DSCK rise and fall times 0.00 3.00 ns J85 DSDI input data setup time 8.00 -- ns J86 DSDI data hold time 5.00 -- ns J87 DSCK low to DSDO data valid 0.00 15.00 ns J88 DSCK low to DSDO invalid 0.00 2.00 ns Figure 31 provides the input timing for the debug port clock. DSCK D61 D62 D61 D62 D63 D63 Figure 31. Debug Port Clock Input Timing Figure 32 provides the timing for the debug port. DSCK D64 D65 DSDI D66 D67 DSDO Figure 32. Debug Port Timings MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 39 Bus Signal Timing Table 14 shows the reset timing for the MPC852T. Table 14. Reset Timing 33 MHz Num 40 MHz 50 MHz 66 MHz Characteristic Unit Min Max Min Max Min Max Min Max J82 CLKOUT to HRESET high impedance (MAX = 0.00 x B1 + 20.00) -- 20.00 -- 20.00 -- 20.00 -- 20.00 ns J83 CLKOUT to SRESET high impedance (MAX = 0.00 x B1 + 20.00) -- 20.00 -- 20.00 -- 20.00 -- 20.00 ns J84 RSTCONF pulse width (MIN = 17.00 x B1) 515.20 -- 425.00 -- 340.00 -- 257.60 -- ns J85 -- -- -- -- -- -- -- -- -- J86 Configuration data to HRESET rising edge 504.50 set up time (MIN = 15.00 x B1 + 50.00) -- 425.00 -- 350.00 -- 277.30 -- ns J87 Configuration data to RSTCONF rising edge set up time (MIN = 0.00 x B1 + 350.00) 350.00 -- 350.00 -- 350.00 -- 350.00 -- ns J88 Configuration data hold time after RSTCONF negation (MIN = 0.00 x B1 + 0.00) 0.00 -- 0.00 -- 0.00 -- 0.00 -- ns J89 Configuration data hold time after HRESET negation (MIN = 0.00 x B1 + 0.00) 0.00 -- 0.00 -- 0.00 -- 0.00 -- ns J90 HRESET and RSTCONF asserted to data out drive (MAX = 0.00 x B1 + 25.00) -- 25.00 -- 25.00 -- 25.00 -- 25.00 ns J91 RSTCONF negated to data out high impedance. (MAX = 0.00 x B1 + 25.00) -- 25.00 -- 25.00 -- 25.00 -- 25.00 ns J92 CLKOUT of last rising edge before chip three-states HRESET to data out high impedance. (MAX = 0.00 x B1 + 25.00) -- 25.00 -- 25.00 -- 25.00 -- 25.00 ns J93 DSDI, DSCK set up (MIN = 3.00 x B1) 90.90 -- 75.00 -- 60.00 -- 45.50 -- ns J94 DSDI, DSCK hold time (MIN = 0.00 x B1 + 0.00) 0.00 -- 0.00 -- 0.00 -- 0.00 -- ns J95 SRESET negated to CLKOUT rising edge 242.40 for DSDI and DSCK sample (MIN = 8.00 x B1) -- 200.00 -- 160.00 -- 121.20 -- ns -- MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 40 Freescale Semiconductor Bus Signal Timing Figure 33 shows the reset timing for the data bus configuration. HRESET R71 R76 RSTCONF R73 R74 R75 D[0:31] (IN) Figure 33. Reset Timing--Configuration from Data Bus Figure 34 provides the reset timing for the data bus weak drive during configuration. CLKOUT R69 HRESET R79 RSTCONF R77 R78 D[0:31] (OUT) (Weak) Figure 34. Reset Timing--Data Bus Weak Drive During Configuration MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 41 IEEE 1149.1 Electrical Specifications Figure 35 provides the reset timing for the debug port configuration. CLKOUT R70 R82 SRESET R80 R80 R81 R81 DSCK, DSDI Figure 35. Reset Timing--Debug Port Configuration 13 IEEE 1149.1 Electrical Specifications Table 15 provides the JTAG timings for the MPC852T shown in Figure 36 through Figure 39. Table 15. JTAG Timing All Frequencies Num Characteristic Unit Min Max J82 TCK cycle time 100.00 -- ns J83 TCK clock pulse width measured at 1.5 V 40.00 -- ns J84 TCK rise and fall times 0.00 10.00 ns J85 TMS, TDI data setup time 5.00 -- ns J86 TMS, TDI data hold time 25.00 -- ns J87 TCK low to TDO data valid -- 27.00 ns J88 TCK low to TDO data invalid 0.00 -- ns J89 TCK low to TDO high impedance -- 20.00 ns J90 TRST assert time 100.00 -- ns J91 TRST setup time to TCK low 40.00 -- ns J92 TCK falling edge to output valid -- 50.00 ns J93 TCK falling edge to output valid out of high impedance -- 50.00 ns J94 TCK falling edge to output high impedance -- 50.00 ns J95 Boundary scan input valid to TCK rising edge 50.00 -- ns J96 TCK rising edge to boundary scan input invalid 50.00 -- ns MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 42 Freescale Semiconductor IEEE 1149.1 Electrical Specifications TCK J82 J83 J82 J83 J84 J84 Figure 36. JTAG Test Clock Input Timing TCK J85 J86 TMS, TDI J87 J88 J89 TDO Figure 37. JTAG Test Access Port Timing Diagram TCK J91 J90 TRST Figure 38. JTAG TRST Timing Diagram TCK J92 J94 Output Signals J93 Output Signals J95 J96 Output Signals Figure 39. Boundary Scan (JTAG) Timing Diagram MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 43 CPM Electrical Characteristics 14 CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module (CPM) of the MPC852T. 14.1 Port C Interrupt AC Electrical Specifications Table 16 provides the timings for port C interrupts. Table 16. Port C Interrupt Timing 33.34 MHz Num Characteristic Unit Min Max 35 Port C interrupt pulse width low (edge-triggered mode) 55 -- ns 36 Port C interrupt minimum time between active edges 55 -- ns Figure 40 shows the port C interrupt detection timing. 36 Port C (Input) 35 Figure 40. Port C Interrupt Detection Timing MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 44 Freescale Semiconductor CPM Electrical Characteristics 14.2 IDMA Controller AC Electrical Specifications Table 17 provides the IDMA controller timings as shown in Figure 41 through Figure 44. Table 17. IDMA Controller Timing All Frequencies Num 40 1 Characteristic Unit Min Max 7 -- ns 3 -- ns DREQ setup time to clock high 1 41 DREQ hold time from clock high 42 SDACK assertion delay from clock high -- 12 ns 43 SDACK negation delay from clock low -- 12 ns 44 SDACK negation delay from TA low -- 20 ns 45 SDACK negation delay from clock high -- 15 ns 46 TA assertion to rising edge of the clock setup time (applies to external TA) 7 -- ns Applies to high-to-low mode (EDM = 1). CLKO (Output) 41 40 DREQ (Input) Figure 41. IDMA External Requests Timing Diagram MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 45 CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) 42 43 DATA 46 TA (Input) SDACK Figure 42. SDACK Timing Diagram--Peripheral Write, Externally-Generated TA CLKO (Output) TS (Output) R/W (Output) 42 44 DATA TA (Output) SDACK Figure 43. SDACK Timing Diagram--Peripheral Write, Internally-Generated TA MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 46 Freescale Semiconductor CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) 42 45 DATA TA (Output) SDACK Figure 44. SDACK Timing Diagram--Peripheral Read, Internally-Generated TA 14.3 Baud Rate Generator AC Electrical Specifications Table 18 provides the baud rate generator timings as shown in Figure 45. Table 18. Baud Rate Generator Timing All Frequencies Num Characteristic Unit Min Max 50 BRGO rise and fall time -- 10 ns 51 BRGO duty cycle 40 60 % 52 BRGO cycle 40 -- ns 50 50 BRGOX 51 51 52 Figure 45. Baud Rate Generator Timing Diagram MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 47 CPM Electrical Characteristics 14.4 Timer AC Electrical Specifications Table 19 provides the general-purpose timer timings as shown in Figure 46. Table 19. Timer Timing All Frequencies Num Characteristic Unit Min Max 61 TIN/TGATE rise and fall time 10 -- ns 62 TIN/TGATE low time 1 -- clk 63 TIN/TGATE high time 2 -- clk 64 TIN/TGATE cycle time 3 -- clk 65 CLKO low to TOUT valid 3 25 ns CLKO 60 61 63 62 TIN/TGATE (Input) 61 64 65 TOUT (Output) Figure 46. CPM General-Purpose Timers Timing Diagram 14.5 SCC in NMSI Mode Electrical Specifications Table 20 provides the NMSI external clock timing. Table 20. NMSI External Clock Timing All Frequencies Num Characteristic Unit Min Max 1/SYNCCLK -- ns 1/SYNCCLK + 5 -- ns -- 15.00 ns 100 RCLK3 and TCLK3 width high1 101 RCLK3 and TCLK3 width low 102 RCLK3 and TCLK3 rise/fall time 103 TXD3 active delay (from TCLK3 falling edge) 0.00 50.00 ns 104 RTS3 active/inactive delay (from TCLK3 falling edge) 0.00 50.00 ns 105 CTS3 setup time to TCLK3 rising edge 5.00 -- ns 106 RXD3 setup time to RCLK3 rising edge 5.00 -- ns MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 48 Freescale Semiconductor CPM Electrical Characteristics Table 20. NMSI External Clock Timing (continued) All Frequencies Num 1 2 Characteristic Unit Min Max 107 RXD3 hold time from RCLK3 rising edge2 5.00 -- ns 108 CD3 setup Time to RCLK3 rising edge 5.00 -- ns The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2.25/1. Also applies to CD and CTS hold time when they are used as an external sync signal. Table 21 provides the NMSI internal clock timing. Table 21. NMSI Internal Clock Timing All Frequencies Num 1 2 Characteristic Unit Min Max 100 RCLK3 and TCLK3 frequency1 0.00 SYNCCLK/3 MHz 102 RCLK3 and TCLK3 rise/fall time -- -- ns 103 TXD3 active delay (from TCLK3 falling edge) 0.00 30.00 ns 104 RTS3 active/inactive delay (from TCLK3 falling edge) 0.00 30.00 ns 105 CTS3 setup time to TCLK3 rising edge 40.00 -- ns 106 RXD3 setup time to RCLK3 rising edge 40.00 -- ns 107 RXD3 hold time from RCLK3 rising edge2 0.00 -- ns 108 CD3 setup time to RCLK3 rising edge 40.00 -- ns The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 3/1. Also applies to CD and CTS hold time when they are used as an external sync signals. MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 49 CPM Electrical Characteristics Figure 47 through Figure 49 show the NMSI timings. RCLK3 102 102 101 106 100 RxD3 (Input) 107 108 CD3 (Input) 107 CD3 (SYNC Input) Figure 47. SCC NMSI Receive Timing Diagram TCLK3 102 102 101 100 TxD3 (Output) 103 105 RTS3 (Output) 104 104 CTS3 (Input) 107 CTS3 (SYNC Input) Figure 48. SCC NMSI Transmit Timing Diagram MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 50 Freescale Semiconductor CPM Electrical Characteristics TCLK3 102 102 101 100 TxD3 (Output) 103 RTS3 (Output) 104 107 104 105 CTS3 (Echo Input) Figure 49. HDLC Bus Timing Diagram 14.6 Ethernet Electrical Specifications Table 22 provides the Ethernet timings as shown in Figure 50 through Figure 54. Table 22. Ethernet Timing All Frequencies Num Characteristic Unit Min Max 120 CLSN width high 40 -- ns 121 RCLK3 rise/fall time -- 15 ns 122 RCLK3 width low 40 -- ns 123 RCLK3 clock period1 80 120 ns 124 RXD3 setup time 20 -- ns 125 RXD3 hold time 5 -- ns 126 RENA active delay (from RCLK3 rising edge of the last data bit) 10 -- ns 127 RENA width low 100 -- ns 128 TCLK3 rise/fall time -- 15 ns 129 TCLK3 width low 40 -- ns 99 101 ns period1 130 TCLK3 clock 131 TXD3 active delay (from TCLK3 rising edge) -- 50 ns 132 TXD3 inactive delay (from TCLK3 rising edge) 6.5 50 ns 133 TENA active delay (from TCLK3 rising edge) 10 50 ns 134 TENA inactive delay (from TCLK3 rising edge) 10 50 ns MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 51 CPM Electrical Characteristics Table 22. Ethernet Timing (continued) All Frequencies Num 1 2 Characteristic Unit Min Max 135 RSTRT active delay (from TCLK3 falling edge) 10 50 ns 136 RSTRT inactive delay (from TCLK3 falling edge) 10 50 ns 137 REJECT width low 1 -- CLK 138 CLKO1 low to SDACK asserted 2 -- 20 ns 139 CLKO1 low to SDACK negated 2 -- 20 ns The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 2/1. SDACK is asserted whenever the SDMA writes the incoming frame DA into memory. CLSN(CTS1) (Input) 120 Figure 50. Ethernet Collision Timing Diagram RCLK3 121 121 124 123 RxD3 (Input) Last Bit 125 126 127 RENA(CD3) (Input) Figure 51. Ethernet Receive Timing Diagram MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 52 Freescale Semiconductor CPM Electrical Characteristics TCLK3 128 128 129 131 121 TxD3 (Output) 132 133 134 TENA(RTS3) (Input) RENA(CD3) (Input) (Note 2) Notes: 1. Transmit clock invert (TCI) bit in GSMR is set. 2. If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, the CSL bit is set in the buffer descriptor at the end of the frame transmission. Figure 52. Ethernet Transmit Timing Diagram RCLK3 RxD3 (Input) 0 1 1 BIT1 Start Frame De- BIT2 136 125 RSTRT (Output) Figure 53. CAM Interface Receive Start Timing Diagram REJECT 137 Figure 54. CAM Interface REJECT Timing Diagram MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 53 CPM Electrical Characteristics 14.7 SPI Master AC Electrical Specifications Table 23 provides the SPI master timings as shown in Figure 55 and Figure 56. Table 23. SPI Master Timing All Frequencies Num Characteristic Unit Min Max 160 MASTER cycle time 4 1024 tcyc 161 MASTER clock (SCK) high or low time 2 512 tcyc 162 MASTER data setup time (inputs) 15 -- ns 163 Master data hold time (inputs) 0 -- ns 164 Master data valid (after SCK edge) -- 10 ns 165 Master data hold time (outputs) 0 -- ns 166 Rise time output -- 15 ns 167 Fall time output -- 15 ns SPICLK (CI = 0) (Output) 161 167 161 166 160 SPICLK (CI = 1) (Output) 163 167 162 SPIMISO (Input) msb 166 Data 165 lsb msb 164 167 SPIMOSI (Output) 166 msb Data lsb msb Figure 55. SPI Master (CP = 0) Timing Diagram MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 54 Freescale Semiconductor CPM Electrical Characteristics SPICLK (CI=0) (Output) 161 167 166 161 160 SPICLK (CI=1) (Output) 163 167 162 166 SPIMISO (Input) msb Data 165 lsb msb 164 167 SPIMOSI (Output) 166 msb Data lsb msb Figure 56. SPI Master (CP = 1) Timing Diagram 14.8 SPI Slave AC Electrical Specifications Table 24 provides the SPI slave timings as shown in Figure 57 and Figure 58. Table 24. SPI Slave Timing All Frequencies Num Characteristic Unit Min Max 170 Slave cycle time 2 -- tcyc 171 Slave enable lead time 15 -- ns 172 Slave enable lag time 15 -- ns 173 Slave clock (SPICLK) high or low time 1 -- tcyc 174 Slave sequential transfer delay (does not require deselect) 1 -- tcyc 175 Slave data setup time (inputs) 20 -- ns 176 Slave data hold time (inputs) 20 -- ns 177 Slave access time -- 50 ns MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 55 CPM Electrical Characteristics SPISEL (Input) 172 171 174 SPICLK (CI = 0) (Input) 173 182 173 181 170 SPICLK (CI = 1) (Input) 177 181 182 180 SPIMISO (Output) msb 178 Data 175 lsb msb 179 176 SPIMOSI (Input) Undef 181 182 msb Data lsb msb Figure 57. SPI Slave (CP = 0) Timing Diagram SPISEL (Input) 172 171 174 170 SPICLK (CI = 0) (Input) 173 182 181 173 181 SPICLK (CI = 1) (Input) 177 182 180 SPIMISO (Output) Undef msb 175 lsb msb 179 176 SPIMOSI (Input) Data 178 msb 181 182 Data lsb msb Figure 58. SPI Slave (CP = 1) Timing Diagram MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 56 Freescale Semiconductor FEC Electrical Characteristics 15 FEC Electrical Characteristics This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V. 15.1 MII Receive Signal Timing (MII_RXD[3:0], MII_RX_DV, MII_RX_ER, MII_RX_CLK) The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK frequency -1%. Table 25 provides information on the MII receive signal timing. Table 25. MII Receive Signal Timing Num Characteristic Min Max Unit M1 MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup 5 -- ns M2 MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold 5 -- ns M3 MII_RX_CLK pulse width high 35% 65% MII_RX_CLK period M4 MII_RX_CLK pulse width low 35% 65% MII_RX_CLK period Figure 59 shows MII receive signal timing. M3 MII_RX_CLK (Input) M4 MII_RXD[3:0] (Inputs) MII_RX_DV MII_RX_ER M1 M2 Figure 59. MII Receive Signal Timing Diagram 15.2 MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN, MII_TX_ER, MII_TX_CLK) The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK frequency - 1%. MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 57 FEC Electrical Characteristics Table 26 provides information about the MII transmit signal timing,. Table 26. MII Transmit Signal Timing Num Characteristic Min Max Unit M5 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid 5 -- ns M6 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid -- 25 -- M7 MII_TX_CLK pulse width high 35% 65% MII_TX_CLK period M8 MII_TX_CLK pulse width low 35% 65% MII_TX_CLK period Figure 60 shows the MII transmit signal timing diagram. M7 MII_TX_CLK (Input) M5 M8 MII_TXD[3:0] (Outputs) MII_TX_EN MII_TX_ER M6 Figure 60. MII Transmit Signal Timing Diagram 15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL) Table 27 provides information about the MII async inputs signal timing. Table 27. MII Async Inputs Signal Timing Num M9 Characteristic MII_CRS, MII_COL minimum pulse width Min Max Unit 1.5 -- MII_TX_CLK period Figure 61 shows the MII asynchronous inputs signal timing diagram. MII_CRS, MII_COL M9 Figure 61. MII Async Inputs Timing Diagram MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 58 Freescale Semiconductor FEC Electrical Characteristics 15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC) Table 28 provides information on the MII serial management channel signal timing. The FEC functions correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation. Table 28. MII Serial Management Channel Timing Num Characteristic Min Max Unit M10 MII_MDC falling edge to MII_MDIO output invalid (minimum propagation delay) 0 -- ns M11 MII_MDC falling edge to MII_MDIO output valid (max prop delay) -- 25 ns M12 MII_MDIO (input) to MII_MDC rising edge setup 10 -- ns M13 MII_MDIO (input) to MII_MDC rising edge hold 0 -- ns M14 MII_MDC pulse width high 40% 60% MII_MDC period M15 MII_MDC pulse width low 40% 60% MII_MDC period Figure 62 shows the MII serial management channel timing diagram. M14 MM15 MII_MDC (Output) M10 MII_MDIO (Output) M11 MII_MDIO (Input) M12 M13 Figure 62. MII Serial Management Channel Timing Diagram MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 59 Mechanical Data and Ordering Information 16 Mechanical Data and Ordering Information Table 29 identifies the packages and operating frequencies orderable for the MPC852T. Table 29. MPC852T Package/Frequency Orderable Package Type Plastic ball grid array (VR and ZT suffix) Plastic ball grid array (CVR and CZTsuffix) 16.1 Temperature (Tj) Frequency (MHz) 0C to 95C 50 MPC852TVR50A MPC852TZT50A 66 MPC852TVR66A MPC852TZT66A 80 MPC852TVR80A MPC852TZT80A 100 MPC852TVR100A MPC852TZT100A 50 MPC852TCVR50A MPC852TCZT50A 66 MPC852TCVR66A MPC852TCZT66A 80 MPC852TCVR80A MPC852TCZT80A 100 MPC852TCVR100A MPC852TCZT100A -40C to 100C Order Number Pin Assignments The following sections give the pinout and pin listing for the JEDEC compliant and the non-JEDEC versions of the 16 x 16 PBGA package. MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 60 Freescale Semiconductor Mechanical Data and Ordering Information 16.1.1 JEDEC Compliant Pinout Figure 63 shows the JEDEC pinout of the PBGA package as viewed from the top surface. For additional information, see the MPC866 PowerQUICCTM Family Reference Manual. NOTE: This is the top view of the device. A N/C CS1 WR CS0 CS7 GPL_A2 WE2 BS_A0 VDDL A28 A18 A23 A19 A14 A7 A2 A1 N/C CE2_A GPL_A3 WE3 MII_CRS BS_A3 A22 A30 A29 A27 A13 A9 A6 A0 N/C B C VDDL GPL_A4 CS3 CS5 GPL_A0 WE1 BS_A2 A26 A25 A21 A17 A12 A8 A3 N/C PC15 CS6 WE0 BS_A1 A31 A24 A20 A15 A10 A4 N/C PB29 VDDL CS4 TSIZ1 TSIZ0 A16 A11 A5 N/C PB31 PC13 PC12 PA11 D BDIP BI CS2 BR TS TEA GPL_A5 CE_1A CR MII_COL OE E F BB TA PB30 TDO TMS TRST BURST BG PB28 TDI VDDL MDIO ALE_A DSCK VFLS_0 FRZ TCK PB25 PA10 PB24 PC5 PC7 PA8 PA9 VDDH PD13 PA2 PC6 PA3 N/C PC4 PA1 PB15 G VFLS_1 RSV H GND J KR AS BADDR30 HRESET K OP0 OP1 OP2 RSTCONF L OP3 BADDR29 BADDR28 VDDL M D26 D14 D9 IRQ1 PD3 PD8 PD15 VDDL PA0 XTAL EXTCLK WAIT_A VSSSYN IP_A5 CLKOUT D25 D21 D15 D10 D17 IRQ7 PD6 PD9 PD12 PD14 PORST VDDSYN VSSSYN1 DP0 DP1 EXTAL VDDL SRESET N/C IP_A3 IP_A1 IP_A6 N P D29 D24 D20 D16 D11 D23 D12 IRQ0 PD4 N/C PD11 PD5 R VDDL IP_A7 IP_A2 DP3 D31 D28 D6 D19 D5 D2 D27 D13 D0 PD10 N/C N/C IP_A0 IP_A4 DP2 D30 D7 D22 VDDL D18 D3 D1 D4 D8 MII_TXEN PD7 N/C 1 2 3 4 5 6 7 8 9 10 11 12 T 13 14 15 16 Figure 63. Pinout of PBGA Package--JEDEC Standard MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 61 Mechanical Data and Ordering Information Table 30 contains a list of the MPC852T input and output signals and shows multiplexing and pin assignments. Table 30. Pin Assignments--JEDEC Standard Name Pin Number Type A[0:31] B15, A15, A14, C14, D13, E11, B14, A13, C13, B13, D12, E10, C12, Bidirectional B12, A12, D11, E9, C11, A9, A11, D10, C10, B8, A10, D9, C9, C8, Three-state (3.3 V only) B11, A8, B10, B9, D8 TSIZ0, REG E8 Bidirectional Three-state (3.3 V only) TSIZ1 E7 Bidirectional Three-state (3.3 V only) RD/WR B1 Bidirectional Three-state (3.3 V only) BURST G3 Bidirectional Three-state (3.3 V only) BDIP, GPL_B5 D1 Output TS E2 Bidirectional Active Pull-up (3.3 V only) TA F4 Bidirectional Active Pull-up (3.3 V only) TEA E3 Open-drain BI D2 Bidirectional Active Pull-up (3.3 V only) IRQ2 RSV G2 Bidirectional Three-state (3.3 V only) IRQ4, KR, RETRY, SPKROUT J1 Bidirectional Three-state (3.3 V only) CR, IRQ3 F1 Input (3.3 V only) D[0:31] R13, T11, R10, T10, T12, R9, R7, T6, T13, M10, N10, P10, P12, R12, M9, N9, P9, N11, T9, R8, P8, N8, T7, P11, P7, N7, M8, R11, R6, P6, T5, R5 Bidirectional Three-state (3.3 V only) DP0, IRQ3 P4 Bidirectional Three-state (3.3 V only) DP1, IRQ4 P5 Bidirectional Three-state (3.3 V only) DP2, IRQ5 T4 Bidirectional Three-state (3.3 V only) DP3, IRQ6 R4 Bidirectional Three-state (3.3 V only) BR E1 Bidirectional (3.3 V only) BG G4 Bidirectional (3.3 V only) BB F3 Bidirectional Active pull-up (3.3 V only) MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 62 Freescale Semiconductor Mechanical Data and Ordering Information Table 30. Pin Assignments--JEDEC Standard (continued) Name Pin Number Type FRZ IRQ6 H4 Bidirectional (3.3 V only) IRQ0 P13 Input (3.3 V only) IRQ1 M11 Input (3.3 V only) M_TX_CLK IRQ7 N12 Input (3.3 V only) CS[0:5] B2, A2, D3, C3, E6, C4 Output CS6 D4 Output CS7 A3 Output WE0 BS_B0 IORD D6 Output WE1 BS_B1 IOWR C6 Output WE2 BS_B2 PCOE A5 Output WE3 BS_B3 PCWE B5 Output BS_A[0:3] A6, D7, C7, B7 Output GPL_A0 GPL_B0 C5 Output OE GPL_A1 GPL_B1 D5 Output GPL_A[2:3] GPL_B[2:3] CS[2-3] A4, B4 Output UPWAITA GPL_A4 C2 Bidirectional (3.3 V only) GPL_A5 E4 Output PORESET P1 Input (3.3 V only) RSTCONF K4 Input (3.3 V only) HRESET J4 Open-drain SRESET M3 Open-drain XTAL N1 Analog Output MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 63 Mechanical Data and Ordering Information Table 30. Pin Assignments--JEDEC Standard (continued) Name Pin Number Type EXTAL M1 Analog Input (1.8 V only) CLKOUT N6 Output EXTCLK N2 Input (1.8 V only) ALE_A H1 Output CE1_A E5 Output CE2_A B3 Output WAIT_A N3 Input (3.3 V only) IP_A0 T2 Input (3.3 V only) IP_A1 M6 Input (3.3 V only) IP_A2, IOIS16_A R3 Input (3.3 V only) IP_A3 M5 Input (3.3 V only) IP_A4 T3 Input (3.3 V only) IP_A5 N5 Input (3.3 V only) IP_A6 M7 Input (3.3 V only) IP_A7 R2 Input (3.3 V only) DSCK H2 Bidirectional Three-state (3.3 V only) IWP[0:1], VFLS[0:1] H3, G1 Bidirectional (3.3 V only) OP0 K1 Bidirectional (3.3 V only) OP1 K2 Output OP2, MODCK1, STS K3 Bidirectional (3.3 V only) OP3, MODCK2, DSDO L1 Bidirectional (3.3 V only) BADDR[28:29] L3, L2 Output BADDR30, REG J3 Output AS J2 Input (3.3 V only) PA11, RXD3 E16 Bidirectional (Optional: Open-drain) (5-V tolerant) PA10, TXD3 H15 Bidirectional (Optional: Open-drain) (5-V tolerant) PA9, RXD4 J16 Bidirectional (Optional: Open-drain) (5-V tolerant) PA8, TXD4 J15 Bidirectional (Optional: Open-drain) (5-V tolerant) MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 64 Freescale Semiconductor Mechanical Data and Ordering Information Table 30. Pin Assignments--JEDEC Standard (continued) Name Pin Number Type PA3, CLK5, BRGO3, TIN3 K16 Bidirectional (5-V tolerant) PA2, CLK6, TOUT3 K14 Bidirectional (5-V tolerant) PA1, CLK7, BRGO4, TIN4 L15 Bidirectional (5-V tolerant) PA0, CLK8, TOUT4 M16 Bidirectional (5-V tolerant) PB31, SPISEL E13 Bidirectional (Optional: Open-drain) (5-V tolerant) PB30, SPICLK F13 Bidirectional (Optional: Open-drain) (5-V tolerant) PB29, SPIMOSI D15 Bidirectional (Optional: Open-drain) (5-V tolerant) PB28, SPIMISO, BRGO4 G13 Bidirectional (Optional: Open-drain) (5-V tolerant) PB25, SMTXD1 H14 Bidirectional (Optional: Open-drain) (5-V tolerant) PB24, SMRXD1 H16 Bidirectional (Optional: Open-drain) (5-V tolerant) PB15, BRGO3 L16 Bidirectional (5-V tolerant) PC15, DREQ0 C16 Bidirectional (5-V tolerant) PC13, RTS3 E14 Bidirectional (5-V tolerant) PC12, RTS4 E15 Bidirectional (5-V tolerant) PC7, CTS3 J14 Bidirectional (5-V tolerant) PC6, CD3 K15 Bidirectional (5-V tolerant) PC5, CTS4, SDACK1 J13 Bidirectional (5-V tolerant) MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 65 Mechanical Data and Ordering Information Table 30. Pin Assignments--JEDEC Standard (continued) Name Pin Number Type PC4, CD4 L14 Bidirectional (5-V tolerant) PD15, MII_RXD3 M14 Bidirectional (5-V tolerant) PD14, MII_RXD2 N16 Bidirectional (5-V tolerant) PD13, MII_RXD1 K13 Bidirectional (5-V tolerant) PD12, MII_MDC N15 Bidirectional (5-V tolerant) PD11, RXD3, MII_TX_ER P16 Bidirectional (5-V tolerant) PD10, TXD3, MII_RXD0 R15 Bidirectional (5-V tolerant) PD9, RXD4, MII_TXD0 N14 Bidirectional (5-V tolerant) PD8, TXD4, MII_RX_CLK M13 Bidirectional (5-V tolerant) PD7, RTS3, MII_RX_ER T15 Bidirectional (5-V tolerant) PD6, RTS4, MII_RX_DV N13 Bidirectional (5-V tolerant) PD5, MII_TXD3 R14 Bidirectional (5-V tolerant) PD4, MII_TXD2 P14 Bidirectional (5-V tolerant) PD3, MII_TXD1 M12 Bidirectional (5-V tolerant) TMS F15 Input (5-V tolerant) TDI, DSDI G14 Input (5-V tolerant) TCK, DSCK H13 Input (5-V tolerant) TRST F16 Input (5-V tolerant) TDO, DSDO F14 Output (5-V tolerant) MII_CRS B6 Input MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 66 Freescale Semiconductor Mechanical Data and Ordering Information Table 30. Pin Assignments--JEDEC Standard (continued) Name Pin Number Type MII_MDIO G16 Bidirectional (5-V tolerant) MII_TXEN T14 Output (5-V tolerant) MII_COL F2 Input VSSSYN N4 PLL analog GND VSSSYN1 P3 PLL analog GND VDDSYN P2 PLL analog VDD GND G6, G7, G8, G9, G10, G11, H6, H7, H8, H9, H10, H11, J6, J7, J8, J9, Power J10, J11, K6, K7, K8, K9, K10, K11 VDDL A7, C1, D16, G15, L4, M2, R1, M15, T8 Power VDDH F5, F6, F7, F8, F9, F10, F11, F12, G5, G12, H5, H12, J5, J12, K5, K12, L5, L6, L7, L8, L9, L10, L11, L12 Power N/C A1, A16, B16, C15, D14, E12, L13, M4, P15, R16, T1, T16 No connect MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 67 Mechanical Data and Ordering Information 16.1.2 The non-JEDEC Pinout Figure 64 shows the non-JEDEC pinout of the PBGA package as viewed from the top surface. For additional information, see the PowerQUICCTM Family Reference Manual. NOTE: This figure shows the top view of the device. B N/C CS1 WR CS0 CS7 GPL_A2 WE2 BS_A0 VDDL A28 A18 A23 A19 A14 A7 A2 A1 N/C A22 A30 A29 A27 A13 A9 A6 A0 N/C C CE2_A GPL_A3 WE3 MII_CRS BS_A3 D VDDL GPL_A4 CS3 CS5 GPL_A0 WE1 BS_A2 A26 A25 A21 A17 A12 A8 A3 N/C PC15 CS6 WE0 BS_A1 A31 A24 A20 A15 A10 A4 N/C PB29 VDDL CS4 TSIZ1 TSIZ0 A16 A11 A5 N/C PB31 PC13 PC12 PA11 E BDIP BI CS2 BR TS TEA GPL_A5 CE_1A CR MII_COL OE F G BB TA PB30 TDO TMS TRST BURST BG PB28 TDI VDDL MDIO ALE_A DSCK VFLS_0 FRZ TCK PB25 PA10 PB24 PC5 PC7 PA8 PA9 PD13 PA2 PC6 PA3 N/C PC4 PA1 PB15 H VFLS_1 RSV J GND K KR AS BADDR30 HRESET L OP0 OP1 OP2 RSTCONF VDDH M OP3 BADDR29 BADDR28 VDDL N D26 D14 D9 IRQ1 PD3 PD8 PD15 VDDL PA0 XTAL EXTCLK WAIT_A VSSSYN IP_A5 CLKOUT D25 D21 D15 D10 D17 IRQ7 PD6 PD9 PD12 PD14 PORST VDDSYN VSSSYN1 DP0 DP1 EXTAL VDDL SRESET N/C IP_A3 IP_A1 IP_A6 P R D29 D24 D20 D16 D11 D23 D12 IRQ0 PD4 N/C PD11 PD5 T VDDL IP_A7 IP_A2 DP3 D31 D28 D6 D19 D5 D2 D27 D13 D0 PD10 N/C N/C IP_A0 IP_A4 DP2 D30 D7 D22 VDDL D18 D3 D1 D4 D8 MII_TXEN PD7 N/C 2 3 6 7 8 9 10 11 12 13 14 17 U 4 5 15 16 Figure 64. Pinout of PBGA Package--Non-JEDEC MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 68 Freescale Semiconductor Mechanical Data and Ordering Information Table 31 contains a list of the MPC852T input and output signals and shows multiplexing and pin assignments. Table 31. Pin Assignments--Non-JEDEC Name Pin Number Type A[0:31] C16, B16, B15, D15, E14, F12, C15, B14, D14, C14, E13, F11, D13, Bidirectional C13, B13, E12, F10, D12, B10, B12, E11, D11, C9, B11, E10, D10, Three-state (3.3 V only) D9, C12, B9, C11, C10, E9 TSIZ0, REG F9 Bidirectional Three-state (3.3 V only) TSIZ1 F8 Bidirectional Three-state (3.3 V only) RD/WR C2 Bidirectional Three-state (3.3 V only) BURST H4 Bidirectional Three-state (3.3 V only) BDIP, GPL_B5 E2 Output TS F3 Bidirectional Active pull-up (3.3 V only) TA G5 Bidirectional Active pull-up (3.3 V only) TEA F4 Open-drain BI E3 Bidirectional Active pull-up (3.3 V only) IRQ2, RSV H3 Bidirectional Three-state (3.3 V only) IRQ4, KR RETRY, SPKROUT K2 Bidirectional Three-state (3.3 V only) CR, IRQ3 G2 Input (3.3 V only) D[0:31] T14, U12, T11, U11, U13, T10, T8, U7, U14, N11, P11, R11, R13, T13, N10, P10, R10, P12, U10, T9, R9, P9, U8, R12, R8, P8, N9, T12, T7, R7, U6, T6 Bidirectional Three-state (3.3 V only) DP0, IRQ3 R5 Bidirectional Three-state (3.3 V only) DP1, IRQ4 R6 Bidirectional Three-state (3.3 V only) DP2, IRQ5 U5 Bidirectional Three-state (3.3 V only) DP3, IRQ6 T5 Bidirectional Three-state (3.3 V only) BR F2 Bidirectional (3.3 V only) BG H5 Bidirectional (3.3 V only) MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 69 Mechanical Data and Ordering Information Table 31. Pin Assignments--Non-JEDEC (continued) Name Pin Number Type BB G4 Bidirectional Active Pull-up (3.3 V only) FRZ, IRQ6 J5 Bidirectional (3.3 V only) IRQ0 R14 Input (3.3 V only) IRQ1 N12 Input (3.3 V only) IRQ7, M_TX_CLK P13 Input (3.3 V only) CS[0:5] C3, B3, E4, D4, F7, D5 Output CS6 E5 Output CS7 B4 Output WE0, BS_B0, IORD E7 Output WE1, BS_B1, IOWR D7 Output WE2, BS_B2, PCOE B6 Output WE3, BS_B3, PCWE C6 Output BS_A[0:3] B7, E8, D8, C8 Output GPL_A0, GPL_B0 D6 Output OE, GPL_A1, GPL_B1 E6 Output GPL_A[2:3], GPL_B[2:3], CS[2-3] B5, C5 Output UPWAITA, GPL_A4 D3 Bidirectional (3.3 V only) GPL_A5 F5 Output PORESET R2 Input (3.3 V only) RSTCONF L5 Input (3.3 V only) HRESET K5 Open-drain SRESET N4 Open-drain XTAL P2 Analog output EXTAL N2 Analog input (3.3 V only) CLKOUT P7 Output EXTCLK P3 Input (3.3 V only) ALE_A J2 Output CE1_A F6 Output CE2_A C4 Output WAIT_A P4 Input (3.3 V only) IP_A0 U3 Input (3.3 V only) MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 70 Freescale Semiconductor Mechanical Data and Ordering Information Table 31. Pin Assignments--Non-JEDEC (continued) Name Pin Number Type IP_A1 N7 Input (3.3 V only) IP_A2, IOIS16_A T4 Input (3.3 V only) IP_A3 N6 Input (3.3 V only) IP_A4 U4 Input (3.3 V only) IP_A5 P6 Input (3.3 V only) IP_A6 N8 Input (3.3 V only) IP_A7 T3 Input (3.3 V only) DSCK J3 Bidirectional Three-state (3.3 V only) IWP[0:1], VFLS[0:1] J4, H2 Bidirectional (3.3 V only) OP0 L2 Bidirectional (3.3 V only) OP1 L3 Output OP2, MODCK1, STS L4 Bidirectional (3.3 V only) OP3, MODCK2, DSDO M2 Bidirectional (3.3 V only) BADDR[28:29] M4, M3 Output BADDR30, REG K4 Output AS K3 Input (3.3 V only) PA11, RXD3 F17 Bidirectional (Optional: Open-drain) (5-V tolerant) PA10, TXD3 J16 Bidirectional (Optional: Open-drain) (5-V tolerant) PA9, RXD4 K17 Bidirectional (Optional: Open-drain) (5-V tolerant) PA8, TXD4 K16 Bidirectional (Optional: Open-drain) (5-V tolerant) PA3, CLK5, BRGO3, TIN3 L17 Bidirectional (5-V tolerant) PA2, CLK6, TOUT3 L15 Bidirectional (5-V tolerant) PA1, CLK7, BRGO4, TIN4 M16 Bidirectional (5-V tolerant) PA0, CLK8, TOUT4 N17 Bidirectional (5-V tolerant) MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 71 Mechanical Data and Ordering Information Table 31. Pin Assignments--Non-JEDEC (continued) Name Pin Number Type PB31, SPISEL F14 Bidirectional (Optional: Open-drain) (5-V tolerant) PB30, SPICLK G14 Bidirectional (Optional: Open-drain) (5-V tolerant) PB29, SPIMOSI E16 Bidirectional (Optional: Open-drain) (5-V tolerant) PB28, SPIMISO, BRGO4 H14 Bidirectional (Optional: Open-drain) (5-V tolerant) PB25, SMTXD1 J15 Bidirectional (Optional: Open-drain) (5-V tolerant) PB24, SMRXD1 J17 Bidirectional (Optional: Open-drain) (5-V tolerant) PB15, BRGO3 M17 Bidirectional (5-V tolerant) PC15, DREQ0 D17 Bidirectional (5-V tolerant) PC13, RTS3 F15 Bidirectional (5-V tolerant) PC12, RTS4 F16 Bidirectional (5-V tolerant) PC7, CTS3 K15 Bidirectional (5-V tolerant) PC6, CD3 L16 Bidirectional (5-V tolerant) PC5, CTS4, SDACK1 K14 Bidirectional (5-V tolerant) PC4, CD4 M15 Bidirectional (5-V tolerant) PD15, MII_RXD3 N15 Bidirectional (5-V tolerant) PD14, MII_RXD2 P17 Bidirectional (5-V tolerant) PD13, MII_RXD1 L14 Bidirectional (5-V tolerant) MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 72 Freescale Semiconductor Mechanical Data and Ordering Information Table 31. Pin Assignments--Non-JEDEC (continued) Name Pin Number Type PD12, MII_MDC P16 Bidirectional (5-V tolerant) PD11, RXD3, MII_TX_ER R17 Bidirectional (5-V tolerant) PD10, TXD3, MII_RXD0 T16 Bidirectional (5-V tolerant) PD9, RXD4, MII_TXD0 P15 Bidirectional (5-V tolerant) PD8, TXD4, MII_RX_CLK N14 Bidirectional (5-V tolerant) PD7, RTS3, MII_RX_ER U16 Bidirectional (5-V tolerant) PD6, RTS4, MII_RX_DV P14 Bidirectional (5-V tolerant) PD5, MII_TXD3 T15 Bidirectional (5-V tolerant) PD4, MII_TXD2 R15 Bidirectional (5-V tolerant) PD3, MII_TXD1 N13 Bidirectional (5-V tolerant) TMS G16 Input (5-V tolerant) TDI, DSDI H15 Input (5-V tolerant) TCK, DSCK J14 Input (5-V tolerant) TRST G17 Input (5-V tolerant) TDO, DSDO G15 Output (5-V tolerant) MII_CRS C7 Input MII_MDIO H17 Bidirectional (5-V tolerant) MII_TX_EN U15 Output (5-V tolerant) MII_COL G3 Input VSSSYN P5 PLL analog GND MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 73 Mechanical Data and Ordering Information Table 31. Pin Assignments--Non-JEDEC (continued) Name Pin Number Type VSSSYN1 R4 PLL analog GND VDDSYN R3 PLL analog VDD GND H7, H8, H9, H10, H11, H12, J7, J8, J9, J10, J11, J12, K7, K8, K9, K10, K11, K12, L7, L8, L9, L10, L11, L12 Power VDDL B8, D2, E17, H16, M5, N3, T2, N16, U9 Power VDDH G6, G7, G8, G9, G10, G11, G12, G13, H6, H13, J6, J13, K6, K13, L6, L13, M6, M7, M8, M9, M10, M11, M12, M13 Power N/C B2, B17, C17, D16, E15, F13, M14, N5, R16, T17, U2, U17 No connect MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 74 Freescale Semiconductor Mechanical Data and Ordering Information 16.2 Mechanical Dimensions of the PBGA Package For more information on the printed-circuit board layout of the PBGA package, including thermal via design and suggested pad layout, refer to Plastic Ball Grid Array Application Note (order number: AN1231) that is available from your local Freescale sales office. Figure 65 shows the mechanical dimensions of the PBGA package. Notes: 1. All dimensions are in millimeters. 2. Interpret dimensions and tolerances per ASME Y14.5M--1994. 3. Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is defined by the spherical crowns of the solder balls. Note: Solder sphere composition is 95.5%Sn 45%Ag 0.5%Cu for MPC852TVRXXX. Solder sphere composition is 62%Sn 36%Pb 2%Ag for MPC852TZTXXX. Figure 65. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 75 Document Revision History 17 Document Revision History Table 32 lists significant changes between revisions of this document. Table 32. Document Revision History Revision Date 4 3.1 Changes * Updated template. * On page 1, updated first paragraph and added a second paragraph. * After Table 2, inserted a new figure showing the undershoot/overshoot voltage (Figure 2) and renumbered the rest of the figures. * In Table 9, for reset timings B29f and B29g added footnote indicating that the formula only applies to bus operation up to 50 MHz. * In Figure 4, changed all reference voltage measurement points from 0.2 and 0.8 V to 50% level. * In Table 17, changed num 46 description to read, "TA assertion to rising edge ..." * In Figure 42, changed TA to reflect the rising edge of the clock. 1/18/2005 Document template update. 3.0 11/2004 * Added sentence to Spec B1A about EXTCLK and CLKOUT being in Alignment for Integer Values * Added a footnote to Spec 41 specifying that EDM = 1 * Broke the Section 16.1, "Pin Assignments," into 2 smaller sections for the JEDEC and non-JEDEC pinouts. 2.0 12/2003 Put 852T on the 1st page in place of 8245. Figure 62 on page 59 had overbars added on signals CR (pin G2) and WAIT_A (pin P4). 1.8 7/2003 Changed the pinout to be JEDEC Compliant, changed timing parameters B28a through B28d, and B29d to show that TRLX can be 0 or 1. 1.7 5/2003 Changed the SPI Master Timing Specs. 162 and 164 1.6 4/2003 Changed the package drawing in Figure 15-63 1.5 4/2003 Changed 5 Port C pins with interrupt capability to 7 Port C pins. Added the Note: solder sphere composition for MPC852TVR and MPC852TCVR devices is 95.5%Sn 45%Ag 0.5%Cu to Figure 15-63 1.4 2/2003 Changed Table 15-30 Pin Assignments for the PLL Pins VSSSYN1, VSSSYN, VDDSYN 1.3 1/2003 Added subscripts to timing diagrams for B1-B35, to specify memory controller settings for the specific edges. 1.2 1/2003 In Table 15-30, specified EXTCLK as 3.3 V. 1.1 12/2002 Added fast Ethernet controller to the features 1 11/2002 Added values for 80 and 100 MHz 0 10/2002 Initial release MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 76 Freescale Semiconductor Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 77 Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 78 Freescale Semiconductor Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC852T PowerQUICCTM Hardware Specifications, Rev. 4 Freescale Semiconductor 79 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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