© Freescale Semiconductor, Inc., 2004, 2007. All rights reserved.
Freescale Semiconducto r
Technical Data
This document contains detailed information for the
MPC852T power considerations, DC/AC electri cal
character isti cs , AC timing specif icat ions, and pertinent
electrical and physical characteristics. For information about
functional characteristics of the processor, refer to the
MPC866 PowerQUICC™ Family Refer ence Manual
(MPC866UM). The M PC852T contains a PowerPC™
processor core built on Power Architecture™ technol ogy.
T o locate published errata or updates for this document, refer
to the MPC852T product summary page on our website
listed on the back cover of this document or, contact your
local Freescale sales office.
Contents
1. Ove rview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 6
4. Thermal Charac teristics . . . . . . . . . . . . . . . . . . . . . . . 7
5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7. Thermal Calculation and Measurement . . . . . . . . . . . 9
8. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9. Power Su pply and Power Sequencing . . . . . . . . . . . 12
10. Mandatory Reset Configurations . . . . . . . . . . . . . . . 12
11. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
12. Bus Sig nal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 14
13. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 4 2
14. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 44
15. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 57
16. Mechanical Data and Ordering Info rmation . . . . . . . 60
17. Document Revision History . . . . . . . . . . . . . . . . . . . 76
MPC852T Po werQUICC™
Hardware Specificatio ns
Document Number: MPC852TE C
Rev. 4, 09/2007
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
2Freescale Semiconductor
Overview
1Overview
The MPC852T is a 0.18-m icron derivative of the MPC860 PowerQUICC™ family, and can operate up to
100 MHz on the MP C8xx core with a 66-MHz exter nal bus . The MPC852T has a 1. 8-V core and a 3. 3-V
I/O operation with 5-V TTL compatibility. The MP C852T integrated communications controller is a
versatile one-chip integrated microprocessor and peripheral combination that c an be use d in a variety of
controller applications. It particularly excel s in Ethernet control applications, including C PE equipment,
Ethernet routers and hubs , VoIP clients, and WiFi acce ss points.
The MPC852T is a PowerPC architecture-based derivative of the MPC860 Quad Integrated
Communications Controller (PowerQUICC). The CPU on the MPC852T is a MPC8xx core, a 32-bit
micr oproce ssor tha t implements the PowerPC arc hite cture, incorporating memory management units
(MMUs) and ins truc tion and data caches. The MPC852T is the subset of this family of devices .
2Features
The MPC852T is comprised of three mod ules that each use a 32-bit internal bus: an MPC8xx core, system
integration unit (SIU), and communication pr ocessor module (CPM).
The following list summarizes the key MPC852T featur es :
Embedded MPC8xx core u p to 100 MH z
Maximum frequency operation of the external bus is 66 MHz
50/66 MHz core frequencies support both 1:1 and 2:1 modes
80/100 MHz core frequencies support 2:1 mode only
Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two
32-bit general-pur pose registers (GPR s)
The core performs branch prediction with conditional prefetch, without conditional execution.
4-Kbyte data cache and 4-Kbyte instructi on cache
4-Kbyte instruction caches is two-way, set-associative with 128 sets
4-Kbyte data cachesis two-way, set-as sociative with 128 sets
Cache coher ency for both instruction and data caches is maintained on 128-bit (4- word)
cache blocks
Caches ar e physically addressed, implement a least recently used ( LRU) replacement
algorithm, and are lockable on a cache block basis
MMUs with 32-entry TL B, fully as sociative instruction, and data TLBs
MMUs support multiple page sizes of 4, 16, and 512 Kbytes , and 8 Mbytes; 16 virtual address
spaces, and 16 protection groups
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
Memory controller (eight banks)
Contains complete dynamic R AM (DRAM) contr oller
Each bank can be a chip select or RAS to support a DRAM bank
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 3
Features
Up to 30 wait states programm able per m emory bank
Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other mem ory
devices
DRAM controller-pr ogrammable to support most size and speed memory interfaces
Four CAS lines, four WE lines, and one OE line
Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
Variable block sizes (32 Kbytes–256 Mbytes)
Selectable write protection
On-chip bus ar bitration logic
Fas t Eth e rne t controller (FE C)
Genera l-pur pose timers
Two 16-bit timers or one 32-bit timer
Gate m ode can enable or disable counting
Interrupt can be masked on reference match and event capture
System inte gration unit (SIU)
Bus monitor
Software watchdog
Periodic interrupt timer (PI T)
Low-power stop mode
Clock synthesizer
Decrem en ter and time base
Reset controller
IEEE 1149.1™ standard test access port (JTAG)
Interrupts
Seven ext ernal interrupt request (IRQ) lines
Seven port pins with interrupt capability
Eighteen internal interrupt sources
Programmable priority between SCCs
Programmable highest-priority r equest
Communications proc essor module (CPM)
RISC cont ro lle r
Communication- specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT
MODE, and RESTART TRANSMIT)
Supports continuous mode transmission and reception on all serial channels
8-Kbytes of dual- port RAM
Eight serial DMA (SDMA) channels
Three parallel I/O regis ters with open-drain capability
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
4Freescale Semiconductor
Features
Two baud rate generators
Independent (can be connected t oany SCC3/4 or SMC1)
Allows changes during operation
Autobaud support option
Two SCCs (serial communic ation contr ollers)
Ethernet/IEEE 802.3® standar d optional on SCC3 and SC C 4, supporting full 10-Mbps
operation
HDLC/SDLC
HDLC bus (impl ements an HDLC -based local area network ( LAN))
Universal asynchronous receiver transmitter (UART )
Totally transparent (bit streams)
Totally transparent (frame-based with optional cyclic redundancy check (CRC) )
One SM C (serial management channel)
UART
One SPI (serial peripheral interface )
Supports master and s lave modes
Supports multima ster operation on the same bus
PCMCIA interface
Master (socket) i nterface, release 2.1 complian t
Supports one independent PCMCIA socket; 8-memory or I/O windows supported
Debug interface
Eight comparator s : four operate on instruction address, two operate on dat a address, and two
operate on data
Supports conditions: = < >
Each watchpoint can generate a br eak point internally
Normal high and norm al low power modes to conserve power
1.8 V core and 3.3-V I/O operation with 5-V TT L compa tibility. Refe r to Table 5 for a listing of
the 5-V tolerant pins.
Figure 1 shows the MPC852T block diagram.
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 5
Features
Figure 1. MPC85 2 T Block Di agra m
Bus
Sy s te m In te r fac e Un it (S I U )
Embedded
Parallel I/O
Memory Controller
2
Timers Interrupt
Controllers 8-Kbyte
Dual-Port RAM 1 Virtual
System Functions
4-Kbyte
Instruction Cache
32-Ent ry ITLB
Instruction MMU
4-Kbyte
Data Cache
32-Entry DTLB
Data MMU
Instruction
Bus
Load/Store
Bus
Unified
Internal
Bus Interface
Unit
External
Bus Interfac e
Unit
Timers
32-Bit RISC Cont rol ler
and Program
ROM
MPC8xx
Processor
Core
DMAs
FIFOs
10/100
MII
Base-T
Media Access
Serial Interface (NMSI)
Control
Fast Ethernet
Controller
PCMCIA-ATA Interface
Generators
2 Baud Rate
IDMA
Channels
DMA
8 Serial
and
SCC3 SCC4 SMC1 SPI
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
6Freescale Semiconductor
Max imu m Tol era ted Rat ing s
3 Maximum Tolerated Ratings
This section provides the maximum tolerated voltage and temperature ranges for the M PC852T. Table 1
provides the maximum ratings and operating t emp eratures.
Figure 2 shows the undershoot and overshoot voltages at the interface of the MPC852T.
Figure 2. Undershoot/ Over shoot Vol tage for VDDH and VDDL
Table 1. Maximum Tolerated Ratings
Rating Symbol Value Unit
Supply voltage1
1The power supply of the device must start its ramp from 0.0 V.
VDDL (core voltage) – 0.3 to 3.4 V
VDDH (I/O voltage) – 0.3 to 4 V
VDDSYN – 0.3 to 3.4 V
Difference between VDDL to VDDSYN 100 mV
Input voltage2
2Functional operating condit ions are pro vided with the DC electri cal s pecificati ons in Table 5. Absolu te maximum rating s are
stress ratings only; functional operation at the maxi m a is not guaranteed. Stresses beyond those listed may affect device
reliability or cause permanent damage to the device.
Caution: All inputs that tolerate 5 V cannot be more than 2.5 V great er th an VDDH. This restriction applies t o power-up and
normal operation (th at i s, if the MPC852T is unpowered, a voltage g reat er t han 2.5 V must not be applied to its i nputs).
Vin GND – 0.3 to VDDH V
Storage tempera tur e range Tstg – 55 to +150 °C
GND
GND – 0.3 V
GND – 0.7 V Not to Exceed 10%
VDDH/VDDL + 20%
VDDH/VDDL
VDDH/VDDL + 5%
of tinterface1
1. tinterface re fers to the clock period associat ed with the bus clock int e rface .
VIH
VIL
Note:
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 7
Thermal Characteristi cs
This devi ce contains circuitry protecting against damage that high-static voltage or electrical fields cause;
however, Frees cale recommends taking normal precautions to avoid application of any voltages highe r
than maximum-r ated voltages to this high-impedance circuit. Reliabili ty of operation is enhanced if
unused inputs are tied to an appropriate logic voltage level (for example, either GND or VDD).
4 Thermal Characteristics
Table 3 shows the thermal char acteristics f or the MPC852T.
Table 2. Operating Temp eratur es
Rating Symbol Value Unit
Temperat ure 1 (standard)
1Minimum temperatures are guaranteed as ambient temperatur e, TA. Maximum temperatur es are guaranteed as junct ion
temperature, Tj.
TA(min) C
Tj(max) 95 °C
Temper ature (e xtended) TA(min) – 40 °C
Tj(max) 100 °C
Table 3. MPC852T Thermal Resistance Data
Rating Environment Symbol Value Unit
Junction-to-ambient1
1Junction temperature is a func ti on of on-chip power dissipation, package thermal resistance, mounting site (board)
temper ature, ambient temperatur e, airflo w , power d iss ipation of oth er component s on the board, and boar d thermal resistan ce.
Natural convection Single-layer board (1s) RθJA2
2Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal
49 °C/W
Four-la yer board ( 2s2p) RθJMA3
3Per JEDEC JESD51-6 with the board horizontal
32
Airfl ow (200 ft/min) Single-layer board (1s) RθJMA341
Four-la yer board ( 2s2p) RθJMA329
Junction-to-board4
4Thermal res istance between the die and the printed-circuit board per JEDEC JESD51-8. B oard t em perature is measured on
the top s urface of the board near the package.
RθJB 24
Junction-to-case5
5Indicates the average thermal resistance between the die and the case top surf ace as m easured by the cold pl ate method
(MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed pad packages
where t he pa d would be e xpecte d to be sol der ed, ju nction -to-case t hermal resistanc e i s a simul ated v al ue fr om the jun ction t o
the exposed pad wi thout contac t resistance.
RθJC 13
Junction- to- package top6
6Thermal char acteri zati on paramet er indi cati ng the temper atur e diff eren ce bet ween pac kage t op and the junc tion tem perat ure
per JEDEC JESD51-2
Natural convection ΨJT 3
Airflow (200 ft/min) ΨJT 2
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
8Freescale Semiconductor
Power Dissip ation
5 Po we r Dissipation
Table 4 provides power dissipation information. The m odes are 1:1, where CPU and bus speeds are equal,
and 2:1 mode, where CPU fr equency is twice bus speed.
6 DC Characteri stics
Table 5 provides the DC elect rical characteristics for the MPC852T.
Table 4. Power Dissipation (PD)
Die Revision Bus Mode Frequency
(MHz) Typical1
1Typical power dissi pation is measured at 1.9 V.
Maximum2
2Maximum power di ssipation at VDDL and VDDSYN is at 1.9 V. and VDDH is at 3.465 V.
NOTE
Valu es in Table 4 represent VDDL- based power
dissipation, and do not include I/O power dissipation
over VDDH. I/O power dissipation varies widely by
application that buffer current can cause, depending on
external circuitry.
The V DDSYN power dissipation is negligible.
Unit
0
1:1 50 110 140 mW
66 150 180 mW
2:1
66 140 160 mW
80 170 200 mW
100 210 250 mW
Table 5. DC Electri cal Sp ecifications
Characteristic Symbol Min Max Unit
Operating voltage VDDH 3.135 3.465 V
VDDL 1.7 1.9 V
VDDSYN 1.7 1.9 V
Difference between
VDDL to V DDSYN
—100mV
Input hi gh volt age (al l i nputs except PA[0:3], PA[8:11],
PB15, PB[24:25]; PB[28:31] , PC[4:7], PC[12:13], PC15,
PD[3:15], TDI, TDO, TCK, TRST, TMS , MII_TXEN,
MII_MDIO)1
VIH 2.0 3.465 V
Input low voltage VIL GND 0.8 V
EXTAL, EXTCLK input high voltage VIHC 0.7 × VDDH VDDH V
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 9
Th er m al C al culati on and Mea surem ent
7 Thermal Calculation and Measurement
For the f ollowing dis cussions, PD= (VDDL x IDDL) + PI/O, where PI/O is the power dissipation of t he I/O
drivers.
NOTE
The VDDSYN power dissipation is negligible.
7.1 Estimati on with Junction-to-Ambient Thermal Resis tance
An estimation of the chip junction tempe r ature , TJ, in °C can be obta ined from the equa tion:
TJ = TA +(RθJA × PD)
Input leakage current, Vin = 5.5 V (Except TMS, TRST,
DSCK and DSDI pins) for 5-V tolerant pins 1Iin 100 µA
Input leakage current, Vin = VDDH (Except TMS, TRST,
DSCK, and DSDI) IIn —10µA
Input leakage current, Vin = 0 V ( Except TMS, TRST,
DSCK and DSDI pins) IIn —10µA
Input capacitance2Cin —20pF
Output hi gh voltage, IOH = - 2.0 mA, VDDH = 3.0 V
Except XTAL and open drain pins VOH 2.4 V
Output low volt age
IOL = 2.0 mA (CLKOUT)
IOL = 3.2 mA3
IOL = 5.3 mA4
IOL = 7.0 mA (Txd1/pa14, txd2/pa12)
IOL = 8.9 mA (TS, TA , TEA, BI, BB, HRESET, SRESET)
VOL 0.5 V
1The PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15, PD[3:15], TDI, TDO, TCK, TRST, TMS,
MII_TXEN, MII_MDIO are 5-V toler ant pins.
2Input capacitance i s peri odically sam pled.
3A(0:31), TSIZ0/REG, TS IZ 1 , D(0 :3 1 ), D P ( 0 :3 )/IRQ (3:6), RD/WR, BURST, R S V /IRQ2, IWP(0:1)/VFLS(0:1) , RXD3/PA11,
TXD3/PA10, RXD4/PA9, TXD4/PA8, TIN3/BRGO3/CL K5/PA3, BRGCLK2/TOUT3/CLK6/ PA2, TIN4/BRGO4/CLK7/PA1,
TOUT4/CLK8/PA0, SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29, BRGO4/SPIMISO/PB28, SMTXD1/PB25,
SMRXD1/PB24, BRGO3/PB15, R TS1/DREQ0/PC15 , RT S3/PC13, RTS4/PC12, CTS3/PC7, CD3/PC6, CTS4/SDACK1/PC5,
CD4/PC4, MII-RXD3/PD1 5, MII-RX D2/PD14, MII -RXD1/PD13, MI I-MDC/PD12, MII -TXERR/ RXD3/PD11,
MII-RX0/TXD3/PD10, MII-TXD0/RXD4/PD9, MII-RXCLK/TXD4/PD8, MII-TXD3/PD5, MII-RXDV/RTS4/PD6,
MII-RXERR/RTS3/PD7, MII-TXD2/ REJECT3/PD4, MII- TXD1/REJECT4/ PD3, MII_CRS, MII_MDIO, MI I_TXEN, and MII _CO L
4BDIP/GPL_B(5), BR , BG, FR Z/ IR Q6 , CS(0 :5 ), CS(6) , C S (7), WE0/BS_B0/IORD, W E 1 /BS_B1/IOWR, WE2 /BS_B2/PCOE,
WE3/ BS_B3/PCWE, B S _A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1, G P L _A(2:3)/GPL_B(2:3)/CS(2:3),
UPWAITA/GPL_A4, GPL_A5, ALE_A, CE1_A, CE2_A, DSCK, OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, and
BADDR(28:30)
Table 5. DC Electrical Specification s (continued)
Characteristic Symbol Min Max Unit
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
10 Freescale Semiconductor
Thermal Calculation and Measurement
where:
TA = ambient temperature (ºC)
RθJA = package j unction-to-ambi ent thermal resistance (ºC/W)
PD = power dissipation in package
The junction-to- ambient thermal res istance is an industry standa rd value that provides a quick and easy
estimation of thermal performance. However , the answer is only an estimate; tes t cases have demonstrated
that errors of a fa ct or of two (in the quantity TJ – TA) are possible.
7.2 Estimation with Junction-to-Case Thermal Resistance
Historically , the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal
resistance and a case- to-ambient thermal resistance:
RθJA = RθJC + RθCA
where:
RθJA = junction-to-ambient thermal resista nce (ºC/W)
RθJC = junc tion-to-case therma l resista nce (º C/W)
RθCA = case-to-ambient thermal resistance (ºC/W)
RθJC is device-related and cannot be influenced by the user. The user adjusts the thermal environment to
af fect the ca se-to-ambi ent thermal resis tance, RθCA. For instance, the us er can change the airflow around
the device, add a heat sink, change the mounting arrangement on the printed-circuit board, or change the
thermal dis sipation on the printed-circuit board surrounding the device. This ther mal model is most useful
for ceram ic packages with heat sinks where some 90% of the heat f lows through the case and the heat sink
to the ambient environment. For most packages , a better model is required.
7.3 Estimat ion with Junc tion-to-Board Thermal Resistance
A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor
model consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case
covers the situation where a heat sink is used or where a substantial amount of heat is di ssipated from the
top of the package. The junction-to-board thermal resistance describes the thermal performance when most
of the heat is conducted to the printed-circuit board. Thermal performance of most plastic packages and
especially PBGA packages is strongly dependent on the board temperature. If the board temper ature is
known, an e stimate of the junction temperature in the environment can be made using the f ollowing
equation:
TJ = TB +(RθJB × PD)
where:
RθJB = junction-to-board thermal r esistance (ºC/W)
TB = board tem perature (ºC)
PD = power dissipation in package
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 11
References
If the board tempe rature is known and the heat loss from the package case to the air can be ignored,
acceptable predictions of junction temperature can be made. For this method to work, the board and board
mounting must be similar to the test board used to determine the junction-to-board thermal resistance,
namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground
plane.
7.4 Estimation Using Simulation
When the board te mperature is not known, a thermal simulation of the application is needed. The simple
two-re sistor mode l can be u sed with the the r ma l sim ulat ion of the applic ation [2], or a mor e accurate a nd
complex model of the package ca n be used in the thermal simulati on.
7.5 Experimental Determination
To determine the junction temperature of the device in the application after prototypes are available, the
therma l character izat ion para met er (ΨJT) can be used to determi ne the junction temperature with a
measurement of the tempe rature at the top center of the package case using the following equation:
TJ = TT + (ΨJT × PD)
where:
ΨJT = thermal char acter ization para mete r
TT = thermocouple temperature on top of package
PD = power dissipation in package
The thermal char acterization parameter is meas ured per JESD51-2 specification published by JEDEC
using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple
should be positioned so that t he thermocouple junction rests on the package. A small amount of epoxy is
placed over the the rmocouple junction and over about 1 mm of wire extending from the junction. The
thermocouple wire is placed flat against the package case to avoid measurement errors that cooling effects
of the the rmocouple wire cause.
8 References
Semiconductor Equipment and Materials International ( 415) 964-5111
805 East Middlefield Rd
Mountain View, CA 94043
MIL-SPEC and EIA/JESD (JEDEC) specif ications 800-854-7179 or
(Available from Global Engineering doc uments) 303-397-7956
JEDEC Specifications http://www.jedec. or g
1. C.E. T ri plett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Contr oller Module,” Proceedi ngs of SemiTherm, San Diego, 1998, pp. 47–54.
2. B. Joiner and V. Adams, “Measurement and Sim ulation of Junction to Board Thermal Resistance
and Its Application in Thermal Modeling, Proceedings of SemiTherm, San Die go, 1999,
pp. 212–220.
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
12 Freescale Semiconductor
Power Supply and Power Sequencing
9 Pow er Supply and Power Sequencing
This section provides design cons iderations for the MPC852T power supply. The MPC852T has a core
voltage (VDDL) and PLL voltage (VDDSYN) that operates at a lower voltage than the I/O voltage VDDH.
The I/O section of the MPC852T is suppl ied with 3.3 V across VDDH and VSS (GND).
The signals PA[0:3], PA[8:11], PB15, PB [24:25]; PB [28:31], PC[4:7] , P C[12:13], PC 15] PD[3:15], TDI ,
TDO, TCK, TRST, T MS, MII_TXEN, MII_MDIO are 5-V t olerant. All inputs cannot be mor e than 2.5 V
greater than VDDH. In addition, 5-V tolerant pins can not exceed 5.5 V, and the remaining input pins cannot
exceed 3.465 V. This restriction applies to power -on reset or power down and normal operation.
One consequence of multiple power supplies is that when power is initially applied, the voltage rails ramp
up at different rates. The rates depend on the nature of the power supply, the type of load on each power
supply, and the manner in which different voltages are derived. The following res trictions apply:
•V
DDL mus t not exceed VDDH dur ing power- on reset or power down.
•V
DDL mus t not exceed 1.9 V, and VDDH must not exceed 3.465.
These cautions are necessary for the long-term reliability of t he part. If they are viol ated, the electrostatic
dischar ge (ESD) protection diodes are f orward-biased, and excessive current can flow through these
diodes. If the system power supply design does not control the voltage sequencing, the circuit shown in
Figure 3 ca n be added to meet these requirements. The MUR420 Schottky diodes control the maximum
potential dif ference between the external bus and core power supplies on power- on reset, and the 1N5820
diodes regulate the maximum potential differe nce on power-down.
Figure 3. Example Vol tage Sequ encing Circuit
10 M and atory Reset C onfigu rations
The MPC852T requires a mandatory configuration during reset.
If hardware reset configuration word (HRCW) is enabled, by as serting the RSTCONF during HRESET
asser tion, the HRCW[ DBGC] val ue that is needed to be set to binary X1 in t he hardw are rese t
configuration word (HRCW) and the SIUMCR[DBGC] should be programmed with the same value in the
boot code after reset.
If hardware reset configuration word (HRCW) is disabled, by nega ting the RSTCONF during the
HRESET assertion, the SIUMCR[DBGC] should be programmed with binary X1 in the boot code after
reset.
VDDH VDDL
1N5820
MUR420
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 13
Lay out Prac tic es
The MBMR[ GPL B4DIS], PAPA R, PADIR, PBPA R, PBDIR, PCPAR , and PCDIR s hould be configured
with the mandatory value in Table 6 in the boot code af ter the reset deasserts.
11 Layout Practices
Each VDD pin on the MPC852T should be provided with a low-impedance path to the board’ s supply . Each
GND pin should likewi se be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on chip. The VDD power supply should be bypassed to gr ound using at least four
0.1 µF bypass capacitors located as close as possible to the four sides of the package. Each board desi gned
should be characterized and additional appropriate decoupling capacitors should be used if required. The
capacitor leads and associat ed printed-circuit traces connecting to chip VDD and GND should be kept to
less than half an inch per capacitor lead. At a minimum, a four -layer boar d employing two inner layers as
VDD and GND planes should be used.
All output pins on th e MPC852T have fast rise and fall times. Printed-circuit (P C) trace interconnection
length should be minimized to minimize undershoot and reflections t hat these f ast output switching times
cause. This recommendation particularly applies to the address and data buses. Maximum PC trace lengths
of six inches ar e recommende d. Capacitance calcula tions should consider all device loads as well as
parasitic capacitances that the PC traces cause. Attention to proper PCB layout and bypassing becomes
especially critical in systems wi th higher capacitive loads, because these loads create higher transient
currents in the VDD and GND circuits. Pull up all unused inputs or signals that are inputs during reset.
Special care should be t aken to minimize the noise levels on the PLL supply pins. For more information,
please refer to the M PC866 PowerQUICC™ Family Reference Manual, Section 14.4.3, “Clock
Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1).
Table 6. M and ator y Reset Configuration of MPC852T
Register/Configuration Field Value
(Binary)
HRCW (Hardware reset configuration wo rd) HRCW[ DBGC] X1
SIUMCR (SIU module configuration r egister) SIUMCR[DBGC] X1
MBMR (Machi ne B mode register) MBMR[GPLB4DI S} 0
PAPAR (Port A pin assignment r egister) PAPAR[4–7]
PAPAR[12–15] 0
PADIR (Port A data direction register) PADIR[4–7]
PADIR[12–15] 1
PBPAR (P ort B pin assig nme nt r egister) PBPAR[14]
PBPAR[16–23]
PBPAR[26–27]
0
PBDIR (Port B data di rection register) PBDIR[14]
PBDIR[16–23]
PBDIR[26–27]
1
PCPAR (P ort C pin assign me nt re gister) PCPAR[8–11]
PCDIR[14] 0
PCDIR (Port C data direction register) PCDIR[8–11]
PCDIR[14] 1
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
14 Freescale Semiconductor
Bus Signal Timing
12 Bus Signal Timing
The maximum bus s peed that the M PC852T supports is 66 MHz. Table 7 shows the frequency ranges for
standard part frequencies.
Table 9 provides the bus operation timing for the MPC852T at 33, 40, 50, and 66 MHz.
The timing for the MPC852T bus shown assumes a 50- pF load for maximum delays and a 0-pF load for
minimum delays. CLKOUT assum es a 100-pF load maximum delay
Table 7. Fr equency Ranges for Standard Part Frequencies (1:1 Bus Mode)
Par t Frequency 50 MHz 66 MHz
Min Max Min Max
Core 40 50 40 66.67
Bus 40 50 40 66.67
Table 8. Fr equency Ranges for Standard Part Frequencies (2:1 Bus Mode)
Par t Frequency 50 MHz 66 MHz 80 MHz 100 MHz
Min Max Min Max Min Max Min Max
Core 40 50 40 66.67 40 80 40 100
Bus 2:1 20 25 20 33.33 20 40 20 50
Table 9. Bus Operati on Timings
Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit
Min Max Min Max Min Max Min Max
B1 Bus period (CLKOUT) See Table 7 ————————ns
B1a EXTCLK to CLKOUT phase skew—If
CLKOUT is an integ er multiple of
EXTCLK, then the rising ed ge of E XTCLK
is aligned wi th th e rising edge of CLK OUT.
For a non-int eger multipl e of EXTCLK, th is
synchronizat ion i s lost, and the rising
edges of EXTCLK and CLKOUT have a
continuousl y varying phase sk ew.
–2 +2 –2 +2 –2 +2 2 +2 ns
B1b CLKOUT frequency jitter peak-t o-peak 1 1 1 1 ns
B1c Frequency jitt er on EXTCLK1 0.50 0.50 0.50 0.50 %
B1d CLKOUT phase j itter peak-t o-peak fo r
OSCLK 15 M H z —4—4—4—4ns
CLKOUT phase jit ter peak-to-peak fo r
OSCLK < 15 MHz —5—5—5—5ns
B2 CLK OUT pul se widt h low ( MIN = 0 .4 × B1,
MAX = 0.6 × B1) 12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 15
Bus Signal Timing
B3 CLKOUT pulse width high (MIN = 0.4 × B1,
MAX = 0.6 × B1) 12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns
B4 CLKOUT rise time 4.00 4.00 4.00 4.00 ns
B5 CLKOUT fall time 4.00 4.00 4.00 4.00 ns
B7 CLKOUT to A(0:31), BADDR(28:3 0),
RD/WR, BURST, D(0:31), DP(0:3) output
hold (MIN = 0. 25 × B1)
7.60 6.30 5.00 3.80 ns
B7 a CL KOUT to TSI Z( 0 :1 ), RE G, RSV, BD IP,
PTR output hold (MIN = 0. 25 × B1) 7.60 6.30 5.00 3.80 ns
B7b CLKOUT to BR, B G, FRZ, VFLS(0:1),
VF(0:2) IWP(0:2), LWP(0:1) , STS output
hold (MIN = 0. 25 × B1)
7.60 6.30 5.00 3.80 ns
B8 CLKOUT to A(0:31), BADDR(28:3 0)
RD/WR, BURST, D(0:31) , DP(0:3) valid
(MAX = 0.25 × B1 + 6.3)
13.80 12.50 11.30 10.00 ns
B8 a CL KOUT to TSI Z( 0 :1 ), RE G, RSV, BD IP,
PTR valid (MAX = 0.25 × B1 + 6.3) 13.80 12.50 11.30 10.00 ns
B8b CLKOUT to BR, B G, VFLS(0: 1), VF(0: 2),
IWP(0:2), FRZ, LWP(0:1), STS Valid3
(MAX = 0.25 × B1 + 6.3)
13.80 12.50 11.30 10.00 ns
B9 CLKOUT to A(0:31), BADDR(28:3 0),
RD/WR, BURST, D(0:31), DP(0:3),
TSIZ(0:1), REG, RSV, PTR High-Z
(MAX = 0.25 × B1 + 6.3)
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
B11 CLKOUT to TS, BB asser tion
(MAX = 0.25 × B1 + 6.0) 7.60 13.60 6.30 12.30 5.00 11.00 3.80 9.80 ns
B11a CLKOUT to TA, BI asse rti on (when driv en
by the memory cont rol ler or PCM CIA
interface) (MAX = 0.00 × B1 + 9.302)
2.50 9.30 2.50 9.30 2.50 9.30 2.50 9.80 ns
B12 CLKOUT to TS, BB negation
(MAX = 0.25 × B1 + 4.8) 7.60 12.30 6.30 11.00 5.00 9.80 3.80 8.50 ns
B12a CLKOUT to TA, B I negation (when driven
by the memory cont rol ler or PCM CIA
interface) (MAX = 0.00 × B1 + 9.00)
2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns
B13 CLKOUT to TS, BB High-Z
(MIN = 0.25 × B1) 7.60 21.60 6.30 20.30 5.00 19.00 3.80 14.00 ns
B13a CLK OUT t o TA, B I High-Z ( when driv en b y
the memor y contr oller or PCMCIA
inter face) (MIN = 0.00 × B1 + 2.5)
2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
B14 CLKOUT to TEA assertion
(MAX = 0.00 × B1 + 9.00) 2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns
Table 9. B us Oper a tio n Timings (c on t inu e d)
Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit
Min Max Min Max Min Max Min Max
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
16 Freescale Semiconductor
Bus Signal Timing
B15 CLKOUT to TEA High-Z
(MIN = 0.00 × B1 + 2.50) 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
B16 TA, B I valid t o CLKOUT (setup time)
(MIN = 0.00 × B1 + 6.00) 6.00 6.00 6.00 6.00 ns
B16a TEA, KR, RETRY, C R v alid to CLKOUT
(setup time) (MIN = 0.00 × B1 + 4.5) 4.50 4.50 4.50 4.50 ns
B16b BB, BG, BR, va lid to CLK OUT (setup ti me)
3 (4MIN = 0.00 × B1 +.000) 4.00 4.00 4.00 4.00 ns
B17 CLK OUT t o TA, T EA, BI, BB, BG , BR valid
(hold time) (MIN = 0.00 ×B1 + 1.004)1.00 1.00 1.00 2.00 ns
B17a CLKOUT to KR, R ETRY, C R valid ( hold
time) (MIN = 0.00 × B1 + 2.00) 2.00 2.00 2.00 2.00 ns
B18 D(0:31 ), DP(0:3) val id to CLKOU T rising
edge (setup time)5
(MIN = 0.00 × B1 + 6.00)
6.00 6.00 6.00 6.00 ns
B19 CLKOUT rising edge t o D(0:31), DP(0:3)
valid (hold time)5 ( MIN = 0.00 × B1 + 1.006)1.00 1.00 1.00 2.00 ns
B20 D(0:31) , DP( 0:3) valid to CLKOUT falling
edge (setup time)7
(MIN = 0.00 × B1 + 4.00)
4.00 4.00 4.00 4.00 ns
B21 CLKOUT falli ng edge to D( 0:31), DP(0:3)
val id ( hold T ime) 7 (MIN = 0.00 × B1 + 2. 00) 2.00 2.00 2.00 2.00 ns
B22 CLKOUT rising edge to CS asser ted
GPCM ACS = 00 (MAX = 0.25 × B1 + 6.3) 7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
B22a CLKOUT falling edge to CS asserted
GPCM ACS = 10, TRLX = 0
(MAX = 0.00 × B1 + 8.00)
8.00 8.00 8.00 8.00 ns
B22b CLKOUT falling edge to CS asserted
GPCM ACS = 11, TRLX = 0, EBDF = 0
(MAX = 0.25 ×B1 + 6.3)
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
B22c CLKOUT falling edge to CS asserted
GPCM ACS = 11, TRLX = 0, EBDF = 1
(MAX = 0.375 × B1 + 6.6)
10.90 18.00 10.90 16.00 7.00 14.10 5.20 12.30 ns
B23 CLKOUT rising edge to CS negated
GPCM read acce ss, GPCM write access
AC S = 00, TRLX = 0 & CSNT = 0
(MAX = 0.00 × B1 + 8.00)
2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns
B24 A(0:31) and BADDR(28: 30) to CS
asserted GPCM ACS = 10, TRLX = 0
(MIN = 0.25 × B1 – 2.00)
5.60 4.30 3.00 1.80 ns
Table 9. B us Oper a tio n Timings (c on t inu e d)
Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit
Min Max Min Max Min Max Min Max
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 17
Bus Signal Timing
B24a A(0:31) and BADDR(28: 30) to CS
asserted GPCM ACS = 11 TRLX = 0
(MIN = 0.50 × B1 – 2.00)
13.20 10.50 8.00 5.60 ns
B25 CLKOUT rising edge to OE,
WE(0:3)/BS_B[ 0:3] asserte d
(MAX = 0.00 × B1 + 9.00)
9.00 9.00 9.00 9.00 ns
B26 CLKOUT rising edge to OE negated
(MAX = 0.00 × B1 + 9.00) 2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns
B27 A(0:31) and BADDR(28: 30) to CS
asserted GPCM ACS = 10, TRLX = 1
(MIN = 1.25 × B1 – 2.00)
35.90 29.30 23.00 16.90 ns
B27a A(0:31) and BADDR(28: 30) to CS
asserted GPCM ACS = 11, TRLX = 1
(MIN = 1.50 × B1 – 2.00)
43.50 35.50 28.00 20.70 ns
B28 CLKOUT rising edge to WE(0:3)/
BS_B[0:3 ] negated GPCM wri te ac cess
CSNT = 0 (MAX = 0.00 × B1 + 9.00)
9.00 9.00 9.00 9.00 ns
B28a CLKOUT falli ng edge to WE (0:3)/
BS_B[0:3 ] negated GPCM wri te ac cess
TRLX = 0,1 CSNT = 1, EBDF = 0
(MAX = 0.25 × B1 + 6.80)
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
B28b CLKOUT falling edge to CS negated
GPCM write acce ss TRLX = 0,1 CSNT = 1
ACS = 10 or ACS = 11, EBDF = 0
(MAX = 0.25 × B1 + 6.80)
14.30 13.00 11.80 10.50 ns
B28c CLKOUT falling edge to
WE(0:3)/BS_B[0:3] negate d GPCM write
access TRLX = 0, 1 CSNT = 1 wri te access
TRLX = 0,1 CSNT = 1, EBDF = 1
(MAX = 0.375 × B1 + 6.6)
10.90 18.00 10.90 18.00 7.00 14.30 5.20 12.30 ns
B28d CLKOUT falling edge to CS negated
GPCM write access TRLX = 0,1 CSNT =
1, ACS = 10, or ACS = 11, EBDF = 1
(MAX = 0.375 × B1 + 6.6)
18.00 18.00 14.30 12.30 ns
B29 WE(0:3)/BS_B[0:3] negated t o D(0: 31),
DP(0:3) High-Z GPCM write access,
CSNT = 0, EBDF = 0
(MIN = 0.25 × B1 – 2.00)
5.60 4.30 3.00 1.80 ns
B29a WE(0:3)/ BS_B[0:3] negated to D(0: 31),
DP(0:3) High-Z GPCM write access, TRLX
= 0, CSNT = 1, EBDF = 0
(MIN = 0.50 × B1 – 2.00)
13.20 10.50 8.00 5.60 ns
Table 9. B us Oper a tio n Timings (c on t inu e d)
Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit
Min Max Min Max Min Max Min Max
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
18 Freescale Semiconductor
Bus Signal Timing
B29b CS negated to D( 0:31) , DP(0:3), High Z
GPCM write access , ACS = 00,
TRLX = 0,1 and CSNT = 0
(MIN = 0.25 × B1 – 2.00)
5.60 4.30 3.00 1.80 ns
B29c CS negated to D(0:31), DP(0:3) Hig h-Z
GPCM wri te access, TRLX = 0 , CSNT = 1,
ACS = 10, or ACS = 11 EBDF = 0
(MIN = 0.50 × B1 – 2.00)
13.20 10.50 8.00 5.60 ns
B29d WE(0:3)/ BS_B[0:3] negated to D(0: 31),
DP(0:3) High-Z GPCM write access, TRLX
= 1, CSNT = 1, EBDF = 0
(MIN = 1.50 × B1 – 2.00)
43.50 35.50 28.00 20.70 ns
B29e CS negated to D(0:31), DP(0:3) High-Z
GPCM wri te access, TRLX = 1 , CSNT = 1,
ACS = 10, or ACS = 11 EBDF = 0
(MIN = 1.50 × B1 – 2.00)
43.50 35.50 28.00 20.70 ns
B29f WE(0:3/BS_B[0:3]) negated to D(0:31),
DP(0:3) High Z GPCM write access,
TRLX = 0, CSNT = 1, EBDF = 1
(MIN = 0.375 × B1 – 6.30 )8
5.00 3.00 1.10 0.00 ns
B29g CS negated to D(0:31), DP(0:3) High-Z
GPCM wri te access, TRLX = 0, CSNT = 1
ACS = 10 or ACS = 11, EBDF = 1
(MIN = 0.375 × B1 – 6.30 )8
5.00 3.00 1.10 0.00 ns
B29h WE(0:3)/ BS_B[0:3] negated to D(0: 31),
DP(0:3) High Z GPCM write access,
TRLX = 1, CSNT = 1, EBDF = 1
(MIN = 0.375 × B1 – 3.30 )
38.40 31.10 24.20 17.50 ns
B29i CS negated to D(0:31), DP(0:3) High-Z
GPCM wri te access, TRLX = 1 , CSNT = 1,
ACS = 10 or ACS = 11, EBDF = 1
(MIN = 0.375 × B1 – 3.30 )
38.40 31.10 24.20 17.50 ns
B30 CS, W E(0: 3)/ BS_B[0:3] negated t o
A(0:31), BADDR( 28:30) Invalid GPCM
write access 9 (MIN = 0.25 × B1 – 2.00)
5.60 4.30 3.00 1.80 ns
B30a WE(0:3)/ BS_B[0:3] negated to A(0: 31),
BADDR(28:30) Inva lid GPCM, write
access , TRLX = 0, CSNT = 1, CS negat ed
to A (0:31) invalid GPC M w r ite acce s s
TRLX = 0, CSNT =1 ACS = 10, or
A CS = = 11 , EBDF = 0
(MIN = 0.50 × B1 – 2.00)
13.20 10.50 8.00 5.60 ns
Table 9. B us Oper a tio n Timings (c on t inu e d)
Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit
Min Max Min Max Min Max Min Max
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 19
Bus Signal Timing
B30b WE(0:3)/ BS_B[0:3] negated to A(0: 31)
Invalid GPCM BADDR(28:30) inval id
GPCM wri te access, TRLX = 1 , CSNT = 1.
CS negated to A(0:31) In valid GPCM write
access TRLX = 1, CSNT = 1, A CS = 10, or
ACS == 11 EBDF = 0
(MIN = 1.50 × B1 – 2.00)
43.50 35.50 28.00 20.70 ns
B30c WE(0:3)/ BS_B[0:3] negated to A(0: 31),
BADDR(28:30) inva lid GPCM write
access , TRLX = 0, CSNT = 1. CS negat ed
to A (0 : 31) in vali d GPC M w r it e a cc e s s,
TRLX = 0, CSNT = 1 ACS = 10,
A CS = = 11 , EBDF = 1
(MIN = 0.375 × B1 – 3.00 )
8.40 6.40 4.50 2.70 ns
B30d WE(0:3)/ BS_B[0:3] negated to A(0: 31),
BADDR(28:30) invalid GPCM write access
TRLX = 1, CSNT =1, CS negated to
A(0:31) inva li d G PCM write acc ess
TRLX = 1, CSNT = 1, ACS = 10 or 11,
EBDF = 1
38.67 31.38 24.50 17.83 ns
B31 CLKOUT falling edge to CS valid - as
requested by control bit CST4 in the
corresponding word i n the UPM
(MAX = 0.00 × B1 + 6.00)
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
B31a CLKOUT falling edge to CS v alid - as
requested by control bit CST1 in the
corresponding word i n the UPM
(MAX = 0.25 × B1 + 6.80)
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
B31b CLKOUT rising edge to CS valid - as
requested by control bit CST2 in the
corresponding word i n the UPM
(MAX = 0.00 × B1 + 8.00)
1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns
B31c CLKOUT rising edge to CS va lid - a s
requested by control bit CST3 in the
corresponding word i n the UPM
(MAX = 0.25 × B1 + 6.30)
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
B31d CLKOUT falling edge to CS valid, as
requested by control bit CST1 in the
corres ponding wor d in t he UPM EBDF = 1
(MAX = 0.375 × B1 + 6.6)
13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns
B32 CLKOUT falling edge to BS vali d- as
requested by control bit BST4 in the
corresponding word i n the UPM
(MAX = 0.00 × B1 + 6.00)
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
Table 9. B us Oper a tio n Timings (c on t inu e d)
Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit
Min Max Min Max Min Max Min Max
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
20 Freescale Semiconductor
Bus Signal Timing
B32a CLKOUT falling edge to BS valid - as
requested by control bit BST1 in the
corresponding word in the UPM, EBDF = 0
(MAX = 0.25 × B1 + 6.80)
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
B32b CLKOUT rising edge to BS valid - as
requested by control bit BST2 in the
corresponding word i n the UPM
(MAX = 0.00 × B1 + 8.00)
1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns
B32c CLKOUT r ising edge to BS valid - as
requested by control bit BST3 in the
corresponding word i n the UPM
(MAX = 0.25 × B1 + 6.80)
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
B32d CLKOUT falling edge to BS valid- as
requested by control bit BST1 in the
corresponding word in the UPM, EBDF = 1
(MAX = 0.375 × B1 + 6.60)
13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns
B33 CLKOUT falling edge to GPL val id - as
requested by cont rol bit GxT4 in the
corresponding word i n the UPM
(MAX = 0.00 × B1 + 6.00)
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
B33a CLKOUT rising edge to GPL Valid - as
requested by cont rol bit GxT3 in the
corresponding word i n the UPM
(MAX = 0.25 × B1 + 6.80)
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
B34 A(0:31) , BADDR( 28:30), and D(0:31) to
CS valid - as requested by control bi t
CST4 in the cor responding word in the
UPM (MIN = 0.25 × B1 – 2.0 0)
5.60 4.30 3.00 1.80 ns
B34a A(0:31) , BADDR( 28:30), and D(0:31) to
CS vali d - as requested b y control bit
CST1 in the cor responding word in the
UPM (MIN = 0.50 × B1 – 2.0 0)
13.20 10.50 8.00 5.60 ns
B34b A(0:31) , BADDR( 28:30), and D(0:31) to
CS vali d - as requested by CST2 in t he
corresponding word i n UPM
(MIN = 0.75 × B1 – 2.00)
20.70 16.70 13.00 9.40 ns
B35 A(0:31), BADDR(28:30) to CS valid - as
requested by control bit BST4 in the
corresponding word i n the UPM
(MIN = 0.25 × B1 – 2.00)
5.60 4.30 3.00 1.80 ns
B35a A(0:31) , BADDR( 28:30), and D(0:31) to
BS valid - As Requested by BST1 in the
corresponding word i n the UPM
(MIN = 0.50 × B1 – 2.00)
13.20 10.50 8.00 5.60 ns
Table 9. B us Oper a tio n Timings (c on t inu e d)
Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit
Min Max Min Max Min Max Min Max