© Freescale Semiconductor, Inc., 2004, 2007. All rights reserved.
Freescale Semiconducto r
Technical Data
This document contains detailed information for the
MPC852T power considerations, DC/AC electri cal
character isti cs , AC timing specif icat ions, and pertinent
electrical and physical characteristics. For information about
functional characteristics of the processor, refer to the
MPC866 PowerQUICC™ Family Refer ence Manual
(MPC866UM). The M PC852T contains a PowerPC™
processor core built on Power Architecture™ technol ogy.
T o locate published errata or updates for this document, refer
to the MPC852T product summary page on our website
listed on the back cover of this document or, contact your
local Freescale sales office.
Contents
1. Ove rview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 6
4. Thermal Charac teristics . . . . . . . . . . . . . . . . . . . . . . . 7
5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7. Thermal Calculation and Measurement . . . . . . . . . . . 9
8. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9. Power Su pply and Power Sequencing . . . . . . . . . . . 12
10. Mandatory Reset Configurations . . . . . . . . . . . . . . . 12
11. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
12. Bus Sig nal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 14
13. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 4 2
14. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 44
15. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 57
16. Mechanical Data and Ordering Info rmation . . . . . . . 60
17. Document Revision History . . . . . . . . . . . . . . . . . . . 76
MPC852T Po werQUICC™
Hardware Specificatio ns
Document Number: MPC852TE C
Rev. 4, 09/2007
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
2Freescale Semiconductor
Overview
1Overview
The MPC852T is a 0.18-m icron derivative of the MPC860 PowerQUICC™ family, and can operate up to
100 MHz on the MP C8xx core with a 66-MHz exter nal bus . The MPC852T has a 1. 8-V core and a 3. 3-V
I/O operation with 5-V TTL compatibility. The MP C852T integrated communications controller is a
versatile one-chip integrated microprocessor and peripheral combination that c an be use d in a variety of
controller applications. It particularly excel s in Ethernet control applications, including C PE equipment,
Ethernet routers and hubs , VoIP clients, and WiFi acce ss points.
The MPC852T is a PowerPC architecture-based derivative of the MPC860 Quad Integrated
Communications Controller (PowerQUICC). The CPU on the MPC852T is a MPC8xx core, a 32-bit
micr oproce ssor tha t implements the PowerPC arc hite cture, incorporating memory management units
(MMUs) and ins truc tion and data caches. The MPC852T is the subset of this family of devices .
2Features
The MPC852T is comprised of three mod ules that each use a 32-bit internal bus: an MPC8xx core, system
integration unit (SIU), and communication pr ocessor module (CPM).
The following list summarizes the key MPC852T featur es :
Embedded MPC8xx core u p to 100 MH z
Maximum frequency operation of the external bus is 66 MHz
50/66 MHz core frequencies support both 1:1 and 2:1 modes
80/100 MHz core frequencies support 2:1 mode only
Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two
32-bit general-pur pose registers (GPR s)
The core performs branch prediction with conditional prefetch, without conditional execution.
4-Kbyte data cache and 4-Kbyte instructi on cache
4-Kbyte instruction caches is two-way, set-associative with 128 sets
4-Kbyte data cachesis two-way, set-as sociative with 128 sets
Cache coher ency for both instruction and data caches is maintained on 128-bit (4- word)
cache blocks
Caches ar e physically addressed, implement a least recently used ( LRU) replacement
algorithm, and are lockable on a cache block basis
MMUs with 32-entry TL B, fully as sociative instruction, and data TLBs
MMUs support multiple page sizes of 4, 16, and 512 Kbytes , and 8 Mbytes; 16 virtual address
spaces, and 16 protection groups
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
Memory controller (eight banks)
Contains complete dynamic R AM (DRAM) contr oller
Each bank can be a chip select or RAS to support a DRAM bank
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 3
Features
Up to 30 wait states programm able per m emory bank
Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other mem ory
devices
DRAM controller-pr ogrammable to support most size and speed memory interfaces
Four CAS lines, four WE lines, and one OE line
Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
Variable block sizes (32 Kbytes–256 Mbytes)
Selectable write protection
On-chip bus ar bitration logic
Fas t Eth e rne t controller (FE C)
Genera l-pur pose timers
Two 16-bit timers or one 32-bit timer
Gate m ode can enable or disable counting
Interrupt can be masked on reference match and event capture
System inte gration unit (SIU)
Bus monitor
Software watchdog
Periodic interrupt timer (PI T)
Low-power stop mode
Clock synthesizer
Decrem en ter and time base
Reset controller
IEEE 1149.1™ standard test access port (JTAG)
Interrupts
Seven ext ernal interrupt request (IRQ) lines
Seven port pins with interrupt capability
Eighteen internal interrupt sources
Programmable priority between SCCs
Programmable highest-priority r equest
Communications proc essor module (CPM)
RISC cont ro lle r
Communication- specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT
MODE, and RESTART TRANSMIT)
Supports continuous mode transmission and reception on all serial channels
8-Kbytes of dual- port RAM
Eight serial DMA (SDMA) channels
Three parallel I/O regis ters with open-drain capability
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
4Freescale Semiconductor
Features
Two baud rate generators
Independent (can be connected t oany SCC3/4 or SMC1)
Allows changes during operation
Autobaud support option
Two SCCs (serial communic ation contr ollers)
Ethernet/IEEE 802.3® standar d optional on SCC3 and SC C 4, supporting full 10-Mbps
operation
HDLC/SDLC
HDLC bus (impl ements an HDLC -based local area network ( LAN))
Universal asynchronous receiver transmitter (UART )
Totally transparent (bit streams)
Totally transparent (frame-based with optional cyclic redundancy check (CRC) )
One SM C (serial management channel)
UART
One SPI (serial peripheral interface )
Supports master and s lave modes
Supports multima ster operation on the same bus
PCMCIA interface
Master (socket) i nterface, release 2.1 complian t
Supports one independent PCMCIA socket; 8-memory or I/O windows supported
Debug interface
Eight comparator s : four operate on instruction address, two operate on dat a address, and two
operate on data
Supports conditions: = < >
Each watchpoint can generate a br eak point internally
Normal high and norm al low power modes to conserve power
1.8 V core and 3.3-V I/O operation with 5-V TT L compa tibility. Refe r to Table 5 for a listing of
the 5-V tolerant pins.
Figure 1 shows the MPC852T block diagram.
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 5
Features
Figure 1. MPC85 2 T Block Di agra m
Bus
Sy s te m In te r fac e Un it (S I U )
Embedded
Parallel I/O
Memory Controller
2
Timers Interrupt
Controllers 8-Kbyte
Dual-Port RAM 1 Virtual
System Functions
4-Kbyte
Instruction Cache
32-Ent ry ITLB
Instruction MMU
4-Kbyte
Data Cache
32-Entry DTLB
Data MMU
Instruction
Bus
Load/Store
Bus
Unified
Internal
Bus Interface
Unit
External
Bus Interfac e
Unit
Timers
32-Bit RISC Cont rol ler
and Program
ROM
MPC8xx
Processor
Core
DMAs
FIFOs
10/100
MII
Base-T
Media Access
Serial Interface (NMSI)
Control
Fast Ethernet
Controller
PCMCIA-ATA Interface
Generators
2 Baud Rate
IDMA
Channels
DMA
8 Serial
and
SCC3 SCC4 SMC1 SPI
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
6Freescale Semiconductor
Max imu m Tol era ted Rat ing s
3 Maximum Tolerated Ratings
This section provides the maximum tolerated voltage and temperature ranges for the M PC852T. Table 1
provides the maximum ratings and operating t emp eratures.
Figure 2 shows the undershoot and overshoot voltages at the interface of the MPC852T.
Figure 2. Undershoot/ Over shoot Vol tage for VDDH and VDDL
Table 1. Maximum Tolerated Ratings
Rating Symbol Value Unit
Supply voltage1
1The power supply of the device must start its ramp from 0.0 V.
VDDL (core voltage) – 0.3 to 3.4 V
VDDH (I/O voltage) – 0.3 to 4 V
VDDSYN – 0.3 to 3.4 V
Difference between VDDL to VDDSYN 100 mV
Input voltage2
2Functional operating condit ions are pro vided with the DC electri cal s pecificati ons in Table 5. Absolu te maximum rating s are
stress ratings only; functional operation at the maxi m a is not guaranteed. Stresses beyond those listed may affect device
reliability or cause permanent damage to the device.
Caution: All inputs that tolerate 5 V cannot be more than 2.5 V great er th an VDDH. This restriction applies t o power-up and
normal operation (th at i s, if the MPC852T is unpowered, a voltage g reat er t han 2.5 V must not be applied to its i nputs).
Vin GND – 0.3 to VDDH V
Storage tempera tur e range Tstg – 55 to +150 °C
GND
GND – 0.3 V
GND – 0.7 V Not to Exceed 10%
VDDH/VDDL + 20%
VDDH/VDDL
VDDH/VDDL + 5%
of tinterface1
1. tinterface re fers to the clock period associat ed with the bus clock int e rface .
VIH
VIL
Note:
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 7
Thermal Characteristi cs
This devi ce contains circuitry protecting against damage that high-static voltage or electrical fields cause;
however, Frees cale recommends taking normal precautions to avoid application of any voltages highe r
than maximum-r ated voltages to this high-impedance circuit. Reliabili ty of operation is enhanced if
unused inputs are tied to an appropriate logic voltage level (for example, either GND or VDD).
4 Thermal Characteristics
Table 3 shows the thermal char acteristics f or the MPC852T.
Table 2. Operating Temp eratur es
Rating Symbol Value Unit
Temperat ure 1 (standard)
1Minimum temperatures are guaranteed as ambient temperatur e, TA. Maximum temperatur es are guaranteed as junct ion
temperature, Tj.
TA(min) C
Tj(max) 95 °C
Temper ature (e xtended) TA(min) – 40 °C
Tj(max) 100 °C
Table 3. MPC852T Thermal Resistance Data
Rating Environment Symbol Value Unit
Junction-to-ambient1
1Junction temperature is a func ti on of on-chip power dissipation, package thermal resistance, mounting site (board)
temper ature, ambient temperatur e, airflo w , power d iss ipation of oth er component s on the board, and boar d thermal resistan ce.
Natural convection Single-layer board (1s) RθJA2
2Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal
49 °C/W
Four-la yer board ( 2s2p) RθJMA3
3Per JEDEC JESD51-6 with the board horizontal
32
Airfl ow (200 ft/min) Single-layer board (1s) RθJMA341
Four-la yer board ( 2s2p) RθJMA329
Junction-to-board4
4Thermal res istance between the die and the printed-circuit board per JEDEC JESD51-8. B oard t em perature is measured on
the top s urface of the board near the package.
RθJB 24
Junction-to-case5
5Indicates the average thermal resistance between the die and the case top surf ace as m easured by the cold pl ate method
(MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed pad packages
where t he pa d would be e xpecte d to be sol der ed, ju nction -to-case t hermal resistanc e i s a simul ated v al ue fr om the jun ction t o
the exposed pad wi thout contac t resistance.
RθJC 13
Junction- to- package top6
6Thermal char acteri zati on paramet er indi cati ng the temper atur e diff eren ce bet ween pac kage t op and the junc tion tem perat ure
per JEDEC JESD51-2
Natural convection ΨJT 3
Airflow (200 ft/min) ΨJT 2
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
8Freescale Semiconductor
Power Dissip ation
5 Po we r Dissipation
Table 4 provides power dissipation information. The m odes are 1:1, where CPU and bus speeds are equal,
and 2:1 mode, where CPU fr equency is twice bus speed.
6 DC Characteri stics
Table 5 provides the DC elect rical characteristics for the MPC852T.
Table 4. Power Dissipation (PD)
Die Revision Bus Mode Frequency
(MHz) Typical1
1Typical power dissi pation is measured at 1.9 V.
Maximum2
2Maximum power di ssipation at VDDL and VDDSYN is at 1.9 V. and VDDH is at 3.465 V.
NOTE
Valu es in Table 4 represent VDDL- based power
dissipation, and do not include I/O power dissipation
over VDDH. I/O power dissipation varies widely by
application that buffer current can cause, depending on
external circuitry.
The V DDSYN power dissipation is negligible.
Unit
0
1:1 50 110 140 mW
66 150 180 mW
2:1
66 140 160 mW
80 170 200 mW
100 210 250 mW
Table 5. DC Electri cal Sp ecifications
Characteristic Symbol Min Max Unit
Operating voltage VDDH 3.135 3.465 V
VDDL 1.7 1.9 V
VDDSYN 1.7 1.9 V
Difference between
VDDL to V DDSYN
—100mV
Input hi gh volt age (al l i nputs except PA[0:3], PA[8:11],
PB15, PB[24:25]; PB[28:31] , PC[4:7], PC[12:13], PC15,
PD[3:15], TDI, TDO, TCK, TRST, TMS , MII_TXEN,
MII_MDIO)1
VIH 2.0 3.465 V
Input low voltage VIL GND 0.8 V
EXTAL, EXTCLK input high voltage VIHC 0.7 × VDDH VDDH V
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 9
Th er m al C al culati on and Mea surem ent
7 Thermal Calculation and Measurement
For the f ollowing dis cussions, PD= (VDDL x IDDL) + PI/O, where PI/O is the power dissipation of t he I/O
drivers.
NOTE
The VDDSYN power dissipation is negligible.
7.1 Estimati on with Junction-to-Ambient Thermal Resis tance
An estimation of the chip junction tempe r ature , TJ, in °C can be obta ined from the equa tion:
TJ = TA +(RθJA × PD)
Input leakage current, Vin = 5.5 V (Except TMS, TRST,
DSCK and DSDI pins) for 5-V tolerant pins 1Iin 100 µA
Input leakage current, Vin = VDDH (Except TMS, TRST,
DSCK, and DSDI) IIn —10µA
Input leakage current, Vin = 0 V ( Except TMS, TRST,
DSCK and DSDI pins) IIn —10µA
Input capacitance2Cin —20pF
Output hi gh voltage, IOH = - 2.0 mA, VDDH = 3.0 V
Except XTAL and open drain pins VOH 2.4 V
Output low volt age
IOL = 2.0 mA (CLKOUT)
IOL = 3.2 mA3
IOL = 5.3 mA4
IOL = 7.0 mA (Txd1/pa14, txd2/pa12)
IOL = 8.9 mA (TS, TA , TEA, BI, BB, HRESET, SRESET)
VOL 0.5 V
1The PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15, PD[3:15], TDI, TDO, TCK, TRST, TMS,
MII_TXEN, MII_MDIO are 5-V toler ant pins.
2Input capacitance i s peri odically sam pled.
3A(0:31), TSIZ0/REG, TS IZ 1 , D(0 :3 1 ), D P ( 0 :3 )/IRQ (3:6), RD/WR, BURST, R S V /IRQ2, IWP(0:1)/VFLS(0:1) , RXD3/PA11,
TXD3/PA10, RXD4/PA9, TXD4/PA8, TIN3/BRGO3/CL K5/PA3, BRGCLK2/TOUT3/CLK6/ PA2, TIN4/BRGO4/CLK7/PA1,
TOUT4/CLK8/PA0, SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29, BRGO4/SPIMISO/PB28, SMTXD1/PB25,
SMRXD1/PB24, BRGO3/PB15, R TS1/DREQ0/PC15 , RT S3/PC13, RTS4/PC12, CTS3/PC7, CD3/PC6, CTS4/SDACK1/PC5,
CD4/PC4, MII-RXD3/PD1 5, MII-RX D2/PD14, MII -RXD1/PD13, MI I-MDC/PD12, MII -TXERR/ RXD3/PD11,
MII-RX0/TXD3/PD10, MII-TXD0/RXD4/PD9, MII-RXCLK/TXD4/PD8, MII-TXD3/PD5, MII-RXDV/RTS4/PD6,
MII-RXERR/RTS3/PD7, MII-TXD2/ REJECT3/PD4, MII- TXD1/REJECT4/ PD3, MII_CRS, MII_MDIO, MI I_TXEN, and MII _CO L
4BDIP/GPL_B(5), BR , BG, FR Z/ IR Q6 , CS(0 :5 ), CS(6) , C S (7), WE0/BS_B0/IORD, W E 1 /BS_B1/IOWR, WE2 /BS_B2/PCOE,
WE3/ BS_B3/PCWE, B S _A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1, G P L _A(2:3)/GPL_B(2:3)/CS(2:3),
UPWAITA/GPL_A4, GPL_A5, ALE_A, CE1_A, CE2_A, DSCK, OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, and
BADDR(28:30)
Table 5. DC Electrical Specification s (continued)
Characteristic Symbol Min Max Unit
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
10 Freescale Semiconductor
Thermal Calculation and Measurement
where:
TA = ambient temperature (ºC)
RθJA = package j unction-to-ambi ent thermal resistance (ºC/W)
PD = power dissipation in package
The junction-to- ambient thermal res istance is an industry standa rd value that provides a quick and easy
estimation of thermal performance. However , the answer is only an estimate; tes t cases have demonstrated
that errors of a fa ct or of two (in the quantity TJ – TA) are possible.
7.2 Estimation with Junction-to-Case Thermal Resistance
Historically , the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal
resistance and a case- to-ambient thermal resistance:
RθJA = RθJC + RθCA
where:
RθJA = junction-to-ambient thermal resista nce (ºC/W)
RθJC = junc tion-to-case therma l resista nce (º C/W)
RθCA = case-to-ambient thermal resistance (ºC/W)
RθJC is device-related and cannot be influenced by the user. The user adjusts the thermal environment to
af fect the ca se-to-ambi ent thermal resis tance, RθCA. For instance, the us er can change the airflow around
the device, add a heat sink, change the mounting arrangement on the printed-circuit board, or change the
thermal dis sipation on the printed-circuit board surrounding the device. This ther mal model is most useful
for ceram ic packages with heat sinks where some 90% of the heat f lows through the case and the heat sink
to the ambient environment. For most packages , a better model is required.
7.3 Estimat ion with Junc tion-to-Board Thermal Resistance
A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor
model consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case
covers the situation where a heat sink is used or where a substantial amount of heat is di ssipated from the
top of the package. The junction-to-board thermal resistance describes the thermal performance when most
of the heat is conducted to the printed-circuit board. Thermal performance of most plastic packages and
especially PBGA packages is strongly dependent on the board temperature. If the board temper ature is
known, an e stimate of the junction temperature in the environment can be made using the f ollowing
equation:
TJ = TB +(RθJB × PD)
where:
RθJB = junction-to-board thermal r esistance (ºC/W)
TB = board tem perature (ºC)
PD = power dissipation in package
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 11
References
If the board tempe rature is known and the heat loss from the package case to the air can be ignored,
acceptable predictions of junction temperature can be made. For this method to work, the board and board
mounting must be similar to the test board used to determine the junction-to-board thermal resistance,
namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground
plane.
7.4 Estimation Using Simulation
When the board te mperature is not known, a thermal simulation of the application is needed. The simple
two-re sistor mode l can be u sed with the the r ma l sim ulat ion of the applic ation [2], or a mor e accurate a nd
complex model of the package ca n be used in the thermal simulati on.
7.5 Experimental Determination
To determine the junction temperature of the device in the application after prototypes are available, the
therma l character izat ion para met er (ΨJT) can be used to determi ne the junction temperature with a
measurement of the tempe rature at the top center of the package case using the following equation:
TJ = TT + (ΨJT × PD)
where:
ΨJT = thermal char acter ization para mete r
TT = thermocouple temperature on top of package
PD = power dissipation in package
The thermal char acterization parameter is meas ured per JESD51-2 specification published by JEDEC
using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple
should be positioned so that t he thermocouple junction rests on the package. A small amount of epoxy is
placed over the the rmocouple junction and over about 1 mm of wire extending from the junction. The
thermocouple wire is placed flat against the package case to avoid measurement errors that cooling effects
of the the rmocouple wire cause.
8 References
Semiconductor Equipment and Materials International ( 415) 964-5111
805 East Middlefield Rd
Mountain View, CA 94043
MIL-SPEC and EIA/JESD (JEDEC) specif ications 800-854-7179 or
(Available from Global Engineering doc uments) 303-397-7956
JEDEC Specifications http://www.jedec. or g
1. C.E. T ri plett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Contr oller Module,” Proceedi ngs of SemiTherm, San Diego, 1998, pp. 47–54.
2. B. Joiner and V. Adams, “Measurement and Sim ulation of Junction to Board Thermal Resistance
and Its Application in Thermal Modeling, Proceedings of SemiTherm, San Die go, 1999,
pp. 212–220.
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
12 Freescale Semiconductor
Power Supply and Power Sequencing
9 Pow er Supply and Power Sequencing
This section provides design cons iderations for the MPC852T power supply. The MPC852T has a core
voltage (VDDL) and PLL voltage (VDDSYN) that operates at a lower voltage than the I/O voltage VDDH.
The I/O section of the MPC852T is suppl ied with 3.3 V across VDDH and VSS (GND).
The signals PA[0:3], PA[8:11], PB15, PB [24:25]; PB [28:31], PC[4:7] , P C[12:13], PC 15] PD[3:15], TDI ,
TDO, TCK, TRST, T MS, MII_TXEN, MII_MDIO are 5-V t olerant. All inputs cannot be mor e than 2.5 V
greater than VDDH. In addition, 5-V tolerant pins can not exceed 5.5 V, and the remaining input pins cannot
exceed 3.465 V. This restriction applies to power -on reset or power down and normal operation.
One consequence of multiple power supplies is that when power is initially applied, the voltage rails ramp
up at different rates. The rates depend on the nature of the power supply, the type of load on each power
supply, and the manner in which different voltages are derived. The following res trictions apply:
•V
DDL mus t not exceed VDDH dur ing power- on reset or power down.
•V
DDL mus t not exceed 1.9 V, and VDDH must not exceed 3.465.
These cautions are necessary for the long-term reliability of t he part. If they are viol ated, the electrostatic
dischar ge (ESD) protection diodes are f orward-biased, and excessive current can flow through these
diodes. If the system power supply design does not control the voltage sequencing, the circuit shown in
Figure 3 ca n be added to meet these requirements. The MUR420 Schottky diodes control the maximum
potential dif ference between the external bus and core power supplies on power- on reset, and the 1N5820
diodes regulate the maximum potential differe nce on power-down.
Figure 3. Example Vol tage Sequ encing Circuit
10 M and atory Reset C onfigu rations
The MPC852T requires a mandatory configuration during reset.
If hardware reset configuration word (HRCW) is enabled, by as serting the RSTCONF during HRESET
asser tion, the HRCW[ DBGC] val ue that is needed to be set to binary X1 in t he hardw are rese t
configuration word (HRCW) and the SIUMCR[DBGC] should be programmed with the same value in the
boot code after reset.
If hardware reset configuration word (HRCW) is disabled, by nega ting the RSTCONF during the
HRESET assertion, the SIUMCR[DBGC] should be programmed with binary X1 in the boot code after
reset.
VDDH VDDL
1N5820
MUR420
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 13
Lay out Prac tic es
The MBMR[ GPL B4DIS], PAPA R, PADIR, PBPA R, PBDIR, PCPAR , and PCDIR s hould be configured
with the mandatory value in Table 6 in the boot code af ter the reset deasserts.
11 Layout Practices
Each VDD pin on the MPC852T should be provided with a low-impedance path to the board’ s supply . Each
GND pin should likewi se be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on chip. The VDD power supply should be bypassed to gr ound using at least four
0.1 µF bypass capacitors located as close as possible to the four sides of the package. Each board desi gned
should be characterized and additional appropriate decoupling capacitors should be used if required. The
capacitor leads and associat ed printed-circuit traces connecting to chip VDD and GND should be kept to
less than half an inch per capacitor lead. At a minimum, a four -layer boar d employing two inner layers as
VDD and GND planes should be used.
All output pins on th e MPC852T have fast rise and fall times. Printed-circuit (P C) trace interconnection
length should be minimized to minimize undershoot and reflections t hat these f ast output switching times
cause. This recommendation particularly applies to the address and data buses. Maximum PC trace lengths
of six inches ar e recommende d. Capacitance calcula tions should consider all device loads as well as
parasitic capacitances that the PC traces cause. Attention to proper PCB layout and bypassing becomes
especially critical in systems wi th higher capacitive loads, because these loads create higher transient
currents in the VDD and GND circuits. Pull up all unused inputs or signals that are inputs during reset.
Special care should be t aken to minimize the noise levels on the PLL supply pins. For more information,
please refer to the M PC866 PowerQUICC™ Family Reference Manual, Section 14.4.3, “Clock
Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1).
Table 6. M and ator y Reset Configuration of MPC852T
Register/Configuration Field Value
(Binary)
HRCW (Hardware reset configuration wo rd) HRCW[ DBGC] X1
SIUMCR (SIU module configuration r egister) SIUMCR[DBGC] X1
MBMR (Machi ne B mode register) MBMR[GPLB4DI S} 0
PAPAR (Port A pin assignment r egister) PAPAR[4–7]
PAPAR[12–15] 0
PADIR (Port A data direction register) PADIR[4–7]
PADIR[12–15] 1
PBPAR (P ort B pin assig nme nt r egister) PBPAR[14]
PBPAR[16–23]
PBPAR[26–27]
0
PBDIR (Port B data di rection register) PBDIR[14]
PBDIR[16–23]
PBDIR[26–27]
1
PCPAR (P ort C pin assign me nt re gister) PCPAR[8–11]
PCDIR[14] 0
PCDIR (Port C data direction register) PCDIR[8–11]
PCDIR[14] 1
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
14 Freescale Semiconductor
Bus Signal Timing
12 Bus Signal Timing
The maximum bus s peed that the M PC852T supports is 66 MHz. Table 7 shows the frequency ranges for
standard part frequencies.
Table 9 provides the bus operation timing for the MPC852T at 33, 40, 50, and 66 MHz.
The timing for the MPC852T bus shown assumes a 50- pF load for maximum delays and a 0-pF load for
minimum delays. CLKOUT assum es a 100-pF load maximum delay
Table 7. Fr equency Ranges for Standard Part Frequencies (1:1 Bus Mode)
Par t Frequency 50 MHz 66 MHz
Min Max Min Max
Core 40 50 40 66.67
Bus 40 50 40 66.67
Table 8. Fr equency Ranges for Standard Part Frequencies (2:1 Bus Mode)
Par t Frequency 50 MHz 66 MHz 80 MHz 100 MHz
Min Max Min Max Min Max Min Max
Core 40 50 40 66.67 40 80 40 100
Bus 2:1 20 25 20 33.33 20 40 20 50
Table 9. Bus Operati on Timings
Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit
Min Max Min Max Min Max Min Max
B1 Bus period (CLKOUT) See Table 7 ————————ns
B1a EXTCLK to CLKOUT phase skew—If
CLKOUT is an integ er multiple of
EXTCLK, then the rising ed ge of E XTCLK
is aligned wi th th e rising edge of CLK OUT.
For a non-int eger multipl e of EXTCLK, th is
synchronizat ion i s lost, and the rising
edges of EXTCLK and CLKOUT have a
continuousl y varying phase sk ew.
–2 +2 –2 +2 –2 +2 2 +2 ns
B1b CLKOUT frequency jitter peak-t o-peak 1 1 1 1 ns
B1c Frequency jitt er on EXTCLK1 0.50 0.50 0.50 0.50 %
B1d CLKOUT phase j itter peak-t o-peak fo r
OSCLK 15 M H z —4—4—4—4ns
CLKOUT phase jit ter peak-to-peak fo r
OSCLK < 15 MHz —5—5—5—5ns
B2 CLK OUT pul se widt h low ( MIN = 0 .4 × B1,
MAX = 0.6 × B1) 12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 15
Bus Signal Timing
B3 CLKOUT pulse width high (MIN = 0.4 × B1,
MAX = 0.6 × B1) 12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns
B4 CLKOUT rise time 4.00 4.00 4.00 4.00 ns
B5 CLKOUT fall time 4.00 4.00 4.00 4.00 ns
B7 CLKOUT to A(0:31), BADDR(28:3 0),
RD/WR, BURST, D(0:31), DP(0:3) output
hold (MIN = 0. 25 × B1)
7.60 6.30 5.00 3.80 ns
B7 a CL KOUT to TSI Z( 0 :1 ), RE G, RSV, BD IP,
PTR output hold (MIN = 0. 25 × B1) 7.60 6.30 5.00 3.80 ns
B7b CLKOUT to BR, B G, FRZ, VFLS(0:1),
VF(0:2) IWP(0:2), LWP(0:1) , STS output
hold (MIN = 0. 25 × B1)
7.60 6.30 5.00 3.80 ns
B8 CLKOUT to A(0:31), BADDR(28:3 0)
RD/WR, BURST, D(0:31) , DP(0:3) valid
(MAX = 0.25 × B1 + 6.3)
13.80 12.50 11.30 10.00 ns
B8 a CL KOUT to TSI Z( 0 :1 ), RE G, RSV, BD IP,
PTR valid (MAX = 0.25 × B1 + 6.3) 13.80 12.50 11.30 10.00 ns
B8b CLKOUT to BR, B G, VFLS(0: 1), VF(0: 2),
IWP(0:2), FRZ, LWP(0:1), STS Valid3
(MAX = 0.25 × B1 + 6.3)
13.80 12.50 11.30 10.00 ns
B9 CLKOUT to A(0:31), BADDR(28:3 0),
RD/WR, BURST, D(0:31), DP(0:3),
TSIZ(0:1), REG, RSV, PTR High-Z
(MAX = 0.25 × B1 + 6.3)
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
B11 CLKOUT to TS, BB asser tion
(MAX = 0.25 × B1 + 6.0) 7.60 13.60 6.30 12.30 5.00 11.00 3.80 9.80 ns
B11a CLKOUT to TA, BI asse rti on (when driv en
by the memory cont rol ler or PCM CIA
interface) (MAX = 0.00 × B1 + 9.302)
2.50 9.30 2.50 9.30 2.50 9.30 2.50 9.80 ns
B12 CLKOUT to TS, BB negation
(MAX = 0.25 × B1 + 4.8) 7.60 12.30 6.30 11.00 5.00 9.80 3.80 8.50 ns
B12a CLKOUT to TA, B I negation (when driven
by the memory cont rol ler or PCM CIA
interface) (MAX = 0.00 × B1 + 9.00)
2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns
B13 CLKOUT to TS, BB High-Z
(MIN = 0.25 × B1) 7.60 21.60 6.30 20.30 5.00 19.00 3.80 14.00 ns
B13a CLK OUT t o TA, B I High-Z ( when driv en b y
the memor y contr oller or PCMCIA
inter face) (MIN = 0.00 × B1 + 2.5)
2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
B14 CLKOUT to TEA assertion
(MAX = 0.00 × B1 + 9.00) 2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns
Table 9. B us Oper a tio n Timings (c on t inu e d)
Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit
Min Max Min Max Min Max Min Max
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
16 Freescale Semiconductor
Bus Signal Timing
B15 CLKOUT to TEA High-Z
(MIN = 0.00 × B1 + 2.50) 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
B16 TA, B I valid t o CLKOUT (setup time)
(MIN = 0.00 × B1 + 6.00) 6.00 6.00 6.00 6.00 ns
B16a TEA, KR, RETRY, C R v alid to CLKOUT
(setup time) (MIN = 0.00 × B1 + 4.5) 4.50 4.50 4.50 4.50 ns
B16b BB, BG, BR, va lid to CLK OUT (setup ti me)
3 (4MIN = 0.00 × B1 +.000) 4.00 4.00 4.00 4.00 ns
B17 CLK OUT t o TA, T EA, BI, BB, BG , BR valid
(hold time) (MIN = 0.00 ×B1 + 1.004)1.00 1.00 1.00 2.00 ns
B17a CLKOUT to KR, R ETRY, C R valid ( hold
time) (MIN = 0.00 × B1 + 2.00) 2.00 2.00 2.00 2.00 ns
B18 D(0:31 ), DP(0:3) val id to CLKOU T rising
edge (setup time)5
(MIN = 0.00 × B1 + 6.00)
6.00 6.00 6.00 6.00 ns
B19 CLKOUT rising edge t o D(0:31), DP(0:3)
valid (hold time)5 ( MIN = 0.00 × B1 + 1.006)1.00 1.00 1.00 2.00 ns
B20 D(0:31) , DP( 0:3) valid to CLKOUT falling
edge (setup time)7
(MIN = 0.00 × B1 + 4.00)
4.00 4.00 4.00 4.00 ns
B21 CLKOUT falli ng edge to D( 0:31), DP(0:3)
val id ( hold T ime) 7 (MIN = 0.00 × B1 + 2. 00) 2.00 2.00 2.00 2.00 ns
B22 CLKOUT rising edge to CS asser ted
GPCM ACS = 00 (MAX = 0.25 × B1 + 6.3) 7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
B22a CLKOUT falling edge to CS asserted
GPCM ACS = 10, TRLX = 0
(MAX = 0.00 × B1 + 8.00)
8.00 8.00 8.00 8.00 ns
B22b CLKOUT falling edge to CS asserted
GPCM ACS = 11, TRLX = 0, EBDF = 0
(MAX = 0.25 ×B1 + 6.3)
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
B22c CLKOUT falling edge to CS asserted
GPCM ACS = 11, TRLX = 0, EBDF = 1
(MAX = 0.375 × B1 + 6.6)
10.90 18.00 10.90 16.00 7.00 14.10 5.20 12.30 ns
B23 CLKOUT rising edge to CS negated
GPCM read acce ss, GPCM write access
AC S = 00, TRLX = 0 & CSNT = 0
(MAX = 0.00 × B1 + 8.00)
2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns
B24 A(0:31) and BADDR(28: 30) to CS
asserted GPCM ACS = 10, TRLX = 0
(MIN = 0.25 × B1 – 2.00)
5.60 4.30 3.00 1.80 ns
Table 9. B us Oper a tio n Timings (c on t inu e d)
Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit
Min Max Min Max Min Max Min Max
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 17
Bus Signal Timing
B24a A(0:31) and BADDR(28: 30) to CS
asserted GPCM ACS = 11 TRLX = 0
(MIN = 0.50 × B1 – 2.00)
13.20 10.50 8.00 5.60 ns
B25 CLKOUT rising edge to OE,
WE(0:3)/BS_B[ 0:3] asserte d
(MAX = 0.00 × B1 + 9.00)
9.00 9.00 9.00 9.00 ns
B26 CLKOUT rising edge to OE negated
(MAX = 0.00 × B1 + 9.00) 2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns
B27 A(0:31) and BADDR(28: 30) to CS
asserted GPCM ACS = 10, TRLX = 1
(MIN = 1.25 × B1 – 2.00)
35.90 29.30 23.00 16.90 ns
B27a A(0:31) and BADDR(28: 30) to CS
asserted GPCM ACS = 11, TRLX = 1
(MIN = 1.50 × B1 – 2.00)
43.50 35.50 28.00 20.70 ns
B28 CLKOUT rising edge to WE(0:3)/
BS_B[0:3 ] negated GPCM wri te ac cess
CSNT = 0 (MAX = 0.00 × B1 + 9.00)
9.00 9.00 9.00 9.00 ns
B28a CLKOUT falli ng edge to WE (0:3)/
BS_B[0:3 ] negated GPCM wri te ac cess
TRLX = 0,1 CSNT = 1, EBDF = 0
(MAX = 0.25 × B1 + 6.80)
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
B28b CLKOUT falling edge to CS negated
GPCM write acce ss TRLX = 0,1 CSNT = 1
ACS = 10 or ACS = 11, EBDF = 0
(MAX = 0.25 × B1 + 6.80)
14.30 13.00 11.80 10.50 ns
B28c CLKOUT falling edge to
WE(0:3)/BS_B[0:3] negate d GPCM write
access TRLX = 0, 1 CSNT = 1 wri te access
TRLX = 0,1 CSNT = 1, EBDF = 1
(MAX = 0.375 × B1 + 6.6)
10.90 18.00 10.90 18.00 7.00 14.30 5.20 12.30 ns
B28d CLKOUT falling edge to CS negated
GPCM write access TRLX = 0,1 CSNT =
1, ACS = 10, or ACS = 11, EBDF = 1
(MAX = 0.375 × B1 + 6.6)
18.00 18.00 14.30 12.30 ns
B29 WE(0:3)/BS_B[0:3] negated t o D(0: 31),
DP(0:3) High-Z GPCM write access,
CSNT = 0, EBDF = 0
(MIN = 0.25 × B1 – 2.00)
5.60 4.30 3.00 1.80 ns
B29a WE(0:3)/ BS_B[0:3] negated to D(0: 31),
DP(0:3) High-Z GPCM write access, TRLX
= 0, CSNT = 1, EBDF = 0
(MIN = 0.50 × B1 – 2.00)
13.20 10.50 8.00 5.60 ns
Table 9. B us Oper a tio n Timings (c on t inu e d)
Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit
Min Max Min Max Min Max Min Max
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
18 Freescale Semiconductor
Bus Signal Timing
B29b CS negated to D( 0:31) , DP(0:3), High Z
GPCM write access , ACS = 00,
TRLX = 0,1 and CSNT = 0
(MIN = 0.25 × B1 – 2.00)
5.60 4.30 3.00 1.80 ns
B29c CS negated to D(0:31), DP(0:3) Hig h-Z
GPCM wri te access, TRLX = 0 , CSNT = 1,
ACS = 10, or ACS = 11 EBDF = 0
(MIN = 0.50 × B1 – 2.00)
13.20 10.50 8.00 5.60 ns
B29d WE(0:3)/ BS_B[0:3] negated to D(0: 31),
DP(0:3) High-Z GPCM write access, TRLX
= 1, CSNT = 1, EBDF = 0
(MIN = 1.50 × B1 – 2.00)
43.50 35.50 28.00 20.70 ns
B29e CS negated to D(0:31), DP(0:3) High-Z
GPCM wri te access, TRLX = 1 , CSNT = 1,
ACS = 10, or ACS = 11 EBDF = 0
(MIN = 1.50 × B1 – 2.00)
43.50 35.50 28.00 20.70 ns
B29f WE(0:3/BS_B[0:3]) negated to D(0:31),
DP(0:3) High Z GPCM write access,
TRLX = 0, CSNT = 1, EBDF = 1
(MIN = 0.375 × B1 – 6.30 )8
5.00 3.00 1.10 0.00 ns
B29g CS negated to D(0:31), DP(0:3) High-Z
GPCM wri te access, TRLX = 0, CSNT = 1
ACS = 10 or ACS = 11, EBDF = 1
(MIN = 0.375 × B1 – 6.30 )8
5.00 3.00 1.10 0.00 ns
B29h WE(0:3)/ BS_B[0:3] negated to D(0: 31),
DP(0:3) High Z GPCM write access,
TRLX = 1, CSNT = 1, EBDF = 1
(MIN = 0.375 × B1 – 3.30 )
38.40 31.10 24.20 17.50 ns
B29i CS negated to D(0:31), DP(0:3) High-Z
GPCM wri te access, TRLX = 1 , CSNT = 1,
ACS = 10 or ACS = 11, EBDF = 1
(MIN = 0.375 × B1 – 3.30 )
38.40 31.10 24.20 17.50 ns
B30 CS, W E(0: 3)/ BS_B[0:3] negated t o
A(0:31), BADDR( 28:30) Invalid GPCM
write access 9 (MIN = 0.25 × B1 – 2.00)
5.60 4.30 3.00 1.80 ns
B30a WE(0:3)/ BS_B[0:3] negated to A(0: 31),
BADDR(28:30) Inva lid GPCM, write
access , TRLX = 0, CSNT = 1, CS negat ed
to A (0:31) invalid GPC M w r ite acce s s
TRLX = 0, CSNT =1 ACS = 10, or
A CS = = 11 , EBDF = 0
(MIN = 0.50 × B1 – 2.00)
13.20 10.50 8.00 5.60 ns
Table 9. B us Oper a tio n Timings (c on t inu e d)
Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit
Min Max Min Max Min Max Min Max
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 19
Bus Signal Timing
B30b WE(0:3)/ BS_B[0:3] negated to A(0: 31)
Invalid GPCM BADDR(28:30) inval id
GPCM wri te access, TRLX = 1 , CSNT = 1.
CS negated to A(0:31) In valid GPCM write
access TRLX = 1, CSNT = 1, A CS = 10, or
ACS == 11 EBDF = 0
(MIN = 1.50 × B1 – 2.00)
43.50 35.50 28.00 20.70 ns
B30c WE(0:3)/ BS_B[0:3] negated to A(0: 31),
BADDR(28:30) inva lid GPCM write
access , TRLX = 0, CSNT = 1. CS negat ed
to A (0 : 31) in vali d GPC M w r it e a cc e s s,
TRLX = 0, CSNT = 1 ACS = 10,
A CS = = 11 , EBDF = 1
(MIN = 0.375 × B1 – 3.00 )
8.40 6.40 4.50 2.70 ns
B30d WE(0:3)/ BS_B[0:3] negated to A(0: 31),
BADDR(28:30) invalid GPCM write access
TRLX = 1, CSNT =1, CS negated to
A(0:31) inva li d G PCM write acc ess
TRLX = 1, CSNT = 1, ACS = 10 or 11,
EBDF = 1
38.67 31.38 24.50 17.83 ns
B31 CLKOUT falling edge to CS valid - as
requested by control bit CST4 in the
corresponding word i n the UPM
(MAX = 0.00 × B1 + 6.00)
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
B31a CLKOUT falling edge to CS v alid - as
requested by control bit CST1 in the
corresponding word i n the UPM
(MAX = 0.25 × B1 + 6.80)
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
B31b CLKOUT rising edge to CS valid - as
requested by control bit CST2 in the
corresponding word i n the UPM
(MAX = 0.00 × B1 + 8.00)
1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns
B31c CLKOUT rising edge to CS va lid - a s
requested by control bit CST3 in the
corresponding word i n the UPM
(MAX = 0.25 × B1 + 6.30)
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
B31d CLKOUT falling edge to CS valid, as
requested by control bit CST1 in the
corres ponding wor d in t he UPM EBDF = 1
(MAX = 0.375 × B1 + 6.6)
13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns
B32 CLKOUT falling edge to BS vali d- as
requested by control bit BST4 in the
corresponding word i n the UPM
(MAX = 0.00 × B1 + 6.00)
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
Table 9. B us Oper a tio n Timings (c on t inu e d)
Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit
Min Max Min Max Min Max Min Max
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
20 Freescale Semiconductor
Bus Signal Timing
B32a CLKOUT falling edge to BS valid - as
requested by control bit BST1 in the
corresponding word in the UPM, EBDF = 0
(MAX = 0.25 × B1 + 6.80)
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
B32b CLKOUT rising edge to BS valid - as
requested by control bit BST2 in the
corresponding word i n the UPM
(MAX = 0.00 × B1 + 8.00)
1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns
B32c CLKOUT r ising edge to BS valid - as
requested by control bit BST3 in the
corresponding word i n the UPM
(MAX = 0.25 × B1 + 6.80)
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
B32d CLKOUT falling edge to BS valid- as
requested by control bit BST1 in the
corresponding word in the UPM, EBDF = 1
(MAX = 0.375 × B1 + 6.60)
13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns
B33 CLKOUT falling edge to GPL val id - as
requested by cont rol bit GxT4 in the
corresponding word i n the UPM
(MAX = 0.00 × B1 + 6.00)
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
B33a CLKOUT rising edge to GPL Valid - as
requested by cont rol bit GxT3 in the
corresponding word i n the UPM
(MAX = 0.25 × B1 + 6.80)
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
B34 A(0:31) , BADDR( 28:30), and D(0:31) to
CS valid - as requested by control bi t
CST4 in the cor responding word in the
UPM (MIN = 0.25 × B1 – 2.0 0)
5.60 4.30 3.00 1.80 ns
B34a A(0:31) , BADDR( 28:30), and D(0:31) to
CS vali d - as requested b y control bit
CST1 in the cor responding word in the
UPM (MIN = 0.50 × B1 – 2.0 0)
13.20 10.50 8.00 5.60 ns
B34b A(0:31) , BADDR( 28:30), and D(0:31) to
CS vali d - as requested by CST2 in t he
corresponding word i n UPM
(MIN = 0.75 × B1 – 2.00)
20.70 16.70 13.00 9.40 ns
B35 A(0:31), BADDR(28:30) to CS valid - as
requested by control bit BST4 in the
corresponding word i n the UPM
(MIN = 0.25 × B1 – 2.00)
5.60 4.30 3.00 1.80 ns
B35a A(0:31) , BADDR( 28:30), and D(0:31) to
BS valid - As Requested by BST1 in the
corresponding word i n the UPM
(MIN = 0.50 × B1 – 2.00)
13.20 10.50 8.00 5.60 ns
Table 9. B us Oper a tio n Timings (c on t inu e d)
Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit
Min Max Min Max Min Max Min Max
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 21
Bus Signal Timing
B35b A(0:31) , BADDR( 28:30), and D(0:31) to
BS v alid - as reque sted b y cont rol bit BST2
in the cor responding wo rd i n the UPM
(MIN = 0.75 × B1 – 2.00)
20.70 16.70 13.00 9.40 ns
B36 A(0:31) , BADDR( 28:30), and D(0:31) to
GPL valid as requested by control bit GxT4
in the cor responding wo rd i n the UPM
(MIN = 0.25 × B1 – 2.00)
5.60 4.30 3.00 1.80 ns
B37 UPWAIT valid to CLKOUT falli ng edge10
(MIN = 0.00 × B1 + 6.00) 6.00 6.00 6.00 6.00 ns
B38 CLKOUT falling edge to UPWAIT valid10
(MIN = 0.00 × B1 + 1.00) 1.00 1.00 1.00 1.00 ns
B39 AS valid to CLKOUT rising edge11
(MIN = 0.00 × B1 + 7.00) 7.00 7.00 7.00 7.00 ns
B40 A(0:31), TSIZ(0 :1), RD/WR, BURST, valid
to CLKOUT rising edge
(MIN = 0.00 × B1 + 7.00)
7.00 7.00 7.00 7.00 ns
B41 TS valid to CLKOUT r ising edge (setup
time) (MIN = 0.00 × B1 + 7.00) 7.00 7.00 7.00 7.00 ns
B42 CLKOUT rising edge to TS vali d ( h old
time) (MIN = 0.00 × B1 + 2.00) 2.00 2.00 2.00 2.00 ns
B43 AS negation to memory controller signals
negati on (MAX = TBD) —TBD—TBD—TBD—TBDns
1If the r ate of change of the frequency of EXTAL is slow (that is, it does not jump between the minimum and m aximum values
in one cyc le) o r the freq uency of the jitter is fas t (that is, i t does not sta y at an extreme val ue for a lo ng ti me), t hen the maximum
all owed jitter on EXTAL can be up to 2%.
2For part speeds above 50MHz, use 9.80ns for B11a.
3The ti ming req uired f or BR input i s rele v ant when the MPC852T i s selec ted to wo rk with int erna l bus arbit er . The timi ng f or BG
input is relevant when the MPC852T is selected to work with external bus arbiter.
4For part speeds above 50MHz, use 2ns for B17.
5The D(0:31) and DP(0:3) input timings B18 and B19 refe r to the rising edge of the CLKOUT in which the TA input signal is
asserted.
6For part speeds above 50MHz, use 2ns for B19.
7The D(0:31) and DP(0:3) input tim ings B20 and B21 refer to the fal li ng edge of the CLKOUT. This timi ng is valid only for read
accesses contr oll ed by chip- selects unde r cont rol of the UPM in the memory controll er, f or data beats where DLT3 = 1 in the
UPM RAM words . ( This is only the case where data is latched on the falling ed ge of CLKOUT.)
8This formula applies to bus operati on up to 50 MHz.
9The ti ming B30 refers t o CS when A CS = 00 and to WE(0:3) when CSNT = 0.
10 The si gnal UPW AIT is consi dered asynch ronous to the CL K OUT and synchroni zed internally. The timing s specifi ed in B37 and
B38 are specified to enable the freeze of the UPM output signals as described in Figure 19.
11 The AS s ig nal i s consi dered a sync hron ous to the CLKOUT. Th e timi ng B39 is specif ied i n order t o all ow th e be havi or spec ifie d
in Figure 22.
Table 9. B us Oper a tio n Timings (c on t inu e d)
Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit
Min Max Min Max Min Max Min Max
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
22 Freescale Semiconductor
Bus Signal Timing
Figure 4 is the control timing diagra m.
Figure 4. Con trol Ti m in g
Figure 5 provide s the timing for the external clock.
Figure 5. External Cloc k Timing
CLKOUT
Outputs
A
B
Outputs
B
A
Inputs
D
C
Inputs
C
D
A Maxim um output delay specificat ion.
B Minimum output hold time.
C Minimum input set up time specification.
D Minimum input hol d ti m e specification.
CLKOUT
B1
B5
B3
B4
B1
B2
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 23
Bus Signal Timing
Figure 6 provides the timing for the synchronous output signals.
Figu re 6. S ync h ronous Output Sign a ls Tim i ng
Figure 7 provides the timing for the synchronous active pull -up and open-drain output signals.
Figure 7. Syn chronous Active Pull-Up Resistor and Open-Drain Ou tpu ts Signals Timing
CLKOUT
Output
Signals
Output
Signals
Output
Signals
B8
B7 B9
B8a
B9B7a
B8b
B7b
CLKOUT
TS, BB
TA, BI
TEA
B13
B12B11
B11a B12a
B13a
B15
B14
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
24 Freescale Semiconductor
Bus Signal Timing
Figure 8 provides the timing for the synchronous input signals.
Figure 8. Synchronous Input Signals Timing
Figure 9 provides normal case timing for input data. It also applies to normal read accesses under the
control of the UPM in the memory controller.
Figure 9. Input Data Timing in Normal Case
CLKOUT
TA, BI
TEA, KR,
RETRY, C R
BB, BG, BR
B16
B17
B16a
B17a
B16b
B17
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 25
Bus Signal Timing
Figure 10 pr ovides the timi ng for the input data controlled by the UPM for data beats where DLT3 = 1 in
the UPM RAM w o rds. (This is only the case where data is latched on the falling edge of CLKOUT.)
Figure 10. Input Data Tim ing When Controlled by UPM in the Memo ry Co ntroller and DLT 3 = 1
Figure 11 through Figure 14 provide the timing for the external bus read that various GPCM factors
control.
Figure 11. Exter nal Bus Read Timi ng (GPCM Controlled—ACS = 00)
CLKOUT
TA
D[0:31],
DP[0:3]
B20
B21
CLKOUT
A[0:31]
CSx
OE
WE[0:3]
TS
D[0:31],
DP[0:3]
B11 B12
B23
B8
B22
B26
B19
B18
B25
B28
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
26 Freescale Semiconductor
Bus Signal Timing
Figure 12. External Bus Read Timing (GPCM Co ntrolled—TRLX = 0, ACS = 10)
Figure 13. External Bus Read Timing (GPCM Co ntrolled—TRLX = 0, ACS = 11)
CLKOUT
A[0:31]
CSx
OE
TS
D[0:31],
DP[0:3]
B11 B12
B8
B22a B23
B26
B19B18
B25B24
CLKOUT
A[0:31]
CSx
OE
TS
D[0:31],
DP[0:3]
B11 B12
B22b
B8
B22c B23
B24a B25 B26
B19B18
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 27
Bus Signal Timing
Figure 14. External Bus Read Timing (GPCM Con trolled—TRL X = 0 or 1, ACS = 10, ACS = 11)
CLKOUT
A[0:31]
CSx
OE
TS
D[0:31],
DP[0:3]
B11 B12
B8
B22a
B27
B27a
B22b B22c B19B18
B26
B23
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
28 Freescale Semiconductor
Bus Signal Timing
Figure 15 through Figure 17 provide the timing for the external bus write that various GPCM factors
control.
Figure 15. External Bus Write Timi ng (GPCM Controlled—T RLX = 0 or 1, CSNT = 0)
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 29
Bus Signal Timing
Figure 16. External Bus Write Timing (GPCM Controlled—T RLX = 0 or 1, CSNT = 1)
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
30 Freescale Semiconductor
Bus Signal Timing
Figure 17. External Bus Write Timing (GPCM Controlled—T RLX = 0 or 1, CSNT = 1)
B23B22
B8
B12B11
CLKOUT
A[0:31]
CSx
WE[0:3]
TS
OE
D[0:31],
DP[0:3]
B30dB30b
B28b B28d
B25 B29e B29i
B26 B29d B29h
B28a B28c B9B8
B29b
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 31
Bus Signal Timing
Figure 18 provide s the timing for the external bus that the UPM controls.
Figure 18. Exter nal Bus Tim ing (UPM Con trolled Signals)
CLKOUT
CSx
B31d
B8
B31
B34
B32b
GPL_A[0:5],
GPL_B[0:5]
BS_A[0:3]
A[0:31]
B31c
B31b
B34a
B32
B32a B32d
B34b
B36
B35b
B35a
B35
B33
B32c
B33a
B31a
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
32 Freescale Semiconductor
Bus Signal Timing
Figure 19 provides the timing for the asynchronous asserted UP WAIT signal that the UPM controls.
Figure 19. As ynchronous UPWAIT Asser ted Detection in UPM Handled Cycles Timing
Figure 20 provides the timing for the asynchronous negated UPWAIT signal that the UPM controls.
Figur e 20. Asynch ronous UPWAIT Negated Detection in UPM Handled Cycles Timin g
CLKOUT
CSx
UPWAIT
GPL_A[0:5],
GPL_B[0:5]
BS_A[0:3]
B37
B38
CLKOUT
CSx
UPWAIT
GPL_A[0:5],
GPL_B[0:5]
BS_A[0:3]
B37
B38
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 33
Bus Signal Timing
Figure 21 provides the timing for the synchronous external master access that the GPCM controls.
Figure 21. Synchronous External Master Access Timin g (GPCM Handled AC S = 00)
Figure 22 provides the timing for the asynchronous external master memory access that the GP CM
controls.
Figure 2 2. Asynchronous Externa l Master Memo ry Access Timing (GPC M Controlled—ACS = 00)
Figure 23 provides the timing for the asynchronous external master control signals negation.
Fig ure 23 . Asyn ch ronou s Ex ternal Master—C ontrol Signals Negatio n Ti m in g
CLKOUT
TS
A[0:31],
TSIZ[0:1],
R/W, BURST
CSx
B41 B42
B40
B22
CLKOUT
AS
A[0:31],
TSIZ[0:1],
R/W
CSx
B39
B40
B22
AS
CSx, WE[0:3],
OE, GPL x,
BS[0:3]
B43
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
34 Freescale Semiconductor
Bus Signal Timing
Table 10 provides interrupt timing for the MPC852T.
.
Figure 24 provide s the interrupt detection timing for the external level- sens itive lines.
Figure 24. Inter rup t Detection Tim ing for External Level Sensitive Lines
Figure 25 provide s the interrupt detection timing for the external edge- sensi tive lines.
Figure 25. Interrupt Detection Timing for E xternal Edge Sensitive Lines
Table 10. Interrupt Timing
Num Characteristic1
1The timi ngs I39 and I40 describe t he testing condit ions under which the IRQ lines are test ed when being defined as
le v el- sens itiv e . The IRQ l ines ar e sync hroniz ed int ernally and need not be asse rted or negated wi th ref ere nce to the CLKOUT.
The timings I41, I42, and I43 are spec ified to al low the co rrect function of the I RQ lines detection circuitry, and have no direct
relation with the tot al s ystem interrupt latency that the MPC8 52T is ab le to support.
All Frequencies Unit
Min Max
I39 IRQx vali d to CLKOUT risi ng edge (set up time) 6.00 ns
I40 IRQx hold time after CLKOUT 2.00 ns
I41 IRQx pulse width low 3.00 ns
I42 IRQx pulse width high 3.00 ns
I43 IRQx edge-to-edge time 4 × TCLOCKOUT
CLKOUT
IRQx
I39
I40
CLKOUT
IRQx
I41 I42
I43
I43
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 35
Bus Signal Timing
Table 11 shows the PCMCIA timing for the MPC852T.
Table 11. PCMCIA Timing
Num Characteristic 33 MHz 40 MHz 50 M H z 66 MHz Unit
Min Max Min Max Min Max Min Max
J82 A( 0:31), REG val id t o PCMCIA Str obe
asserted.1 (M IN = 0. 7 5 × B1 – 2.00)
1PSST = 1. Otherwise add PSST times cy cle t ime.
PSHT = 0. Otherwi se add PSHT tim es cycle time.
These synchronous timings define when the WAITA signals are detected in or der to freeze ( or relieve) the
PCMC IA curre nt cycle. The WAI TA assert ion is effective only if it is det ected 2 cy cles bef ore the PSL
timer expirat ion. See the PCMCIA Inter f ace section in th e MPC866 Power QUICC™ Family Reference
Manual.
20.70 16.70 13.00 9.40 ns
J83 A(0:31), REG valid to ALE negation.1
(MIN = 1.00 × B1 – 2.00) 28.30 23.00 18.00 13.20 ns
J84 C LKO U T t o R E G va lid
(MAX = 0.25 × B1 + 8.00) 7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns
J85 C LKO U T t o R E G Invalid.
(MIN = 0.25 × B1 + 1.00) 8.60 7.30 6.00 4.80 ns
J86 C LKO U T t o C E 1, CE2 asse rted.
(MAX = 0.25 × B1 + 8.00) 7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns
J87 C LKO U T t o C E 1, CE2 negated.
(MAX = 0.25 × B1 + 8.00) 7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns
J88 CLKOUT to PCOE, IO RD, PCWE, IO WR
assert time. (MAX = 0.00 × B1 + 11.00) 11.00 11.00 11.00 11.00 ns
J89 CLKOUT to PCOE, IO RD, PCWE, IO WR
negate tim e. (MAX = 0.00 × B1 + 11.00) 2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00 ns
J90 CLKOUT to ALE asser t time
(MAX = 0.25 × B1 + 6.30) 7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
J91 CLKOUT to ALE negate time
(MAX = 0.25 ×B1 + 8.00) 15.60 14.30 13.00 11.80 ns
J92 PCWE, IOWR negat ed to D(0 :31) invalid.1
(MIN = 0.25 × B1 – 2.00) 5.60 4.30 3.00 1.80 ns
J93 WAITA and WAITB valid to CLK OUT rising
edge.1 (MIN = 0.00 ×B1 + 8.00) 8.00 8.00 8.00 8.00 ns
J94 CLKOUT rising edge to WAITA and WAITB
invalid.1 (MIN = 0.00 ×B1 + 2.00 ) 2.00 2.00 2.00 2.00 ns
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
36 Freescale Semiconductor
Bus Signal Timing
Figure 26 provides the PCMCIA access cycle t iming for the external bus read.
Fi gure 26 . P CMCIA Access Cycles Timing External Bus Read
CLKOUT
A[0:31]
REG
CE1/CE2
PCOE, IORD
TS
D[0:31]
ALE
B19B18
P53P52 P52
P51P50
P48 P49
P46 P45
P44
P47
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 37
Bus Signal Timing
Figure 27 provides the PCMCIA access cycle t iming for the external bus write.
Figure 27. PCM C IA A ccess Cycles Timing Extern al Bus Write
Figure 28 provides the PCMCIA WAIT signals detection timing.
Figure 28. PCMCIA WAIT S ignals Detection Timing
CLKOUT
A[0:31]
REG
CE1/CE2
PCWE, IOWR
TS
D[0:31]
ALE
B9B8
P53P52 P52
P51P50
P48 P49
P46 P45
P44
P47
P54
CLKOUT
WAITA
P55
P56
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
38 Freescale Semiconductor
Bus Signal Timing
Table 12 shows the PCMCIA port timing for the MPC852T.
Figure 29 provides the PCMCIA output por t timing for the MPC852T.
Figure 29. PCMCIA Output Port Timing
Figure 30 provides the PCMCIA output por t timing for the MPC852T.
Figure 30. PCMCIA I nput Port Timing
Ta b le 1 2 . PC MCIA Por t T i min g
Num Characteristic 33 MHz 40 MHz 50 M H z 66 MHz Unit
Min Max Min Max Min Max Min Max
J95 CLKOUT to OPx Va lid
(MAX = 0.00 × B1 + 19.00) 19.00 19.00 19.00 19.00 ns
J96 HRESET negated to OPx drive1
(MIN = 0.75 × B1 + 3.00)
1OP2 and OP3 onl y.
25.70 21.70 18.00 14.40 ns
J97 IP_Xx val id to CLKOUT rising edge
(MIN = 0.00 × B1 + 5.00) 5.00 5.00 5.00 5.00 ns
J98 CLKOUT rising edge to IP_Xx invalid
(MIN = 0.00 × B1 + 1.00) 1.00 1.00 1.00 1.00 ns
CLKOUT
HRESET
Output
Signals
OP2, OP3
P57
P58
CLKOUT
Input
Signals
P59
P60
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 39
Bus Signal Timing
Table 13 shows the debug port timing for the MPC852T.
Figure 31 provides the input timing for the debug port clock.
Fi gure 31. De bug Port Cl ock I nput Timing
Figure 32 provides the timing for the debug port.
Figure 32. Debug Port Timings
Table 13. D ebug Port Tim in g
Num Characteristic All Frequencies Unit
Min Max
J82 DSCK cycle time 3 × TCLOCKOUT ——
J83 DSCK clock pul se width 1.25 × TCLOCKOUT ——
J84 DSCK rise and fall times 0.00 3.00 ns
J85 DSDI input da ta setup time 8.00 ns
J86 DSDI data hol d time 5.00 ns
J87 DSCK low to DSDO data valid 0.00 15.00 ns
J88 DSCK low to DSDO invali d 0.00 2.00 ns
DSCK
D61
D61
D63
D62
D62
D63
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
40 Freescale Semiconductor
Bus Signal Timing
Table 14 shows the reset timing for the MPC852T.
Table 14. Reset Ti ming
Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit
Min Max Min Max Min Max Min Max
J82 CLKOUT to HRESET hi gh impedance
(MAX = 0.00 × B1 + 20.00) 20.00 20.00 20.00 20.00 ns
J83 CLKOUT to SRESET high impedance
(MAX = 0.00 × B1 + 20.00) 20.00 20.00 20.00 20.00 ns
J84 RSTCONF pul se widt h (MIN = 17 .00 × B1) 515.20 425.00 340.00 257.60 ns
J85 ————————
J86 Configuration data to HRESET rising edge
se t up time (M IN = 15 . 0 0 × B1 + 50.00) 504.50 425.00 350.00 277.30 ns
J87 Configurati on data to RSTCONF risin g
edge set up ti m e
(MIN = 0.00 × B1 + 350.0 0)
350.00 350.00 350.00 350.00 ns
J88 Configur ati on data hold time aft er
RSTCONF negation
(MIN = 0.00 × B1 + 0.00)
0.00 0.00 0.00 0.00 ns
J89 Configur ati on data hold time aft er
HRESET negation
(MIN = 0.00 × B1 + 0.00)
0.00 0.00 0.00 0.00 ns
J90 HRESET a nd RSTCONF asserted to data
out drive (MAX = 0.00 × B1 + 25.00) 25.00 25.00 25.00 25.00 ns
J91 RSTCONF negat ed to data out high
impedance. (MAX = 0.00 × B1 + 25.00) 25.00 25.00 25.00 25.00 ns
J92 CLKOUT of last rising edge before c hip
three-states HRESET to data out high
impedance. (MAX = 0.00 × B1 + 25.00)
25.00 25.00 25.00 25.00 ns
J93 DSDI, DSCK set up (MI N = 3.00 × B1) 90.90 75.00 60.00 45.50 ns
J94 DSDI, DSCK hold time
(MIN = 0.00 × B1 + 0.00) 0.00 0.00 0.00 0.00 ns
J95 SRESET negat ed to CLKOUT risi ng edge
for DSDI and DSCK sample
(MIN = 8.00 × B1)
242.40 200.00 160.00 121.20 ns
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 41
Bus Signal Timing
Figure 33 shows the reset timing for the data bus configuration.
Figure 33. Reset Timing—Configuration from Data Bus
Figure 34 provide s the reset timing for the data bus weak drive during configuration.
Figure 34. Reset Timing— Data Bus Weak Drive During Configuration
HRESET
RSTCONF
D[0:31] (IN)
R71
R74
R73
R75
R76
CLKOUT
HRESET
D[0:31] (OUT)
(Weak)
RSTCONF
R69
R79
R77 R78
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
42 Freescale Semiconductor
IEEE 1149.1 Electrical Specifications
Figure 35 provides the reset timing for the debug port configurati on.
Figure 35. Reset Timi ng—Debug P ort Con figuration
13 IEEE 1149.1 Electrical Spec ifications
Table 15 provides the JTAG timings for the MPC852T shown in Figure 36 through Figure 39.
Table 15. JTAG Timing
Num Characteristic All Frequencies Unit
Min Max
J82 TCK cycle time 100.00 ns
J83 TCK clock pulse width measured at 1.5 V 40.00 ns
J84 TCK rise and fall times 0.00 10.00 ns
J85 TMS, TDI data setup time 5.00 ns
J86 TMS, TDI data hold time 25.00 ns
J87 TCK low to TDO data valid 27.00 ns
J88 T CK low to TD O d at a invalid 0. 00 ns
J89 TCK low to TDO high impedance 20.00 ns
J90 TRST assert time 100.00 ns
J91 TRST setup time to TCK lo w 40.00 ns
J92 TCK falli ng edge to output valid 50.00 ns
J93 TCK falling edge to out put valid out of high im pedance 50.00 ns
J94 TCK falli ng edge to output high impedance 50.00 ns
J95 Bounda ry scan inpu t valid to TCK rising edge 50.00 ns
J96 TCK rising edg e to boundary sc an input invalid 50.00 ns
CLKOUT
SRESET
DSCK, DSDI
R70
R82
R80R80
R81 R81
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 43
IEEE 1149.1 Electrical Specifications
Figure 36. JTAG Test Clock In pu t Timing
Figure 37. JTAG Test Access Port Timing Diagram
Figure 38. JTAG TRST Ti m i ng Dia gram
Fig ure 39. Bo undar y Scan (JTAG) Ti m ing Diagr am
TCK
J82 J83
J82 J83
J84 J84
TCK
TMS, T D I
TDO
J85
J86
J87
J88 J89
TCK
TRST
J91
J90
TCK
Output
Signals
Output
Signals
Output
Signals
J92 J94
J93
J95 J96
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
44 Freescale Semiconductor
CP M Electrical Characteristics
14 CPM Electrical Characteristics
This section provides the AC and DC electrical specifications for the communications process or module
(CPM) of the M PC852T.
14 .1 Port C Interr u pt AC El ectrical Specifications
Table 16 provid es the timings for port C interrupts.
Figure 40 shows the port C interrupt detection timing.
Figure 40. Port C In te rrup t Detectio n Ti m in g
Table 16. Por t C Inte rru pt Ti m in g
Num Characteristic 33.34 MHz Unit
Min Max
35 Por t C i nterrupt pulse width low (edge-triggered m ode) 55 ns
36 Por t C i nterrupt minimum time between active edges 55 ns
Port C
35
36
(Input)
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 45
CPM Electrical Characterist ics
14.2 IDMA Controller AC Electrical Specifications
Table 17 provides the IDMA control ler timings as shown in Figure 41 through Figure 44.
Figure 41. IDMA External Requests Timin g Diagram
Table 17. IDMA Controller Timing
Num Characteristic All Frequencies Unit
Min Max
40 DREQ s et u p ti m e to cl o ck hig h 7 n s
41 DREQ hold time from clock high 1
1Appl ies to hig h- t o -low m o de (E D M = 1) .
3—ns
42 SDACK ass ertion delay fro m clock high 12 ns
43 SDACK nega tion delay from cloc k low 12 ns
44 SDACK nega ti on delay f rom TA low 20 ns
45 SDACK nega tion delay from cloc k high 15 ns
46 TA assertion to rising edge of the clock setup time (applies to external TA)7 ns
41
40
DREQ
(Input)
CLKO
(Output)
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
46 Freescale Semiconductor
CP M Electrical Characteristics
Figu re 42. S DAC K Timing Diagram Peripheral Writ e, Extern ally-Gen erated TA
Figure 43. SD ACK Timing Diagram— Peripheral Write, Internal ly-Generated TA
DATA
42 44
CLKO
(Output)
TS
(Output)
R/W
(Output)
TA
(Output)
SDACK
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 47
CPM Electrical Characterist ics
Fi gure 44 . SDACK Timing Diagram— Peripheral Read, Internally-Gener ated TA
14 .3 Baud Rate Generator AC Electrical Specifications
Table 18 provid es the baud rate gener a tor timings as shown in Figure 45.
Figure 45. Baud Rate Generator Timing Dia gram
Table 18. Baud Rate Generator Timing
Num Characteristic All Frequencies Unit
Min Max
50 BRGO rise and fall time 10 ns
51 BRGO duty cyc le 40 60 %
52 BRGO cycl e 40 ns
DATA
42 45
CLKO
(Output)
TS
(Output)
R/W
(Output)
TA
(Output)
SDACK
52
50
51
BRGOX
50
51
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
48 Freescale Semiconductor
CP M Electrical Characteristics
14 .4 Timer AC Electrical Specif icati on s
Table 19 provides the gener al-purpo se timer timings as shown in Figure 46.
Figure 46. CPM General-Purpose Timers Timing Diagram
14.5 SCC in NMSI Mode Electrical Specificati ons
Table 20 provides the NMSI external clock timing.
Tabl e 19 . Time r Timing
Num Characteristic All Frequencies Unit
Min Max
61 TIN/TGATE rise and fal l ti me 10 ns
62 TIN/TGATE low ti m e 1 clk
63 TIN/TGATE high time 2 clk
64 TIN/TGATE cycle time 3 clk
65 CLKO low to TOUT valid 3 25 ns
Table 20. NMSI External Clock Timing
Num Characteristic All Frequencies Unit
Min Max
100 RCLK3 and TCLK3 width high11/SYNCCLK ns
101 RCLK3 and TCLK3 width low 1/SYNCCLK + 5 ns
102 RCLK3 and TCLK3 rise/fall ti me 15.00 ns
103 TXD3 active delay (from TCLK3 falling edge) 0.00 50.00 ns
104 RTS3 active/inactive delay (from TCLK3 falling edge) 0.00 50.00 ns
105 CTS3 setup time to TCLK3 risin g edge 5.00 ns
106 RXD3 setup time to RCLK3 rising edge 5. 00 ns
CLKO
TIN/TGATE
(Input)
TOUT
(Output)
64
65
61
626361
60
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 49
CPM Electrical Characterist ics
Table 21 pr ovides the NMSI internal clock timing.
107 RXD3 hold time from RCLK3 rising edge25.00 ns
108 CD3 setup Time to RCLK3 rising edge 5.00 ns
1The ratios SyncCLK/RCLK3 and Sy ncCLK/TCLK3 must be gr eater than or equal to 2.25/1.
2Also applies to CD and CTS hold time when they are used as an external sync signal .
Table 21. NMSI Intern al Clock Timing
Num Characteristic All Frequencies Unit
Min Max
100 RCLK3 and TCLK3 frequency1
1The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 3/1.
0.00 SYNCCLK/3 MHz
102 RCLK3 and TCLK3 rise/fall ti me ns
103 TXD3 active delay (from TCLK3 falling edge) 0.0 0 30.00 ns
104 RTS3 active/inactive delay (from TCLK3 falling edge) 0.00 30.00 ns
105 CTS3 setup time to TCLK3 risin g edge 40.00 ns
106 RXD3 setup time to RCLK3 rising edge 40.00 ns
107 RXD3 hold time from RCLK3 rising edge2
2Also applies to CD and CTS hold time when they are used as an external sync signal s.
0.00 ns
108 CD3 setup tim e to RCLK3 rising edge 40.00 ns
Tabl e 2 0. NMSI Exte rnal Clock Ti m in g (c ontinue d)
Num Characteristic All Frequencies Unit
Min Max
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
50 Freescale Semiconductor
CP M Electrical Characteristics
Figure 47 through Figure 49 show the NMSI timings.
Figur e 47. SCC NMSI Receive Timing Diag ram
Figure 48. SCC NMSI Transmit Ti ming Di ag ram
RCLK3
CD3
(Input )
102
100
107
108
107
RxD3
(Input)
CD3
(SYNC Input)
102 101
106
TCLK3
CTS3
(Input )
102
100
104
107
TxD3
(Output)
CTS3
(SYNC Input)
102 101
RTS3
(Output)
105
103
104
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 51
CPM Electrical Characterist ics
Figure 49. HDLC Bu s Timing Diagram
14.6 Ethernet Electrical Specifications
Table 22 provides the E thernet timings as shown in Figure 50 through Figure 54.
Table 22. Ethe rnet Ti m in g
Num Characteristic All Frequencies Unit
Min Max
120 CLSN width high 40 ns
121 RCLK3 ris e/fall time 15 ns
122 RCLK3 width low 40 ns
123 RCLK3 clock peri od 180 120 ns
124 RXD3 setup time 20 ns
125 R X D 3 hold ti me 5 ns
126 RENA active delay (from RCLK3 rising edge of the last data bit) 10 ns
127 RENA width low 100 ns
128 TCLK3 rise/fall time 15 ns
129 TCLK3 width low 40 ns
130 TCLK3 clock period199 101 ns
131 TXD3 active dela y (f rom TCLK3 ris ing edge) 50 ns
132 TXD3 inactiv e delay (from TCLK3 rising edge) 6.5 50 ns
133 TENA active del ay (from TCLK3 rising edge) 10 50 ns
134 TENA inactive delay (from TCLK3 rising edge) 10 50 ns
TCLK3
CTS3
(Echo Input)
102
100
104
TxD3
(Output)
102 101
RTS3
(Output)
103
104107
105
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
52 Freescale Semiconductor
CP M Electrical Characteristics
Figure 50. Ethe rn e t Co lli s io n Ti m in g Di ag ram
Figure 51. Ethernet Receive Timing Diagram
135 RSTRT active delay (from TCLK3 falling edge) 10 50 ns
136 RSTRT inactive delay (from TCLK3 falling edge) 10 50 ns
137 REJECT width low 1 CLK
138 C L KO1 low to SDACK asserted2—20ns
139 C L KO1 low to SDACK negated 2—20ns
1The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 2/1.
2SDACK is asserted whenever t he SDMA writes the incomi ng frame DA i nto memory.
Table 22. Et hernet Ti m i ng (c on t inu ed)
Num Characteristic All Frequencies Unit
Min Max
CLSN(CTS1)
120
(Input)
RCLK3
121
RxD3
(Input)
121
RENA(CD3)
(Input)
125
124 123
127
126
Last Bit
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 53
CPM Electrical Characterist ics
Figure 52. Ethernet Tran smi t Timing Diagram
Figure 53. CAM Interf ace Receive Start Timing Di agram
Figure 54. CAM Interface REJECT Ti m in g Diagram
TCLK3
128
TxD3
(Output)
128
TENA(RTS3)
(Input)
Notes:
Tra nsmit clock in vert (TCI) bit in GSMR i s set.
If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, the CSL bit is set in the
buffer descriptor at the end of the frame transmission.
1.
2.
RENA(CD3)
(Input)
133 134
132
131 121
129
(Note 2)
RCLK3
RxD3
(Input)
RSTRT
(Output)
0
136
125
1 1 BIT1 BIT2
Start Frame De-
REJECT
137
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
54 Freescale Semiconductor
CP M Electrical Characteristics
14.7 SPI Master AC Electrical Specifications
Table 23 provides the SPI master timings as shown in Figure 55 and Figure 56.
Figure 55. SPI Master (CP = 0) Timin g Diagram
Ta ble 23. S P I Master Tim ing
Num Characteristic All Frequencies Unit
Min Max
160 MASTER cycle time 4 1024 tcyc
161 MASTER c lock (SCK) high or low t ime 2 512 tcyc
162 MASTER data setup time (inputs) 15 ns
163 Master data hold t ime (inputs) 0 ns
164 Master data valid (after SCK edge) 10 ns
165 Master data hold t ime (outputs) 0 ns
166 Rise time output 15 ns
167 Fall time output 15 ns
SPIMOSI
(Output)
SPICLK
(CI = 0)
(Output)
SPICLK
(CI = 1)
(Output)
SPIMISO
(Input)
162
Data
166167161
161 160
msb lsb msb
msb Data lsb msb
167 166
163
166
167
165 164
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 55
CPM Electrical Characterist ics
Figure 56. SPI Master (CP = 1) Timin g Diagram
14.8 SPI Slave AC Electrical Specifications
Table 24 provides the SPI slave timings as shown in Figure 57 and Figure 58.
Ta ble 24. S P I Slave Timing
Num Characteristic All Frequencies Unit
Min Max
170 Slave cycle time 2 tcyc
171 Slave enable lead time 15 ns
172 Slave enable lag time 15 ns
173 Slave clock (SPICLK) high or low time 1 tcyc
174 Slave sequential transfer delay (does not require deselect) 1 tcyc
175 Slave data setup time (inputs) 20 ns
176 Slave data hold tim e (i nputs) 20 ns
177 S lave acce ss ti me 5 0 n s
SPIMOSI
(Output)
SPICLK
(CI=0)
(Output)
SPICLK
(CI=1)
(Output)
SPIMISO
(Input)
Data
166167161
161 160
msb lsb msb
msb Data lsb msb
167 166
163
166
167
165 164
162
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
56 Freescale Semiconductor
CP M Electrical Characteristics
Figure 57. SPI Sla ve (CP = 0) Timing Diagram
Figure 58. SPI Sla ve (CP = 1) Timing Diagram
SPIMOSI
(Input)
SPICLK
(CI = 0)
(Input)
SPICLK
(CI = 1)
(Input)
SPIMISO
(Output)
180
Data
181182173
173 170
msb lsb msb
181
177 182
175 179
SPISEL
(Input)
171172
174
Datamsb lsb msbUndef
181
178
176 182
SPIMOSI
(Input)
SPICLK
(CI = 0)
(Input)
SPICLK
(CI = 1)
(Input)
SPIMISO
(Output)
180
Data
181182
msb lsb
181
177 182
175 179
SPISEL
(Input)
174
Data
msb lsbUndef
178
176 182
msb
msb
172
173
173
171 170
181
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 57
FEC Electrical Characteristics
15 FEC Electrical Chara cteristics
This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the
timing specifications for the M II signals are independent of sys tem clock frequency (part speed
designation). Also, MII signals use TTL signa l levels compa tible with devices operating at either 5.0 V or
3.3 V.
15.1 MII Receive Signal Timing (MII_RXD[3:0], MII_RX_DV, MII_RX_ER,
MII_RX_CLK)
The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25MHz +1%. There is no
minimum frequency requirement. I n addi tion, the processor clock frequency must exceed th e
MII_RX_CLK frequency –1%.
Table 25 provid es information on the MII rec eiv e signal timing.
Figure 59 shows MII re ceive signal timing.
Figure 59. M II Receive S ignal Timing Diagram
15.2 MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN,
MII_TX_ER, MII_TX_CLK)
The transmitter functions correc tly up to a MII_TX_C LK maximum frequenc y of 25 MHz + 1%. There is
no minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_TX_CLK frequency – 1% .
Table 25. MII Receive Signal Timing
Num Characteristic Min Max Unit
M1 MII_RXD[3:0], MII _RX_DV, MII_RX_ER to MII_RX_CLK setup 5 ns
M2 MII_RX_CLK to MII_RXD[3:0], M II_RX_DV, MII_R X_ER hol d 5 ns
M3 MII_RX_CLK pul se width high 35% 65% MII _RX_CLK peri od
M4 MII_RX_CLK pul se width low 35% 65% MII_RX_CLK period
M1 M2
MII_RX_CLK (Input)
MII_RXD[3:0] (Inputs)
MII_RX_DV
MII_RX_ER
M3
M4
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
58 Freescale Semiconductor
FEC Electrical Characteristics
Table 26 provides information about the MII transmit signal timing,.
Figure 60 shows the M II trans mit signal timing diagra m.
Figure 60. MII Transmit Sig nal T iming Diagra m
15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)
Table 27 provides information about the MII async inputs signal timing.
Figure 61 shows the MII as ynchronous inputs signal timing diagram.
Figure 61. MII Async Inputs Timi ng Diagram
Table 26. MII Tran smi t Signal Tim ing
Num Characteristic Min Max Unit
M5 MII_TX_CLK to MII_T XD[3: 0], MII_TX_EN, MII_TX_ER in valid 5 ns
M6 MII_TX_CLK t o MII_T XD[3: 0], MII_TX_EN, MII_TX_ER valid 25
M7 MII_TX_CLK pulse width high 35% 65% MII_TX_CLK period
M8 MII_TX_CLK pulse width lo w 35% 65% MII_TX_CLK period
Table 27. MII Async Inputs Signal Timing
Num Characteristic Min Max Unit
M9 MII_CRS, MII_COL minimum pulse width 1.5 M II _TX_CLK peri od
MII_TX_CLK (Input)
MII_TXD[3:0] (Outputs)
MII_TX_EN
MII_TX_ER
M5
M7
M8
M6
MI I_ C R S, MI I_ C OL
M9
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 59
FEC Electrical Characteristics
15 .4 MII Serial Management Channe l Timi ng (MII_MDIO, MII_MDC)
Table 28 provides information on the MII serial management channel signal timing. The FEC functions
correctly with a maximum MDC frequency in excess of 2.5 MHz. T he exact upper bound is under
investigation.
Figure 62 shows the MII serial mana gem ent channel timing diagram.
Figure 62. MII Serial Management Channel Timing Diagram
Table 28. MII Se ri al M ana g e m ent Channe l Ti m in g
Num Characteristic Min Max Unit
M10 MII_MDC falling edge to MII_MDIO output invalid (minimum propagation
delay) 0— ns
M11 MII_MDC falling edge to MII_MDIO output valid (max prop delay) 25 ns
M12 MII_M DIO (i nput) to MII_MDC rising edge setup 10 ns
M13 MII_M DIO (i nput) to MII_MDC rising edge hold 0 ns
M14 MII_MDC pulse width high 40% 60% MII_MDC peri od
M15 MII_MDC pulse width low 40% 60% MII_MDC period
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
60 Freescale Semiconductor
Mec han ic al Data and Ord eri ng Informa tion
16 Mechanical Data and Ordering Information
Table 29 identifies the packages and oper a ting frequencies orderable for the MPC852T.
16 .1 Pin Assignmen t s
The following sec tions give the pinout and pin lis ting for the JED EC compliant and the non-JEDEC
versions of the 16 × 16 PB GA package.
Tabl e 29. MPC852T P ackage/Frequency Orderable
P ackage Type T em p erature (Tj) Frequency ( M Hz) Order Number
Plas tic ba l l grid array
(VR and ZT suffix) 0°C to 95°C 50 MPC852TVR50A
MPC852TZT50A
66 MPC852TVR66A
MPC852TZT66A
80 MPC852TVR80A
MPC852TZT80A
100 MPC852TVR100A
MPC852TZT100A
Plas tic ba l l grid array
(CVR and CZTsuff ix ) –40°C to 100°C 50 MPC852TCVR50A
MPC852TCZT50A
66 MPC852TCVR66A
MPC852TCZT66A
80 MPC852TCVR80A
MPC852TCZT80A
100 MPC852TCVR100A
MPC852TCZT100A
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 61
Mec han ic al Data and Or deri ng Info r ma tion
16.1.1 JEDEC Compliant Pinout
Figure 63 s hows the JEDEC pinout of the PBGA package as viewed from the t op surface. For additional
information, see the MPC866 PowerQUICC™ Family Reference M anual.
NOTE: This is the top view of the device.
Figure 63 . Pi nout of PBGA Package —JE DE C Stan dard
N/C
WR
VDDL
BDIP
BR
CR
ALE_A
KR
OP0
OP3
EXTAL
N/C
CS7 GPL_A2 WE2 BS_A0 VDDL A28 A18 A23 A19 A14 A7 A2 A1 N/C
CS0 CE2_A GPL_A3 WE3
GPL_A0
GPL_A4 CS3 CS5 WE1 BS_A2 A26 A25 A21 A17 A12 A8 A3 N/C
BI CS2 OE
MII_CRSBS_A3 A22 A30
WE0 BS_A1 A24
TS TEA
A29A27A13A9A6A0N/C
A20A15A10A4N/CPB29VDDL
A
B
C
D
E
MII_COL BB
VFLS_1 RSV BURST
DSCK VFLS_0
AS BADDR30
OP1 OP2
BADDR29 BADDR28
VDDL
XTAL EXTCLK WAIT_A
PORST VDDSYN VSSSYN1
PC12 PA11
TMS TRST
VDDL MDIO
PA10 PB24
G
H
J
F
PA8 PA9
PC6 PA3
PA1 PB15
VDDL PA0
PD12 PD14
N/C PD11
GND
K
L
VDDH
M
N
VDDL IP_A7 IP_A2 PD10 N/CD31
IP_A0 IP_A4 DP2
D6 D19 D5 D2 D27 D13 D0 PD5
PD7 N/C
D28
D7 D22 VDDL D18 D3 D1 D4 D8 MII_TXEN
P
R
T
D30
1234567 891011
12 13 14 15 16
GPL_A5
TA
BG
HRESET
RSTCONF
VDDL
N/C
VSSSYN
DP0
DP3
IP_A5 D25 D21 D15 D10 D17 IRQ7 PD6 PD9CLKOUT
D29 D24 D20 D16 D11 D12 IRQ0 PD4DP1
PB31 PC13
PB30 TDO
PB28 TDI
TCK PB25
PC5 PC7
PD13 PA2
N/C PC4
PD8 PD15
A31CS6
PC15
D23
SRESET
FRZ
CE_1A CS4 TSIZ1 A16 A11 A5 N/CTSIZ0
IP_A3 IP_A6 D26 D14 D9 IRQ1 PD3IP_A1
CS1
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
62 Freescale Semiconductor
Mec han ic al Data and Ord eri ng Informa tion
Table 30 contains a lis t of the MPC852T i nput and output s ignals and shows multiplexing and pin
assignments.
Table 30. Pin Assignmen ts— JED EC Stand ard
Name Pin Number Type
A[0:31 ] B15, A15 , A14, C14, D13, E11, B14, A1 3, C13, B13, D1 2, E10, C12 ,
B12, A12, D11, E9, C11, A9 , A11, D10, C10, B8, A10, D9, C9, C8,
B11, A8, B10, B9, D8
Bidirectional
Three-state (3.3 V only)
TSIZ0, REG E8 Bidirectional
Three-state (3.3 V only)
TSIZ1 E7 Bidirectional
Three-state (3.3 V only)
RD/WR B1 Bidirectional
Three-state (3.3 V only)
BURST G3 Bidirectional
Three-state (3.3 V only)
BDIP, G P L _B5 D1 Output
TS E2 Bidirectional
Active Pul l-up (3.3 V only)
TA F4 Bidirectional
Active Pul l-up (3.3 V only)
TEA E3 Open-drain
BI D2 Bidirectional
Active Pul l-up (3.3 V only)
IRQ2
RSV G2 Bidirectional
Three-state (3.3 V only)
IRQ4, KR, RET RY,
SPKROUT J1 Bidirectional
Three-state (3.3 V only)
CR, IRQ3 F1 Input (3.3 V only)
D[0:31] R13, T11, R10, T10, T12, R9, R7, T6, T13, M10, N10, P1 0, P12,
R12, M9, N9, P9, N11, T9, R8, P8, N8, T7, P11, P7, N7, M8, R11,
R6, P6, T5, R5
Bidirectional
Three-state (3.3 V only)
DP0, IRQ3 P4 Bidirectional
Three-state (3.3 V only)
DP1, IRQ4 P5 Bidirectional
Three-state (3.3 V only)
DP2, IRQ5 T4 Bidirectional
Three-state (3.3 V only)
DP3, IRQ6 R4 Bidirectional
Three-state (3.3 V only)
BR E1 Bidirectional (3.3 V onl y)
BG G4 Bidirectional (3.3 V only)
BB F3 Bidirectional
Active pull-up (3.3 V only)
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 63
Mec han ic al Data and Or deri ng Info r ma tion
FRZ
IRQ6 H4 Bidirectional (3.3 V only)
IRQ0 P13 Input (3.3 V only)
IRQ1 M11 Input (3.3 V only)
M_TX_CLK
IRQ7 N12 Input (3.3 V only)
CS[0 :5 ] B2, A2 , D3, C 3 , E 6 , C4 Output
CS6 D4 Output
CS7 A3 Output
WE0
BS_B0
IORD
D6 Output
WE1
BS_B1
IOWR
C6 Output
WE2
BS_B2
PCOE
A5 Output
WE3
BS_B3
PCWE
B5 Output
BS_A[0:3] A6, D7, C7, B7 Output
GPL_A0
GPL_B0 C5 Output
OE
GPL_A1
GPL_B1
D5 Output
GPL_A[2:3]
GPL_B[2:3]
CS[2–3]
A4, B4 Output
UPWAITA
GPL_A4 C2 Bidirectional (3.3 V onl y)
GPL_A5 E4 Output
PORESET P1 Input (3.3 V only)
RSTCONF K4 Input (3.3 V only)
HRESET J4 Open-drain
SRESET M3 Open-drain
XTAL N1 Analog Output
Table 30. Pi n Assi gnments—JEDE C Standard (continu ed)
Name Pin Number Type
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
64 Freescale Semiconductor
Mec han ic al Data and Ord eri ng Informa tion
EXTAL M1 Analog Input (1.8 V only)
CLKOUT N6 Output
EXTCLK N2 Input (1.8 V only)
ALE_A H1 Output
CE1_A E5 Output
CE2_A B3 Output
WAIT_A N3 Input (3.3 V only)
IP_A0 T2 Input (3.3 V only)
IP_A1 M6 Input (3.3 V only)
IP_A2, I O IS16_A R3 Input (3.3 V only)
IP_A3 M5 Input (3.3 V only)
IP_A4 T3 Input (3.3 V only)
IP_A5 N5 I nput (3.3 V only)
IP_A6 M7 Input (3.3 V only)
IP_A7 R2 I nput (3.3 V only)
DSCK H2 Bidirectional
Three-state (3.3 V only)
IWP[0:1], VFLS[0: 1] H3, G1 Bidirectional (3.3 V only)
OP0 K1 Bidirectional (3.3 V only)
OP1 K2 Output
OP2, MODCK1, STS K3 Bidirectional (3.3 V only)
OP3, MODCK2, DSDO L1 Bidirectional (3.3 V only)
BADDR[28:29] L3, L2 Output
BADDR30, REG J3 Output
AS J2 Input (3.3 V only)
PA11, RXD3 E16 Bidirectional
(Opti onal: Open-drain)
(5 -V toleran t)
PA10, TXD3 H15 Bidirect ional
(Opti onal: Open-drain)
(5 -V toleran t)
PA9, RXD4 J16 Bidirectional
(Opti onal: Open-drain)
(5 -V toleran t)
PA8, TXD4 J15 Bidir ectional
(Opti onal: Open-drain)
(5 -V toleran t)
Table 30. Pi n Assi gnments—JEDE C Standard (continu ed)
Name Pin Number Type
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 65
Mec han ic al Data and Or deri ng Info r ma tion
PA3, CLK5, BRGO3, TIN3 K16 Bidirectional
(5 -V toleran t)
PA2, CLK6, TOUT3 K14 Bidirectional
(5 -V toleran t)
PA1, CLK7, BRGO4, TIN4 L15 Bidirectional
(5 -V toleran t)
PA0, CLK8, TOUT4 M16 Bidirectional
(5 -V toleran t)
PB31, SPISEL E13 Bidirectional
(Opti onal: Open-drain)
(5 -V toleran t)
PB30, SPICLK F13 Bidirectional
(Opti onal: Open-drain)
(5 -V toleran t)
PB29, SPIMOSI D15 Bidi rectional
(Opti onal: Open-drain)
(5 -V toleran t)
PB28, SPIMISO, BRGO4 G13 Bidirectional
(Opti onal: Open-drain)
(5 -V toleran t)
PB25, SM TXD1 H14 Bidirectional
(Opti onal: Open-drain)
(5 -V toleran t)
PB24, SM RXD1 H16 Bidirectional
(Opti onal: Open-drain)
(5 -V toleran t)
PB15, BR GO3 L16 Bidirectional
(5 -V toleran t)
PC15, DREQ0 C16 Bidirectional
(5 -V toleran t)
PC13, RTS3 E14 Bidirectional
(5 -V toleran t)
PC12, RTS4 E15 Bidirectional
(5 -V toleran t)
PC7, CTS3 J14 Bidirectional
(5 -V toleran t)
PC6, CD3 K15 Bidirectional
(5 -V toleran t)
PC5, CTS4, SDACK1 J13 Bidirectional
(5 -V toleran t)
Table 30. Pi n Assi gnments—JEDE C Standard (continu ed)
Name Pin Number Type
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
66 Freescale Semiconductor
Mec han ic al Data and Ord eri ng Informa tion
PC4, CD4 L14 Bidirectional
(5 -V toleran t)
PD15, MII_RXD3 M14 Bidi rectional
(5 -V toleran t)
PD14, MII_RXD2 N16 Bidirectional
(5 -V toleran t)
PD13, MII_RXD1 K13 Bidirectional
(5 -V toleran t)
PD12, MII_MDC N15 Bidirectional
(5 -V toleran t)
PD11, RXD3, MII_TX_ER P16 Bidirectional
(5 -V toleran t)
PD10, TXD3, MII_RXD0 R15 Bidirectional
(5 -V toleran t)
PD9, RXD4, M II_TXD0 N14 Bidirectional
(5 -V toleran t)
PD8, TXD4, MII_RX_CLK M13 Bidirectional
(5 -V toleran t)
PD7, RTS3, MII_RX_ER T15 Bidirect ional
(5 -V toleran t)
PD6, RTS4, MII_RX_DV N13 Bidirect ional
(5 -V toleran t)
PD5, MII_TXD3 R14 Bidirectional
(5 -V toleran t)
PD4, MII_TXD2 P14 Bidirectional
(5 -V toleran t)
PD3, MII_TXD1 M12 Bidi rectional
(5 -V toleran t)
TMS F15 Input
(5 -V toleran t)
TDI, DSDI G14 Input
(5 -V toleran t)
TCK, DSCK H13 I nput
(5 -V toleran t)
TRST F16 Input
(5 -V toleran t)
TDO, DSDO F1 4 Ou tp ut
(5 -V toleran t)
MII_CRS B6 Input
Table 30. Pi n Assi gnments—JEDE C Standard (continu ed)
Name Pin Number Type
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 67
Mec han ic al Data and Or deri ng Info r ma tion
MII_MDIO G16 Bidirectional
(5 -V toleran t)
MII_TXEN T14 Output
(5 -V toleran t)
MII_COL F2 Input
VSSSYN N4 PLL analog GND
VSSSYN1 P3 PLL analog GND
VDDSYN P2 PLL analog VDD
GND G6, G7, G8, G9, G10, G11, H6, H7, H8, H9, H10, H11, J6, J7, J8, J9,
J10, J11, K6, K7, K8, K9, K10, K11 Power
VDDL A7, C1 , D1 6 , G15 , L4 , M2, R 1 , M 1 5, T8 Power
VDDH F5, F 6, F7 , F 8, F9, F 10 , F1 1 , F12 , G 5 , G 1 2, H5, H 1 2 , J5, J1 2 ,
K5, K12, L5, L6, L7, L8, L9, L10, L11, L12 Power
N/C A1, A16, B16, C15, D14, E12, L13, M4 , P15, R16, T1, T16 No conne ct
Table 30. Pi n Assi gnments—JEDE C Standard (continu ed)
Name Pin Number Type
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
68 Freescale Semiconductor
Mec han ic al Data and Ord eri ng Informa tion
16 .1.2 Th e no n -JE D EC Pi no ut
Figure 64 shows the non-JEDEC pinout of the PBGA package as viewed from the top surface. For
additional infor mation, see the PowerQUICC™ Family Reference Manual.
NOTE: Thi s figure shows the top vi ew of the device.
Figure 64. Pinout of PBGA Package—No n-JE DEC
N/C
WR
VDDL
BDIP
BR
CR
ALE_A
KR
OP0
OP3
EXTAL
N/C
CS7 GPL_A2 WE2 BS_A0 VDDL A28 A18 A23 A19 A14 A7 A2 A1 N/C
CS0 CE2_A GPL_A3 WE3
GPL_A0
GPL_A4 CS3 CS5 WE1 BS_A2 A26 A25 A21 A17 A12 A8 A3 N/C
BI CS2 OE
MII_CRSBS_A3 A22 A30
WE0 BS_A1 A24
TS TEA
A29A27A13A9A6A0N/C
A20A15A10A4N/CPB29V
DDL
B
C
D
E
MII_COL BB
VFLS_1 RSV BURST
DSCK VFLS_0
AS BADDR30
OP1 OP2
BADDR29 BADDR28
VDDL
XTAL EXTCLK WAIT_A
PORST VDDSYN VSSSYN1
PC12 PA11
TMS TRST
VDDL MDIO
PA10 PB24
G
H
J
F
PA8 PA9
PC6 PA3
PA1 PB15
VDDL PA0
PD12 PD14
N/C PD11
GND
K
L
VDDH
M
N
VDDL IP_A7 IP_A2 PD10 N/CD31
IP_A0 IP_A4 DP2
D6 D19 D5 D2 D27 D13 D0 PD5
PD7 N/C
D28
D7 D22 VDDL D18D3D1D4D8MII_TXEN
P
R
T
D30
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
GPL_A5
TA
BG
HRESET
RSTCONF
VDDL
N/C
VSSSYN
DP0
DP3
IP_A5 D25 D21 D15 D10 D17 IRQ7 PD6 PD9CLKOUT
D29 D24 D20 D16 D11 D12 IRQ0 PD4DP1
PB31 PC13
PB30 TDO
PB28 TDI
TCK PB25
PC5 PC7
PD13 PA2
N/C PC4
PD8 PD15
A31CS6
PC15
D23
SRESET
FRZ
CE_1A CS4 TSIZ1 A16 A11 A5 N/CTSIZ0
IP_A3 IP_A6 D26 D14 D9 IRQ1 PD3IP_A1
CS1
U
17
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 69
Mec han ic al Data and Or deri ng Info r ma tion
Table 31 contains a lis t of the MPC852T i nput and output s ignals and shows multiplexing and pin
assignments.
Table 31. Pin Assignments—Non-JEDEC
Name Pin Number Type
A[0:31] C16, B16, B15, D15, E14, F12, C15, B14, D14, C14 , E13, F11, D13,
C13, B13, E12, F10, D12, B10, B12, E11, D11, C9, B11, E10, D10,
D9, C12, B9, C11, C10, E9
Bidirectional
Three-state (3.3 V only)
TSIZ0, REG F9 Bidirectional
Three-state (3.3 V only)
TSIZ1 F8 Bidirectional
Three-state (3.3 V only)
RD/WR C2 Bidirectional
Three-state (3.3 V only)
BURST H4 Bidirectional
Three-state (3.3 V only)
BDIP, GPL_B5 E2 Output
TS F3 Bidirectional
Active pul l-up (3.3 V only)
TA G5 Bidirectional
Active pul l-up (3.3 V only)
TEA F4 Open-drain
BI E3 Bidirectional
Active pul l-up (3.3 V only)
IRQ2, RS V H3 Bidirectional
Three-state (3.3 V only)
IRQ4, K R
RETRY, SPKROUT K2 Bidirectional
Three-state (3.3 V only)
CR, IRQ3 G2 Input (3 .3 V o n ly)
D[0:31] T14, U12, T11, U11, U13, T10, T8, U7, U14, N11, P11, R11, R13,
T13, N10, P10, R10, P12, U10, T9, R9, P9, U8, R12, R8, P8, N9,
T12, T7, R7, U6, T6
Bidirectional
Three-state (3.3 V only)
DP0, IRQ3 R5 Bidirectional
Three-state (3.3 V only)
DP1, IRQ4 R6 Bidirectional
Three-state (3.3 V only)
DP2, IRQ5 U5 Bidirectional
Three-state (3.3 V only)
DP3, IRQ6 T5 Bidirectional
Three-state (3.3 V only)
BR F2 Bidi rectional (3.3 V only)
BG H5 Bidirectional (3.3 V only)
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
70 Freescale Semiconductor
Mec han ic al Data and Ord eri ng Informa tion
BB G4 Bidirectional
Active Pull-up (3.3 V only)
FRZ, IRQ6 J5 Bidirectional (3.3 V only)
IRQ0 R14 Input (3.3 V only)
IRQ1 N12 Input (3.3 V only)
IRQ7, M_TX_CLK P13 Input (3.3 V only)
CS[0:5] C3, B3, E4, D4, F7, D5 Output
CS6 E5 Output
CS7 B4 Output
WE0, BS_B0, IORD E7 Output
WE1, BS_B1, IOWR D7 Output
WE2, BS_B2, PCOE B6 Output
WE3, BS_B3, PCWE C6 Output
BS_A[0:3] B7, E8, D8, C8 Output
GPL_A0, GPL _B 0 D6 Output
OE, GPL_A1, GPL _B1 E6 Output
GPL_A[2:3], GPL_B[2:3],
CS[2–3] B5, C5 Output
UPWAITA, GPL_A4 D3 Bidirectional (3.3 V only)
GPL_A5 F5 Output
PORESET R2 In put (3.3 V only)
RSTCONF L5 Inpu t (3.3 V o n ly)
HRESET K5 Open-drain
SRESET N4 Open-drain
XTAL P2 Analog output
EXTAL N2 Analog in put (3.3 V onl y)
CLKOUT P7 Output
EXTCLK P3 Input (3.3 V onl y)
ALE_A J2 Output
CE1_A F6 Output
CE2_A C4 Output
WAIT_A P4 Inpu t (3.3 V o n ly)
IP_A0 U3 Inp ut ( 3.3 V onl y)
Ta ble 31. Pin Assignments— Non-JE DEC (continued)
Name Pin Number Type
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 71
Mec han ic al Data and Or deri ng Info r ma tion
IP_A1 N7 Inp ut ( 3.3 V onl y)
IP_A2, IOI S 16_A T4 Input (3.3 V only)
IP_A3 N6 Inp ut ( 3.3 V onl y)
IP_A4 U4 Inp ut ( 3.3 V onl y)
IP_A5 P6 Input (3.3 V only)
IP_A6 N8 Inp ut ( 3.3 V onl y)
IP_A7 T3 Input (3.3 V only)
DSCK J3 Bidirectional
Three-state (3.3 V only)
IWP[0:1] , VFLS[0 :1] J4, H2 Bidi rectional (3.3 V only)
OP0 L2 Bidi rectional (3.3 V only)
OP1 L3 Output
OP2, MODCK1, STS L4 Bi directional (3.3 V only)
OP3, MODCK2, DSDO M2 Bidirectional (3.3 V only)
BADDR[28:29] M4, M3 Output
BADDR30, REG K4 Output
AS K3 Input (3 .3 V o n ly)
PA11, RXD3 F17 Bidirectional
(Opti onal: Open-drain)
(5-V tolerant)
PA10, TXD3 J16 Bidirectional
(Opti onal: Open-drain)
(5-V tolerant)
PA9, RXD4 K17 Bidirectional
(Opti onal: Open-drain)
(5-V tolerant)
PA8, TXD4 K16 Bidirectional
(Opti onal: Open-drain)
(5-V tolerant)
PA3, CLK5, BRGO3, TIN3 L17 Bi directional
(5-V tolerant)
PA2, CLK6, TOUT3 L15 Bidirectional
(5-V tolerant)
PA1, CLK7, BRGO4, TIN4 M16 Bidirectional
(5-V tolerant)
PA0, CLK8, TOUT4 N17 Bidirectional
(5-V tolerant)
Ta ble 31. Pin Assignments— Non-JE DEC (continued)
Name Pin Number Type
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
72 Freescale Semiconductor
Mec han ic al Data and Ord eri ng Informa tion
PB31, SPISEL F14 Bidirectional
(Opti onal: Open-drain)
(5-V tolerant)
PB30, SPICLK G14 Bidirectional
(Opti onal: Open-drain)
(5-V tolerant)
PB29, SPIMOSI E16 Bidirectional
(Opti onal: Open-drain)
(5-V tolerant)
PB28, SPIMISO, BRGO4 H14 Bidirectional
(Opti onal: Open-drain)
(5-V tolerant)
PB25, SMTXD1 J15 Bi directional
(Opti onal: Open-drain)
(5-V tolerant)
PB24, SMRXD1 J17 Bidirectional
(Opti onal: Open-drain)
(5-V tolerant)
PB15, BRGO3 M17 Bidirectional
(5-V tolerant)
PC15, DREQ0 D17 Bidirectional
(5-V tolerant)
PC13, RTS3 F15 Bidirectional
(5-V tolerant)
PC12, RTS4 F16 Bidirectional
(5-V tolerant)
PC7, CTS3 K15 Bidirectional
(5-V tolerant)
PC6, CD3 L16 Bidirectional
(5-V tolerant)
PC5, CTS4, SDACK1 K14 Bidirectional
(5-V tolerant)
PC4, CD4 M15 Bidirectional
(5-V tolerant)
PD15, MII_RXD3 N15 Bidirectional
(5-V tolerant)
PD14, MII_RXD2 P17 Bidirectional
(5-V tolerant)
PD13, MII_RXD1 L14 Bi directional
(5-V tolerant)
Ta ble 31. Pin Assignments— Non-JE DEC (continued)
Name Pin Number Type
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 73
Mec han ic al Data and Or deri ng Info r ma tion
PD12, MII_MDC P16 Bidirectional
(5-V tolerant)
PD11, RXD3, M II_TX_ER R17 Bidirectional
(5-V tolerant)
PD10, TXD3, MII_RXD0 T16 Bidi rectional
(5-V tolerant)
PD9, RXD4, MII_TXD0 P15 Bidirect ional
(5-V tolerant)
PD8, TXD4, MI I_RX_CLK N14 Bidirectional
(5-V tolerant)
PD7, RTS3, MII_RX_ER U16 Bidirectional
(5-V tolerant)
PD6, RTS4, MI I_RX_DV P14 Bidir ectional
(5-V tolerant)
PD5, MII_TXD3 T15 Bidirecti onal
(5-V tolerant)
PD4, MII_TXD2 R15 Bidirect ional
(5-V tolerant)
PD3, MII_TXD1 N13 Bidirect ional
(5-V tolerant)
TMS G16 Input
(5-V tolerant)
TDI, DSDI H15 Input
(5-V tolerant)
TCK, DSCK J14 Input
(5-V tolerant)
TRST G17 Input
(5-V tolerant)
TDO, DSDO G15 Out put
(5-V tolerant)
MII_CRS C7 Input
MII_MDIO H17 Bidirectional
(5-V tolerant)
MII_TX_EN U15 Output
(5-V tolerant)
MII_COL G3 Input
VSSSYN P5 PLL analog GND
Ta ble 31. Pin Assignments— Non-JE DEC (continued)
Name Pin Number Type
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
74 Freescale Semiconductor
Mec han ic al Data and Ord eri ng Informa tion
VSSSYN1 R4 PLL analog GND
VDDSYN R3 PLL anal og VDD
GND H7, H8, H9, H10, H11, H12, J7, J8, J9, J10, J11, J12, K7, K8, K9,
K10, K11, K12, L7, L8, L9, L10, L11, L12 Power
VDDL B8, D2 , E 17 , H16 , M 5 , N3, T2, N16 , U9 Po wer
VDDH G 6, G7, G8, G9, G1 0, G11, G12, G13, H6, H13, J6, J13, K6, K13,
L6, L13, M6, M7, M8, M9, M 10, M11, M12, M 13 Power
N/C B2, B17, C17, D16, E15, F13, M14, N5, R16, T17, U2, U17 No connect
Ta ble 31. Pin Assignments— Non-JE DEC (continued)
Name Pin Number Type
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 75
Mec han ic al Data and Or deri ng Info r ma tion
16.2 Mechanical Dimensions of the PBGA Package
For more information on the printed- circuit board layout of the PBGA package, including thermal via
design and s uggeste d pad layout, ref er to Pl astic Ball Grid Array Application Note ( order number:
AN1231) that is available from your local Freescale sales office. Figure 65 shows the mechanical
dimensions of the PBGA package.
Figure 65. Mech anical Dimen sions and Bottom Surface Nomenclature of the PBGA Package
Note: Solder sphere composition is 95.5%Sn 45%Ag 0.5%Cu for MPC852TVR XXX.
Solder sphere composition is 62%Sn 36%Pb 2%Ag for MPC852TZTXXX.
1. All dimensions a re in millimeters.
2. Interpret dimensions and tole rances per ASME Y14.5M—1 994.
3. Maximum solder ball diameter measured parallel to datum A.
4. Datum A, the seating plane, is defined by the spherical crowns of the solder balls.
Notes:
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
76 Freescale Semiconductor
Docume nt Revision Hist ory
17 Document Revision History
Table 32 lists significant changes between revisions of this document.
Table 32. Documen t Revision History
Revision Date Changes
4 Updated template.
On page 1, updated f irst paragraph and added a sec ond paragr aph.
After Table 2, inserted a new fi gure showing the undershoot/overshoot vol tage (Figure 2) and
renumbered the rest of the figures.
•In Table 9, f or reset timings B29f and B29g added footnote indicating that the formula only appli es
to bus operati on up to 50 MHz.
•In Figure 4, changed all reference v oltage measure me nt poi nts from 0.2 and 0.8 V to 50% leve l.
•In Table 17, changed num 46 description to read, TA assertion to rising edge ...
•In Figure 42, ch anged TA to ref lect the risin g edge of the c lock.
3.1 1/18/2005 Document template update.
3.0 11/2004 Added sen tence to Spec B1A about EXTCLK and CLKOUT being in Alignment for I nteger Values
Added a footnote to Spec 41 specifying th at EDM = 1
Broke the Section 1 6.1, “ Pin Assi gnment s,” into 2 smal ler s ectio ns f or the J EDEC and no n-JEDEC
pinouts.
2.0 12/2003 Put 852T on the 1st page in place of 8245.
Figure 62 on page 59 had over bars added on signals CR (pi n G2) and WAIT_A (pin P4).
1.8 7/2003 Change d the pi nout t o be JEDEC Com pli ant, changed timi ng parameter s B28a through B28d, and
B29d to show that TRLX can be 0 or 1.
1.7 5/2003 Changed the SPI Master Timing Specs. 162 and 164
1.6 4/2003 Change d the package dr awing in Figure 15-63
1.5 4/2003 Change d 5 Port C pins with interrupt capability to 7 Port C pins. Added the Note: solder sphere
compos it ion for MPC85 2TVR and MPC8 52TCVR devices is 95.5%Sn 45%Ag 0.5%Cu to Figur e
15-63
1.4 2/2003 Change d Table 15-30 Pin Assignments for the PLL Pins VSSSYN1, VSSSYN, VDDSYN
1.3 1/20 03 Added sub scripts to t iming diagr a ms f or B1- B35, t o sp ecify memory co ntrol ler setti ngs f or the sp ecifi c
edges.
1.2 1/2003 In Table 15-30, specified EXTCLK as 3.3 V.
1.1 12/2002 Added fast Ethernet controller to the features
1 11/2002 Added values for 80 and 100 M Hz
0 10/2002 Initia l re lease
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 77
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
78 Freescale Semiconductor
Docume nt Revision Hist ory
THIS PAGE INTENTIONALLY LEFT BLANK
MPC852T PowerQUICC™ Hardware Specifications, Re v. 4
Freescale Semiconductor 79
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
Document Number: MPC852TEC
Rev. 4
09/2007
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
F reescal e Semiconductor r eserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any parti cular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be
provided in Freescale Semiconductor data sheets and/or specifications can and do
vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other appl ication i n which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death ma y occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized applic ation, Buyer shall indemni fy and hold Freescale Semiconduc tor
and its officers , employees , subsidiaries, affiliates, and distributors harmless agains t all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regardi ng the design or manufacture of the part.
How to Reach Us:
Home Pag e:
www.freescale.com
Web Support:
http://www.freescale.com/support
USA/Europe or Loca ti ons Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
+1- 80 0-521- 6 27 4 or
+1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:
Freescale Halbleiter Deut schland GmbH
Tech ni ca l Inf or m atio n Center
Schatzbogen 7
81829 Mu en c he n, G erm any
+44 1296 380 45 6 (E ng li sh )
+46 8 52200080 (English)
+49 89 9210 3 55 9 (G erman )
+33 1 69 35 48 48 (French)
www.freescale.com/support
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku
Tokyo 153-0064
Japan
0120 191014 or
+81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Tech ni ca l Inf or m atio n Center
2 Dai Kin g Stre et
Tai Po Industrial Estate
Tai P o, N.T., Hong Kong
+800 2666 8080
support.asia@freescale.com
For Lite rat ur e Req ues ts Only:
Freescale Semiconductor
Lit e rature Dis t r ibutio n Cen t er
P.O. Box 5405
Denver, Colorado 80217
+1-800 441-2447 or
+1-303-675-2140
Fax: +1-303-675-2150
LDCForFreescaleSemiconductor
@hibbertgroup.com
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
The Pow er Architectur e and P ower.org word marks and the P ower and P ower.org logos
and related marks are trademarks and service marks licensed by Power.org. The
described product contains a PowerPC processor core. The PowerPC name is a
trademark of IBM Corp. and used under license. IEEE 1149.1 and 802.3 are
trademarks or registered trademarks of the Institute of Electrical and Electronics
Engineer s, Inc. (IEEE). This pr oduct is not endors ed or appr oved b y the IEEE. All other
product or servi ce names are the property of their respective owners.
© Freescale Se miconductor, Inc., 200 4, 2007. All rights reserv ed.