a Precision Low Noise, Low Input Bias Current Operational Amplifiers OP1177/OP2177/OP4177 FEATURES Low Offset Voltage: 60 V Max Very Low Offset Voltage Drift: 0.7 V/C Max Low Input Bias Current: 2 nA Max Low Noise: 8 nV/Hz CMRR, PSRR, and AVO > 120 dB Min Low Supply Current: 400 A/Amp Dual Supply Operation: 2.5 V to 15 V Unity Gain Stable No Phase Reversal Inputs Internally Protected Beyond Supply Voltage APPLICATIONS Wireless Base Station Control Circuits Optical Network Control Circuits Instrumentation Sensors and Controls Thermocouples RTDs Strain Bridges Shunt Current Measurements Precision Filters GENERAL DESCRIPTION The OPx177 family consists of very high precision, single, dual, and quad amplifiers featuring extremely low offset voltage and drift, low input bias current, low noise, and low power consumption. Outputs are stable with capacitive loads of over 1,000 pF with no external compensation. Supply current is less than 500 A per amplifier at 30 V. Internal 500 series resistors protect the inputs, allowing input signal levels several volts beyond either supply without phase reversal. Unlike previous high voltage amplifiers with very low offset voltages, the OP1177 and OP2177 are available in the tiny MSOP 8-lead surface-mount package, while the OP4177 is available in TSSOP-14. Moreover, specified performance in the MSOP/ TSSOP packages is identical to performance in the SOIC package. OPx177 family offers the widest specified temperature range of any high precision amplifier in surface-mount packaging. All versions are fully specified for operation from -40C to +125C for the most demanding operating environments. Applications for these amplifiers include precision diode power measurement, voltage and current level setting, and level detection in optical and wireless transmission systems. Additional applications include line powered and portable instrumentation PIN CONFIGURATIONS 8-Lead MSOP (RM-Suffix) 1 NC IN IN V 8 NC V+ OUT NC OP1177 4 8-Lead SOIC (R-Suffix) 5 NC 1 8 NC IN 2 +IN 3 NC = NO CONNECT 7 V+ OP1177 6 OUT 5 NC V 4 NC = NO CONNECT 8-Lead SOIC (R-Suffix) 8-Lead MSOP (RM-Suffix) 1 OUT A IN A IN A V 8 OP2177 4 5 V+ OUT B -IN B +IN B OUT A 8 V+ 1 IN A 2 7 OUT B OP2177 6 IN B +IN A 3 5 +IN B V 4 14-Lead SOIC (R-Suffix) 14-Lead TSSOP (RU-Suffix) OUT A 1 14 OUT D IN A 2 13 IN D +IN A 3 12 +IN D V+ 4 +IN B 5 OP4177 OP4177 11 V OUT A -IN A +IN A V+ +IN B -IN B OUT B 1 14 OP4177 7 8 OUT D -IN D +IN D V- +IN C -IN C OUT C 10 +IN C IN B 6 9 IN C OUT B 7 8 OUT C and controls--thermocouple, RTD, strain-bridge, and other sensor signal conditioning--and precision filters. The OP1177 (single) and the OP2177 (dual) amplifiers are available in the 8-lead MSOP and 8-lead SOIC packages. The OP4177 (quad) is available in 14-lead narrow SOIC and 14-lead TSSOP packages. MSOP and TSSOP packages are available in tape and reel only. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2004 Analog Devices, Inc. All rights reserved. (@ VS = 5.0 V, VCM = 0 V, TA = 25C, unless OP1177/OP2177/OP4177-SPECIFICATIONS otherwise noted.) Parameter Symbol INPUT CHARACTERISTICS Offset Voltage OP1177 OP2177/OP4177 OP1177/OP2177 OP4177 Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio VOS VOS VOS VOS IB IOS Conditions -40C < TA < +125C -40C < TA < +125C -40C < TA < +125C -40C < TA < +125C Min -2 -1 -3.5 120 118 1,000 AVO VCM = -3.5 V to +3.5 V -40C < TA < +125C RL = 2 k , VO = -3.5 V to +3.5 V VOS/T VOS/T -40C < TA < +125C -40C < TA < +125C OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Current VOH VOL IOUT IL = 1 mA, -40C < TA < +125C IL = 1 mA, -40C < TA < +125C VDROPOUT < 1.2 V +4 POWER SUPPLY Power Supply Rejection Ratio OP1177 PSRR VS = 2.5 V to 15 V, -40C < TA < +125C VS = 2.5 V to 15 V, -40C < TA < +125C VO = 0 V -40C < TA < +125C 120 115 118 114 Large Signal Voltage Gain Offset Voltage Drift OP1177/OP2177 OP4177 OP2177/OP4177 Supply Current/Amplifier CMRR PSRR ISY Typ* Max Unit 15 15 25 25 +0.5 +0.2 60 75 100 120 +2 +1 +3.5 V V V V nA nA V dB dB V/mV 0.2 0.3 0.7 0.9 V/C V/C +4.1 -4.1 10 -4 V V mA 126 125 2,000 130 125 121 120 400 500 DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product SR GBP RL = 2 k 0.7 1.3 NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density en p-p en in 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz 0.4 7.9 0.2 MULTIPLE AMPLIFIERS CHANNEL SEPARATION CS DC f = 100 kHz 0.01 -120 500 600 dB dB dB dB A A V/s MHz 8.5 V p-p nV/Hz pA/Hz V/V dB *Typical values cover all parts within one standard deviation of the average value. Average values, given in many competitors' data sheets as "typical," give unrealistically low estimates for parameters that can have both positive and negative values. Specifications subject to change without notice. -2- REV. C OP1177/OP2177/OP4177 ELECTRICAL CHARACTERISTICS Parameter Symbol INPUT CHARACTERISTICS Offset Voltage OP1177 OP2177/OP4177 OP1177/OP2177 OP4177 Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio VOS VOS VOS VOS IB IOS Conditions -40C < TA < +125C -40C < TA < +125C -40C < TA < +125C -40C < TA < +125C Min -2 -1 -13.5 AVO VCM = -13.5 V to +13.5 V -40C < TA < +125C RL = 2 kW , VO = -13.5 V to +13.5 V DVOS/DT DVOS/DT -40C < TA < +125C -40C < TA < +125C OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Current Short Circuit Current VOH VOL IOUT ISC IL = 1 mA, -40C < TA < +125C IL = 1 mA, -40C < TA < +125C VDROPOUT < 1.2 V +14 POWER SUPPLY Power Supply Rejection Ratio OP1177 PSRR VS = 2.5 V to 15 V, -40C < TA < +125C VS = 2.5 V to 15 V, -40C < TA < +125C VO = 0 V -40C < TA < +125C 120 115 118 114 Large Signal Voltage Gain Offset Voltage Drift OP1177/OP2177 OP4177 OP2177/OP4177 Supply Current/Amplifier CMRR (@ VS = 15 V, VCM = 0 V, TA = 25C, unless otherwise noted.) PSRR ISY 120 1,000 Typ* Max Unit 15 15 25 25 +0.5 +0.2 60 75 100 120 +2 +1 +13.5 mV mV mV mV nA nA V 125 3,000 0.2 0.3 +14.1 -14.1 10 35 130 125 121 120 400 500 DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product SR GBP RL = 2 kW 0.7 1.3 NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density en p-p en in 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz 0.4 7.9 0.2 MULTIPLE AMPLIFIERS CHANNEL SEPARATION CS DC f = 100 kHz 0.01 -120 dB V/mV 0.7 0.9 -14 500 600 mV/C mV/C V V mA mA dB dB dB dB mA mA V/ms MHz 8.5 mV p-p nV//Hz pA//Hz mV/V dB *Typical values cover all parts within one standard deviation of the average value. Average values, given in many competitors' data sheets as "typical," give unrealistically low estimates for parameters that can have both positive and negative values. Specifications subject to change without notice. REV. C -3- OP1177/OP2177/OP4177 ABSOLUTE MAXIMUM RATINGS* Package Type Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS- to VS+ Differential Input Voltage . . . . . . . . . . . . . . Supply Voltage Storage Temperature Range R, RM, and RU Packages . . . . . . . . . . . -65C to +150C Operating Temperature Range OP1177/OP2177/OP4177 . . . . . . . . . . . -40C to +125C Junction Temperature Range R, RM, and RU Packages . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering, 10 sec) . . . . . . . 300C 2 8-Lead MSOP (RM) 8-Lead SOIC (R) 14-Lead SOIC (R) 14-Lead TSSOP (RU) JA1 JC Unit 190 158 120 240 44 43 36 43 C/W C/W C/W C/W NOTES 1 JA is specified for worst-case conditions, i.e., JA is specified for device soldered in circuit board for surface-mount packages. 2 MSOP is only available in tape and reel. *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range Package Description Package Option OP1177AR OP1177AR-REEL OP1177AR-REEL7 OP1177ARM-R2 OP1177ARM-REEL OP2177AR OP2177AR-REEL OP2177AR-REEL7 OP2177ARM-R2 OP2177ARM-REEL OP4177AR OP4177AR-REEL OP4177AR-REEL7 OP4177ARU OP4177ARU-REEL -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead MSOP 8-Lead MSOP 14-Lead SOIC 14-Lead SOIC 14-Lead SOIC 14-Lead TSSOP 14-Lead TSSOP R-8 R-8 R-8 RM-8 RM-8 R-8 R-8 R-8 RM-8 RM-8 R-14 R-14 R-14 RU-14 RU-14 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP1177/OP2177/OP4177 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. -4- Branding AZA AZA B2A B2A WARNING! ESD SENSITIVE DEVICE REV. C Typical Performance Characteristics- OP1177/OP2177/OP4177 35 30 25 20 15 10 10 20 30 40 30 20 10 0 INPUT OFFSET VOLTAGE - V 50 40 30 20 100 80 60 40 20 0.05 0.15 0.25 0.35 0.45 TCVOS - V/C 0 0.55 SOURCE 0.6 SINK 0.4 0.2 0.1 1 0.01 LOAD CURRENT - mA 0.001 1 2 30 60 AV = 100 40 AV = 10 AV = 1 40 45 0 0 20 0 150 50 100 TEMPERATURE - C AV = 10 AV = 1 300 250 AV = 100 200 150 100k 1M FREQUENCY - Hz -90 10M VSY = 15V CL = 300pF RL = 2k VIN = 4V AV = 1 400 350 -45 TPC 6. Open-Loop Gain and Phase Shift vs. Frequency VSY = 15V VIN = 50mV p-p 450 GND 100 0 10k 100k 1M 10M FREQUENCY - Hz 100M TPC 7. Closed-Loop Gain vs. Frequency REV. C PHASE 50 60 80 1k 90 10 VOLTAGE - 1V/DIV 80 135 GAIN 20 10 TPC 5. Input Bias Current vs. Temperature OUTPUT IMPEDANCE - VSY = 15V VIN = 4mV p-p CL = 0 RL = 100 20 0 180 40 500 120 0 1 3 50 10 TPC 4. Output Voltage to Supply Rail vs. Load Current 20 2 OPEN-LOOP GAIN - dB INPUT BIAS CURRENT - nA 50 1.0 0.7 270 VSY = 15V CL = 0 225 RL = VSY = 15V 1.2 0.8 0.1 0.2 0.3 0.4 0.5 0.6 INPUT BIAS CURRENT - nA 60 3 VSY = 15V TA = 25C 1.4 0 TPC 3. Input Bias Current Distribution TPC 2. Input Offset Voltage Drift Distribution 1.8 1.6 OUTPUT VOLTAGE - V 60 0 40 TPC 1. Input Offset Voltage Distribution CLOSED-LOOP GAIN - dB 70 10 5 0 VSY = 15V 120 NUMBER OF AMPLIFIERS 40 0 140 VSY = 15V 80 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 90 VSY = 15V 45 100 1k 100k 10k FREQUENCY - Hz 1M TPC 8. Output Impedance vs. Frequency -5- TIME - 100s/DIV TPC 9. Large Signal Transient Response PHASE SHIFT - Degrees 50 50 VSY = 15V CL = 1,000pF RL = 2k VIN = 100mV AV = 1 SMALL SIGNAL OVERSHOOT - % VOLTAGE - 100mV/DIV OP1177/OP2177/OP4177 GND 40 0V 15V 30 OUTPUT 25 +OS 20 +200mV 15 10 OS 5 TIME - 100s/DIV 0V INPUT 1 10 100 1k CAPACITANCE - pF 10k TIME - 10s/DIV TPC 12. Positive Overvoltage Recovery TPC 11. Small Signal Overshoot vs. Load Capacitance 140 140 VSY = 15V VSY = 15V OUTPUT CMRR - dB VSY = 15V RL = 10k AV = 100 VIN = 200mV 0V 200mV 120 120 100 100 PSRR - dB 15V 0V VSY = 15V RL = 10k AV = 100 VIN = 200mV 35 0 TPC 10. Small Signal Transient Response VSY = 15V RL = 2k VIN = 100mV p-p 45 80 60 PSRR +PSRR 80 60 40 40 20 20 INPUT 0 10 TIME - 4s/DIV TPC 13. Negative Overvoltage Recovery 100 1k 10k 100k FREQUENCY - Hz 1M 0 10 10M 10M VSY = 15V 16 SHORT CIRCUIT CURRENT - mA VOLTAGE NOISE DENSITY - nV/ Hz VNOISE - 0.2V/DIV TPC 16. 0.1 Hz to 10 Hz Input Voltage Noise 1M 35 VSY = 15V 14 12 10 8 6 4 2 TIME - 1s/DIV 1k 10k 100k FREQUENCY - Hz TPC 15. PSRR vs. Frequency TPC 14. CMRR vs. Frequency 18 VSY = 15V 100 0 50 100 150 FREQUENCY - Hz 200 250 TPC 17. Voltage Noise Density -6- 30 ISC 25 ISC 20 15 10 5 0 50 0 50 100 TEMPERATURE - C 150 TPC 18. Short Circuit Current vs. Temperature REV. C OP1177/OP2177/OP4177 0.5 VSY = 15V VOH 14.25 VOL 14.20 INPUT OFFSET VOLTAGE - V 14.30 0.3 0.2 0.1 0 0.1 14.15 0.2 14.10 0.3 14.05 0.4 14.00 50 0.5 150 50 100 TEMPERATURE - C 133 VSY = 15V 130 125 124 124 50 100 TEMPERATURE - C TPC 22. CMRR vs. Temperature 50 100 TEMPERATURE - C 60 VSY = 5V TA = 25C 1.0 0.8 0.6 SINK SOURCE 0.4 0.2 0 0.001 0.1 1 0.01 LOAD CURRENT - mA 10 40 35 30 25 20 15 10 270 120 225 100 30 135 GAIN 90 20 PHASE 45 10 0 0 -45 1M FREQUENCY - Hz -90 10M TPC 26. Open-Loop Gain and Phase Shift vs. Frequency -7- 40 TPC 24. Input Offset Voltage Distribution 180 20 100k 5V VVSY SY==15V 0 10 20 30 40 30 20 10 0 INPUT OFFSET VOLTAGE - V 150 40 10 TPC 25. Output Voltage to Supply Rail vs. Load Current REV. C VSY = 5V CL = 0 RL = 50 OPEN-LOOP GAIN - dB OUTPUT VOLTAGE - V 1.2 0 TPC 23. PSRR vs. Temperature 1.4 150 50 100 TEMPERATURE - C 5 123 50 150 45 127 125 0 50 128 126 0 TPC 21. |VOS | vs. Temperature 129 126 123 50 0 50 NUMBER OF AMPLIFIERS 131 130 PSRR - dB CMRR - dB 131 127 6 4 VSY = 15V 132 128 8 TPC 20. Warm-Up Drift 133 129 10 100 120 140 0 20 40 60 80 TIME FROM POWER SUPPLY TURN-ON - Sec TPC 19. Output Voltage Swing vs. Temperature 132 14 12 2 PHASE SHIFT - Degrees 0 VSY = 15V 16 CLOSED-LOOP GAIN - dB 14.35 18 VSY = 15V 0.4 OFFSET VOLTAGE - V OUTPUT VOLTAGE SWING - V 14.40 VSY = 5V VIN = 4mV p-p CL = 0 RL = 80 60 AV = 100 40 20 0 AV = 10 AV = 1 20 40 60 80 1k 10k 100k 1M 10M FREQUENCY - Hz 100M TPC 27. Closed-Loop Gain vs. Frequency OP1177/OP2177/OP4177 500 VSY = 5V VIN = 50mV p-p 400 350 AV = 10 AV = 1 300 250 AV = 100 200 150 VOLTAGE - 50mV/DIV VSY = 5V CL = 300pF RL = 2k VIN = 1V AV = 1 VOLTAGE - 1V/DIV OUTPUT IMPEDANCE - 450 GND 100 VSY = 5V CL = 1,000pF RL = 2k VIN = 100mV AV = 1 GND 50 0 100 1k 100k 10k FREQUENCY - Hz 1M TPC 28. Output Impedance vs. Frequency SMALL SIGNAL OVERSHOOT - % 50 TPC 29. Large Signal Transient Response VSY = 5V RL = 2k VIN = 100mV 45 40 0V 35 5V 30 +OS TPC 30. Small Signal Transient Response VSY = 5V RL = 10k AV = 100 VIN = 200mV VSY = 5V RL = 10k AV = 100 VIN = 200mV OUTPUT 5V 0V OUTPUT 25 20 +200mV 0V 15 OS 10 200mV 0V 5 0 INPUT 1 10 100 1k CAPACITANCE - pF 10k VS = 5V AV = 1 RL = 10k INPUT INPUT TIME - 4s/DIV TPC 31. Small Signal Overshoot vs. Load Capacitance TIME - 4s/DIV TPC 32. Positive Overvoltage Recovery TPC 33. Negative Overvoltage Recovery 140 200 VSY = 5V 160 100 140 PSRR - dB GND 80 60 PSRR 100 80 +PSRR 40 20 20 OUTPUT TPC 34. No Phase Reversal 120 60 40 TIME - 200s/DIV VSY = 5V 180 120 CMRR - dB VOLTAGE - 2V/DIV TIME - 10s/DIV TIME - 100s/DIV 0 10 100 1k 10k 100k FREQUENCY - Hz 1M TPC 35. CMRR vs. Frequency -8- 10M 0 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M TPC 36. PSRR vs. Frequency REV. C OP1177/OP2177/OP4177 18 35 VSY = 5V VSY = 5V 16 SHORT CIRCUIT CURRENT - mA VNOISE - 0.2V/DIV VOLTAGE NOISE DENSITY - nV/ Hz VSY = 5V 14 12 10 8 6 4 2 0 TIME - 1s/DIV TPC 37. 0.1 Hz to 10 Hz Input Voltage Noise 100 150 FREQUENCY - Hz 200 4.25 VOL 4.15 4.10 15 10 5 0 50 150 50 100 TEMPERATURE - C TPC 40. Output Voltage Swing vs. Temperature 0 50 100 TEMPERATURE - C 150 TA = 25C CHANNEL SEPARATION - dB SUPPLY CURRENT - A 20 350 300 250 200 150 100 40 60 80 100 120 140 50 5 10 15 20 25 SUPPLY VOLTAGE - V 30 35 TPC 43. Supply Current vs. Supply Voltage REV. C 50 100 TEMPERATURE - C 150 160 10 VSY = 15V 400 VSY = 5V 300 200 100 1k 10k 100k FREQUENCY - Hz 1M TPC 44. Channel Separation vs. Frequency -9- 0 50 0 50 100 TEMPERATURE - C TPC 42. Supply Current vs. Temperature 0 450 0 0 100 TPC 41. |VOS | vs. Temperature 400 0 5 500 20 4.05 0 10 600 SUPPLY CURRENT - A INPUT OFFSET VOLTAGE - V VOH 4.00 50 15 VSY = 5V 4.30 4.20 ISC 20 TPC 39. Short Circuit Current vs. Temperature 25 VSY = 5V 4.35 ISC 25 0 50 250 TPC 38. Voltage Noise Density 4.40 OUTPUT VOLTAGE SWING - V 50 30 150 OP1177/OP2177/OP4177 FUNCTIONAL DESCRIPTION Where BW is the bandwidth in Hertz. OP1177 is the fourth generation of ADI's industry-standard OP07 amplifier family. OP1177 is a very high precision, low noise operational amplifier with the highly desirable combination of extremely low offset voltage and very low input bias currents. Unlike JFET amplifiers, the low bias and offset currents are relatively insensitive to ambient temperatures, even up to 125C. NOTE: The above analysis is valid for frequencies larger than 50 Hz. When considering lower frequencies, flicker noise (also known as 1/f noise) must be taken into account. For the first time, Analog Devices' proprietary process technology and linear design expertise have produced a high voltage amplifier with superior performance to the OP07, OP77, and OP177 in a tiny MSOP 8-lead package. Despite its small size, the OP1177 offers numerous improvements including low wideband noise, very wide input and output voltage range, lower input bias current, and complete freedom from phase inversion. Gain Linearity OP1177 has the widest specified operating temperature range of any similar device in a plastic surface-mount package. This is increasingly important as PC board and overall system sizes continue to shrink, causing internal system temperatures to rise. Power consumption is reduced by a factor of four from the OP177 while bandwidth and slew rate increase by a factor of two. The low power dissipation and very stable performance versus temperature also act to reduce warm-up drift errors to insignificant levels. For a reference on noise calculations refer to Bandpass KRC or Sallen-Key Filter section. Gain linearity reduces errors in closed-loop configurations. The straighter the gain curve, the lower the maximum error over the input signal range will be. This is especially true for circuits with high closed-loop gains. The OP1177 has excellent gain linearity even with heavy loads, shown in Figure 1. Compare its performance to the OPA277, shown in Figure 2. Both devices were measured under identical conditions with RL = 2 kW. The OP2177 (dual) has virtually no distortion at lower voltages. It was compared to the OPA277 at several supply voltages and various loads. Its performance far exceeded that of its counterpart. VSY = 15V RL = 2k SCALE - V Open-loop gain linearity under heavy loads is superior to competitive parts like OPA277, improving dc accuracy and reducing distortion in circuits with high closed-loop gains. Inputs are internally protected from overvoltage conditions referenced to either supply rail. Like any high performance amplifier, maximum performance is achieved by following appropriate circuit and PC board guidelines. The following sections provide practical advice on getting the most out of the OP1177 under a variety of application conditions. OP1177 Total Noise Including Source Resistors The low input current noise and input bias current of the OP1177 make it useful for circuits with substantial input source resistance. Input offset voltage increases by less than 1 mV max per 500 W of source resistance. SCALE - V Figure 1. Gain Linearity VSY = 15V RL = 2k The total noise density of the OP1177 is en, TOTAL = en + (in RS ) + 4kTRS 2 NEED LABEL FOR THIS AXIS SCALE - V 2 Where, en is the input voltage noise density in is the input current noise density RS is the source resistance at the noninverting terminal k is Boltzman's constant (1.38 10-23 J/K) T is the ambient temperature in Kelvin (T = 273 + C) For RS < 3.9 kW, en dominates and OPA277 en, TOTAL en For 3.9 kW < RS < 412 kW, voltage noise of the amplifier, current noise of the amplifier translated through the source resistor, and thermal noise from the source resistor all contribute to the total noise. For RS > 412 kW, the current noise dominates and en, TOTAL in RS The total equivalent rms noise over a specific bandwidth is expressed as E n = (en , TOTAL ) BW SCALE - V Figure 2. Gain Linearity Input Overvoltage Protection When their input voltage exceeds the positive or negative supply voltage, most amplifiers require external resistors to protect them from damage. The OP1177 has internal protective circuitry that allows voltages as high as 2.5 V beyond the supplies to be applied at the input of either terminal without any harmful effects. -10- REV. C OP1177/OP2177/OP4177 Use an additional resistor in series with the inputs if the voltage exceeds the supplies by more than 2.5 V. The value of the resistor can be determined from the formula (VIN - VS ) RS + 500 W 5 mA With the OP1177's low input offset current of <1 nA max, placing a 5 kW resistor in series with both inputs adds less than 5 mV to input offset voltage and has a negligible impact on the overall noise performance of the circuit. demanded by the circuit's transfer function lies beyond the maximum output voltage capability of the amplifier. A 10 V input applied to an amplifier in a closed-loop gain of 2 will demand an output voltage of 20 V. This is beyond the output voltage range of the OP1177 when operating at 15 V supplies and will force the output into saturation. Recovery time is important in many applications, particularly where the op amp must amplify small signals in the presence of large transient voltages. R2 100k 5 kW will protect the inputs to more than 27 V beyond either supply. Refer to the THD + N section for additional information on noise versus source resistance. V Output Phase Reversal 200mV Phase reversal is defined as a change of polarity in the amplifier transfer function. Many operational amplifiers exhibit phase reversal when the voltage applied to the input is greater than the maximum common-mode voltage. In some instances this can cause permanent damage to the amplifier. In feedback loops, it can result in system lockups or equipment damage. The OP1177 is immune to phase reversal problems even at input voltages beyond the supplies. VSY = 10V AV = 1 VOLTAGE - 5V/DIV VIN VOUT + R1 2 1k 3 4 1 7 VOUT 10k OP1177 V+ Figure 4. Test Circuit for Overload Recovery Time TPC 12 shows the positive overload recovery time of the OP1177. The output recovers in less than 4 ms after being overdriven by more than 100%. The negative overload recovery of the OP1177 is 1.4 ms as seen in TPC 13. THD + Noise The OP1177 has very low total harmonic distortion. This indicates excellent gain linearity and makes the OP1177 a great choice for high closed-loop gain precision circuits. Figure 5 shows that the OP1177 has approximately 0.00025% distortion in unity gain, the worst-case configuration for distortion. 0.1 VSY = 15V RL = 10k BW = 22kHz 0.01 THD + N - % TIME - 400s/DIV Figure 3. No Phase Reversal Settling Time Settling time is defined as the time it takes an amplifier output to reach and remain within a percentage of its final value after application of an input pulse. It is especially important in measurement and control circuits where amplifiers buffer A/D inputs or DAC outputs. 0.001 0.0001 To minimize settling time in amplifier circuits, use proper bypassing of power supplies and an appropriate choice of circuit components. Resistors should be metal film types as these have less stray capacitance and inductance than their wire-wound counterparts. Capacitors should be polystyrene or polycarbonate types to minimize dielectric absorption. The leads from the power supply should be kept as short as possible to minimize capacitance and inductance. The OP1177 has a settling time of about 45 ms to 0.01% (1 mV) with a 10 V step applied to the input in a noninverting unity gain. Overload Recovery Time Overload recovery is defined as the time it takes the output voltage of an amplifier to recover from a saturated condition to its linear response region. A common example is where the output voltage REV. C 20 100 1k 6k FREQUENCY - Hz Figure 5. THD + N vs. Frequency Capacitive Load Drive OP1177 is inherently stable at all gains and capable of driving large capacitive loads without oscillation. With no external compensation, the OP1177 will safely drive capacitive loads up to 1000 pF in any configuration. As with virtually any amplifier, driving larger capacitive loads in unity gain requires additional circuitry to assure stability. In this case, a "snubber network" is used to prevent oscillation and reduce the amount of overshoot. A significant advantage of this method is that it does not reduce the output swing because the resistor RS is not inside the feedback loop. -11- OP1177/OP2177/OP4177 Figure 6 is a scope photograph of the output of the OP1177 in response to a 400 mV pulse. The load capacitance is 2 nF. The circuit is configured in positive unity gain, the worst-case condition for stability. V 1 400mV As shown in Figure 8, placing an R-C network parallel to the load capacitance CL will allow the amplifier to drive higher values of CL without causing oscillation or excessive overshoot. RS () CS 10 50 200 20 30 200 0.33 mF 6.8 nF 0.47 mF 7 OP1177 RS CL CS Figure 8. Snubber Network Configuration CAUTION: The snubber technique cannot recover the loss of bandwidth induced by large capacitive loads. Stray Input Capacitance Compensation The effective input capacitance in an op amp circuit, Ct, consists of three components. These are the internal differential capacitance between the input terminals; the internal common mode capacitance of each input to ground; and the external capacitance including parasitic capacitance. In the circuit in Figure 9, the closed-loop gain increases as the signal frequency increases. Table I. Optimum Values for Capacitive Loads CL (nF) VOUT 3 + V+ There is no ringing and overshoot is reduced from 27% to 5% using the snubber network. Optimum values for RS and CS are tabulated in Table I for several capacitive loads up to 200 nF. Values for other capacitive loads can be determined experimentally. 4 2 The transfer function of the circuit is 0 VSY = 5V RL = 10k CL = 2nF 0 1+ R2 (1 + sCt R1) R1 VOLTAGE - 200mV/DIV 0 indicating a zero at 0 s= 0 0 GND Depending on the value of R1 and R2, the cutoff frequency of the closed-loop gain may be well below the crossover frequency. In this case, the phase margin, Fm, can be severely degraded resulting in excessive ringing or even oscillation. 0 0 0 0 0 0 0 0 0 0 TIME - 10s/DIV 0 0 0 0 Figure 6. Capacitive Load Drive without Snubber VSY = 5V RL = 10k RS = 200 CL = 2nF CS = 0.47F 0 0 A simple way to overcome this problem is to insert a capacitor in the feedback path as shown in Figure 10. The resulting pole can be positioned to adjust the phase margin. Setting Cf = (R1/R2)Ct , achieves a phase margin of 90. 0 VOLTAGE - 200mV/DIV R2 + R1 1 = R2R1Ct 2p ( R1 / R2 ) Ct R1 R2 V + 0 2 V1 - Ct 0 4 1 VOUT 3 OP1177 7 GND0 V+ 0 Figure 9. Stray Input Capacitance 0 Cf 0 0 0 0 0 0 0 0 TIME - 10s/DIV 0 0 0 0 R1 Figure 7. Capacitive Load Drive with Snubber R2 V + 2 V1 - Ct 4 1 3 VOUT 7 V+ OP1177 Figure 10. Compensation Using Feedback Capacitor -12- REV. C OP1177/OP2177/OP4177 Reducing Electromagnetic Interference A number of methods can be utilized to reduce the effects of EMI on amplifier circuits. In one method, stray signals on either input are coupled to the opposite input of the amplifier. The result is that the signal is rejected according to the amplifier's CMRR. This is usually achieved by inserting a capacitor between the inputs of the amplifier as shown in Figure 11. However, this method may also cause instability depending on the value of capacitance. R1 R2 V + 4 2 V1 - C 1 VOUT 3 OP1177 7 V+ Figure 11. EMI Reduction A variation in temperature across the PC board can cause a mismatch in the Seebeck voltages at solder joints and other points where dissimilar metals are in contact, resulting in thermal voltage errors. To minimize these thermocouple effects, resistors should be oriented so heat sources warm both ends equally. Input signal paths should contain matching numbers and types of components where possible in order to match the number and type of thermocouple junctions. For example, dummy components such as zero value resistors can be used to match real resistors in the opposite input path. Matching components should be located in close proximity and should be oriented in the same manner. Leads should be of equal length so that thermal conduction is in equilibrium. Heat sources on the PC board should be kept as far away from amplifier input circuitry as practical. The use of a ground plane is highly recommended. A ground plane reduces EMI noise and also helps to maintain a constant temperature across the circuit board. Difference Amplifiers Placing a resistor in series with the capacitor (Figure 12) increases the dc loop gain and reduces the output error. Positioning the breakpoint (introduced by R-C) below the secondary pole of the op amp improves the phase margin and hence stability. Difference amplifiers are used in high accuracy circuits to improve the common-mode rejection ratio (CMRR). R2 100k R can be chosen independently of C for a specific phase margin according to the formula V R1 2 V1 R2 R2 R= - 1+ ajf2 R1 4 1 3 7 VOUT OP1177 V+ where a is the open-loop gain of the amplifier and f2 is the frequency at which the phase of a = m - 180. V2 R3 = R1 R4 R2 = R3 R1 R2 V1 + - Figure 13. Difference Amplifier V R1 R C 2 4 1 3 VOUT 7 V+ OP1177 In the single instrumentation amplifier (circuit in Figure 13), where R4 R2 = R3 R1 Figure 12. Compensation Using Input RC Network VO = Proper Board Layout The OP1177 is a high precision device. In order to ensure optimum performance at the PC board level, care must be taken in the design of the board layout. To avoid leakage currents, the surface of the board should be kept clean and free of moisture. Coating the surface creates a barrier to moisture accumulation and helps reduce parasitic resistance on the board. Keeping supply traces short and properly bypassing the power supplies will minimize power supply disturbances due to output current variation, such as when driving an ac signal into a heavy load. Bypass capacitors should be connected as closely as possible to the device supply pins. Stray capacitances are a concern at the output and the inputs of the amplifier. It is recommended that signal traces be kept at least 5 mm from supply lines to minimize coupling. REV. C R4 = R1 R2 (V2 - V1 ) R1 a mismatch between the ratio R2/R1 and R4/R3 will cause the common-mode rejection ratio to be reduced. To better understand this effect, consider the following: By definition ADM ACM where ADM is the differential gain and ACM is the common-mode gain. CMRR = ADM = -13- VO V and ACM = O VDIFF VCM OP1177/OP2177/OP4177 1 (V + V2 ) 2 1 VDIFF = V1 - V2 and VCM = In order for this circuit to act as a difference amplifier, its output must be proportional to the differential input signal. From Figure 13, 1 + R2 VO = - V1 + R1 1 + R2 R1 V2 R3 R4 R4R1 + R3R2 + 2R4R2 2R4R1 - 2R2R3 Maximum measurement accuracy requires cold junction compensation of the thermocouple as described below. To perform the cold junction compensation, apply a copper wire short across the terminating junctions (inside the isothermal block) simulating a 0C point. Adjust the output voltage to zero using the trimming resistor R5 and then remove the copper wire. The OP1177 is an ideal amplifier for thermocouple circuits since it has a very low offset voltage, excellent PSRR and CMRR, and low noise at low frequencies. Arranging terms and combining the equations above yields: CMRR = coefficient specific to the dissimilar metals used in the thermocouple. VTC is the thermocouple voltage. VTC becomes larger with increasing temperature. (1) The sensitivity of CMRR with respect to the R1 is obtained by taking the derivative of CMRR, in Equation 1, with respect to R1. It can be used to create a thermocouple circuit with great linearity. Resistors R1 and R2 and diode D1 shown in Figure 14 are mounted in an isothermal block. VCC C1 2.2F CMRR R1R4 2R2R4 + R2R3 = + R1 R1 2R1R4 - 2R2R3 2R1R4 - 2R2R3 1 (2R2R3) 2- R1R4 TJ (+) R2 4.02k TR () R(1 - ) < R1, R2, R3, R4 < R(1 + ). CMRRMIN 1 2 where is the tolerance of the resistors. Lower tolerance value resistors result in higher common-mode rejection (up to the CMRR of the op amp). Using 5% tolerance resistors, the highest CMRR that can be guaranteed is 20 dB. On the other hand, using 0.1% tolerance resistors would result in a common-mode rejection ratio of at least 54 dB (assuming that the op amp CMRR 54 dB). With the CMRR of OP1177 at 120 dB minimum, the resistor match will be the limiting factor in most circuits. A trimming resistor can be used to further improve resistor matching and CMRR of the difference amp circuit. A High Accuracy Thermocouple Amplifier A thermocouple consists of two dissimilar metal wires placed in contact. The dissimilar metals produce a voltage VTC = (TJ - TR ) where TJ is the temperature at the measurement of the hot junction, TR is the temperature at the cold junction, and is the Seebeck 0.1F Cu R8 1k R6 50 TR 3 Cu ISOTHERMAL BLOCK 10F 2 4 R5 100 VTC R1 50 The worst-case CMRR error arises when +15V 10F D1 Assuming that R1 R2 R3 R4 R and R1 = R4 = R(1 + ) and R2 = R3 = R(1 - ). Plugging these values into Equation 1 yields R7 80.6k R3 47k D1 CMRR = R1 R9 200k ADR293 7 1 VOUT OP1177 10F R4 10F 50 15V 0.1F Figure 14. Type K Thermocouple Amplifier Circuit Low Power Linearized RTD A common application for a single element varying bridge is an RTD thermometer amplifier as shown in Figure 15. The excitation is delivered to the bridge by a 2.5 V reference applied at the top of the bridge. RTDs may have thermal resistance as high as 0.5C to 0.8C per mW. In order to minimize errors due to resistor drift, the current through each leg of the bridge must be kept low. In this circuit, the amplifier supply current flows through the bridge. However, at the OP1177 maximum supply current of 600 A, the RTD dissipates less than 0.1 mW of power even at the highest resistance. Errors due to power dissipation in the bridge are kept under 0.1C. Calibration of the bridge can be made at the minimum value of temperature to be measured by adjusting RP until the output is zero. To calibrate the output span, set the full-scale and linearity potentiometers to midpoint and apply a 500C temperature to the sensor or substitute the equivalent 500C RTD resistance. Adjust the full-scale pot for a 5 V output. Finally, apply 250C or the equivalent RTD resistance and adjust the linearity potentiometer for 2.5 V output. The circuit achieves better than 0.5C accuracy after adjustment. -14- REV. C OP1177/OP2177/OP4177 +15V REALIZATION OF ACTIVE FILTERS Bandpass KRC or Sallen-Key Filter 0.1F The low offset voltage and the high CMRR of the OP1177 make it an excellent choice for precision filters such as the KRC filter shown in Figure 17. This filter type offers the capability to tune the gain and the cutoff frequency independently. 500 4.12k ADR421 4.37k 200 15V 6 4.12k 4 100 8 100 Since the common-mode voltage into the amplifier varies with the input signal in the KRC filter circuit, a high CMRR is required to minimize distortion. Also, the low offset voltage of the OP1177 allows a wider dynamic range when the circuit gain is chosen to be high. VOUT 7 5 20 1/2 OP2177 +15V The circuit of Figure 17 consists of two stages. The first stage is a simple high-pass filter whose corner frequency fC is 5k 49.9k 100 RTD 1 15V 2 4 1 and whose VOUT 3 8 (2) 2p C1C2R1R2 1/2 OP2177 Q=K +15V Figure 15. Low Power Linearized RTD Circuit R1 R2 (3) where K is the dc gain. Single Op Amp Bridge Choosing equal capacitor values minimizes the sensitivity and simplifies Equation 2 to The low input offset voltage drift of the OP1177 makes it very effective for bridge amplifier circuits used in RTD signal conditioning. It is often more economical to use a single bridge op amp as opposed to an instrumentation amplifier. 1 2pC R1R2 In the circuit of Figure 16, the output voltage at the op amp is The value of Q determines the peaking of the gain versus frequency (ringing in transient response). Commonly chosen values for Q are generally near unity. E E I A R2 I d VO = VREF A R I R1 A R1 E I A R + AE1 + R2 (1 + d ) E II Setting Q = 1 2 , where d = DR/R is the fractional deviation of the RTD resistance with respect to the bridge resistance due to the change in temperature at the RTD. yields minimum gain peaking and minimum ringing. For d << 1, the expression above becomes For Q = Determine values for R1 and R2 by use of Equation 3. , R1/R2 = 2 in the circuit example. Pick R1 = 5 kW 2 and R2 = 10 kW for simplicity. E E R2 d A EE R2 E R1 E R1 VO @ A VREF A =I + 1+ V d R1 R1 IAE R AE R2 AE R2 REF E R A1+ + E R R2 The second stage is a low-pass filter whose corner frequency can be determined in a similar fashion. For R3 = R4 = R. fC = With VREF constant, the output voltage is linearly proportional to d with a gain factor of E R2 EE R1 E R1 VREF A + IA1 + R2 AE R2 E R IE RF ADR421 V R R 2 4 1 R(1+) R 2pR C3 C4 and Q = 1 C3 2 C4 VOUT Multiple amplifiers on a single die are often required to reject any signals originating from the inputs or outputs of adjacent channels. OP2177 input and bias circuitry is designed to prevent feedthrough of signals from one amplifier channel to the other. As a result, the OP2177 has an impressive channel separation of greater than -120 dB for frequencies up to 100 kHz and greater than -115 dB for signals up to 1 MHz. 3 7 OP1177 V+ RF Figure 16. Single Bridge Amplifier REV. C 1 Channel Separation 15V 0.1F 1 -15- OP1177/OP2177/OP4177 C3 680pF R2 10k V V C2 10nF V1 + - 6 C1 10nF 4 R3 33k 7 R4 33k 2 1 3 5 8 R1 20k 4 8 1/2 OP2177 C4 330pF V+ VOUT 1/2 OP2177 V+ Figure 17. Two-Stage, Band-Pass Filter 10k V 6 V 4 4 7 5 V1 + 50mV - SPICE Model 8 V+ 2 100 1 1/2 OP2177 1/2 OP2177 3 8 V+ The SPICE macro-model for the OP1177 can be downloaded from Analog Devices' website at www.analog.com. This model will accurately simulate a number of parameters, both dc and ac. References on Noise Dynamics and Flicker Noise S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits, McGraw-Hill 1998. The Best of Analog Dialogue, Analog Devices, Inc. Figure 18. Channel Separation Test Circuit -16- REV. C OP1177/OP2177/OP4177 OUTLINE DIMENSIONS 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) 14-Lead Standard Small Outline Package [SOIC] Narrow Body (R-14) Dimensions shown in millimeters and (inches) Dimensions shown in millimeters and (inches) 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 8 5 1 4 0.50 (0.0196) 45 0.25 (0.0099) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY SEATING 0.10 PLANE 4.00 (0.1575) 3.80 (0.1496) 6.20 (0.2440) 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 8.75 (0.3445) 8.55 (0.3366) 14 8 1 7 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) 8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) 6.20 (0.2441) 5.80 (0.2283) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 0.50 (0.0197) 45 0.25 (0.0098) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8-Lead Mini Small Outline Package [MSOP] (RM-8) 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters Dimensions shown in millimeters 5.10 5.00 4.90 3.00 BSC 8 5 4.90 BSC 3.00 BSC 1 14 8 4.50 4.40 4.30 4 PIN 1 0.65 BSC 6.40 BSC 1 7 PIN 1 1.10 MAX 0.15 0.00 0.38 0.22 COPLANARITY 0.10 0.23 0.08 8 0 1.05 1.00 0.80 0.80 0.60 0.40 0.65 BSC 1.20 MAX 0.15 0.05 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187AA 0.30 0.19 0.20 0.09 SEATING COPLANARITY PLANE 0.10 8 0 COMPLIANT TO JEDEC STANDARDS MO-153AB-1 REV. C -17- 0.75 0.60 0.45 OP1177/OP2177/OP4177 Revision History Location Page 4/04--Data Sheet changed from REV. B to REV. C. Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to TPC 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to TPC 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4/02--Data Sheet changed from REV. A to REV. B. Added OP4177 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to ELECTRICAL CHARACTERISTICS headings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 11/01--Data Sheet changed from REV. 0 to REV. A. Edit to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to TPC 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -18- REV. C -19- -20- C02627-0-4/04(C)