a
OP1177/OP2177/OP4177
REV. C
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reliable. However, no responsibility is assumed by Analog Devices for its
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may result from its use. No license is granted by implication or otherwise
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
Precision Low Noise, Low Input
Bias Current Operational Amplifiers
FEATURES
Low Offset Voltage: 60 V Max
Very Low Offset Voltage Drift: 0.7 V/ⴗC Max
Low Input Bias Current: 2 nA Max
Low Noise: 8 nV/
√
Hz
CMRR, PSRR, and AVO > 120 dB Min
Low Supply Current: 400 A/Amp
Dual Supply Operation: ⴞ2.5 V to ⴞ15 V
Unity Gain Stable
No Phase Reversal
Inputs Internally Protected Beyond Supply Voltage
APPLICATIONS
Wireless Base Station Control Circuits
Optical Network Control Circuits
Instrumentation
Sensors and Controls
Thermocouples
RTDs
Strain Bridges
Shunt Current Measurements
Precision Filters
GENERAL DESCRIPTION
The OPx177 family consists of very high precision, single, dual,
and quad amplifiers featuring extremely low offset voltage and
drift, low input bias current, low noise, and low power con-
sumption. Outputs are stable with capacitive loads of over
1,000 pF with no external compensation. Supply current is less
than 500 µA per amplifier at 30 V. Internal 500 Ω series resis-
tors protect the inputs, allowing input signal levels several volts
beyond either supply without phase reversal.
Unlike previous high voltage amplifiers with very low offset voltages,
the OP1177 and OP2177 are available in the tiny MSOP 8-lead
surface-mount package, while the OP4177 is available in
TSSOP-14. Moreover, specified performance in the MSOP/
TSSOP packages is identical to performance in the SOIC package.
OPx177 family offers the widest specified temperature range of
any high precision amplifier in surface-mount packaging. All
versions are fully specified for operation from –40°C to +125°C for
the most demanding operating environments.
Applications for these amplifiers include precision diode power
measurement, voltage and current level setting, and level detec-
tion in optical and wireless transmission systems. Additional
applications include line powered and portable instrumentation
PIN CONFIGURATIONS
8-Lead MSOP
(RM-Suffix)
ⴚIN
ⴙIN
Vⴚ
V+
NC
NC
1
45
8
OP1177
NC
OUT
NC = NO CONNECT
8-Lead SOIC
(R-Suffix)
1
2
3
4
8
7
6
5
ⴚIN
Vⴚ
+IN
V+
OUT
NC
NC
NC
NC = NO CONNECT
OP1177
8-Lead SOIC
(R-Suffix)
1
2
3
4
8
7
6
5
OP2177
ⴚIN A
Vⴚ
+IN A
OUT B
ⴚIN B
V+
+IN B
OUT A
8-Lead MSOP
(RM-Suffix)
ⴚIN A
ⴙIN A
Vⴚ
OUT B
–IN B
+IN B
V+
1
45
8
OP2177
OUT A
14-Lead TSSOP
(RU-Suffix)
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
–IN D
+IN D
V–
OUT D
–IN C
OUT C
+IN C
14
8
1
7
OP4177
14-Lead SOIC
(R-Suffix)
OUT B 78
+IN B 510
ⴚIN B 69
V+ 411
OP4177
ⴚIN A 213
+IN A 312
OUT A 114
OUT C
+IN C
ⴚIN C
Vⴚ
ⴚIN D
+IN D
OUT D
OP4177
and controls—thermocouple, RTD, strain-bridge, and other
sensor signal conditioning—and precision filters.
The OP1177 (single) and the OP2177 (dual) amplifiers are
available in the 8-lead MSOP and 8-lead SOIC packages. The
OP4177 (quad) is available in 14-lead narrow SOIC and 14-lead
TSSOP packages. MSOP and TSSOP packages are available in
tape and reel only.
REV. C
–2–
OP1177/OP2177/OP4177–SPECIFICATIONS
(@ VS = ⴞ5.0 V, VCM = 0 V, TA = 25ⴗC, unless
otherwise noted.)
Parameter Symbol Conditions Min Typ*Max Unit
INPUT CHARACTERISTICS
Offset Voltage
OP1177 V
OS
15 60 µV
OP2177/OP4177 V
OS
15 75 µV
OP1177/OP2177 V
OS
–40°C < T
A
< +125°C25100 µV
OP4177 V
OS
–40°C < T
A
< +125°C25120 µV
Input Bias Current I
B
–40°C < T
A
< +125°C–2+0.5 +2 nA
Input Offset Current I
OS
–40°C < T
A
< +125°C–1+0.2 +1 nA
Input Voltage Range –3.5 +3.5 V
Common-Mode Rejection Ratio CMRR V
CM
= –3.5 V to +3.5 V 120 126 dB
–40°C < T
A
< +125°C118 125 dB
Large Signal Voltage Gain A
VO
R
L
= 2 kΩ , V
O
= –3.5 V to +3.5 V 1,000 2,000 V/mV
Offset Voltage Drift
OP1177/OP2177 ∆V
OS
/∆T–40°C < T
A
< +125°C0.2 0.7 µV/°C
OP4177 ∆V
OS
/∆T–40°C < T
A
< +125°C0.3 0.9 µV/°C
OUTPUT CHARACTERISTICS
Output Voltage High V
OH
I
L
= 1 mA, –40°C < T
A
< +125°C+4 +4.1 V
Output Voltage Low V
OL
I
L
= 1 mA, –40°C < T
A
< +125°C–4.1 –4 V
Output Current I
OUT
V
DROPOUT
< 1.2 V ±10 mA
POWER SUPPLY
Power Supply Rejection Ratio
OP1177 PSRR V
S
= ±2.5 V to ±15 V, 120 130 dB
–40°C < T
A
< +125°C115 125 dB
OP2177/OP4177 PSRR V
S
= ±2.5 V to ±15 V, 118 121 dB
–40°C < T
A
< +125°C114 120 dB
Supply Current/Amplifier I
SY
V
O
= 0 V 400 500 µA
–40°C < T
A
< +125°C500 600 µA
DYNAMIC PERFORMANCE
Slew Rate SR R
L
= 2 kΩ0.7 V/µs
Gain Bandwidth Product GBP 1.3 MHz
NOISE PERFORMANCE
Voltage Noise e
n
p-p 0.1 Hz to 10 Hz 0.4 µV p-p
Voltage Noise Density e
n
f = 1 kHz 7.9 8.5 nV/√Hz
Current Noise Density i
n
f = 1 kHz 0.2 pA/√Hz
MULTIPLE AMPLIFIERS
CHANNEL SEPARATION C
S
DC 0.01 µV/V
f = 100 kHz –120 dB
*Typical values cover all parts within one standard deviation of the average value. Average values, given in many competitors’ data sheets as “typical,” give unrealistically
low estimates for parameters that can have both positive and negative values.
Specifications subject to change without notice.
REV. C –3–
OP1177/OP2177/OP4177
ELECTRICAL CHARACTERISTICS
(@ VS = ⴞ15 V, VCM = 0 V, TA = 25ⴗC, unless otherwise noted.)
Parameter Symbol Conditions Min Typ*Max Unit
INPUT CHARACTERISTICS
Offset Voltage
OP1177 V
OS
15 60 mV
OP2177/OP4177 V
OS
15 75 mV
OP1177/OP2177 V
OS
–40∞C < T
A
< +125∞C25100 mV
OP4177 V
OS
–40∞C < T
A
< +125∞C25120 mV
Input Bias Current I
B
–40∞C < T
A
< +125∞C–2+0.5 +2 nA
Input Offset Current I
OS
–40∞C < T
A
< +125∞C–1+0.2 +1 nA
Input Voltage Range –13.5 +13.5 V
Common-Mode Rejection Ratio CMRR V
CM
= –13.5 V to +13.5 V
–40∞C < T
A
< +125∞C120 125 dB
Large Signal Voltage Gain A
VO
R
L
= 2 kW , V
O
= –13.5 V to +13.5 V 1,000 3,000 V/mV
Offset Voltage Drift
OP1177/OP2177 DV
OS
/DT–40∞C < T
A
< +125∞C0.2 0.7 mV/∞C
OP4177 DV
OS
/DT–40∞C < T
A
< +125∞C0.3 0.9 mV/∞C
OUTPUT CHARACTERISTICS
Output Voltage High V
OH
I
L
= 1 mA, –40∞C < T
A
< +125∞C+14 +14.1 V
Output Voltage Low V
OL
I
L
= 1 mA, –40∞C < T
A
< +125∞C–14.1 –14 V
Output Current I
OUT
V
DROPOUT
< 1.2 V ±10 mA
Short Circuit Current I
SC
±35 mA
POWER SUPPLY
Power Supply Rejection Ratio
OP1177 PSRR V
S
= ±2.5 V to ±15 V, 120 130 dB
–40∞C < T
A
< +125∞C115 125 dB
OP2177/OP4177 PSRR V
S
= ±2.5 V to ±15 V, 118 121 dB
–40∞C < T
A
< +125∞C114 120 dB
Supply Current/Amplifier I
SY
V
O
= 0 V 400 500 mA
–40∞C < T
A
< +125∞C500 600 mA
DYNAMIC PERFORMANCE
Slew Rate SR R
L
= 2 kW0.7 V/ms
Gain Bandwidth Product GBP 1.3 MHz
NOISE PERFORMANCE
Voltage Noise e
n
p-p 0.1 Hz to 10 Hz 0.4 mV p-p
Voltage Noise Density e
n
f = 1 kHz 7.9 8.5 nV/÷Hz
Current Noise Density i
n
f = 1 kHz 0.2 pA/÷Hz
MULTIPLE AMPLIFIERS
CHANNEL SEPARATION C
S
DC 0.01 mV/V
f = 100 kHz –120 dB
*Typical values cover all parts within one standard deviation of the average value. Average values, given in many competitors’ data sheets as “typical,” give unrealistically
low estimates for parameters that can have both positive and negative values.
Specifications subject to change without notice.
REV. C
OP1177/OP2177/OP4177
–4–
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
S–
to V
S+
Differential Input Voltage . . . . . . . . . . . . . . ±Supply Voltage
Storage Temperature Range
R, RM, and RU Packages . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP1177/OP2177/OP4177 . . . . . . . . . . . –40°C to +125°C
Junction Temperature Range
R, RM, and RU Packages . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 10 sec) . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Package Type
JA1
JC
Unit
8-Lead MSOP (RM)
2
190 44 °C/W
8-Lead SOIC (R) 158 43 °C/W
14-Lead SOIC (R) 120 36 °C/W
14-Lead TSSOP (RU) 240 43 °C/W
NOTES
1
θ
JA
is specified for worst-case conditions, i.e., θ
JA
is specified for device soldered
in circuit board for surface-mount packages.
2
MSOP is only available in tape and reel.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP1177/OP2177/OP4177 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Temperature Package Package
Model Range Description Option Branding
OP1177AR –40°C to +125°C8-Lead SOIC R-8
OP1177AR-REEL –40°C to +125°C8-Lead SOIC R-8
OP1177AR-REEL7 –40°C to +125°C8-Lead SOIC R-8
OP1177ARM-R2 –40°C to +125°C8-Lead MSOP RM-8 AZA
OP1177ARM-REEL –40°C to +125°C8-Lead MSOP RM-8 AZA
OP2177AR –40°C to +125°C8-Lead SOIC R-8
OP2177AR-REEL –40°C to +125°C8-Lead SOIC R-8
OP2177AR-REEL7 –40°C to +125°C8-Lead SOIC R-8
OP2177ARM-R2 –40°C to +125°C8-Lead MSOP RM-8 B2A
OP2177ARM-REEL –40°C to +125°C8-Lead MSOP RM-8 B2A
OP4177AR –40°C to +125°C14-Lead SOIC R-14
OP4177AR-REEL –40°C to +125°C14-Lead SOIC R-14
OP4177AR-REEL7 –40°C to +125°C14-Lead SOIC R-14
OP4177ARU –40°C to +125°C14-Lead TSSOP RU-14
OP4177ARU-REEL –40°C to +125°C14-Lead TSSOP RU-14
REV. C –5–
OP1177/OP2177/OP4177
INPUT OFFSET VOLTAGE – V
NUMBER OF AMPLIFIERS
50
15
0
ⴚ40 40
ⴚ30 ⴚ20 ⴚ10 02030
V
SY
= ⴞ15V
10
45
20
10
5
30
25
40
35
TPC 1. Input Offset Voltage
Distribution
LOAD CURRENT – mA
⌬OUTPUT VOLTAGE – V
1.8
0.8
00.001 0.01 10
0.1 1
0.4
V
SY
= ⴞ15V
T
A
= 25ⴗC
0.2
0.6
1.0
SINK
SOURCE
1.4
1.6
1.2
TPC 4. Output Voltage to Supply
Rail vs. Load Current
CLOSED-LOOP GAIN – dB
120
100
ⴚ80
80
60
40
20
0
ⴚ20
ⴚ40
ⴚ60
FREQUENCY – Hz
1k 10k 100M
100k 1M 10M
V
SY
= ⴞ15V
V
IN
= 4mV p-p
C
L
= 0
R
L
=
A
V
= 100
A
V
= 10
A
V
= 1
TPC 7. Closed-Loop Gain vs.
Frequency
TCV
OS
– V/ⴗC
NUMBER OF AMPLIFIERS
90
30
00.05 0.15 0.25 0.35 0.45 0.55
40
20
10
60
50
80
70
V
SY
= ⴞ15V
TPC 2. Input Offset Voltage
Drift Distribution
TEMPERATURE –ⴗC
INPUT BIAS CURRENT – nA
3
ⴚ3
ⴚ50 150
050100
2
0
ⴚ1
ⴚ2
VSY = ⴞ15V
1
TPC 5. Input Bias Current vs.
Temperature
OUTPUT IMPEDANCE – ⍀
500
450
0
400
350
300
250
200
150
100
50
FREQUENCY –Hz
100 1k 10k 100k 1M
VSY = ⴞ15V
VIN = 50mV p-p
AV = 100
AV = 10
AV = 1
TPC 8. Output Impedance vs.
Frequency
INPUT BIAS CURRENT – nA
NUMBER OF AMPLIFIERS
140
00.6
0.1 0.2 0.3 0.5
120
80
60
40
20
100
00.4
V
SY
= ⴞ15V
0.7
TPC 3. Input Bias Current
Distribution
VSY = ⴞ15V
CL = 0
RL =
FREQUENCY – Hz
PHASE SHIFT – Degrees
180
90
0
–90
270
100k 1M 10M
GAIN
PHASE
OPEN-LOOP GAIN – dB
60
50
40
30
20
10
0
ⴚ10
ⴚ20
225
135
45
–45
TPC 6. Open-Loop Gain and
Phase Shift vs. Frequency
VSY = ⴞ15V
CL = 300pF
RL = 2k⍀
VIN = 4V
AV = 1
TIME – 100s/DIV
VOLTAGE – 1V/DIV
GND
TPC 9. Large Signal Transient
Response
Typical Performance Characteristics–
REV. C
OP1177/OP2177/OP4177
–6–
TIME – 100s/DIV
VOLTAGE – 100mV/DIV
V
SY
= ⴞ15V
C
L
= 1,000pF
R
L
= 2k⍀
V
IN
= 100mV
A
V
= 1
GND
TPC 10. Small Signal Transient
Response
0V
15V
TIME – 4s/DIV
INPUT
OUTPUT
VSY = ⴞ15V
RL = 10k⍀
AV = ⴚ100
VIN = 200mV
ⴚ200mV
0V
TPC 13. Negative Overvoltage
Recovery
TIME – 1s/DIV
VNOISE – 0.2V/DIV
VSY = ⴞ15V
TPC 16. 0.1 Hz to 10 Hz Input
Voltage Noise
+OS
CAPACITANCE – pF
SMALL SIGNAL OVERSHOOT – %
110 10
k
100
V
SY
= ⴞ15V
R
L
= 2k⍀
V
IN
= 100mV p-p
50
45
0
40
35
30
25
20
15
10
5
1k
ⴚOS
TPC 11. Small Signal Overshoot vs.
Load Capacitance
FREQUENCY – Hz
CMRR – dB
0
10 10k 10M
140
120
100
80
60
40
20
100 1k 100k 1M
VSY = ⴞ15V
TPC 14. CMRR vs. Frequency
VOLTAGE NOISE DENSITY – nV/ Hz
FREQUENCY – Hz
2
0 25050 100 150 200
4
6
8
10
12
14
16
18
VSY = ⴞ15V
TPC 17. Voltage Noise Density
0V
ⴚ15V
TIME – 10s/DIV
INPUT
OUTPUT
V
SY
= ⴞ15V
R
L
= 10k⍀
A
V
= ⴚ100
V
IN
= 200mV
+200mV
0V
TPC 12. Positive Overvoltage
Recovery
FREQUENCY – Hz
PSRR – dB
0
10 10k 10M
140
120
100
80
60
40
20
100 1k 100k 1M
+PSRR
ⴚPSRR
VSY = ⴞ15V
TPC 15. PSRR vs. Frequency
VSY = ⴞ15V
ⴚISC
TEMPERATURE –ⴗC
SHORT CIRCUIT CURRENT – mA
35
0
ⴚ50 150
050100
30
5
25
20
15
10
ⴙISC
TPC 18. Short Circuit Current vs.
Temperature
REV. C –7–
OP1177/OP2177/OP4177
VSY = ⴞ15V
ⴚVOL
TEMPERATURE –ⴗC
OUTPUT VOLTAGE SWING – V
14.40
14.00
ⴚ50 150
050100
14.30
14.05
14.25
14.20
14.15
14.10
ⴙVOH
14.35
TPC 19. Output Voltage Swing vs.
Temperature
TEMPERATURE –ⴗC
CMRR – dB
123
ⴚ50 150
050100
127
125
V
SY
= ⴞ15V
128
129
124
126
130
131
132
133
TPC 22. CMRR vs. Temperature
LOAD CURRENT – mA
⌬OUTPUT VOLTAGE – V
1.4
0.8
0
0.001 0.01 10
0.1 1
0.4
V
SY
= ⴞ5V
T
A
= 25ⴗC
0.2
0.6
1.0
SINK
SOURCE
1.2
TPC 25. Output Voltage to
Supply Rail vs. Load Current
TIME FROM POWER SUPPLY TURN-ON – Sec
⌬OFFSET VOLTAGE – V
0
ⴚ0.5 0 140
20 40 60 80 120
0.1
ⴚ0.1
V
SY
= ⴞ15V
ⴚ0.4
ⴚ0.3
ⴚ0.2
0.5
0.4
0.3
0.2
100
TPC 20. Warm-Up Drift
TEMPERATURE –ⴗC
PSRR – dB
123
ⴚ50 150
050100
130
127
V
SY
= ⴞ15V
132
133
125
129
124
126
128
131
TPC 23. PSRR vs. Temperature
VSY = ⴞ5V
CL = 0
RL =
OPEN-LOOP GAIN – dB
60
50
40
30
20
10
0
ⴚ10
ⴚ20
FREQUENCY – Hz
PHASE SHIFT – Degrees
180
135
90
45
0
–45
225
100k 1M
GAIN
PHASE
10M
270
–90
TPC 26. Open-Loop Gain and Phase
Shift vs. Frequency
TEMPERATURE –ⴗC
INPUT OFFSET VOLTAGE – V
0
ⴚ50 150
050100
12
8
4
V
SY
= ⴞ15V
14
18
2
6
10
16
TPC 21.
|
V
OS
|
vs. Temperature
ⴚ40 40
ⴚ30 ⴚ20 ⴚ10 02030
V
SY
= ⴞ15V
10
INPUT OFFSET VOLTAGE – V
NUMBER OF AMPLIFIERS
50
15
0
45
20
10
5
30
25
40
35
V
SY
= ⴞ5V
TPC 24. Input Offset Voltage
Distribution
CLOSED-LOOP GAIN – dB
120
100
ⴚ80
80
60
40
20
0
ⴚ20
ⴚ40
ⴚ60
FREQUENCY –Hz
1k 10k 100M
100k
A
V
= 100
1M 10M
V
SY
= ⴞ5V
V
IN
= 4mV p-p
C
L
= 0
R
L
=
A
V
= 10
A
V
= 1
TPC 27. Closed-Loop Gain vs.
Frequency
REV. C
OP1177/OP2177/OP4177
–8–
OUTPUT IMPEDANCE – ⍀
500
450
0
400
350
300
250
200
150
100
50
FREQUENCY –Hz
100 1k 10k 100k 1M
V
SY
= ⴞ5V
V
IN
= 50mV p-p
A
V
= 100
A
V
= 10 A
V
= 1
TPC 28. Output Impedance vs.
Frequency
CAPACITANCE – pF
SMALL SIGNAL OVERSHOOT – %
110 10
k
100
V
SY
= ⴞ5V
R
L
= 2k⍀
V
IN
= 100mV
50
45
0
40
35
30
25
20
15
10
5
1k
+OS
ⴚOS
TPC 31. Small Signal Overshoot vs.
Load Capacitance
TIME – 200s/DIV
VOLTAGE – 2V/DIV
INPUT V
S
= ⴞ5V
A
V
= 1
R
L
= 10k⍀
OUTPUT
GND
TPC 34. No Phase Reversal
V
SY
= ⴞ5V
C
L
= 300pF
R
L
= 2k⍀
V
IN
= 1V
A
V
= 1
TIME – 100s/DIV
VOLTAGE – 1V/DIV
GND
TPC 29. Large Signal
Transient Response
0V
ⴚ5V
TIME – 4s/DIV
INPUT
OUTPUT
VSY = ⴞ5V
RL = 10k⍀
AV = ⴚ100
VIN = 200mV
+200mV
0V
TPC 32. Positive Overvoltage
Recovery
FREQUENCY – Hz
CMRR – dB
0
10 10k 10M
140
120
100
80
60
40
20
100 1k 100k 1M
V
SY
= ⴞ5V
TPC 35. CMRR vs. Frequency
V
SY
= ⴞ5V
C
L
= 1,000pF
R
L
= 2k⍀
V
IN
= 100mV
A
V
= 1
TIME – 10s/DIV
VOLTAGE – 50mV/DIV
GND
TPC 30. Small Signal
Transient Response
0V
5V
TIME – 4s/DIV
INPUT
OUTPUT
V
SY
= ⴞ5V
R
L
= 10k⍀
A
V
= ⴚ100
V
IN
= 200mV
ⴚ200mV
0V
TPC 33. Negative Overvoltage
Recovery
FREQUENCY – Hz
PSRR – dB
010 10k 10M
200
120
100
80
60
40
20
100 1k 100k 1M
+PSRR
ⴚPSRR
V
SY
= ⴞ5V
180
160
140
TPC 36. PSRR vs. Frequency
REV. C –9–
OP1177/OP2177/OP4177
TIME – 1s/DIV
V
NOISE
– 0.2V/DIV
V
SY
= ⴞ5V
TPC 37. 0.1 Hz to 10 Hz Input Voltage
Noise
V
SY
= ⴞ5V
ⴚV
OL
TEMPERATURE –ⴗC
OUTPUT VOLTAGE SWING – V
4.40
4.00
ⴚ50 150
050100
4.30
4.05
4.25
4.20
4.15
4.10
ⴙV
OH
4.35
TPC 40. Output Voltage Swing vs.
Temperature
SUPPLY VOLTAGE – V
SUPPLY CURRENT – A
450
005 35
10 15 20 25 30
300
200
150
100
50
250
T
A
= 25ⴗC
400
350
TPC 43. Supply Current vs. Supply
Voltage
V
SY
= ⴞ5V
VOLTAGE NOISE DENSITY – nV/ Hz
FREQUENCY – Hz
2
0 25050 100 150 200
4
6
8
10
12
14
16
18
TPC 38. Voltage Noise Density
TEMPERATURE –ⴗC
INPUT OFFSET VOLTAGE – V
0
ⴚ50 150
050100
15
10
5
V
SY
= ⴞ5V
20
25
TPC 41.
|
V
OS
|
vs. Temperature
FREQUENCY – Hz
CHANNEL SEPARATION – dB
ⴚ20
ⴚ16010 100 1M
1k 10k 100k
ⴚ40
ⴚ60
ⴚ140
ⴚ80
ⴚ100
ⴚ120
0
TPC 44. Channel Separation vs.
Frequency
V
SY
= ⴞ5V
ⴚI
SC
TEMPERATURE –ⴗC
SHORT CIRCUIT CURRENT – mA
35
0
ⴚ50 150
050100
30
5
25
20
15
10
ⴙI
SC
TPC 39. Short Circuit Current vs.
Temperature
TEMPERATURE –ⴗC
SUPPLY CURRENT – A
600
0
ⴚ50 150
050100
500
300
V
SY
= ⴞ15V
400
200
100
V
SY
= ⴞ5V
TPC 42. Supply Current vs.
Temperature
REV. C
OP1177/OP2177/OP4177
–10–
FUNCTIONAL DESCRIPTION
OP1177 is the fourth generation of ADI’s industry-standard OP07
amplifier family. OP1177 is a very high precision, low noise opera-
tional amplifier with the highly desirable combination of extremely
low offset voltage and very low input bias currents. Unlike JFET
amplifiers, the low bias and offset currents are relatively insensitive
to ambient temperatures, even up to 125∞C.
For the first time, Analog Devices’ proprietary process technology
and linear design expertise have produced a high voltage
amplifier with superior performance to the OP07, OP77, and
OP177 in a tiny MSOP 8-lead package. Despite its small size,
the OP1177 offers numerous improvements including low wide-
band noise, very wide input and output voltage range, lower
input bias current, and complete freedom from phase inversion.
OP1177 has the widest specified operating temperature range of
any similar device in a plastic surface-mount package. This is
increasingly important as PC board and overall system sizes
continue to shrink, causing internal system temperatures to rise.
Power consumption is reduced by a factor of four from the OP177
while bandwidth and slew rate increase by a factor of two. The low
power dissipation and very stable performance versus temperature
also act to reduce warm-up drift errors to insignificant levels.
Open-loop gain linearity under heavy loads is superior to competitive
parts like OPA277, improving dc accuracy and reducing distortion
in circuits with high closed-loop gains. Inputs are internally protected
from overvoltage conditions referenced to either supply rail.
Like any high performance amplifier, maximum performance is
achieved by following appropriate circuit and PC board guidelines.
The following sections provide practical advice on getting the most
out of the OP1177 under a variety of application conditions.
Total Noise Including Source Resistors
The low input current noise and input bias current of the OP1177
make it useful for circuits with substantial input source resistance.
Input offset voltage increases by less than 1 mV max per 500 W
of source resistance.
The total noise density of the OP1177 is
eeiRTR
nTOTAL nnS S
,
=+
()
+
22
4k
Where, e
n
is the input voltage noise density
i
n
is the input current noise density
R
S
is the source resistance at the noninverting terminal
k is Boltzman’s constant (1.38 10
–23
J/K)
T is the ambient temperature in Kelvin (T = 273 + ∞C)
For R
S
< 3.9 kW, e
n
dominates and
ee
n TOTAL n,
ª
For 3.9 kW < R
S
< 412 kW, voltage noise of the amplifier, current
noise of the amplifier translated through the source resistor, and
thermal noise from the source resistor all contribute to the total
noise.
For R
S
> 412 kW, the current noise dominates and
eiR
nTOTAL n S,
ª
The total equivalent rms noise over a specific bandwidth is
expressed as
Ee BW
nnTOTAL
=
()
,
Where BW is the bandwidth in Hertz.
NOTE: The above analysis is valid for frequencies larger than
50 Hz. When considering lower frequencies, flicker noise (also
known as 1/f noise) must be taken into account.
For a reference on noise calculations refer to Bandpass KRC or
Sallen-Key Filter section.
Gain Linearity
Gain linearity reduces errors in closed-loop configurations. The
straighter the gain curve, the lower the maximum error over the
input signal range will be. This is especially true for circuits with
high closed-loop gains.
The OP1177 has excellent gain linearity even with heavy loads,
shown in Figure 1. Compare its performance to the OPA277,
shown in Figure 2. Both devices were measured under identical
conditions with R
L
= 2 kW. The OP2177 (dual) has virtually no
distortion at lower voltages. It was compared to the OPA277 at
several supply voltages and various loads. Its performance far
exceeded that of its counterpart.
SCALE – V
V
SY
= ⴞ15V
R
L
= 2k⍀
OP1177
SCALE – V
Figure 1. Gain Linearity
SCALE – V
NEED LABEL FOR THIS AXIS
VSY = ⴞ15V
RL = 2k⍀
OPA277
SCALE – V
Figure 2. Gain Linearity
Input Overvoltage Protection
When their input voltage exceeds the positive or negative supply
voltage, most amplifiers require external resistors to protect them
from damage.
The OP1177 has internal protective circuitry that allows volt-
ages as high as 2.5 V beyond the supplies to be applied at the
input of either terminal without any harmful effects.
REV. C
OP1177/OP2177/OP4177
–11–
Use an additional resistor in series with the inputs if the voltage
exceeds the supplies by more than 2.5 V. The value of the resis-
tor can be determined from the formula
VV
R
IN S
S
-
()
+£
500 5
WmA
With the OP1177’s low input offset current of <1 nA max, placing
a 5 kW resistor in series with both inputs adds less than 5 mV to
input offset voltage and has a negligible impact on the overall
noise performance of the circuit.
5 kW will protect the inputs to more than 27 V beyond either supply.
Refer to the THD + N section for additional information on
noise versus source resistance.
Output Phase Reversal
Phase reversal is defined as a change of polarity in the amplifier
transfer function. Many operational amplifiers exhibit phase reversal
when the voltage applied to the input is greater than the maxi-
mum common-mode voltage. In some instances this can cause
permanent damage to the amplifier. In feedback loops, it can
result in system lockups or equipment damage. The OP1177 is
immune to phase reversal problems even at input voltages beyond
the supplies.
VOLTAGE – 5V/DIV
V
OUT
V
IN
V
SY
= ⴞ10V
A
V
= 1
TIME – 400s/DIV
Figure 3. No Phase Reversal
Settling Time
Settling time is defined as the time it takes an amplifier output
to reach and remain within a percentage of its final value after
application of an input pulse. It is especially important in mea-
surement and control circuits where amplifiers buffer A/D inputs
or DAC outputs.
To minimize settling time in amplifier circuits, use proper bypassing
of power supplies and an appropriate choice of circuit components.
Resistors should be metal film types as these have less stray
capacitance and inductance than their wire-wound counterparts.
Capacitors should be polystyrene or polycarbonate types to
minimize dielectric absorption.
The leads from the power supply should be kept as short as
possible to minimize capacitance and inductance. The OP1177
has a settling time of about 45 ms to 0.01% (1 mV) with a 10 V
step applied to the input in a noninverting unity gain.
Overload Recovery Time
Overload recovery is defined as the time it takes the output voltage
of an amplifier to recover from a saturated condition to its linear
response region. A common example is where the output voltage
demanded by the circuit’s transfer function lies beyond the maxi-
mum output voltage capability of the amplifier. A 10 V input
applied to an amplifier in a closed-loop gain of 2 will demand an
output voltage of 20 V. This is beyond the output voltage range of
the OP1177 when operating at ±15 V supplies and will force the
output into saturation.
Recovery time is important in many applications, particularly where
the op amp must amplify small signals in the presence of large
transient voltages.
10k⍀
100k⍀
R2
1k⍀
R1
V+
1
4
2
3
7
OP1177
+
ⴚ
Vⴚ
V
OUT
200mV
Figure 4. Test Circuit for Overload Recovery Time
TPC 12 shows the positive overload recovery time of the OP1177.
The output recovers in less than 4 ms after being overdriven by
more than 100%.
The negative overload recovery of the OP1177 is 1.4 ms as seen
in TPC 13.
THD + Noise
The OP1177 has very low total harmonic distortion. This indicates
excellent gain linearity and makes the OP1177 a great choice for
high closed-loop gain precision circuits.
Figure 5 shows that the OP1177 has approximately 0.00025%
distortion in unity gain, the worst-case configuration for distortion.
FREQUENCY – Hz
0.1
0.01
0.000120 100
THD + N – %
1k
0.001
6k
VSY = ⴞ15V
RL = 10k⍀
BW = 22kHz
Figure 5. THD + N vs. Frequency
Capacitive Load Drive
OP1177 is inherently stable at all gains and capable of driving
large capacitive loads without oscillation. With no external com-
pensation, the OP1177 will safely drive capacitive loads up to
1000 pF in any configuration. As with virtually any amplifier,
driving larger capacitive loads in unity gain requires additional
circuitry to assure stability.
In this case, a “snubber network” is used to prevent oscillation
and reduce the amount of overshoot. A significant advantage of
this method is that it does not reduce the output swing because
the resistor R
S
is not inside the feedback loop.
REV. C
OP1177/OP2177/OP4177
–12–
Figure 6 is a scope photograph of the output of the OP1177 in
response to a 400 mV pulse. The load capacitance is 2 nF. The
circuit is configured in positive unity gain, the worst-case condition
for stability.
As shown in Figure 8, placing an R-C network parallel to the
load capacitance C
L
will allow the amplifier to drive higher
values of C
L
without causing oscillation or excessive overshoot.
There is no ringing and overshoot is reduced from 27% to 5%
using the snubber network.
Optimum values for R
S
and C
S
are tabulated in Table I for several
capacitive loads up to 200 nF. Values for other capacitive loads
can be determined experimentally.
Table I. Optimum Values for Capacitive Loads
C
L
(nF) R
S
(⍀)C
S
10 20 0.33 mF
50 30 6.8 nF
200 200 0.47 mF
0
0
0
000
VOLTAGE – 200mV/DIV
00000000
0
0
0
0
0
0
GND
V
SY
= ⴞ5V
R
L
= 10k⍀
C
L
= 2nF
TIME – 10s/DIV
Figure 6. Capacitive Load Drive without Snubber
0
0
0
000
VOLTAGE – 200mV/DIV
00000000
0
0
0
0
0
0
GND
V
SY
= ⴞ5V
R
L
= 10k⍀
R
S
= 200⍀
C
L
= 2nF
C
S
= 0.47F
TIME – 10s/DIV
Figure 7. Capacitive Load Drive with Snubber
RS
V+
Vⴚ
1
4
2
3
7OP1177
CS
CL
400mV +
ⴚ
VOUT
Figure 8. Snubber Network Configuration
CAUTION: The snubber technique cannot recover the loss of
bandwidth induced by large capacitive loads.
Stray Input Capacitance Compensation
The effective input capacitance in an op amp circuit, C
t
, con-
sists of three components. These are the internal differential
capacitance between the input terminals; the internal common
mode capacitance of each input to ground; and the external
capacitance including parasitic capacitance. In the circuit in
Figure 9, the closed-loop gain increases as the signal frequency
increases.
The transfer function of the circuit is
11++
()
R2
R1 sC R1
t
indicating a zero at
sR2 R1
R2R1C R1 / R2 C
tt
=+=
()
1
2p
Depending on the value of R1
and R2, the cutoff frequency of the
closed-loop gain may be well below the crossover frequency. In
this case, the phase margin, F
m,
can be severely degraded resulting
in excessive ringing or even oscillation.
A simple way to overcome this problem is to insert a capacitor in
the feedback path as shown in Figure 10.
The resulting pole can be positioned to adjust the phase margin.
Setting C
f
= (R1/R2)C
t
, achieves a phase margin of 90∞.
V
OUT
R2
V+
Vⴚ
1
4
2
3
OP1177
R1
Ct
V1
7
+
–
Figure 9. Stray Input Capacitance
VOUT
R2
V+
Vⴚ
1
4
2
3
OP1177
R1
Ct
V1
7
Cf
+
–
Figure 10. Compensation Using Feedback Capacitor
REV. C
OP1177/OP2177/OP4177
–13–
Reducing Electromagnetic Interference
A number of methods can be utilized to reduce the effects of
EMI on amplifier circuits.
In one method, stray signals on either input are coupled to the
opposite input of the amplifier. The result is that the signal is
rejected according to the amplifier’s CMRR.
This is usually achieved by inserting a capacitor between the inputs
of the amplifier as shown in Figure 11. However, this method may
also cause instability depending on the value of capacitance.
V
OUT
R2
V+
Vⴚ
1
4
2
3
OP1177
R1
C
V1
7
+
–
Figure 11. EMI Reduction
Placing a resistor in series with the capacitor (Figure 12) increases
the dc loop gain and reduces the output error. Positioning the
breakpoint (introduced by R-C) below the secondary pole of the
op amp improves the phase margin and hence stability.
R can be chosen independently of C for a specific phase margin
according to the formula
RR2
ajf
R2
R1
2
=−+
1
where a is the open-loop gain of the amplifier and f
2
is the frequency
at which the phase of a = Φ
m
– 180°.
V
OUT
1
4
2
3
OP1177
7
V+
R
C
R1
R2
V1
Vⴚ
+
–
Figure 12. Compensation Using Input RC Network
Proper Board Layout
The OP1177 is a high precision device. In order to ensure optimum
performance at the PC board level, care must be taken in the design
of the board layout.
To avoid leakage currents, the surface of the board should be kept
clean and free of moisture. Coating the surface creates a barrier to
moisture accumulation and helps reduce parasitic resistance on
the board.
Keeping supply traces short and properly bypassing the power
supplies will minimize power supply disturbances due to output
current variation, such as when driving an ac signal into a heavy
load. Bypass capacitors should be connected as closely as pos-
sible to the device supply pins. Stray capacitances are a concern
at the output and the inputs of the amplifier. It is recommended
that signal traces be kept at least 5 mm from supply lines to
minimize coupling.
A variation in temperature across the PC board can cause a
mismatch in the Seebeck voltages at solder joints and other
points where dissimilar metals are in contact, resulting in thermal
voltage errors. To minimize these thermocouple effects, resistors
should be oriented so heat sources warm both ends equally.
Input signal paths should contain matching numbers and types
of components where possible in order to match the number
and type of thermocouple junctions. For example, dummy com-
ponents such as zero value resistors can be used to match real
resistors in the opposite input path. Matching components
should be located in close proximity and should be oriented in
the same manner. Leads should be of equal length so that ther-
mal conduction is in equilibrium. Heat sources on the PC board
should be kept as far away from amplifier input circuitry as
practical.
The use of a ground plane is highly recommended. A ground
plane reduces EMI noise and also helps to maintain a constant
temperature across the circuit board.
Difference Amplifiers
Difference amplifiers are used in high accuracy circuits to improve
the common-mode rejection ratio (CMRR).
100k⍀
R2
R1
V+
1
4
2
3
7
OP1177
Vⴚ
V
OUT
V1
V2
R3 = R1 R4 = R1
R4
R3 =R2
R1
Figure 13. Difference Amplifier
In the single instrumentation amplifier (circuit in Figure 13),
where
R4
R3
R2
R1
=
VR2
R1
VV
O21
=−
()
a mismatch between the ratio R2/R1
and R4/R3
will cause the
common-mode rejection ratio to be reduced. To better under-
stand this effect, consider the following:
By definition
CMRR A
A
DM
CM
=
where ADM is the differential gain and ACM is the common-mode
gain.
AV
VAV
V
DM
O
DIFF
CM
O
CM
==and
REV. C
OP1177/OP2177/OP4177
–14–
VVVV VV
DIFF 1 2 CM 1 2
=− = +
()
and 1
2
In order for this circuit to act as a difference amplifier, its output
must be proportional to the differential input signal.
From Figure 13,
VR2
R1 V
R2
R1
R3
R4
V
O1 2
=−
+
+
+
1
1
Arranging terms and combining the equations above yields:
CMRR R4R1 R3R2 R4R2
R4R1 R2R3
=++
−
2
22
(1)
The sensitivity of CMRR with respect to the R1 is obtained by
taking the derivative of CMRR, in Equation 1, with respect to R1.
δ
δ
δ
δ
CMRR
R1 R1
R1R4
R1R4 R2R3
R2R4 R2R3
R1R4 R2R3
=−++
−
22
2
22
δ
δ
CMRR
R1 R2R3
R1R4
=
−
()
1
22
Assuming that R1
≈ R2
≈ R3
≈ R4
≈ R and
R(1 – δ) < R1, R2, R3, R4 < R(1 + δ).
The worst-case CMRR error arises when
R1
= R4
= R(1 + δ) and R2
= R3
= R(1 – δ). Plugging these
values into Equation 1 yields
CMRR
MIN
≅1
2δ
where δ is the tolerance of the resistors.
Lower tolerance value resistors result in higher common-mode
rejection (up to the CMRR of the op amp).
Using 5% tolerance resistors, the highest CMRR that can be
guaranteed is 20 dB. On the other hand, using 0.1% tolerance
resistors would result in a common-mode rejection ratio of at
least 54 dB (assuming that the op amp CMRR 54 dB).
With the CMRR of OP1177 at 120 dB minimum, the resistor
match will be the limiting factor in most circuits. A trimming
resistor can be used to further improve resistor matching and
CMRR of the difference amp circuit.
A High Accuracy Thermocouple Amplifier
A thermocouple consists of two dissimilar metal wires placed in
contact. The dissimilar metals produce a voltage
VTT
TC R
=−
()
α
J
where T
J
is the temperature at the measurement of the hot junction,
T
R
is the temperature at the cold junction, and is the Seebeck
coefficient specific to the dissimilar metals used in the thermocouple.
V
TC
is the
thermocouple voltage. V
TC
becomes larger with increasing
temperature.
Maximum measurement accuracy requires cold junction compen-
sation of the thermocouple as described below.
To perform the cold junction compensation, apply a copper
wire short across the terminating junctions (inside the isothermal
block) simulating a 0°C point. Adjust the output voltage to zero
using the trimming resistor R5 and then remove the copper wire.
The OP1177 is an ideal amplifier for thermocouple circuits since
it has a very low offset voltage, excellent PSRR and CMRR, and
low noise at low frequencies.
It can be used to create a thermocouple circuit with great linearity.
Resistors R1 and R2 and diode D1 shown in Figure 14 are
mounted in an isothermal block.
R1
50⍀
VOUT
R9
200k⍀
ⴚ15V
+15V
1
4
2
3
OP1177
7
(+)
TJ
(ⴚ)
0.1F
10F
10F
0.1F
10F
R5
100⍀
R4
50⍀
R7
80.6k⍀
R6
50⍀
R3
47k⍀
10F
R2
4.02k⍀R8
1k⍀
Cu
Cu
TR
TR
ISOTHERMAL
BLOCK
VTC
D1
D1
ADR293
VCC
C1
2.2F
Figure 14. Type K Thermocouple Amplifier Circuit
Low Power Linearized RTD
A common application for a single element varying bridge is an
RTD thermometer amplifier as shown in Figure 15. The excita-
tion is delivered to the bridge by a 2.5 V reference applied at the
top of the bridge.
RTDs may have thermal resistance as high as 0.5°C to 0.8°C
per mW. In order to minimize errors due to resistor drift, the
current through each leg of the bridge must be kept low. In this
circuit, the amplifier supply current flows through the bridge.
However, at the OP1177 maximum supply current of 600 µA,
the RTD dissipates less than 0.1 mW of power even at the high-
est resistance. Errors due to power dissipation in the bridge are
kept under 0.1°C.
Calibration of the bridge can be made at the minimum value
of temperature to be measured by adjusting R
P
until the out-
put is zero.
To calibrate the output span, set the full-scale and linearity
potentiometers to midpoint and apply a 500°C temperature to
the sensor or substitute the equivalent 500°C RTD resistance.
Adjust the full-scale pot for a 5 V output. Finally, apply 250°C
or the equivalent RTD resistance and adjust the linearity poten-
tiometer for 2.5 V output.
The circuit achieves better than ±0.5°C accuracy after adjustment.
REV. C
OP1177/OP2177/OP4177
–15–
200⍀
+15V
ⴚ15V
7
4
6
5
81/2 OP2177
VOUT
500⍀
4.37k⍀
100⍀
100⍀20⍀
4.12k⍀
4.12k⍀
5k⍀
49.9k⍀
ADR421
+15V
0.1F
+15V
ⴚ15V
1
4
2
3
8
VOUT
100⍀
RTD
1/2 OP2177
Figure 15. Low Power Linearized RTD Circuit
Single Op Amp Bridge
The low input offset voltage drift of the OP1177 makes it very
effective for bridge amplifier circuits used in RTD signal condi-
tioning. It is often more economical to use a single bridge op amp
as opposed to an instrumentation amplifier.
In the circuit of Figure 16, the output voltage at the op amp is
VR2
RVR1
R
R1
R2
O REF
=
++
Ê
Ë
Áˆ
¯
˜+
()
Ê
Ë
Á
Á
Á
Á
ˆ
¯
˜
˜
˜
˜
È
Î
Í
Í
Í
Í
Í
˘
˚
˙
˙
˙
˙
˙
d
d11
where d = DR/R is the fractional deviation of the RTD resis-
tance with respect to the bridge resistance due to the change in
temperature at the RTD.
For d << 1, the expression above becomes
VR2
RVR1
R
R1
R2
R2
R
R1
R2
R1
R2 V
O REF REF
@Ê
Ë
Áˆ
¯
˜++
Ê
Ë
Á
Á
Á
ˆ
¯
˜
˜
˜
=Ê
Ë
Áˆ
¯
˜+
Ê
Ë
Áˆ
¯
˜+Ê
Ë
Áˆ
¯
˜
È
Î
͢
˚
˙
dd
1
1
With V
REF
constant, the output voltage is linearly proportional to
d with a gain factor of
VR2
R
R1
R2
R1
R2
REF
Ê
Ë
Áˆ
¯
˜+
Ê
Ë
Áˆ
¯
˜+Ê
Ë
Áˆ
¯
˜
È
Î
͢
˚
˙
1
VOUT
1
4
2
3
OP1177
7
V+
Vⴚ
RF
RF
R
RR
R(1+␦)
ADR421
15V
0.1F
Figure 16. Single Bridge Amplifier
REALIZATION OF ACTIVE FILTERS
Bandpass KRC or Sallen-Key Filter
The low offset voltage and the high CMRR of the OP1177 make
it an excellent choice for precision filters such as the KRC filter
shown in Figure 17. This filter type offers the capability to tune
the gain and the cutoff frequency independently.
Since the common-mode voltage into the amplifier varies with the
input signal in the KRC filter circuit, a high CMRR is required to
minimize distortion. Also, the low offset voltage of the OP1177 allows
a wider dynamic range when the circuit gain is chosen to be high.
The circuit of Figure 17 consists of two stages. The first stage is
a simple high-pass filter whose corner frequency f
C
is
1
2pC1C2R1R2
(2)
and whose
QK
R1
R2
=
(3)
where K is the dc gain.
Choosing equal capacitor values minimizes the sensitivity and
simplifies Equation 2 to
1
2pC R1R2
The value of Q determines the peaking of the gain versus frequency
(ringing in transient response). Commonly chosen values for Q
are generally near unity.
Setting
Q=1
2
,
yields minimum gain peaking and minimum ringing.
Determine values for R1 and R2 by use of Equation 3.
For
Q=1
2
, R1/R2 = 2 in the circuit example. Pick R1 = 5 kW
and R2 = 10 kW for simplicity.
The second stage is a low-pass filter whose corner frequency can
be determined in a similar fashion. For R3
= R4
= R.
fC
RC3
C4
and Q C3
C4
==
1
2
1
2
p
Channel Separation
Multiple amplifiers on a single die are often required to reject
any signals originating from the inputs or outputs of adjacent
channels. OP2177 input and bias circuitry is designed to prevent
feedthrough of signals from one amplifier channel to the other. As
a result, the OP2177 has an impressive channel separation of
greater than –120 dB for frequencies up to 100 kHz and greater
than –115 dB for signals up to 1 MHz.
REV. C
OP1177/OP2177/OP4177
–16–
4
6
51/2 OP2177
8
V+
Vⴚ
V1
50mV
1
42
3
8
V+
Vⴚ
10k⍀
100⍀
7
1/2 OP2177
+
–
Figure 18. Channel Separation Test Circuit
7
4
6
5
1/2 OP2177
8
V+
Vⴚ
R2
10k⍀
R1
20k⍀
V1
1
4
2
3
1/2 OP2177
8
V+
Vⴚ
R3
33k⍀
R4
33k⍀
C4
330pF
C3
680pF
V
OUT
C2
10nF
C1
10nF
+
–
Figure 17. Two-Stage, Band-Pass Filter
SPICE Model
The SPICE macro-model for the OP1177 can be downloaded
from Analog Devices’ website at www.analog.com. This model
will accurately simulate a number of parameters, both dc and ac.
References on Noise Dynamics and Flicker Noise
S. Franco, Design with Operational Amplifiers and Analog Integrated
Circuits, McGraw-Hill 1998.
The Best of Analog Dialogue, Analog Devices, Inc.
REV. C
OP1177/OP2177/OP4177
–17–
OUTLINE DIMENSIONS
14-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COPLANARITY
0.10
14 8
7
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
8.75 (0.3445)
8.55 (0.3366)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
8ⴗ
0ⴗ
0.50 (0.0197)
0.25 (0.0098)ⴛ 45ⴗ
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AB
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) ⴛ 45ⴗ
8ⴗ
0ⴗ
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
85
41
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
0.80
0.60
0.40
8ⴗ
0ⴗ
85
4
1
4.90
BSC
PIN 1
0.65 BSC
3.00
BSC
SEATING
PLANE
0.15
0.00
0.38
0.22
1.10 MAX
3.00
BSC
COPLANARITY
0.10
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MO-187AA
14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
4.50
4.40
4.30
14 8
71
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65
BSC
SEATING
PLANE
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09
8ⴗ
0ⴗ
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
COPLANARITY
0.10
REV. C
OP1177/OP2177/OP4177
–18–
Revision History
Location Page
4/04—Data Sheet changed from REV. B to REV. C.
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to TPC 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to TPC 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4/02—Data Sheet changed from REV. A to REV. B.
Added OP4177 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ELECTRICAL CHARACTERISTICS headings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
11/01—Data Sheet changed from REV. 0 to REV. A.
Edit to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to TPC 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
–19–
–20–
C02627–0–4/04(C)