LM48560 November 10, 2011
High Voltage Class H Ceramic Speaker Driver with
Automatic Level Control
General Description
The LM48560 is a high voltage, high efficiency, Class H driver
for ceramic speakers and piezo actuators. The LM48560’s
Class H architecture offers significant power savings com-
pared to traditional Class AB amplifiers. The device provides
30VP-P output drive while consuming just 4mA of quiescent
current from a 3.6V supply.
The LM48560 features National’s unique automatic level con-
trol (ALC) that provides output limiter functionality. The
LM48560 features two fully differential inputs with separate
gain settings, and a selectable control interface. In software
control mode, the gain control and device modes are config-
ured through the I2C interface. In hardware control mode, the
gain and input mux are configured through a pair of logic in-
puts.
The LM48560 has a low power shutdown mode that reduces
quiescent current consumption to 0.1μA. The LM48560 is a
available in an ultra-small 16–bump micro SMD package
(1.97mm x 1.97mm).
Key Specifications
■ Output Voltage at VDD = 3.6V
RL = 1.5μF+10Ω, THD+N ≤ 1% 30VP-P (typ)
■ Quiescent Power Supply Current
at 3.6V (ALC enabled) 4mA (typ)
■ Power Dissipation at 25VP-P 1W (typ)
■ Shutdown current 0.1μA (typ)
Features
■Class H Topology
■Integrated Boost Converter
■Bridge-Tied Load (BTL) Output
■Selectable Differential Inputs
■Selectable Control Interfaces
(Hardware or Software mode)
■I2C Programmable ALC
■Low Supply Current
■Minimum External Components
■Micro-Power Shutdown
■Available in Space-Saving micro SMD Package
Applications
■Touch screen Smart Phones
■Tablet PCs
■Portable Electronic Devices
■MP3 Players
Typical Application
30150733
FIGURE 1. Typical Application Circuit
Boomer® is a registered trademark of National Semiconductor Corporation.
© 2011 Texas Instruments Incorporated 301507 www.ti.com
LM48560 High Voltage Class H Ceramic Speaker Driver with Automatic Level Control
Connection Diagrams
TL Package
1.97mm x 1.97mm x 0.6mm
30150704
Top View
Order Number LM48560TL
See NS Package Number TLA16Z1A
16–Bump micro SMD Marking
30150739
Top View
XY = Date code
TT = Die traceability
G = Boomer Family
XX = LM48560TL
Ordering Information
Ordering Information Table
Order Number Package
Package
Drawing
Number
Transport Media MSL Level Green Status
LM48560TL 16 Bump µSMD TLA16Z1A 250 units on tape and reel 1 RoHS & no Sb/Br
LM48560TLX 16 Bump µSMD TLA16Z1A 2500 units on tape and reel 1 RoHS & no Sb/Br
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LM48560
TABLE 1. Bump Descriptions
Bump Name Description
A1 OUT+ Amplifier Non-Inverting Output
A2 SGND Amplifier Ground
A3 IN1– Amplifier Inverting Input 1
A4 IN1+ Amplifier Non-Inverting Input 1
B1 OUT- Amplifier Inverting Output
B2 SHDN Active Low Shutdown. Connect SHDN to GND to disable device.
Connect SHDN to VDD for normal operation
B3 IN2– Amplifier Inverting Input 2
B4 IN2+ Amplifier Non-Inverting Input 2
C1 VBST Boost Converter Output
C2 SW/HW
Mode Selection Control:
SW/HW = 0 → Hardware Mode
SW/HW = 1 → Software Mode
C3 SCL/GAIN
I2C Serial Clock Input (Software Mode)
Gain Select Input (Hardware Mode)
see (Table 3)
C4 SDA/SEL
I2C Serial Data Input (Software Mode)
Amplifier Input Select (Hardware Mode)
see (Table 3)
D1 SET ALC Timing Input
D2 VDD Power Supply
D3 SW Boost Converter Switching Node
D4 PGND Boost Converter Ground
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LM48560
Absolute Maximum Ratings (Note 1, Note
2)
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
Supply Voltage (Note 1) 6V
SW Voltage 25V
VBST Voltage 21V
Input Voltage −0.3V to VDD + 0.3V
Power Dissipation (Note 3) Internally limited
ESD Rating, Human Body Model
(Note 4) 2kV
ESD Rating, Machine Model
(Note 5) 100V
ESD Rating, Charge Device Model
(Note 6) 500V
Storage Temperature −65°C to + 150°C
Junction Temperature 150°C
Thermal Resistance
θJA (TLA16Z1A) 55 °C/W
Soldering Information
See AN-1112 "Micro SMD Wafer Level Chip
Scale Package."
Operating Ratings
Temperature Range
TMIN ≤ TA ≤ TMAX −40°C ≤ TA ≤ +85°C
Supply Voltage
VDD 2.7V ≤ VDD ≤ 5.5V
Electrical Characteristics VDD = 3.6V (Note 1, Note 2)
The following specifications apply for RL = 1.5μF + 10Ω, CBST = 1μF, CIN = 0.47μF, AV = 24dB unless otherwise specified. Limits
apply for TA = 25°C.
Symbol Parameter Conditions
LM48560 Units
(Limits)
Min
(Note 8)
Typ
(Note 7)
Max
(Note 8)
VDD Supply Voltage Range 2.7 5.5 V
IDD Quiescent Power Supply Current
VIN = 0V, RL = ∞
ALC Enabled 4 6 mA
ALC Disabled 3.6 mA
PDPower Consumption VOUT = 25VP-P, f = 1kHz 1 W
ISD Shutdown Current Software Mode 2.5 4.4 µA
Hardware Mode 0.1 2 µA
TWU Wake-up Time From Shutdown 15 ms
VOS Differential Output Offset Voltage AV = 24V 10 90 mV
AV = 0dB (Boost Disabled) 5 20 mV
AV
Gain (Hardware Mode)
IN1
GAIN = 0
GAIN = 1
0.5
5.5
0
6
0.5
6.5
dB
dB
IN2
GAIN = 0
GAIN = 1
23.5
29.5
24
30
24.5
30.5
dB
dB
Gain (Software Mode)
Boost Disabled
GAIN1 = 0, GAIN0 = 0
GAIN1 = 0, GAIN0 = 1
GAIN1 = 1, GAIN0 = 0
GAIN1 = 1, GAIN0 = 1
–0.5
5.5
11.5
17.5
0
6
12
18
0.5
6.5
12.5
18.5
dB
dB
dB
dB
Boost Enabled
GAIN1 = 0, GAIN0 = 0
GAIN1 = 0, GAIN0 = 1
GAIN1 = 1, GAIN0 = 0
GAIN1 = 1, GAIN0 = 1
20.5
23.5
26.5
29.5
21
24
27
30
21.5
24.5
27.5
30.5
dB
dB
dB
dB
Gain Step Size
(Software Mode) 3 dB
RIN Input Resistance AV = 0dB
AV = 30dB
46
46
50
50
58
58
kΩ
kΩ
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LM48560
Symbol Parameter Conditions
LM48560 Units
(Limits)
Min
(Note 8)
Typ
(Note 7)
Max
(Note 8)
VOUT Output Voltage
THD+N = 1%
f = 200Hz
f = 1kHz 25
30
30
VP-P
VP-P
THD+N Total Harmonic Distortion + Noise VOUT = 18VP-P, f = 1kHz 0.08 %
PSRR Power Supply Rejection Ratio
(Figure 2)
VDD = 3.6V + 200mVP-P sine, Inputs = AC GND
fRIPPLE = 217Hz 55 78 dB
fRIPPLE = 1kHz 76 dB
CMRR Common Mode Rejection Ratio
(Figure 3)
VCM = 200mVP-P sine
fRIPPLE = 217Hz 68 dB
fRIPPLE = 1kHz 78 dB
SNR Signal-to-Noise-Ratio Boost Disabled, A-weighted 107 dB
Boost Enabled A-weighted 98 dB
εOS Output Noise
A-weighted
AV = 24dB
AV = 0dB (Boost Disabled)
134
16
μVRMS
μVRMS
TAAttack Time ATK1:ATK0 = 00 0.75 ms
TRRelease time RLT1:RLT0 = 00 1 s
fSW
Boost Converter Switching
Frequency 2 MHz
ILIMIT Boost Converter Current Limit 1.5 A
VIH Logic High Input Threshold SHDN 1.4 V
VIL Logic Low Input Threshold SHDN 0.5 V
IIN Input Leakage Current SHDN 0.1 0.2 μA
I2C Interface Characteristics (Note 1, Note 2)
The following specifications apply for RPU = 1kΩ to VDD, SW/HW = 1 (Software Mode) unless otherwise specified. Limits apply for
TA = 25°C.
Symbol Parameter Conditions
LM48560 Units
(Limits)
Min
(Note 7)
Typ
(Note 6)
Max
(Note 7)
VIH Logic Input High Threshold SDA, SCL 1.1 V
VIL Logic Input Low Threshold SDA, SCL 0.5 V
SCL Frequency 400 kHz
t1SCL Period 2.5 μs
t2SDA Setup Time 250 ns
t3SDA Stable Time 250 ns
t4Start Condition Time 250 ns
t5Stop Condition Time 250 ns
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LM48560
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum
allowable power dissipation is PDMAX = (TJMAX − TA) / θJA or the given in Absolute Maximum Ratings, whichever is lower.
Note 4: Human body model, applicable std. JESD22-A114C.
Note 5: Machine model, applicable std. JESD22-A115-A.
Note 6: Charge device model, applicable std. JESD22-C101-C.
Note 7: Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 8: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
30150737
FIGURE 2. PSRR Test Circuit
30150735
FIGURE 3. CMRR Test Circuit
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LM48560
Typical Performance Characteristics
All typical performance curves are taken with conditions seen in Figure 1 (Typical Application Circuit), unless otherwise specified.
THD+N vs FREQUENCY
CL = 0.6μF, VDD = 3.6V, Boosted, AV = 24dB
30150754
THD+N vs FREQUENCY
CL = 1.0μF, VDD = 3.6V, Boosted, AV = 24dB
30150755
THD+N vs FREQUENCY
CL = 1.5μF, VDD = 3.6V, Boosted, AV = 24dB
30150756
THD+N vs FREQUENCY
VDD = 3.6V, CL = 0.6μF, VOUT = 5VP-P
Unboosted, AV = 0dB
30150773
THD+N vs FREQUENCY
VDD = 3.6V, CL = 1μF, VOUT = 5VP-P
Unboosted , AV = 0dB
30150775
THD+N vs FREQUENCY
VDD = 3.6V, CL = 1.5μF, VOUT = 5VP-P
Unboosted, AV = 0dB
30150774
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LM48560
OUTPUT VOLTAGE vs FREQUENCY
CL = 1.5μF, THD+N ≤ 1%, Boosted
30150778
OUTPUT VOLTAGE vs FREQUENCY
CL = 1.5μF, THD+N ≤ 1%, Unboosted
30150777
THD+N vs OUTPUT VOLTAGE
CL = 0.6μF, VDD = 3.6V, Boosted, AV = 24dB
30150760
THD+N vs OUTPUT VOLTAGE
CL = 1.0μF, VDD = 3.6V, Boosted, AV = 24dB
30150762
THD+N vs OUTPUT VOLTAGE
CL = 1.5μF, VDD = 3.6V, Boosted, AV = 24dB
30150761
THD+N vs OUTPUT VOLTAGE
CL = 1.5μF, VDD = 3.6V, Unboosted, AV = 0dB
30150781
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LM48560
INPUT VOLTAGE vs OUTPUT VOLTAGE
ALC Enabled, AV = 21dB, VDD = 3.6V
30150753
SUPPLY CURRENT vs SUPPLY VOLTAGE
RL = ∞
30150749
TOTAL POWER CONSUMPTION vs OUTPUT VOLTAGE
VDD = 3.6V, CL = 0.6μF
30150751
TOTAL POWER CONSUMPTION vs OUTPUT VOLTAGE
VDD = 3.6V, CL = 1.0μF
30150752
TOTAL POWER CONSUMPTION vs OUTPUT VOLTAGE
VDD = 3.6V, CL = 1.5μF
30150750
COMMON MODE REJECTION RATIO vs FREQUENCY
VCM= 200mVP-P, CIN = 10μF, VDD = 3.6V, CL = 1.5μF
30150729
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LM48560
POWER SUPPLY REJECTION RATIO vs FREQUENCY
VRIPPLE = 200mVP-P, VDD = 3.6V, CL = 1.5μF
30150742
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LM48560
Application Information
READ/WRITE I2C COMPATIBLE INTERFACE
The LM48560 is controlled through an I2C compatible serial
interface that consists of a serial data line (SDA) and a serial
clock (SCL). The clock line is uni-directional. The data line is
bi-directional (open drain). The LM48560 and the master can
communicate at clock rates up to 400kHz. Figure 4 shows the
I2C interface timing diagram. Data on the SDA line must be
stable during the HIGH period of SCL. The LM48560 is a
transmit/receive slave-only device, reliant upon the master to
generate the SCL signal. Each transmission sequence is
framed by a START condition and a STOP condition Figure
5. Each data word, device address and data, transmitted over
the bus is 8 bits long and is always followed by an acknowl-
edge pulse Figure 6. The LM48560 device address is
1101111.
I2C BUS FORMAT
30150740
FIGURE 4. I2C Timing Diagram
30150741
FIGURE 5. Start and Stop Diagram
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LM48560
WRITE SEQUENCE
The example write sequence is shown in Figure 6. The
START signal, the transition of SDA from HIGH to LOW while
SDA is HIGH, is generated, altering all devices on the bus that
a device address is being written to the bus.
The 7-bit device address is written to the bus, most significant
bit (MSB) first, followed by the R/W bit (R/W = 0 indicating the
master is writing to the LM48560). The data is latched in on
the rising edge of the clock. Each address bit must be stable
while SDA is HIGH. After the R/W bit is transmitted, the mas-
ter device releases SDA, during which time, an acknowledge
clock pulse is generated by the slave device. If the LM48560
receives the correct address, the device pulls the SDA line
low, generating and acknowledge bit (ACK).
Once the master device registers the ACK bit, the 8-bit reg-
ister address word is sent, MSB first. Each data bit should be
stable while SCL is HIGH. After the 8-bit register address is
sent, the LM48560 sends another ACK bit. Upon receipt of
the acknowledge, the 8-bit register data is sent, MSB first. The
register data word is followed by an ACK, upon receipt of
which, the master issues a STOP bit, allowing SDA to go high
while SDA is high.
30150736
FIGURE 6. Example I2C Write Cycle
READ SEQUENCE
The example read sequence is shown in Figure 7. The
START signal, the transition of SDA from HIGH to LOW while
SDA is HIGH, is generated, altering all devices on the bus that
a device address is being written to the bus.
The 7-bit device address is written to the bus, followed by the
R/W = 1 (R/W = 1 indicating the master wants to read data
from the LM48560). After the R/W bit is transmitted, the mas-
ter device releases SDA, during which time, an acknowledge
clock pulse is generated by the slave device. If the LM48560
receives the correct address, the device pulls the SDA line
low, generating and acknowledge bit (ACK). Once the master
device registers the ACK bit, the 8-bit register address word
is sent, MSB first, followed by an ACK and selected register
data from the LM48560. The register data is sent MSB first.
Following the acknowledgement of the register data word
[7:0], the master issues a STOP bit, allowing SDA to go high
while SDA is high.
30150743
FIGURE 7. Example I2C Read Cycle
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LM48560
TABLE 2. Device Address
B7 B6 B5 B4 B3 B2 B1 B0 (R/W)
Device Address 1 1 0 1 1 1 1 0
TABLE 3. Mode Selection
SW/HW SDA/SEL SCL/GAIN MODE
0
0
(Boost Disabled)
0IN1, AV = 0
1IN1, AV = 6
1
(Boost Enabled)
0IN2, AV = 24
1IN2, AV = 30
1 X X I2C Mode
TABLE 4. I2C Control Registers
REGISTER
ADDRESS
Register
Name B7 B6 B5 B4 B3 B2 B1 B0
0x00h SHUTDOWN
CONTROL X X X X TURN
_ON IN_SEL BOOST
_EN SHDN
0x01h NO CLIP
CONTROL X RLT1 RLT0 ATK1 ATK0 PLEV2 PLEV1 PLEV0
0x02h GAIN CONTROL X X X X X X GAIN1 GAIN0
0x03h TEST MODE X X X X X X X X
TABLE 5. Shutdown Control Register
BIT NAME VALUE DESCRIPTION
B7:B4 UNUSED X Unused, set to 0
B3 TURN_ON 0Normal turn on time, tWU = 15ms
1Fast turn on time, tWU = 5ms
B2 IN_SEL 0 Input 1 selected
1 Input 2 selected
B1 BOOST_EN 0 Boost disabled
1 Boost enabled
B0 SHDN 0 Device shutdown
1 Device enabled
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LM48560
TABLE 6. No Clip Control Register
BIT NAME VALUE DESCRIPTION
B7 UNUSED X Unused, set to 0
B6:B5 RLT1 (B6)
RLT0 (B5)
B6 B5 Sets Release Time based on CSET.
See “Release Time” section.
00 TR = 0.5s
01 TR = 0.38s
10 TR = 0.21s
11 TR = 0.17s
B4:B3 ATK1 (B4)
ATK0 (B3)
B4 B3 Sets Attack Time based on CSET.
See ”Attack Time” section.
0 0 TA = 0.83ms
0 1 TA = 1.2ms
1 0 TA = 1.5ms
1 1 TA = 2.2ms
B2:B0
PLEV2 (B2)
PLEV1 (B1)
PLEV0 (B0)
B2 B1 B0 Sets output voltage limit level.
0 0 0 Voltage Limit disabled
0 0 1 VTH(VLIM) = 14VP-P
0 1 0 VTH(VLIM) = 17VP-P
0 1 1 VTH(VLIM) = 20VP-P
1 0 0 VTH(VLIM) = 22VP-P
1 0 1 VTH(VLIM) = 25VP-P
1 1 0 VTH(VLIM) = 28VP-P
1 1 1 Voltage Limit disabled
TABLE 7. Gain Control Register
BIT NAME VALUE DESCRIPTION
B7:B2 UNUSED X Unused, set to 0
B1:B0 GAIN1(B1)
GAIN0 (B0)
B1 B0 Sets amplifier gain.
Boost disabled (BOOST_EN = 0)
0 0 0dB
0 1 6dB
1 0 12dB
1 1 18dB
B1:B0 GAIN1(B1)
GAIN0 (B0)
B1 B0 Sets amplifier gain.
Boost enabled (BOOST_EN = 1)
0 0 21dB
0 1 24dB
1 0 27dB
1 1 30dB
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LM48560
GENERAL AMPLIFIER FUNCTION
The LM48560 is a fully differential, Class H piezo driver for
ceramic speakers and haptic actuators. The integrated, high
efficiency boost converter dynamically adjusts the amplifier’s
supply voltage based on the output signal, increasing head-
room and improving efficiency compared to a conventional
Class AB driver. The fully differential amplifier takes advan-
tage of the increased headroom and bridge-tied load (BTL)
architecture, delivering significantly more voltage than a sin-
gle-ended amplifier.
CLASS H OPERATION
Class H is a modification of another amplifier class (typically
Class B or Class AB) to increase efficiency and reduce power
dissipation. To decrease power dissipation, Class H uses a
tracking power supply that monitors the output signal and ad-
justs the supply accordingly. When the amplifier output is
below 3VP-P, the nominal boost voltage is 6V. As the amplifier
output increases above 3VP-P, the boost voltage tracks the
amplifier output as shown in Figure 8. When the amplifier out-
put falls below 3VP-P, the boost converter returns to its nom-
inal output voltage. Power dissipation is greatly reduced
compared to conventional Class AB drivers.
30150728
FIGURE 8. Class H Operation
DIFFERENTIAL AMPLIFIER EXPLANATION
The LM48560 features a fully differential amplifier. A differ-
ential amplifier amplifies the difference between the two input
signals. A major benefit of the fully differential amplifier is the
improved common mode rejection ratio (CMRR) over single
ended input amplifiers. The increased CMRR of the differen-
tial amplifier reduces sensitivity to ground offset related noise
injection, especially important in noisy systems.
AUTOMATIC LEVEL CONTROL (ALC)
The ALC is available in software mode only, and only in
boosted mode. In hardware mode ALC is always disabled.
The ALC limits the peak output voltage to the programmed
value. Consequently, it limits the peak boost voltage, as this
is derived from the output voltage. The ALC is continuous, in
that it provides a continuous adjustment of the voltage gain in
order to limit the output voltage to the programmed value. The
available gain adjustment range is typically 8dB. When the
input amplitude is further increased beyond the ALC attenu-
ation range, the output will again increase. This is illustrated
in the Typical Performance Graphs, as seen on the 14VPP plot
in the Input voltage vs Output Voltage curve. The attack and
decay of the ALC is programmed by software and works in
conjunction with the external capacitor CSET. Typically CSET
is 1μF, although it can be changed from 0.1μF to 4.7μF to
select other ranges of attack and decay time.
ATTACK TIME
Attack time (tATK) is the time it takes for the gain to be reduced
by 6dB once the audio signal exceeds the ALC threshold. Fast
attack times allow the ALC to react quickly and prevent tran-
sients such as symbol crashes from being distorted. Howev-
er, fast attack times can lead to volume pumping, where the
gain reduction and release becomes noticeable, as the ALC
cycles quickly. Slower attack times cause the ALC to ignore
the fast transients, and instead act upon longer, louder pas-
sages. Selecting an attack time that is too slow can lead to
increased distortion in the case of the No Clip function, and
possible output overload conditions in the case of the Voltage
limiter. The attack time is set by a combination of the value of
CSET and the attack time coefficient as given by equation (2):
tATK = 20kΩCSET / αATK (1)
Where αATK is the attack time coefficient () set by bits B4:B3
in the Voltage Limit Control Register (see ). The attack time
coefficient allows the user to set a nominal attack time. The
internal 20kΩ resistor is subject to temperature change, and
it has tolerance between -11% to +20%.
TABLE 8. Attack Time Coefficient
B5 B4 αATK
0 0 2.4
0 1 1.7
1 0 1.3
1 1 0.9
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LM48560
RELEASE TIME
Release time (tRL) is the time it takes for the gain to return
from 6dB to its normal level once the audio signal returns be-
low the ALC threshold. A fast release time allows the ALC to
react quickly to transients, preserving the original dynamics
of the audio source. However, similar to a fast attack time, a
fast release time contributes to volume pumping. A slow re-
lease time reduces the effect of volume pumping. The release
time is set by a combination of the value of CSET and release
time coefficient as given by equation (3):
tRL = 20MΩCSET / αRL (s) (2)
where αRL is the release time coefficient (Table 11) set by bits
B4:B3 in the No Clip Control Register. The release time co-
efficient allows the user to set a nominal release time. The
internal 20MΩ is subject to temperature change, and it has
tolerance between -11% to +20%.
TABLE 9. Release Time Coefficient
B5 B4 αRL
0 0 4
0 1 5.3
1 0 9.5
1 1 11.8
BOOST CONVERTER
The LM48560 features an integrated boost converter with a
dynamic output control. The device monitors the output signal
of the amplifier, and adjusts the output voltage of the boost
converter to maintain sufficient headroom while improving ef-
ficiency.
SOFTWARE/HARDWARE MODE
Device operation in hardware or software mode is determined by the state of the SW/HW pin. Connect SW/HW to ground for
hardware mode, and connect to VDD for software mode.
SW/HW SDA/SEL SCL/GAIN MODE
0
0
(Boost Disabled)
0 IN1, Av = 0
1 IN1, Av = 6
1
(Boost Enabled)
0 IN2, Av = 24
1 IN2, Av = 30
1 SDA SCL I2C Mode
GAIN SETTING
The LM48560 features four internally configured gain settings 0db, 6dB, and 30dB. The device gain is selected through a single
pin (GAIN). The gain settings are shown in Table 10.
TABLE 10. Gain Setting
GAIN GAIN SETTING
IN1
GAIN SETTING
IN2
0 0dB 24dB
1 6dB 30dB
SHUTDOWN FUNCTION
The LM48560 features a low current shutdown mode. Set SD = GND to disable the amplifier and boost converter and reduce
supply current to 0.01µA.
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LM48560
SINGLE-ENDED INPUT CONFIGURATION
The LM48560 is compatible with single-ended sources. When configured for single-ended inputs, input capacitors must be used
to block and DC component at the input of the device. Figure 9 shows the typical single-ended applications circuit.
30150738
FIGURE 9. Single-Ended Input Configuration
PROPER SELECTION OF EXTERNAL COMPONENTS
ALC Timing (CSET) Capacitor Selection
The recommended range value of CSET is between .01μF to
1μF. Lowering the value below .01μF can increase the attack
time but LM48560 ALC ability to regulate its output can be
disrupted and approaches the hard limiter circuit. This in turn
increases the THD+N and audio quality will be severely af-
fected.
Power Selection of External Components
Proper power supply bypassing is critical for low noise per-
formance and high PSRR. Place the supply bypass capaci-
tors as close to the device as possible. Place a 1µF ceramic
capacitor from VDD to GND. Additional bulk capacitance may
be added as required.
Boost Converter Capacitor Selection
The LM48560 boost converter requires three external capac-
itors for proper operation: a 1μF supply bypass capacitor, and
1μF + 100pF output reservoir capacitors. Place the supply
bypass capacitor as close to VDD as possible. Place the reser-
voir capacitors as close to VBST and VAMP as possible. Low
ESR surface-mount multi-layer ceramic capacitors with X7R
or X5R temperature characteristics are recommended. Select
output capacitors with voltage rating of 25V or higher. Tanta-
lum, OS-CON and aluminum electrolytic capacitors are not
recommended. See Table 4 for suggested capacitor manu-
facturers.
Inductor Selection
The LM48560 boost converter is designed for use with a
4.7μH inductor. Choose an inductor with a saturation current
rating greater than the maximum operating peak current of
the LM48560 (> 1A). This ensures that the inductor does not
saturate, preventing excess efficiency loss, over heating and
possible damage to the inductor. Additionally, choose an in-
ductor with the lowest possible DCR (series resistance) to
further minimize efficiency losses.
Diode Selection
Use a Schottkey diode as shown in Figure 1. A 20V diode
such as the NSR0520V2T1G from On Semiconductor is rec-
ommended. The NSR0520V2T1G is designed to handle a
maximum average current of 500mA.
PCB LAYOUT GUIDELINES
Minimize trace impedance of the power, ground and all output
traces for optimum performance. Voltage loss due to trace
resistance between the LM48560 and the load results in de-
creased output power and efficiency. Trace resistance be-
tween the power supply and ground has the same effect as a
poorly regulated supply, increased ripple and reduced peak
output power. Use wide traces for power supply inputs and
amplifier outputs to minimize losses due to trace resistance,
as well as route heat away from the device. Proper grounding
improves audio performance, minimizes crosstalk between
channels and prevents switching noise from interfering with
the audio signal. Use of power and ground planes is recom-
mended.
Place all digital components and route digital signal traces as
far as possible from analog components and traces. Do not
run digital and analog traces in parallel on the same PCB lay-
er. If digital and analog signal lines must cross either over or
under each other, ensure that they cross in a perpendicular
fashion.
17 www.ti.com
LM48560
DEMO BOARD USER GUIDE
Quick Start Guide (Hardware Mode):
1. Short pins 1 (VDD) and 2 of JU1 for normal operation.
2. Short pins 2 and 3(GND) of JU7 to set the device in hardware mode.
3. Short pins 2 and 3 (GND) of JU3 to select IN1.
4. Short pins 2 and 3 (GND) of JU2 for 0dB gain.
5. Connect a power supply (2.7V-5.5V) and ground reference respectively to the VDD and GND headers on the demo board.
6. Connect a differential audio input to IN1+ and IN2-
7. Power on the board and observe the output on OUT+ and OUT-
Quick Start Guide (Software Mode):
1. Short pins 1 (VDD) and 2 of JU1 for normal operation.
2. Short pins 1 (VDD) and 2 of JU7 to set the device in software mode.
3. Short pins 1 (VDD) and 2 of JU3 to select IN2.
4. Short pins 2 and 3 (GND) of JU2 for 24dB gain.
5. Connect a power supply (2.7V-5.5V) and ground reference respectively to the VDD and GND headers on the demo board.
6. Connect a differential audio input to IN1+ and IN2-
7. Connect the USB/I2C board to the LM48560 demo board.
8. Connect the USB/I2C board to a PC
9. Turn on the power supply
10. Launch the LM48560 software GUI
11. Verify that the bottom left corner of the GUI reads “USB Connected ALL ACK” (note 1)
12. Select the following:
a. INPUT SELECT = INPUT 1
b. BOOST = ON
c. TURN ON TIME = NORMAL
d. GAIN = 0dB
Note: If the GUI reads “USB I/O error NAK” the device has not been acknowledged, please double check your connections.
www.ti.com 18
LM48560
Header Functionality
Designator Function Notes
VDD VDD Power Supply
GND GND Ground reference
OUT+ OUTPUT Positive output terminal
OUT- OUTPUT Negative output terminal
IN1+ INPUT 1 Positive input terminal 1
IN1- INPUT 1 Negative input terminal 1
IN2+ INPUT 2 Positive input terminal 2
IN2- INPUT 2 Negative input terminal 2
JU1 Shutdown Short pin 1 (VDD) and pin 2 for normal operation Short pin 2 and pin 3 (GND)
for device shutdown
JU2 SCL/Gain Select
Hardware mode: Short pin 2 to pin 1 (VDD) for higher gain. Short pin 2 to pin
3(GND) for lower gain. (See Table 10) Software mode: Keep pins 1-3 open.
Pin 2 = SCL for I2C communication
JU3 SDA/Input Select
Hardware mode: Short pin 2 to pin 1 (VDD) to select IN2. Short pin 2 to pin 3
(GND) to select IN1. (See Table 10) Software mode: Keep pins 1-3 open. Pin
2 = SCL for I2C communication
JU4 SCL Pullup Short JU4 to connect pullup resistor to VDD. Open to use external I2C supply
voltage
JU5 SDA pullup Short JU5 to connect pullup resistor to VDD. Open to use external I2C supply
voltage
JU6 I2C VDD Short JU6 to use VDD as I2C VDD. Open to use external I2C supply voltage
JU7 SW/HW Software Mode: Short pins 1 (VDD) and 2 Hardware Mode: Short pins 2 and
3(GND)
19 www.ti.com
LM48560
Demo Board Schematic
30150779
www.ti.com 20
LM48560
PC Board Layout
30150769
Top Silk Screen
30150771
Solder Mask Top
30150772
Top Layer 30150766
Layer 2
30150765
Layer 3 30150764
Drill Drawing
21 www.ti.com
LM48560
30150768
Silk Bottom 30150770
Solder Mask Bottom
30150763
Bottom Layer
www.ti.com 22
LM48560
Revision History
Rev Date Description
1.0 08/16/11 Initial WEB released.
1.01 09/21/11 Input edits under CLASS H OPERATION.
1.02 11/01/11 Edited curves 30150753, 54, 55, 56, and Figure 7 (I2C Read Cycle).
1.03 11/10/11 Edited Figure 7.
23 www.ti.com
LM48560
Physical Dimensions inches (millimeters) unless otherwise noted
Thin micro SMD
Order Number LM48560TL
NS Package Number TLA16Z1A
X1 = 1.970±0.03mm X2 = 1.970±0.03mm X3 = 0.600±0.075mm
www.ti.com 24
LM48560
Notes
25 www.ti.com
LM48560
Notes
LM48560 High Voltage Class H Ceramic Speaker Driver with Automatic Level Control
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