MB89943 - Fujitsu - Datasheet.Live

DS07-12536-2E

FUJITSU SEMICONDUCTOR

DATA SHEET

8-bit Proprietary Microcontroller

CMOS

F2MC-8L MB89940 Series

MB89943/P945/PV940

■OUTLINE

The MB89940 series is specially designed for automotive instrumentation applications. It features a combination

of two PWM pulse generators and four high-drive-current outputs for controlling a stepping motor. It also contains

two analog inputs, two PWM pulse generators and 10-digit LCD controller/driver for various sensor/indicator

devices. The MB89940 series is manufactured with high performance CMOS technologies and packaged in a

48-pin QFP.

■FEATURES

• 8-bit core CPU; 4 MHz system clock (8 MHz external, 500 ns instruction cycle)

• 21-bit watchdog timer

• Clock generator/controller

• 16-bit interval timer

• Two PWM pulse generators with four high-drive-current outputs

• Tw o-channel 8-bit A/D converter

• Three external interrupt

• Low supply voltage reset

• External voltage monitor interrupt

• Two more PWM pulse generators for controlling indicator devices

• 4-common 17-segment LCD driver/controller

• Package; 48-pin plastic QFP, 48-pin ceramic MQFP

(Continued)

■PACKAGE

48-pin Plastic QFP

(FPT-48P-M16)

48-pin Ceramic MQFP

(MQP-48C-P01)

MB89940 Series

(Continued)

• 5.0 V single power supply (VPP required for MB89P945)

•0.8 µm CMOS technology (MB89PV940 and MB89P945)

•0.5 µm CMOS technology (MB89943)

• On-chip voltage regulator for internal 3.0 V power supply (MB89943)

■PRODUCT LINEUP

(Continued)

MB89P945 MB89PV940

Classification Mass-produced products

(mask ROM products) One-time PROM Piggyback

ROM size 8 K × 8 bits

(internal mask ROM) 16 K × 8 bits

(internal PROM) 32 K × 8 bits

(external on piggyback)

RAM size 512 × 8 bits 1 K × 8 bits

CPU functions The number of instructions: 136

Instruction cycle: 0.5 µs*1@8 MHz

Interrupt response time: 4.0 µs*1@8 MHz

Multiply instruction time: 19 instruction cycles

Divide instruction time: 21 instruction cycles

Direct addressing memory-to/from-register data transfer:

7 instruction cycles

Ports Output: 5-bit N-ch open-drain

Input/Output: Two 8-bit CMOS schmitt I/Os and 8-bit CMOS I/Os

Timebase timer 21 bits

Interrupt interval: 1 ms, 4.1 ms, 32.8 ms or 524.3 ms

8-bit/16-bit timer Can be used as two 8-bit timers or one 16-bit timer

Operation clock: 1 µs, 16 µs, 256 µs or external *1

Watchdog Reset Reset interval: Approx. 524 ms to 1049 ms

Stepping motor

controller Two 8-bit PWM pulse generators

Synchronized 4-channel high current output

Operation clock: 250 ns, 500 ns, 1 µs or 4 µs*1

8-bit PWM timers Two 8-bit PWM timers

External interrupt 3 channels, selective positive edge or negative edge trigger

A/D converter 8-bit resolution, two-channel input

Conversion time: 44 instruction cycles for A/D conversion, 12 instruction cycles

for sense mode operation

LCD controller 4-common and 17-segment outputs

Number of outputs programmable

Low supply voltage

reset Autonomous reset when low supply voltage

Reset voltage: 3.3 V, 3.6 V, 4.0 V

External voltage

monitor interrupt Interrupts when voltage at external pin is lower than the reference voltage

Standby modes Stop mode and sleep mode

Operating

voltage*23.5 V to 5.5 V

MB89943

Part number

Item

MB89940 Series

(Continued)

*1: Execution times and clock cycle times are dependent on the use of MCU.

*2: Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”) In the case

of the MB89PV940, the voltage varies with the vestrictions of the EPROM for use.

■PACKAGE AND CORRESPONDING PRODUCTS

: Available × : Not available

Note: For more information about each package, see section “■ P ackage Dimensions.”

MB89P945 MB89PV940

Process CMOS

External EPROM MBM27C256A-20TVM

Package MB89943

MB89P945 MB89PV940

FPT-48P-M16 ×

MQP-48C-P01 ×

MB89943

Part number

Item

MB89940 Series

■DIFFERENCES AMONG PRODUCTS

1. Memory Size

Prior to evaluating/developing the software for the MB89940 ser ies, please check the differences between the

product types.

• RAM/ROM configurations are dependent on the product type.

• If the bottom address of the stack is set to the upper limit of the RAM address, it should be relocated when

changing the product type.

2. Power Dissipation

• For the piggyback product, add the power dissipation of the EEPROM on the piggyback.

• The power dissipation differs between the product types.

3. Technology

The mask ROM product is fabricated with a 0.5 µm CMOS technolog y whereas the other products with 0.8 µm

CMOS technology.

Also the mask ROM product contains the on-chip v oltage regulator f or the internal 3.0 power supply. F or details,

refer to

MB89940 Series Hardware Manual

4. Mask Option

Functions that can be selected as options and how to designate these options vary by the product.

Before using options check section “■ Mask Options.”

• No options are available for the piggyback product.

• The power-on reset and reset output options are always activated with the mask ROM product.

• Pull-up option must not be specified with the pins used as LCD outputs.

MB89940 Series

■PIN ASSIGNMENT

AVCC

RST

P41/COM0

P42/COM1

VCC

P43/COM2

P44/COM3

P27/INT2

P26/INT1

P25/INT0

DVCC

P30/FUELO

P00/SEG00

P01/SEG01

P02/SEG02

P03/SEG03

P04/SEG04

P05/SEG05

P06/SEG06

P07/SEG07

P10/SEG08

P11/SEG09

MODE

VINT

P40/PW

P37/FUELI

P36/TEMPI

AVSS

DVSS

P35/PWM2M

P34/PWM2P

P33/PWM1M

P32/PWM1P

P31/TEMPO

P24/V3

P23/TO/V2

P22/EC/V1

P21/V0

P20/SEG16

P17/SEG15

VSS

P16/SEG14

P15/SEG13

P14/SEG12

P13/SEG11

P12/SEG10

(Top view)

(FPT-48P-M16)

MB89940 Series

• Pin assignment on package top (MB89PV940 only)

N.C.: Internally connected. Do not use.

Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name

49A1557N.C.65O473OE

50A1258A266O574N.C.

51 A7 59 A1 67 O6 75 A11

52 A6 60 A0 68 O7 76 A9

53 A5 61 O1 69 O8 77 A8

54 A4 62 O2 70 CE 78 A13

55 A3 63 O3 71 A10 79 A14

56 N.C. 64 VSS 72 N.C. 80 VCC

AVCC

RST

P41/COM0

P42/COM1

VCC

P43/COM2

P44/COM3

P27/INT2

P26/INT1

P25/INT0

DVCC

P30/FUELO

P00/SEG00

P01/SEG01

P02/SEG02

P03/SEG03

P04/SEG04

P05/SEG05

P06/SEG06

P07/SEG07

P10/SEG08

P11/SEG09

MODE

VINT

P40/PW

P37/FUELI

P36/TEMPI

AVSS

DVSS

P35/PWM2M

P34/PWM2P

P33/PWM1M

P32/PWM1P

P31/TEMPO

P24/V3

P23/TO/V2

P22/EC/V1

P21/V0

P20/SEG16

P17/SEG15

VSS

P16/SEG14

P15/SEG13

P14/SEG12

P13/SEG11

P12/SEG10

(Top view)

(MQP-48C-P01)

MB89940 Series

■PIN DESCRIPTION

(Continued)

*1: FPT-48P-M16

*2: MQP-48C-P01

Pin no. Pin name Circuit

type Function

QFP*1MQFP*2

5 5 X0 A These pins are used for crystal oscillation.

X0 and X1 can be directly connected to a crystal

oscillator.

When the oscillation clock is provided to X0

externally, X1 should be left open.

66X1

48 48 MODE B The mode input is used f or entering the MPU into the

test mode.

In user applications, MODE is connected to VSS.

22RST C Applying a reset pulse to this pin forces the MPU to

enter the initial state. RST is active low and drives

low state when an internal reset occurs.

Reset pulses of the duration less than the minimum

pulse width may cause the MCU to enter undefined

states.

34 to 27 34 to 27 P00/SEG00 to

P07/SEG07 H These pins have two functions.

Their functions can be switched between Port 0 and

LCD segment signal outputs by setting the internal

registers of the LCD controller.

26 to 20,

18 26 to 20,

18 P10/SEG08 to

P17/SEG15 J These pins have two functions.

Their functions can be switched between Port 1 and

LCD segment signal outputs by setting the internal

registers of the LCD controller.

17 17 P20/SEG15 I This pin can be used as the bit 0 of Port 2 or an LCD

segment signal output by setting the internal register

of the LCD controller.

16 16 P21/V0 F This pin is the bit 1 of Port 2.

This pin can also be used for an external LCD bias

voltage input.

15 15 P22/EC/V1 F This pin can be used as the bit 2 of Port 2 or the

external clock input for the interval timer.

This pin can also be used for an external LCD bias

voltage input.

14 14 P23/TO/V2 F This pin can be used as the bit 3 of Port 2 or the

output for the interval timer.

Its function can be switched by setting the internal

This pin can also be used for an external LCD bias

voltage input.

13 13 P24/V3 F This pin can be used as the bit 4 of Port 2 or an

external LCD bias voltage input.

12, 11, 10 12, 11, 10 P25/INT0 to

P27/INT2 E These pins are used for Port 2.

They can also be used for external interrupt inputs.

35 35 P30/FUELO D This pin can be used for the bit 0 of Port 3 or the

output from PWM3.

The function of this pin can be switched by setting

the internal register of PWM3.

MB89940 Series

(Continued)

*1: FPT-48P-M16

*2: MQP-48C-P01

Pin no. Pin name Circuit

type Function

QFP*1MQFP*2

37 37 P31/TEMPO G This pin can be used for the bit 1 of Port 3 or the

output from PWM4.

The function of this pin can be switched by setting

the internal register of PWM4. This output has a high

drive-current capability.

38,

39 38,

39 P32/PWM1P,

P33/PWM1M G These pins are the pair of high-current driver outputs

for one of two motor coils.

The y can be also used for the bits 2 and 3 of Port 3

by setting the internal register of the stepper motor

controller.

40,

41 40,

41 P34/PWM2P,

P35/PWM2M G These pins are the pair of high-current driver outputs

for one of two motor coils.

The y can be also used for the bits 4 and 5 of Port 3

by setting the internal register of the stepper motor

controller.

44 44 P36/TEMPI M This analog input is connected to channel 1 of the

A/D converter.

It can also be used f or the bit 6 of Port 3 when this A/

D input enable register bit is set to ‘0’.

45 45 P37/FUELI M This analog input is connected to channel 0 of the

A/D converter.

It can also be used f or the bit 7 of Port 3 when this A/

D input enable register bit is set to ‘0’.

46 46 P40/PW L This pin has two functions.

When this pin is used as an open-drain output of

Port 4, the external voltage monitor reset should be

in the power down mode.

When it is used as the PW input of external voltage

monitor reset, the corresponding bit of the port data

3, 4

8, 9 3, 4

8, 9 P41/COM0 to

P44/COM3 K These pins are the LCD common signal outputs.

When LCD is not used, these pins can be also used

for Port 4.

47 47 VINT — An external capacitor should be connected to this

pin for stabilizing the internal 3.0 V power supply.

For MB89PV940 and MB89P945, this pin should be

left open.

77V

CC —VCC

19 19 VSS —VSS

11AVCC — The power supply pin for the analog circuit

The same voltage should be applied as VCC.

43 43 AVSS —The power supply pin for the analog circuit

The same voltage should be applied as VSS.

36 36 DVCC — The dedicated power supply pin for the high-current

driver output

The same voltage should be applied as VCC.

42 42 DVSS — The dedicated power supply pin for the high-current

driver output

The same voltage should be applied as VSS.

MB89940 Series

• External EPROM pins (MB89PV940 only)

Pin no. Pin name I/O Function

A15

A12

O Address output pins

I Data input pins

70 CE O ROM chip enable pin

Outputs “H” during standby.

71 A10 O Address output pin

73 OE O ROM output enable pin

Outputs “L” at all times.

A11

A13

A14

O Address output pin

80 VCC O EPROM power supply pin

64 VSS O Power supply (GND) pin

N.C. — Internally connected pins

Be sure to leave them open.

MB89940 Series

■I/O CIRCUIT TYPE

(Continued)

Type Circuit Remarks

A • Oscillator I/O

With feedback resistor of approx. 2 MΩ.

B • Schmitt-trigger input

(Pull-down resistance only for MB89943)

C • Open-drain output with pull-up resistor

(Approx. 50 kΩ).

• Schmitt-trigger input

• Hysteresis input

D•CMOS I/O

E • CMOS I/O (Schmitt trigger)

• Pull-up resistor optional

Standby control signal

P-ch

N-ch

P-ch

N-ch

P-ch

N-ch

Mask Option

MB89940 Series

(Continued)

Type Circuit Remarks

F • CMOS I/O (Schmitt trigger)

• External bias input

• Pull-up resistor optional

G • CMOS I/O (High output current)

H•CMOS I/O

• LCD controller/driver output

I•CMOS I/O

• LCD controller/driver output

• Pull-up resistor optional

• Hysteresis input

P-ch

N-ch

P-ch

N-ch

Mask Option

P-ch

N-ch

P-ch

N-ch

P-ch

N-ch

P-ch

N-ch

P-ch

N-ch

P-ch

N-ch

P-ch

N-ch

MB89940 Series

(Continued)

Type Circuit Remarks

J•CMOS I/O

• LCD controller/driver output

• Pull-up resistor optional

(Except P11/SEG09, P10/SEG08)

K • N-ch open-drain output

• LCD controller/driver output

L • N-ch open-drain output

• Analog input

M•CMOS I/O

• Analog input

P-ch

N-ch

P-ch

N-ch

P-ch

N-ch

Mask Option

N-ch

P-ch

N-ch

P-ch

N-ch

P-ch

N-ch

MB89940 Series

■HANDLING DEVICES

1. Preventing Latchup

Latchup ma y occur on CMOS ICs if v oltage higher than VCC or lower than VSS is applied to input and output pins

other than medium- and high-vo ltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also , tak e care to prev ent the analog pow er supply (AVCC and AVR) and analog input from e xceeding the digital

power supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving un used input pins open could cause malfunctions . The y should be connected to a pull-up or pull-down

resistor.

The VINT pin of MB89PV940 and MB89P945 is the only exception.

3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters

Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.

4. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

5. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is

therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations

(P-P v alue) will be less than 10% of the standard VCC v a lue at the commercial frequency (50 to 60 Hz) and the

transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power

is switched.

MB89940 Series

■PROGRAMMING TO THE EPROM ON THE MB89P945

1. Programming MB89P945

Using the EPROM adapter (provided by Fujitsu) and a standard EPROM programmer, user-defined data can

be written into the OTPROM and option PROM. The EPROM programmer should be set to MB27C256A-20TVM

and electro-signature mode should not be used. When programming the data, the internal addresses are mapped

as follows.

2. Memory Space

3. EPROM Programmer Socket Adapter

Please contact Fujitsu for socket adapters for the MB89P945 and the EPROM on the MB89PV940.

4. Screening MB89P945

It is recommended that high-temperature aging is performed on the MB89P945 prior to the assembly.

One Time PROM

16 KB One Time PROM

16 KB

FFFFH

0000H

8000H

Single chipAddress

C000H

7FFFH

0000H

3FF0H

4000H

Option PROM

EPROM mode

(Corresponding addresses on the EPROM programmer)

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

MB89940 Series

5. Setting OTPROM Options

For MB89P945, mask options are descr ibed in the internal option PROM area. The table below shows the bit

map of the option PROM. The option data can be written by a standard EPROM programmer.

• OTPROM option bit map

Notes: Default values are all ‘1’.

TOSC: One oscillation clock cycle time

When the bit 0 of “3FF3H” is “0”, it activates the option setting for the Low Voltage Reset Control register.

When this option is activated, software setting in the register has no effect.

PROM

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

3FF0HUnused Unused Unused Reserved Reset

output

1: Active

0: Inactive

Power-on

reset

1: Active

0: Inactive

Oscillation stabilization

time

11: 218 TOSC 10: 217 TOSC

01: 214 TOSC

3FF1HP17

Pull-up

1: Inactive

0: Active

P16

Pull-up

1: Inactive

0: Active

P15

Pull-up

1: Inactive

0: Active

P14

Pull-up

1: Inactive

0: Active

P13

Pull-up

1: Inactive

0: Active

P12

Pull-up

1: Inactive

0: Active

Unused Unused

3FF2HP27

Pull-up

1: Inactive

0: Active

P26

Pull-up

1: Inactive

0: Active

P25

Pull-up

1: Inactive

0: Active

P24

Pull-up

1: Inactive

0: Active

P23

Pull-up

1: Inactive

0: Active

P22

Pull-up

1: Inactive

0: Active

P21

Pull-up

1: Inactive

0: Active

P20

Pull-up

1: Inactive

0: Active

3FF3HUnused Unused Unused Low volt.

PDX bit Low volt.

S1 bit Low volt.

S0 bit Low volt.

LVE bit Low volt.

1: Register

active

0: Option

active

3FF4HUnused Unused Unused Unused Unused Unused Unused Unused

3FF5HUnused Unused Unused Unused Unused Unused Unused Unused

3FF6HUnused Unused Unused Unused Unused Unused Unused Unused

MB89940 Series

■PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C256A-20TVM

2. Programming Socket Adapter

Please consult Fujitsu.

3. Memory Space

The memory space of the piggybac k EPROM is mapped onto the internal memory space as shown in the figure

below.

For EPROM devices suitable for MB89PV940, please consult Fujitsu.

4. Programming to the EPROM

(1) Set the EPROM programmer to the MBM27C256A-20TVM.

(2) Load program data into the EPROM programmer at 0000H to 7FFFH.

(3) Program to 0000H to 7FFFH with the EPROM programmer.

Piggy Back

FFFFH

0000H

8000H

Single chipAddress

7FFFH

0000H

Corresponding addresses on the EPROM programmer

EPROM

32 KB

MB89940 Series

■BLOCK DIAGRAM

P41/COM0 to

P44/COM3

F2MC-8L

core CPU

Interrupt

controller

Oscillator

External voltage

monitor interrupt

Stepper motor

macro

Port 3

8-bit A/D

converter

RST

P40/PW

P37/FUELI

P36/TEMPI

DVCC

DVSS

P30/FUELO

P31/TEMPO

P32/PWM1P

P33/PWM1M

P34/PWM2P

P35/PWM2M

Clock controller

Timebase timer

Reset circuit

Low supply

voltage reset

Internal bus

Port 0, 1 and 4

Port 2

RAM

ROM

PWM3

PWM4

PWM1

PWM2

Interval timer

LCD

controller driver

Port 4

High-drive-current

VCC, VSS

AVCC, AVSS

VINT

Other pins

P10/SEG08 to

P17/SEG15

P00/SEG00 to

P07/SEG07

P20/SEG16

P21/V0

P22/EC/V1

P23/TO/V2

P24/V3

MODE

P25/INT0 to

P27/INT2

MB89940 Series

■CPU CORE

1. Memory Space

The MB89940 Series has a memor y space of 64 Kbytes. All peripheral registers, RAM and ROM areas are

mapped onto the 0000H to FFFFH range. The peripheral registers address below 007FH and the RAM addresses

the range 0080H to 027FH (0080H to 047FH for MB89PV940). A par t of this RAM area is also assigned as the

general-purpose registers. The ROM addresses above E000H. The One-Time PROM addresses the range above

C000H. The exter nal ROM for the piggy sample addresses the range above 8000H. The reset vector, interr upt

vectors and vectors for vector-call instructions are stored in the highest addresses of the memory space.

Memory Space

ROM

8 KB

512 B

16 KB

512 B

32 KB

1 KB

FFFFH

0000H

0100H

017FH

007FH

MB89943

E000H

RAM

General-

purpose

registers

Peripheral

registers

One-time

PROM

FFFFH

0000H

017FH

027FH027FH

0100H

007FH

MB89P945

C000H

RAM

General-

purpose

registers

Peripheral

registers

External

ROM

FFFFH

0000H

017FH

047FH

0100H

007FH

MB89PV940

8000H

RAM

General-

purpose

registers

Peripheral

registers

MB89940 Series

2. Registers

The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-pur pose registers

in the memory. The following dedicated registers are provided:

Progra m counter (PC): A 16-bit register for indicating instruction storage positions

Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator

When the instruction is an 8-bit data processing instruction, the lower byte is used.

Index register (IX): A 16-bit register for index modification

Extra pointer (EP): A 16-bit pointer for indicating a memory address

Stack pointer (SP): A 16-bit register for indicating a stack area

Program status (PS): A 16-bit register for storing a register pointer, a condition code

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits f o r

use as a condition code register (CCR). (See the diagram below.)

16 bits

: Program counter

: Accumulator

: Temporary accumulator

: Index register

: Extra pointer

: Stack pointer

: Program status

FFFDH

Indeterminate

I-flag = 0, IL1, 0 = 11

The other bit values are indeterminate.

Initial value

Structure of the Program Status Register

Vacancy

H I IL1, 0 N Z VC

RPPS

109876 321015 14 13 12 11

RP CCR

Vacancy Vacancy

MB89940 Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared

otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared

to ‘0’ at the reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

N-flag: Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ otherwise.

Z-flag: Set to ‘1’ when an arithmetic operation results in 0. Cleared to ‘0’ otherwise.

V-flag: Set to ‘1’ if the complement on ‘2’ ov erflo ws as a result of an arithmetic operation. Cleared to ‘0’ if the

overflow does not occur.

C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to

‘0’ otherwise. Set to ‘1’ to the shift-out value in the case of a shift instruction.

IL1 IL0 Interrupt level High-low

00 1High

Low

10 2

11 3

Rule for Conversion of Actual Addresses of the General-purpose Register Area

“0”

↓

A15

“0”

↓

A14

“0”

↓

A13

“0”

↓

A12

“0”

↓

A11

“0”

↓

A10

“0”

↓

“1”

↓

Generated addresses

Lower OP codes

MB89940 Series

The following general-purpose registers are provided:

General-purpose registers: An 8-bit register for storing data

The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains

eight registers and up to a total of 16 banks can be used on the MB89943 (RAM 512 × 8 bits). The bank currently

in use is indicated by the register bank pointer (RP).

Note: The number of register banks that can be used varies with the RAM size. Up to a total of 32 banks can

be used on other than the MB89943.

This address = 0100H + 8 × (RP)

Memory area

16 banks

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

MB89940 Series

■ I/O MAP

(Continued)

Address Read/write Register name Register description

00H(R/W) PDR0 Port 0 data register

01H(W) PDD0 Port 0 data direction register

02H(R/W) PDR1 Port 1 data register

03H(W) PDD1 Port 1 data direction register

04H to 06HVacancy

07H(R/W) SCC System clock control register

08H(R/W) SMC Standby mode control register

09H(R/W) WDTC Watchdog timer control register

0AH(R/W) TBTC Timebase timer control register

0BH(R/W) LVRC Low voltage reset control

0CH(R/W) PDR2 Port 2 data register

0DH(W) PDD2 Port 2 data direction register

0EH(R/W) PDR3 Port 3 data register

0FH(W) PDD3 Port 3 data direction register

10H(R/W) PDR4 Port 4 data register

11H(R/W) ADE Port 3 A/D input enable register

12H to 17HVacancy

18H(R/W) T2CR Timer 2 control register

19H(R/W) T1CR Timer 1 control register

1AH(R/W) T2DR Timer 2 data register

1BH(R/W) T1DR Timer 1 data register

1CH to 1FHVacancy

20H(R/W) ADC1 A/D converter control register 1

21H(R/W) ADC2 A/D converter control register 2

22H(R/W) ADCD A/D converter data register

23H(R/W) CNTR PWM control register

24H(W) COMP1 PWM1 compare register

25HVacancy

26H(W) COMP2 PWM2 compare register

27H(R/W) SELR1 PWM1 select register

28H(R/W) SELR2 PWM2 select register

29H(R/W) CNTR3 PWM3 control register

2AH(W) COMP3 PWM3 compare register

2BH(R/W) CNTR4 PWM4 control register

MB89940 Series

(Continued)

Address Read/write Register name Register description

2CH(W) COMP4 PWM4 compare register

2DH(R/W) SELT Selector test register

2EH(R/W) PFC Power fail control register

2FH(R/W) EIR1 External interrupt control 1 register

30H(R/W) EIR2 External interrupt control 2 register

31H to 5FHVacancy

60H to 68H(R/W) VRAM Display data RAM

69H to 71HVacancy

72H(R/W) LCR1 LCD controller/driver register

73H(R/W) LCR2 LCD controller/driver 2 register

74H to 7BHVacancy

7CH(W) ILR1 Interrupt level setting register 1

7DH(W) ILR2 Interrupt level setting register 2

7EH(W) ILR3 Interrupt level setting register 3

7FHVacancy

MB89940 Series

■ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(VSS = 0.0 V)

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Parameter Symbol Value Unit Remarks

Min. Max.

Power supply voltage VCC VSS – 0.3 VSS + 6.5 V

AVCC VSS – 0.3 VSS + 6.5 V Should not exceed VCC

DVCC VSS – 0.3 VSS + 6.5 V Should not exceed VCC

Input voltage

VI1 VSS – 0.3 VCC + 0.3 V Except P31 to P35 and P41 to P44

VI2 VSS – 0.3 DVCC + 0.3 V P31 to P35

VI3 VSS – 0.3 VSS + 6.5 V P41 to P44

MB89PV940/945

VI4 VSS – 0.3 VCC + 0.3 V P41 to P44

MB89943

Output voltage

VO1 VSS – 0.3 VCC + 0.3 V Except P31 to P35 and P41 to P44

VO2 VSS – 0.3 DVCC + 0.3 V P31 to P35

VO3 VSS – 0.3 VSS + 6.5 V P41 to P44

MB89PV940/945

VO4 VSS – 0.3 VCC + 0.3 V P41 to P44

MB89943

“L” level maximum output

current VOL — 20 mA Except P31 to P35

— 50 mA P31 to P35

“L” level average output

current VOLAV — 4 mA Except P31 to P35

— 40 mA P31 to P35

“L” level total maximum

output current VOLTOTALMAX — 100 mA Except P31 to P35

— 200 mA P31 to P35

“L” level total average

output current VOLTOTALAV — 40 mA Except P31 to P35

— 100 mA P31 to P35

“H” level maximum output

current VOH — –20 mA Except P31 to P35

— –50 mA P31 to P35

“H” level average output

current VOHAV — –4 mA Except P31 to P35

— –40 mA P31 to P35

“H” level total maximum

output current VOHTOTALMAX — –50 mA Except P31 to P35

— –200 mA P31 to P35

“H” level total average

output current VOHTOTALAV — –20 mA Except P31 to P35

— –100 mA P31 to P35

Power consumption PD— 300 mW

Operating temperature TA–40 +85 °C

Storage temperature Tstg –55 +150 °C

MB89940 Series

2. Recommended Operating Conditions

(AVCC = VCC = DVCC = 5.0 V, VSS = AVSS = DVSS = 0.0 V)

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the

device’s electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside

these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representative beforehand.

3. DC Characteristics

(AVCC = VCC = DVCC = 5.0 V, VSS = AVSS = DVSS = 0.0 V)

(Continued)

Parameter Symbol Value Unit Remarks

Min. Typ. Max.

Operating supply voltage range VCC

AVCC

DVCC 3.5 — 5.5 V

RAM data retention supply voltage range VCC

AVCC

DVCC 3.0 — 5.5 V

Operating temperature range TA–40 — +85 °C

Parameter Symbol Pin name Condition Value Unit Remarks

Min. Typ. Max.

“H” level input voltage VIH P00 to P07, P10 to P17

P30 to P37, P40 to P47 — 0.7 VCC —VCC + 0.3 V

VIHS RST, MODE, P20 to P27 — 0.8 VCC —VCC + 0.3 V

“L” level input voltage VIL P00 to P07, P10 to P17

P30 to P37, P40 to P47 —VSS − 0.3 — 0.3 VCC V

VILS RST, MODE, P20 to P27 —VSS − 0.3 — 0.2 VCC V

Open-drain output

pin application voltage

VD—VSS − 0.3 —VCC + 0.3 V

VD2 —VSS − 0.3 —VSS + 5.5 VMB89PV940/

945

VD3 —VSS − 0.3 —VCC + 0.3 V MB89943

“H” level output

voltage

VOH P10 to P17, P20 to

P27, P30, P36, P37 IOH = –2.0 mA 4.0 — — V

VOH2 P31 to P36 IOH = –30

VCC = DVCC VCC − 0.5 ——V

“L” level output

voltage

VOL P10 to P17, P20 to P27,

P30, P36, P37,

P40 to P44 IOL = 4.0 mA — — 0.4 V

VOL2 P31 to P36 IOL = 30 mA

VSS = DVSS ——0.5V

P40

P41 to P44

MB89940 Series

(Continued)

(AVCC = VCC = DVCC = 5.0 V, VSS = AVSS = DVSS = 0.0 V)

* :For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”

4. AC Characteristics

(1) Reset Timing

(AVSS = VSS = DVSS, TA = –40°C to +85°C)

tHCYL: One oscillation clock cycle time

Parameter Symbol Pin name Condition Value Unit Remarks

Min. Typ. Max.

Input leakage current IIL1 MODE, P10 to P17,

P20 to P27, P30 to P37,

P40 to P44

0.0 V< VI < VCC,

VCC = DVCC –5 — +5 µAWithout

pull-up option

Pull-up resistance RPULL RST, P12 to P17,

P20 to P27 — 25 50 100 kΩWith pull-up

option

LCD internal bias

voltage resister RLCD V0-V1, V1-V2, V2-V3 — 50 100 200 kΩ

Power supply current

ICC

VCC

FC = 8 MHz,

tinst* = 0.5 µs

ICC = I(VCC)

+ I(DVCC)

12 20 mA MB89PV940

12 20 mA MB89943,

MB89P945

ICCS

FC = 8 MHz

tinst* = 0.5 µs

ICCS = I(VCC)

+ I(DVCC)

in Sleep mode

—3 7mA

ICCH

In Stop mode

TA = 25°C

ICCH = I(VCC)

+ I(DVCC)

—510µA

AVCC

FC = 8 MHz

IA = I(AVCC)

A/D in operation —6 8mA

IAH

FC = 8 MHz

IAH = I(AVCC)

A/D stopped —510µA

Input capacitance CIN —f = 1 MHz—10—pF

External capacitor

at VINT CVINT ———0.1—µFMB89943 only

Parameter Symbol Condition Value Unit Remarks

Min. Max.

RST “L” pulse width tZLZH — 16 tHCYL —ns

—

MB89940 Series

If power-on reset option is not activated, the external reset signal must be kept asserted until the oscillation is

stabilized.

(2) Power-on Profile

(AVSS = VSS = DVSS, TA = –40°C to +85°C)

tHCYL: One oscillation clock cycle time

Note: Power supply voltage should reach the minimum operation voltage within the specified default duration of

the oscillation stabilization time.

(3) Clock Timing

(AVSS = VSS = DVSS, TA = –40°C to +85°C)

Parameter Symbol Condition Value Unit Remarks

Min. Max.

Power supply voltage rising time tR——50ms

MB89PV940,

MB89P945

Power supply voltage rising time tR——

219 tHCYL ns MB89943

Power-off minimum period tOFF —1—ms

Parameter Symbol Condition Value Unit Remarks

Min. Max.

Clock frequency FC

—

18MHz

Clock cycle time tCYC 1000 125 ns

Input clock pulse width tWH

tWL 20 — ns

Input clock rising/falling time tCR

tCF —10ns

0.2 VCC

0.8 VCC

RST

tZLZH

0.2 V 0.2 V

3.5 V

0.2 V

VCC

tOFF

MB89940 Series

(4) Instruction Cycle

Note: When operating at 8 MHz, the cycle varies with the set execution time.

(5) Peripheral Input Timing (AVSS = VSS= DVSS, TA = –40°C to +85°C)

* :For information on tinst, see “(4) Instruction Cycle.”

Parameter Symbol Value (typical) Unit Remarks

Instruction cycle

(minimum execution time) tinst 4/FC, 8/FC, 16/FC, 64/FCµs(4/FC) tinst = 0.5 µs when operating at

FC = 8 MHz

Parameter Symbol Pin name Value Unit Remarks

Min. Max.

Peripheral input “H” pulse width tWH INT0, INT1,

INT2, EC 2 tinst*—µs

Peripheral input “L” pulse width tWL INT0, INT1,

INT2, EC 2 tinst*—µs

0.2 VCC

X0 0.2 VCC

X0 X1

tCYC

When a crystal

ceramic resonator is used

X0 X1

When an external clock is used

Open

0.2 VCC

0.8 VCC 0.8 VCC

tCR tCF tWLtWL

X0 and X1 Timing and Conditions

Clock Conditions

MB89940 Series

5. A/D Converter Electrical Characteristics

(AVSS = VSS = DVSS, TA = –40°C to +85°C)

* :For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”

6. A/D Converter Glossary

• Resolution

Analog changes that are identifiable with the A/D converter

When the number of bits is 8, analog voltage can be divided into 28 = 256.

• Linearity error (unit: LSB)

The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the

full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics

• Differential linearity error (unit: LSB)

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value

• Total error (unit: LSB)

The difference between theoretical and actual conversion values

Parameter Symbol Pin

name Condition Value Unit Remarks

Min. Typ. Max.

Resolution

—

——

—— 8bit

Total error — — ±1.5 LSB

Linearlity error — — ±1.0 LSB

Differential linearlity error ——±0.9 LSB

Zero transition voltage VOT AVSS – 1.0 LSB AVSS + 0.5 LSB A V SS + 2.0 LSB VMB89PV940/P945

AVSS + 5/8 LSB AVSS + 7/8 LSB AVSS + 11/8 LSB V MB89943

Full-scale transition

voltage VFST AVCC – 3.0 LSB AVCC – 1.5 LSB AVCC VMB89PV940/P945

AVCC – 13/8 LSB AVCC – 9/8 LSB AVCC – 7/8 LSB V MB89943

Interchannel disparity

—

——0.5LSB

A/D mode

conversion time ——44 tinst*µsMB89PV940/P945

——52 tinst*µs MB89943

Analog input current IAIN ——10µA

Analog input v oltage

range —0—AV

CC V

INT0, INT1,

INT2, EC 0.2 VCC

0.2 VCC

0.8 VCC 0.8 VCC

tWLtWL

MB89940 Series

7. Notes on Using A/D Converter

• Input impedance of the analog input pins

The A/D conver ter used for the MB89940 ser ies contains a sample hold circuit as illustrated below to fetch

analog input v oltage into the sample hold capacitor for eight instruction cycles after activ ating A/D conv ersion.

F or this reason, if the output impedance of the external circuit f or the analog input is high, analog input voltage

might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output

impedance of the external circuit low (below 10 kΩ).

Note that if the impedance cannot be kept low, it is recommended to connect an exter n al capacitor of about

0.1 µF for the analog input pin.

•Error

The smaller the | AVCC – AVSS |, the greater the error would become relatively.

VOT VNT V(N + 1)T VFST

Digital output

(1 LSB × N + VOT)

0000

0000 0000

0001

0010

1111

1111 1110

1111

1 LSB = AVR

256

Linearity error =

Differential linearity error =

Analog input

Actual conversion value

Theoretical conversion value

Total error =

VNT – (1 LSB × N + VOT)

1 LSB

V( N + 1 ) T – VNT

1 LSB – 1

1 LSB

VNT – (1 LSB × N + 1 LSB)

Linearity error

•

Analog Input Equivalent Circuit

Sample hold circuit

Analog channel selector

Close for 8 instruction cycles after activating

A/D conversion.

If the analog input

impedance is higher

than 10 kΩ, it is

recommended to

connect an external

capacitor of approx.

0.1 µF.

Analog input pin Comparator

R = 6 kΩ

C = 33 pF

MB89940 Series

8. Low Supply Voltage Reset Electrical Characteristics

9. External Voltage Monitor Interrupt Electrical Characteristics

Parameter Symbol Value Unit Remarks

Min. Max.

Reset voltage

VDL1 3.0 3.6 V When the voltage is

dropping.

Refer to the register

definition.

VDL2 3.3 3.9 V

VDL3 3.7 4.3 V

Hysteresis of reset voltage VHYS 0.1 — V When the voltage is

recovering.

Delay time to reset tD—2.0µs

Supply voltage slew rate dV/dt — 0.1 V/µs

Parameter Symbol Value Unit Remarks

Min. Max.

Reference voltage VREF 1.18 1.38 V

Delay time to interrupt TD—2.0µsRefer to the register

definition.

Input slew rate dV/dt — 0.1 V/µs

MB89940 Series

■INSTRUCTIONS (136 INSTRUCTIONS)

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

•Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

Symbol Meaning

dir D irect address (8 bits)

off Offset (8 bits)

ext Extended address (16 bits)

#vct Vector table number (3 bits)

#d8 Immediate data (8 bits)

#d16 Immediate data (16 bits)

dir: b Bit direct address (8:3 bits)

rel Branch relative address (8 bits)

@ Register indirect (Example: @A, @IX, @EP)

A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

AH Upper 8 bits of accumulator A (8 bits)

AL Lower 8 bits of accumulator A (8 bits)

T Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)

TH Upper 8 bits of temporary accumulator T (8 bits)

TL Lower 8 bits of temporary accumulator T (8 bits)

IX Index register IX (16 bits)

EP Extra pointer EP (16 bits)

PC Program counter PC (16 bits)

SP Stack pointer SP (16 bits)

PS Program status PS (16 bits)

dr Accumulator A or index register IX (16 bits)

CCR Condition code register CCR (8 bits)

RP Register bank pointer RP (5 bits)

Ri General-purpose register Ri (8 bits, i = 0 to 7)

×Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

( × )Indicates that the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

(( × )) The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

MB89940 Series

Columns indicate the following:

Mnemonic: Assembler notation of an instruction

~: The number of instructions

#: The number of bytes

Operation: Operation of an instruction

TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

•“–” indicates no change.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH prior to the instruction executed.

• 00 becomes 00.

N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

OP code: Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

MB89940 Series

Table 2 Transfer Instructions (48 instructions)

Notes: •During byte transfer to A, T ← A is restricted to low bytes.

•Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F2MC-8 family)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

SETB dir: b

CLRB dir: b

XCH A,T

XCHW A,T

XCHW A,EP

XCHW A,IX

XCHW A,SP

MOVW A,PC

(dir) ← (A)

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

(A) ← (Ri)

(dir) ← d8

( (IX) +off ) ← d8

( (EP) ) ← d8

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)

(A) ← (EP)

(EP) ← d16

(IX) ← (A)

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

–

– – – –

+ + – –

– – – –

+ + – –

– – – –

+ + + +

– – – –

48 to 4F

08 to 0F

88 to 8F

A8 to AF

A0 to A7

MB89940 Series

Table 3 Arithmetic Operation Instructions (62 instructions)

(Continued)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

ROLC A

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

DAS

XOR A

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +off

XOR A,Ri

AND A

AND A,#d8

AND A,dir

(A) ← (A) + (Ri) + C

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) ∧ (T)

(A) ← (A) ∨ (T)

(A) ← (A) ∀ (T)

(TL) − (AL)

(T) − (A)

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

(A) − (Ri)

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) ∀ (TL)

(A) ← (AL) ∀ d8

(A) ← (AL) ∀ (dir)

(A) ← (AL) ∀ ( (EP) )

(A) ← (AL) ∀ ( (IX) +off)

(A) ← (AL) ∀ (Ri)

(A) ← (AL) ∧ (TL)

(A) ← (AL) ∧ d8

(A) ← (AL) ∧ (dir)

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

+ + + +

+ + R –

28 to 2F

38 to 3F

C8 to CF

D8 to DF

18 to 1F

58 to 5F

←

→→

MB89940 Series

(Continued)

Table 4 Branch Instructions (17 instructions)

Table 5 Other Instructions (9 instructions)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

DECW SP

(A) ← (AL) ∧ ( (EP) )

(A) ← (AL) ∧ ( (IX) +off)

(A) ← (AL) ∧ (Ri)

(A) ← (AL) ∨ (TL)

(A) ← (AL) ∨ d8

(A) ← (AL) ∨ (dir)

(A) ← (AL) ∨ ( (EP) )

(A) ← (AL) ∨ ( (IX) +off)

(A) ← (AL) ∨ (Ri)

(dir) – d8

( (EP) ) – d8

( (IX) + off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

–

+ + R –

+ + + +

– – – –

68 to 6F

78 to 7F

98 to 9F

Mnemonic ~ # Operation TL TH AH N Z V C OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

BN rel

BP rel

BLT rel

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

RETI

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V ∀ N = 1 then PC ← PC + rel

If V ∀ N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

– – – –

– + – –

– – – –

Restore

B0 to B7

B8 to BF

E8 to EF

Mnemonic ~ # Operation TL TH AH N Z V C OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

CLRI

SETI

–

– – – –

– – – R

– – – S

– – – –

MB89940 Series

■INSTRUCTION MAP

0123456789ABCDEF

0NOP SWAP RET RETI PUSHWAPOPWAMOV

A,ext MOVW

A,PS CLRI SETI CLRB

dir: 0 BBC

dir: 0,rel INCW ADECWAJMP@A MOVW

A,PC

1MULUADIVU AJMP

addr16 CALL

addr16 PUSHW

IX POPW

IX MOV

ext,A MOVW

PS,A CLRC SETC CLRB

dir: 1 BBC

dir: 1,rel INCW

SP DECW

SP MOVW

SP,A MOVW

A,SP

2ROLC ACMP AADDC ASUBC AXCHA, T XOR AAND AOR AMOV

@A,T MOV

A,@A CLRB

dir: 2 BBC

dir: 2,rel INCWIX DECW

IX MOVW

IX,A MOVW

A,IX

3RORCACMPWAADDCW

ASUBCWAXCHW

A, T XORWAANDWAORW AMOVW

@A,T MOVW

A,@A CLRB

dir: 3 BBC

dir: 3,rel INCW

EP DECW

EP MOVW

EP,A MOVW

A,EP

4MOV

A,#d8 CMP

A,#d8 ADDC

A,#d8 SUBC

A,#d8 XOR

A,#d8 AND

A,#d8 OR

A,#d8 DAA DAS CLRB

dir: 4 BBC

dir: 4,rel MOVW

A,ext MOVW

ext,A MOVW

A,#d16 XCHW

A,PC

5MOV

A,dir CMP

A,dir ADDC

A,dir SUBC

A,dir MOV

dir,A XOR

A,dir AND

A,dir OR A,dir MOV

dir,#d8 CMP

dir,#d8 CLRB

dir: 5 BBC

dir: 5,rel MOVW

A,dir MOVW

dir,A MOVW

SP,#d16 XCHW

A,SP

6MO V

A,@IX +d CMP

A,@IX +d ADDC

A,@IX +d SUBC

A,@IX +d MOV @IX

+d,A XOR

A,@IX +d AND

A,@IX +d OR

A,@IX +d MOV

@IX +d,#d8 CMP

@IX +d,#d8 CLRB

dir: 6 BBC

dir: 6,rel MO VW

A,@IX +d MO VW

@IX +d,A MOVW

IX,#d16 XCHW

A,IX

7MO V

A,@EP CMP

A,@EP ADDC

A,@EP SUBC

A,@EP MOV

@EP,A XOR

A,@EP AND

A,@EP OR

A,@EP MO V

@EP,#d8 CMP

@EP,#d8 CLRB

dir: 7 BBC

dir: 7,rel MO VW

A,@EP MO VW

@EP,A MOVW

EP,#d16 XCHW

A,EP

8MOV

A,R0 CMP

A,R0 ADDC

A,R0 SUBC

A,R0 MOV

R0,A XOR

A,R0 AND

A,R0 ORA,R0 MOV

R0,#d8 CMP

R0,#d8 SETB

dir: 0 BBS

dir: 0,rel INC R0 DEC R0 CALLV

#0 BNC rel

9MOV

A,R1 CMP

A,R1 ADDC

A,R1 SUBC

A,R1 MOV

R1,A XOR

A,R1 AND

A,R1 ORA,R1 MOV

R1,#d8 CMP

R1,#d8 SETB

dir: 1 BBS

dir: 1,rel INC R1 DEC R1 CALLV

#1 BC rel

AMOV

A,R2 CMP

A,R2 ADDC

A,R2 SUBC

A,R2 MOV

R2,A XOR

A,R2 AND

A,R2 ORA,R2 MOV

R2,#d8 CMP

R2,#d8 SETB

dir: 2 BBS

dir: 2,rel INC R2 DEC R2 CALLV

#2 BP rel

BMOV

A,R3 CMP

A,R3 ADDC

A,R3 SUBC

A,R3 MOV

R3,A XOR

A,R3 AND

A,R3 ORA,R3 MOV

R3,#d8 CMP

R3,#d8 SETB

dir: 3 BBS

dir: 3,rel INC R3 DEC R3 CALLV

#3 BN rel

CMOV

A,R4 CMP

A,R4 ADDC

A,R4 SUBC

A,R4 MOV

R4,A XOR

A,R4 AND

A,R4 ORA,R4 MOV

R4,#d8 CMP

R4,#d8 SETB

dir: 4 BBS

dir: 4,rel INC R4 DEC R4 CALLV

#4 BNZ rel

DMOV

A,R5 CMP

A,R5 ADDC

A,R5 SUBC

A,R5 MOV

R5,A XOR

A,R5 AND

A,R5 ORA,R5 MOV

R5,#d8 CMP

R5,#d8 SETB

dir: 5 BBS

dir: 5,rel INC R5 DEC R5 CALLV

#5 BZ rel

EMOV

A,R6 CMP

A,R6 ADDC

A,R6 SUBC

A,R6 MOV

R6,A XOR

A,R6 AND

A,R6 ORA,R6 MOV

R6,#d8 CMP

R6,#d8 SETB

dir: 6 BBS

dir: 6,rel INC R6 DEC R6 CALLV

#6 BGE rel

FMOV

A,R7 CMP

A,R7 ADDC

A,R7 SUBC

A,R7 MOV

R7,A XOR

A,R7 AND

A,R7 ORA,R7 MOV

R7,#d8 CMP

R7,#d8 SETB

dir: 7 BBS

dir: 7,rel INC R7 DEC R7 CALLV

#7 BLT rel

MB89940 Series

■MASK OPTIONS

■ORDERING INFORMATION

No.

Part number MB89943 MB89P945 MB89PV940

Specifying procedure Specify when

ordering

masking Set with EPROM

Programmer Setting not

possible

1Pull-up resistors

P12 to P17,

P20 to P27

Selectable per pin

(P20 and P12 to

P17 must be set to

without pull-up

resistor when they

are used as LCD

outputs.)

Can be set per pin Fixed to without

pull-up resistor

2Power-on reset

With power-on reset

Without power-on reset Fixed to with

power-on reset Setting possible Fixed to with

power-on reset

Main clock oscillation stabilization time

selection (when operating at 8 MHz)

Approx. 218/FC (Approx. 32.8 ms)

Approx. 217/FC (Appro x. 16.4 ms)

Approx. 214/FC (Appro x. 2.0 ms)

Selectable Setting possible Fixed to

approx. 218/FC

(Approx. 32.8 ms)

4Reset pin output

With reset output

Without reset output Fixe d to with reset

output Setting possible Fixed to with reset

output

Part number Package Remarks

MB89943PF

MB89P945PF 48-pin Plastic QFP

(FPT-40P-M16)

MB89PV940CF 48-pin Ceramic MQFP

(MQP-48C-P01)

MB89940 Series

■PACKAGE DIMENSION

1994 FUJITSU LIMITED F48026S-1C-1

Details of "A" part

17.20±0.40

0.30±0.06

(.012±.002) 0.16(.006) M

13.60±0.40

8.80 (.535±.016)

(.346)

REF

0.15(.006)

INDEX

Details of "B" part

121

37 24

1348

0.80(.0315)TYP

LEAD No.

(.677±.016)SQ

"A"

0.15(.006)

0.20(.008)

0.50(.020)MAX

0.15(.006)MAX

0~10°

1.80±0.30

(.071±.012)

"B"

(STAND OFF)

0.05(.002)MIN

.472 –.004

+.012

–0.10

+0.30

12.00

.006 –.0004

+.002

–0.01

+0.05

0.15

2.70(.106)MAX

(Mounting height)

Dimensions in mm (inches)

(FPT-48P-M16)

48-pin Plastic QFP

1994 FUJITSU LIMITED M48001SC-4-2

14.82±0.35

(.583±.014)

15.00±0.25

(.591±.010)

17.20(.677)TYP

PIN No.1 INDEX

.430 –0

+.005

–0.0

+0.13

10.92

1.02±0.13

(.040±.005)

7.14(.281) 8.71(.343)

TYP

0.30(.012)TYP 4.50(.177)TYP

PAD No.1 INDEX

0.15±0.05

(.006±.002)

8.50(.335)MAX

0.60(.024)TYP1.10 +0.45

–0.25

+.018

–.010

.043 0.40±0.08

(.016±.003)

0.80±0.22

(.0315±.0087)

8.80(.346)REF

1.00(.040)TYP

1.50(.059)TYP

PIN No.1 INDEX

Dimensions in mm (inches)

(MQP-48C-P01)

48-pin Ceramic MQFP

MB89940 Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-88, Japan

Tel: (044) 754-3763

Fax: (044) 754-3329

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, U.S.A.

Tel: (408) 922-9000

Fax: (408) 432-9044/9045

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

63303 Dreieich-Buchschlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

Asia Paciﬁc

FUJITSU MICROELECTR ONICS ASIA PTE. LIMITED

#05-08, 151 Lorong Chuan

New Tech Park

Singapore 556741

Tel: (65) 281-0770

Fax: (65) 281-0220

F9704

 FUJITSU LIMITED Printed in Japan

The contents of this document are subject to change without

notice. Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information and circuit diagrams in this document presented

as examples of semiconductor device applications, and are not

intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the

use of this information or circuit diagrams.

FUJITSU semiconductor devices are intended for use in

standard applications (computers, office automation and other

office equipment, industrial, communications, and measurement

equipment, personal or household devices, etc.).

CAUTION:

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage,

or where extremely high levels of reliability are demanded (such

as aerospace systems, atomic energy controls, sea floor

repeaters, vehicle operating controls, medical devices for life

support, etc.) are requested to consult with FUJITSU sales

representatives before such use. The company will not be

responsible for damages arising from such use without prior

approval.

Any semiconductor devices have inherently a certain rate of

failure. You must protect against injury, damage or loss from

such failures by incorporating safety design measures into your

facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating

conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required

for export of those products from Japan.