240pin Fully Buffered DDR2 SDRAM DIMMs based on 1Gb E-ver.
This document is a general product description and is subject to change without notice. Hynix Electronics does not
assume any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / Sep. 2008 1
This Hynix’s Fully Buffered DIMM is a high-bandwidth & large capacity channel solution that has a narrow
host interface. Hynix’s FB-DIMM features novel architecture including the Advanced Memory Buffer that
isolates the DDR2 SDRAMs from the channel. This single component located in the front side center of
each DIMM, acts as a repeater and buff er f or all signals and comm ands which are ex changed between the
host controller and the DDR2 SDRAMs including data in and output. The AMB communicates with the host
controller and adjacent DIMMs on a system board using an industry standard Differential Point to Point
Link Interface at 1.5V power.
The AMB also allows buffering of memory traffic to support large memory capacities. All memory control
for the DDR2 SDRAM devices resides in the host, including memory request initiation, timing, refresh,
scrubbing, sparing, configuration access and power management. The AMB interface is responsible for
handling channel and memory requests to and from the local FBDIMM and for f orw ar ding request to other
FBDIMMs on the memory channel.
FEATURES
• 240 pin Fully Buffered ECC Dual-In-Line DDR2 SDRAM Module
• JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply
• All inputs and outputs are compatible with SSTL_1.8 interface
• Built with 1Gb DDR2 SDRAMs in 60ball FBGA
• Host interface and AMB component industry standard compliant
• MBIST, IBIST test functions
•8 Bank architecture
• OCD (Off-Chip Driver Impedance Adjustment)
•ODT (On-Die Termination)
• Fully differential clock operations (CK & CK)
• Programmable Burst Length 4 / 8 with both sequential and interleave mode
• Auto refresh and self refresh supported
• 8192 refresh cycles / 64ms
• Serial presence detect with EEPROM
• 133.35 x 30.35 mm form factor
•RoHS compliant
• Full DIMM Heat Spreader
Rev. 0.2 / Sep. 2008 2
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240pin Fully Buffered DDR2 SDRAM DIMMs
ORDERING INFORMATION
Note
*: The 17th and 18th digits stand for AMB vendor and revision.
**: ‘R’ of Part Number;11th digit, stands for lead & Halogen free products.
***: Intel AMB for H/F is under development
SPEED GRADE & KEY PARAMETERS
ADDRESS TABLE
Part Name Density Org. # of
DRAMs # of
ranks
AMB H. S type Height
Vendor Version
HMP112F7EFR8C-Y5N3 1GB 128Mx72 9 1 Intel D1
Full
Module 30.35mm
HMP112F7EFR8C-Y5/S5/S6D3 IDT C1
HMP112F7EFR8C-Y5/S5/S6D5 AMB+
HMP125F7EFR8C-Y5N3 2GB 256Mx72 18 2 Intel D1
HMP125F7EFR8C-Y5/S5/S6D3 IDT C1
HMP125F7EFR8C-Y5/S5/S6D5 AMB+
HMP151F7EFR4C-Y5N3 4GB 512Mx72 36 2 Intel D1
HMP151F7EFR4C-Y5/S5/S6D3 IDT C1
HMP151F7EFR4C-Y5/S5/S6D5 AMB+
HMP151F7EFR8C-Y5/S5/S6D5 4GB 512Mx72 36 4 IDT AMB+
HMP31GF7EMR4C-Y5/S5/S6D5 8GB 1Gx72 72 4 AMB+
Speed Grade Y5 S5/6 Unit
DDR2 DRAM Speed Grade DDR2 667 5-5-5 DDR2 800 5-5-5 / 6-6-6
FB-DIMM Speed Grade PC2 5300 PC2 6400
FB-DIMM Peak Channel Throughput 8.0 9.6 GByte/S
FB-DIMM Link Transfer Rate 4.0 4.8 GT/s
Density Organization Ranks SDRAMs # of
DRAMs # of row/bank/column Address Refresh
Method
1GB 128M x 72 1 128Mbx8 9 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 8K / 64ms
2GB 256M x 72 2 128Mbx8 18 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 8K / 64ms
4GB 512M x 72 2 256Mbx4 36 14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64ms
4GB 512M x 72 4 128Mbx8 36 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 8K / 64ms
8GB 1G x 72 4 256Mbx4 72 14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64ms
Rev. 0.2 / Sep. 2008 3
1
240pin Fully Buffered DDR2 SDRAM DIMMs
Input/Output Functional Description
Pin Name type Polarity Function Description Count
SCK Input Positive System clock input 1
SCK Input Negative System cl oc k input 1
PN[13:0] Output Positive Primary Northbound Data 14
PN[13:0] Output Negative Primary Northbound Data 14
PS[9:0] Input Positive Primary Southbound Data 10
PS[9:0] Input Negative Primary Southboun d Data 10
SN[13:0] Output Positive Secondary Northbound Data 14
SN[13:0] Output Negative Secondary Northbound Data 14
SS[9:0] Input Positive Secondary Southbound Data 10
SS[9:0] Input Negative Secondary Southbound Data 10
SCL Input - Serial Presence Detec t (SP D) Clock Input 1
SDA Input / Output - SPD Data Input / Output 1
SA[2:0] Input - SPD Address inputs, also used to select the DIMM number in the AMB 3
VID[1:0] Input - Voltage ID: These pins must be unconnected for DDR2-based Fully buff-
ered DIMMs 2
RESET Input Active Low AMB reset signal 1
RFU - - Reserved for Future Use 16
VCC Supply +1.5V AMB Core Power and AMB channel Interface Power(1.5volt) 8
VDD Supply +1.8V DRAM Power and AMB DRAM I/O Power 24
VTT Supply +0.9V DRAM Address/Command/Clock Terminat io n Power(VDD/2) 4
VDDSPD Supply +3.3V SPD Power 1
VSS Supply Ground 80
DNU/M_Test - / Analog - / 0.9V
The DNU/M_Test pin provides an external connection on R/Cs A-D for
testing the margin of Vref which is produced by a voltage divider on the
module. It is not intended to be used in normal system operation and
must not be connected(DNU) in a system. This test pin may have other
features on future card designs and if it does, will be included in this
specification at that time.
1
Total 240
Rev. 0.2 / Sep. 2008 4
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240pin Fully Buffered DDR2 SDRAM DIMMs
PIN ASSIGNMENT
NC= No Connect, RFU= Reserved for Future Use.
Note:
*: These pin positions are reserved for forwarded clocks to be used in future module implementations
**: These pin positions are reserved for future architecture flexibility
1) The following signals are CRC bits and thus appear out of the normal sequence:
PN12/ PN12, SN12 / SN12, PN13 / PN13, SN13 / SN13,PS9 / PS9, SS9 / SS9
Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name
1 VDD 41 PN13 81 VSS 121 VDD 161 SN13 201 VSS
2 VDD 42 VSS 82 PS4 122 VDD 162 VSS 202 SS4
3 VDD 43 VSS 83 PS4 123 VDD 163 VSS 203 SS4
4 VSS 44 RFU* 84 VSS 124 VSS 164 RFU* 204 VSS
5 VDD 45 RFU* 85 VSS 125 VDD 165 RFU* 205 VSS
6 VDD 46 VSS 86 RFU* 126 VDD 166 VSS 206 RFU*
7 VDD 47 VSS 87 RFU* 127 VDD 167 VSS 207 RFU*
8 VSS 48 PN12 88 VSS 128 VSS 168 SN12 208 VSS
9 VCC 49 PN12 89 VSS 129 VCC 169 SN12 209 VSS
10 VCC 50 VSS 90 PS9 130 VCC 170 VSS 210 SS9
11 VSS 51 PN6 91 PS9 131 VSS 171 SN6 211 SS9
12 VTT 52 PN6 92 VSS 132 VCC 172 SN6 212 VSS
13 VCC 53 VSS 93 PS5 133 VCC 173 VSS 213 SS5
14 VSS 54 PN7 94 PS5 134 VSS 174 SN7 214 SS5
15 VTT 55 PN7 95 VSS 135 VTT 175 SN7 215 VSS
16 VID1 56 VSS 96 PS6 136 VID0 176 VSS 216 SS6
17 RESET 57 PN8 97 PS6 137 DNU/M_Test 177 SN8 217 SS6
18 VSS 58 PN8 98 VSS 138 VSS 178 SN8 218 VSS
19 RFU** 59 VSS 99 PS7 139 RFU** 179 VSS 219 SS7
20 RFU** 60 PN9 100 PS7 140 RFU** 180 SN9 220 SS7
21 VSS 61 PN9 101 VSS 141 VSS 181 SN9 221 VSS
22 PN0 62 VSS 102 PS8 142 SN0 182 VSS 222 SS8
23 PN0 63 PN10 103 PS8 143 SN0 183 SN10 223 SS8
24 VSS 64 PN10 104 VSS 144 VSS 184 SN10 224 VSS
25 PN1 65 VSS 105 RFU** 145 SN1 185 VSS 225 RFU*
26 PN1 66 PN11 106 RFU** 146 SN1 186 SN11 226 RFU*
27 VSS 67 PN11 107 VSS 147 VSS 187 SN11 227 VSS
28 PN2 68 VSS 108 VDD 148 SN2 188 VSS 228 SCK
29 PN2 Key 109 VDD 149 SN2 Key 229 SCK
30 VSS 69 VSS 110 VSS 150 VSS 189 VSS 230 VSS
31 PN3 70 PS0 111 VDD 151 SN3 190 SS0 231 VDD
32 PN3 71 PS0 112 VDD 152 SN3 191 SS0 232 VDD
33 VSS 72 VSS 113 VDD 153 VSS 192 VSS 233 VDD
34 PN4 73 PS1 114 VSS 154 SN4 193 SS1 234 VSS
35 PN4 74 PS1 115 VDD 155 SN4 194 SS1 235 VDD
36 VSS 75 VSS 116 VDD 156 VSS 195 VSS 236 VDD
37 PN5 76 PS2 117 VTT 157 SN5 196 SS2 237 VTT
38 PN5 77 PS2 118 SA2 158 SN5 197 SS2 238 VDDSPD
39 VSS 78 VSS 119 SDA 159 VSS 198 VSS 239 SA0
40 PN13 79 PS3 120 SCL 160 SN13 199 SS3 240 SA1
80 PS3 200 SS3
Rev. 0.2 / Sep. 2008 5
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240pin Fully Buffered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
1GB(128Mbx72) ECC FB-DIMM
Notes :
1. DQ-to-I/O wiring may be changed within a byte.
2. There are two physical copies of each address/command/control/clock.
/S0
D0
DQ0 I/O 0
DQ1 I/O 1
DQ2 I/O 2
DQ3 I/O 3
DQ4 I/O 4
DQ5 I/O 5
DQ6 I/O 6
I/O 7
DQ7
/DQS0
DQS9
DQS0
/CS DQS /DQS
DM
RDQS NU
/RDQS
D1
DQ8 I/O 0
DQ9 I/O 1
DQ10 I/O 2
DQ11 I/O 3
DQ12 I/O 4
DQ13 I/O 5
DQ14 I/O 6
I/O 7
DQ15
/DQS1
DQS10
DQS1
/CS DQS /DQS
DM
RDQS NU
/RDQS
D2
DQ16 I/O 0
DQ17 I/O 1
DQ18 I/O 2
DQ19 I/O 3
DQ20 I/O 4
DQ21 I/O 5
DQ22 I/O 6
I/O 7
DQ23
/DQS2
DQS11
DQS2
/CS DQS /DQS
DM
RDQS NU
/RDQS
D3
DQ24 I/O 0
DQ25 I/O 1
DQ26 I/O 2
DQ27 I/O 3
DQ28 I/O 4
DQ29 I/O 5
DQ30 I/O 6
I/O 7
DQ31
/DQS3
DQS12
DQS3
/CS DQS /DQS
DM
RDQS NU
/RDQS
D8
CB0 I/O 0
CB1 I/O 1
CB2 I/O 2
CB3 I/O 3
CB4 I/O 4
CB5 I/O 5
CB6 I/O 6
I/O 7
CB7
/DQS8
DQS17
DQS8
/CS DQS /DQS
DM
RDQS NU
/RDQS
D4
DQ32 I/O 0
DQ33 I/O 1
DQ34 I/O 2
DQ35 I/O 3
DQ36 I/O 4
DQ37 I/O 5
DQ38 I/O 6
I/O 7
DQ39
/DQS4
DQS13
DQS4
/CS DQS /DQS
DM
RDQS NU
/RDQS
D5
DQ40 I/O 0
DQ41 I/O 1
DQ42 I/O 2
DQ43 I/O 3
DQ44 I/O 4
DQ45 I/O 5
DQ46 I/O 6
I/O 7
DQ47
/DQS5
DQS14
DQS5
/CS DQS /DQS
DM
RDQS NU
/RDQS
D6
DQ48 I/O 0
DQ49 I/O 1
DQ50 I/O 2
DQ51 I/O 3
DQ52 I/O 4
DQ53 I/O 5
DQ54 I/O 6
I/O 7
DQ55
/DQS6
DQS15
DQS6
/CS DQS /DQS
DM
RDQS NU
/RDQS
D7
DQ56 I/O 0
DQ57 I/O 1
DQ58 I/O 2
DQ59 I/O 3
DQ60 I/O 4
DQ61 I/O 5
DQ62 I/O 6
I/O 7
DQ63
/DQS7
DQS16
DQS7
/CS DQS /DQS
DM
RDQS NU
/RDQS
SA0 SA1 SA2
WP
SCL SDA
A0 A1 A2
Serial PD
SCL U0 SDA
All address/comm and/co ntrol/clock VTT
A
M
B
PN0-PN13 SN0-SN13
/PN0-/PN13 /SN0-/SN13
PS0-PS9 SS0-SS9
/PS0-/PS9 /SS0-/SS9
DQ0-DQ63 /S0-/CS(all SDRAMs)
CB0-CB7 CKE0 -> CKE
DQS0-DQS17
/DQS0-/DQS8 ODT -> ODT
SCL
SDA BA0-BA2
SA0-SA2 A0-A15
/RESET /RAS
/CAS
/WE
CK/ /CK
SCK/ /SCK
VDD SPD
VDD
VREF
VSS
Serial PD ,AMB
DO-D8, AMB
DO-D8
DO-D8,SPD, AMB
VCC AMB
VTT Terminators
Rev. 0.2 / Sep. 2008 6
1
240pin Fully Buffered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
2GB(256Mbx72) ECC FB-DIMM
Notes :
1. DQ-to-I/O wiring may be changed within a byte.
2. There are two physical copies of each address/command/control/clock.
z
/S0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
/S1
/DQS1
DQS10
DQS1
D1
DM
RDQS NU
/RDQS
/CS DQS /DQS
D10
DM
RDQS NU
/RDQS
/CS DQS /DQS
/DQS
DQS9
DQS
D0
DM
RDQS NU
/RDQS
/CS DQS /DQS
D9
DM
RDQS NU
/RDQS
/CS DQS /DQS
/DQS2
DQS11
DQS2
D2
DM
RDQS NU
/RDQS
/CS DQS /DQS
D11
DM
RDQS NU
/RDQS
/CS DQS /DQS
/DQS3
DQS12
DQS3
D3
DM
RDQS NU
/RDQS
/CS DQS /DQS
D12
DM
RDQS NU
/RDQS
/CS DQS /DQS
/DQS4
DQS13
DQS4
D4
DM
RDQS NU
/RDQS
/CS DQS /DQS
D13
DM
RDQS NU
/RDQS
/CS DQS /DQS
/D Q S5
DQS14
DQS5
D5
DM
RDQS NU
/RDQS
/CS DQS /DQS
D14
DM
RDQS NU
/RDQS
/CS DQS /DQS
/DQS6
DQS15
DQS6
D6
DM
RDQS NU
/RDQS
/CS DQS /DQS
D15
DM
RDQS NU
/RDQS
/CS DQS /DQS
/DQS7
DQS16
DQS7
D7
DM
RDQS NU
/RDQS
/CS DQS /DQS
D16
DM
RDQS NU
/RDQS
/CS DQS /DQS
/DQS8
DQS17
DQS8
D8
DM
RDQS NU
/RDQS
/CS DQS /DQS
D17
DM
RDQS NU
/RDQS
/CS DQS /DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
A ll a ddr e s s /c om ma n d/c o n tr o l/ c lo c k VTT
SA0 SA1 SA2
WP
SCL SDA
A0 A1 A2
Serial PD
SCL U0 SDA
I/O 0
I/O 1
I/O 2
I/O 3
I/ O 4
I/O 5
I/O 6
I/O 7
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/O 4
I/ O 5
I/ O 6
I/ O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/ O 4
I/O 5
I/O 6
I/O 7
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/O 4
I/ O 5
I/ O 6
I/ O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/ O 4
I/O 5
I/O 6
I/O 7
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/O 4
I/ O 5
I/ O 6
I/ O 7
CKE0 -> CKE (D0-D 8)
CKE1 -> CKE (D9-D 17)
A
M
B
PN0-PN13 SN0-SN13
/PN0-/PN13 /SN0-/SN13
PS0-PS9 SS0-SS9
/PS0-/PS9 /SS0-/SS9
DQ0-DQ63 /S 0-/C S (D 0-D 8 )
CB0-CB7
DQS0-DQS17
/DQS0-/DQS8 ODT -> ODT (all SDRAMs)
SCL
SDA BA0-BA2 (all SDRAM s)
SA0-SA2 A 0 -A1 5 (a ll S D R AM s )
/RESET /R A S (a ll S D R A M s)
/C AS (all S D R AM s )
/WE ( a ll S D R A Ms )
C K , / C K ( a ll SDR A Ms )
SCK, /SCK
/S1-/CS (D9-D17)
VDD SPD
VDD
VREF
VSS
Serial PD,AM B
DO-D17, AMB
DO-D17
DO-D17,SPD, AMB
VCC AMB
VTT Terminators
Rev. 0.2 / Sep. 2008 7
1
240pin Fully Buffered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
4GB(512Mbx72) ECC FB-DIMM - 2 Rank
Notes:
1. DQ-to-I/O wiring may be changed within a byte.
2. There are two physical copies of each address/command/control/clock.
/S0
VSS
D0
DQS /CS DM
DQ0
DQ1
DQ2
DQ3
/DQS0
/D Q S
DQS0
D1
DQS /CS DM
/D Q S
D2
DQS /CS DM
DQ16
DQ17
DQ18
DQ19
/D Q S
D3
DQS /CS DM
/D Q S
D4
DQS /CS DM
/D Q S
D5
DQS /CS DM
/D Q S
D6
DQS /CS DM
/D Q S
D7
DQS /CS DM
/D Q S
D8
DQS /CS DM
CB0
CB1
CB2
CB3
/D Q S
D18
DQS /CS DM
/D Q S
D19
DQS /CS DM
/D Q S
D20
DQS /CS DM
/D Q S
D21
DQS /CS DM
/D Q S
D22
DQS /CS DM
/D Q S
D23
DQS /CS DM
/D Q S
D24
DQS /CS DM
/D Q S
D25
DQS /CS DM
/D Q S
D26
DQS /CS DM
/D Q S
DQ8
DQ9
DQ10
DQ11
DQ24
DQ25
DQ26
DQ27
DQ32
DQ33
DQ34
DQ35
DQ40
DQ41
DQ42
DQ43
DQ48
DQ49
DQ50
DQ51
DQ56
DQ57
DQ58
DQ59
A ll a dd r e s s/ c o mma n d/ c o n t r o l/ c lo c k VTT
D9
DQS /CS DM
DQ4
DQ5
DQ6
DQ7
/DQS9
/D Q S
DQS9
D10
DQS /CS DM
/DQS10
/D Q S
DQS10
D11
DQS /CS DM
DQ20
DQ21
DQ22
DQ23
/DQS11
/D Q S
DQS11
D12
DQS /CS DM
/DQS14
/D Q S
DQS14
D13
DQS /CS DM
/DQS13
/D Q S
DQS13
D14
DQS /CS DM
/DQS14
/D Q S
DQS14
D15
DQS /CS DM
/DQS15
/D Q S
DQS15
D16
DQS /CS DM
/DQS16
/D Q S
DQS16
D17
DQS /CS DM
CB4
CB5
CB6
CB7
/DQS17
/D Q S
DQS17
D27
DQS /CS DM
/D Q S
D28
DQS /CS DM
/D Q S
D29
DQS /CS DM
/D Q S
D30
DQS /CS DM
/D Q S
D31
DQS /CS DM
/D Q S
D32
DQS /CS DM
/D Q S
D33
DQS /CS DM
/D Q S
D34
DQS /CS DM
/D Q S
D35
DQS /CS DM
/D Q S
DQ12
DQ13
DQ15
DQ28
DQ29
DQ30
DQ31
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQ46
DQ47
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQ62
DQ63
/S1
DQ14
/DQS1
DQS1
/DQS2
DQS2
/DQS3
DQS3
/DQS4
DQS4
/DQS5
DQS5
/DQS6
DQS6
/DQS7
DQS7
/DQS8
DQS8
SA0 SA1 SA2
WP
SCL SDA
A0 A1 A2
Serial PD
SCL U0 SDA
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
PN0-PN13 SN0-SN13
/PN0-/PN13 /SN0-/SN13
PS0-PS9 SS0-SS9
/PS0-/PS9 /SS0-/SS9
DQ0-DQ63 /S0- /C S ( a ll SD RA Ms )
CB0-CB7 CKE0 -> CKE (all SDRAMs)
DQS0-DQS17
/DQS0-/DQS17 ODT -> ODT (all SDRAMs)
SCL
SDA BA0-BA2 (all SDRAMs)
SA0-SA2 A0-A15 (all SD RAM s)
/RESET / R AS ( a ll S D RAMs)
/CA S (all SD R A M s)
/W E (all SD R A M s )
CK, /CK (all SDRAMs)
SCK, /SCK
A
M
B
VDD SPD
VDD
VREF
VSS
Serial PD,AM B
DO-D35, AMB
DO-D35
DO-D35, SPD, AMB
VCC AMB
VTT Terminators
Rev. 0.2 / Sep. 2008 8
1
240pin Fully Buffered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
4GB(512Mbx72) ECC FB-DIMM - 4 Rank
S2
S1
DQS0
DQS0
DQS9
DQ0
DQ1
DQ2
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D0
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
DQ3
DQ4
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D9
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D18
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D27
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
S0 S3
DQS1
DQS1
DQS10
DQ8
DQ9
DQ10
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D1
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
DQ11
DQ12
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D10
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D19
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D28
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
DQS2
DQS2
DQS11
DQ16
DQ17
DQ18
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
DQ19
DQ20
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D11
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D20
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D29
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
DQS3
DQS3
DQS12
DQ24
DQ25
DQ26
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D3
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
DQ27
DQ28
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D12
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D21
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D30
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
DQS4
DQS4
DQS13
DQ32
DQ33
DQ34
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D4
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
DQ35
DQ36
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D13
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D22
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D31
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
Rev. 0.2 / Sep. 2008 9
1
240pin Fully Buffered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
4GB(512Mbx72) ECC FB-DIMM - 4 Rank
SN0-SN13
PN0-PN13
PN0-PN13
PS0-PS9
PS0-PS9
DQ0-DQ63
CB0-CB7
DQS0-DQS17
DQS0-DQS8
SCL
SA1-SA2
SDA
RESET
SCK/SCK
SN0-SN13
SS0-SS9
SS0-SS9
CKE0 -> CKE(D0-D17)
CKE1 -> CKE(D18-D35)
ODT0 -> ODT(D0-D17)
ODT1 -> ODT(D18-D26)
ODT2 -> ODT(D27-D35)
BA0-BA2 (all SDRAMs)
A0,A1-A3-A 5-A7-A15(all SDRA Ms)
A
Serial PD
WP A0 A1 A2
SA0 SA1SA2
SCL SDA
S2
S1
DQS5
DQS5
DQS14
DQ40
DQ41
DQ42
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D5
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
DQ43
DQ44
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D14
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D23
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D32
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
S0 S3
DQS6
DQS6
DQS15
DQ48
DQ49
DQ50
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D6
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
DQ51
DQ52
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D15
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D24
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D33
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
DQS7
DQS7
DQS16
DQ56
DQ57
DQ58
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D7
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
DQ59
DQ60
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D16
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D25
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D34
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
DQS8
DQS8
DQS17
DQ24
DQ25
DQ26
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D8
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
DQ27
DQ28
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D17
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D26
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
I/O 0
I/O 1
I/O 2
NU/ CS
DM/
D35
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
RDQS RDQS DQS DQS
M
B
A2,A6 (D0-D7, D8-D16, D‘8-D2 5, D2 7-D34)
A2_ECC, A6_ECC (D8, D17 , D26, D35)
RAS (all SDRAMs)
CAS (all SDRAMs)
WE (all SDRAMs)
CK/CK (all SDRAMs)
SA0
D0–D17,AMB
V
CC
SPD,AMB
V
DDSPD
V
TT
D0–D17
V
REF
Terminators
V
DD
V
SS
AMB
D0–D17,SPD,AMB
All address/command/control/clock
V
TT
Note:
1. DQ-to-I/O wiring may be changed within a byte.
2. There are two physical copies of each address/command/control/clock excluding
CKE0/1, ODT1/2, CS
Rev. 0.2 / Sep. 2008 10
1
240pin Fully Buffered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
8GB(1Gbx72) ECC FB-DIMM - 4 Rank
S1
S3
S0
S2
D0
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
VSS
D54
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D36
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D18
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS0
DQS0
D1
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D55
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D37
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D19
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS9
DQS9
D2
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D56
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D38
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D20
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS1
DQS1
D3
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D57
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D39
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D21
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS10
DQS10
D4
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D58
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D40
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D22
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS2
DQS2
D5
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D59
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D41
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D23
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS11
DQS11
D6
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D60
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D42
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D24
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS3
DQS3
D7
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D61
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D43
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D25
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS12
DQS12
D8
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D62
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D44
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D26
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS8
DQS8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CB0
CB1
CB2
CB3
DQ20
DQ21
DQ22
DQ23
Rev. 0.2 / Sep. 2008 11
1
240pin Fully Buffered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
8GB(1Gbx72) ECC FB-DIMM - 4 Rank
S1
S3
S0
S2
D9
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
VSS
D63
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D45
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D27
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS4
DQS4
D10
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D64
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D46
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D28
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS13
DQS13
D11
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D65
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D47
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D29
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS5
DQS5
D12
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D66
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D48
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D30
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS14
DQS14
D13
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D67
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D49
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D31
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS6
DQS6
D14
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D68
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D50
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D32
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS15
DQS15
SN0-SN13
PN0-PN13
PN0-PN13
PS0-PS9
PS0-PS9
DQ0-DQ63
CB0-CB7
DQS0-DQS17
DQS0-DQS17
SCL
SA1-SA2
SDA
RESET
SCK/SCK
SN0-SN13
SS0-SS9
SS0-SS9
S0-CS(D36-D53)
S1-CS(D54-D71)
S2-CS(D0-D17)
S3-CS(D18-D35)
CKE0 -> CKE(D0-D17, D36-D53)
CKE2 -> CKE(D18-D35, D54-D71)
ODT -> ODT0(D36-D71)
A
Serial PD
WP A0 A1 A2
SA0 SA1 SA2
SCL SDA
M
B
BA0-BA2 (all SDRAMs)
A0-A13 (all SDRAMs)
ECCA2, ECCA6 -> NC
RAS (all SDRAMs)
CAS (all SDRAMs)
WE (all SDRAMs)
SA0
D0–D71,AMB
V
CC
SPD,AMB
V
DDSPD
V
TT
D0–D71
V
REF
Terminators
V
DD
V
SS
AMB
D0–D71,SPD,AMB
All address/command/control/clock
V
TT
Note:
1. DQ-to-I/O wiring may be changed within a byte.
2. There are two physical copies of each address/command/control /clock excluding CS.
3. There are four physical copies of each clock.
4. ECCA2 and ECCA6 does not use(NC)
5. ODT pin(D0-D35) is connected to VSS
CK/CK (all SDRAMs)
D15
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D69
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D51
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D33
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS7
DQS7
D16
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D70
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D52
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D34
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS16
DQS16
D17
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D71
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
D53
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3 D35
DQS
DM CS DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS17
DQS17
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CB4
CB5
CB6
CB7
DQ52
DQ53
DQ54
DQ55
Rev. 0.2 / Sep. 2008 12
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240pin Fully Buffered DDR2 SDRAM DIMMs
Architecture
Advanced Memory Buffer Pin Description
Pin Name Pin Description Count
FB-DIMM Channel Signals 99
SCK System Clock Input, positive line 1
SCK System Clock Input, negative line 1
PN[13:0] Primary Northbound Data, positive lines 14
PN[13:0] Primary Northbound Data, negative lines 14
PS[9:0] Primary Southbound Data, positive lines 10
PS[9:0] Primary Southbound Data, negative lines 10
SN[13:0] Secondary Northbound Data, positive lines 14
SN[13:0] Secondary Northbound Data, negative lines 14
SS[9:0] Secondary Southbound Data, positive lines 10
SS[9:0] Secondary Southbound Data, negative lines 10
FBDRES To an external precision calibration resistor connected to Vcc 1
DDR2 Interface Signals 175
DQS[8:0] Data Strobes, positive lines 9
DQS[8:0] Data Strobes, negative lines 9
DQS[17:9]/DM[8:0] Data Strobes(x4 DRAM only), positive lines. These signals are driven low to x8
DRAM on writes. 9
DQS[17:9] Data Strobes(x4 DRAM only), negative lines 9
DQ[63:0] Data 64
CB[7:0] Checkbits 8
A[15:0]A,A[15:0]B Addresses. A10 is part of the pre-charge command 32
BA[2:0]A,BA[2:0]B Bank Addresses 6
RASA,RASB Part of command, with CAS, WE and CS[1:0] 2
CASA,CASB Part of command, with RAS, WE and CS[1:0] 2
WEA,WEB Part of command , with RAS, WE and CS[1:0] 2
ODTA,ODTB On-die Termination Enable 2
CKE[1:0]A,CKE[1:0]B Clock Enable(one per rank) 4
CS[1:0]A,CS[1:0]B Chip Select(One per rank) 4
CLK[3:0] CLK[1:0] used on 9 and 18 device DIMMs, CLK[3:0] used on 36 device DIMMs.
CLK[3:2] should be output disabled when not in use. 4
CLK[3:0] Negative lines for CLK[3:0] 4
DDRC_C14 DDR Compensation: Common return pin for DDRC_B18 and DDRC_C18 1
DDRC_B18 DDR Compensation: Resistor connected to common return pin DDRC_C14 1
DDRC_C18 DDR Compensation: Resistor connected to common return pin DDRC_C14 1
DDRC_B12 DDR Compensation: Resistor connected to VSS 1
DDRC_C12 DDR Compensation: Resistor connected to VDD 1
Rev. 0.2 / Sep. 2008 13
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240pin Fully Buffered DDR2 SDRAM DIMMs
Advanced Memory Buffer Pin Description
Note:
1. System Clock Signals SCK and SCK switch at one half the DRAM CK/ CK frequency.
2. TESTLO_AB20 and TESTLO_AC20 should be configured for debug purposes on protype DIMMs : each pin should
have a zero ohm resistor pulldown to ground, and an unpopulated resistor pull-up to VCC.
These resistors can be replaced on production DIMMs with a direct connection to ground.
Pin Name Pin Description Count
SPD Bus Interface Signals 5
SCL Serial Presence Detect (SPD) Clock Input 1
SDA SPD Data Input / Outpu t 1
SA{2:0] SPD Address Inputs, also used to select the DIMM number in the AMB 3
Miscellaneous Signals 163
PLLTSTO PLL Clock Observability Output 1
VCCAPLL Analog VCC for the PLL. Tied with low pass filter to VCC. 1
VSSAPLL Analog VSS for the PLL. Tied to 1
TEST_pin# Leave floating on the DI MM 6
TESTLO_pin# Tie to ground on the DIMM25
BFUNC Tie to ground to set functionality as “buffer on DIMM.” 1
RESET AMB reset signal 1
NC No connect. Many NC are connected to VDD on the DIMM, to lower the
impedance of the VDD power islands. 129
RFU Reserved for Future Use 18
Power/Ground Signals 213
VCC AMB Core Power(1.5 Volt) 24
VCCFBD AMB Channel I/O Power(1.5 Volt) 8
VDD AMB DRAM I/O Power (1.8 Volt) 24
VDDSPD SPD Power (3.3 Volt) 1
VSS Ground 156
Total 655
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240pin Fully Buffered DDR2 SDRAM DIMMs
Pin Assignments for the Advanced Memory Buffer(AMB) (Top View)
655-Ball LFBGA 0.8 mm x 0.8 mm pitch
Left Side
NC= No Connect, RFU= Reserved for Future Use.
Note:
a. These pin positions are reserved for forwarded clocks to be used in future AMB implementations
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
AVSS DQ26 DQ12 VDD DQS10 DQ13 VDD DQS1 DQ10 VDD TEST VDD VDD
BVDD DQS3 DQS3VSS DQ14DQS10 VSS DQ11 DQS1 VSS DDRC TESTLO VDD VSS
C VSS DQS2 DQ18 VSS DQ4 DQS9 VSS DQ15 DQ9 VSS DQ8 DDRC VSS DDRC DQS17
D DQ19 DQS2 VSS DQ16 DQ24 VSS DQS9 DQ7 VSS DQ3 DQS0 VSS DQS8DQS8VDD
E DQ21 VSS DQ17 DQ29 VSS DQ25 DQ6 VSS DQ5 DQ1 VSS DQ0 CB1 VSS CB2
F VSS DQ20 DQ23 VSS DQ31 DQ27 VSS TESTLO TEST VSS DQS0DQ2 VDD CB0CB3
GDQS
11 DQS11 NC NC NC VSS DQS12 DQS12 NC NC NC BFUNC RFU RFU RFU
H DQ22 VSS NC NC NC DQ28 DQ30 VSS NC NC NC VSS VDD VSS VDD
J VSS CLK2 NC NC NC BA1A VSS CKE1A NC NC NC VDD VSS VDD VSS
KCLK
2CLK0 NC NC NC VSS WEARASA NC NC NC VSS VCC VSS VCC
LCLK
0 VSS NC NC NC A0A CKE0A VSS NC NC NC VCC VSS VCC VSS
MODT0ARFU NC NC NC CAS
A VSS BA2A NC NC NC VSS VCC VSS VCC
NCS
1A CS0A NC NC NC VSS BA0A A10A NC NC NC VCC VSS VCC VSS
P A6A VSS NC NC NC A2A A1A A3A NC NC NC VSS VCC VSS VCC
R VSS A8A NC NC NC A11A VSS A5A NC NC NC VCC VSS VCC VSS
T A4A A13A NC NC NC VSS A9A A7A NC NC NC VSS VCC VSS VCC
UPN0PN
0 NC NC NC A15A A14A A12A NC NC NC RFU VCCFBD VSS VSS
VPN1PN
1VSSSN0SN0 VCCFBD VSS VCCFBD VSS RFUaRFUaVCCFBD VSS VSS VSS
WPN2PN
2VSSSN1SN1SN3SN4SN5SN13 SN12 SN6SN7SN8SN9SN10
YPN3PN
3VSSSN2SN0 SN3 SN4 SN6 SN13 SN12 SN6 SN7 SN8 SN9 SN10
AA VSS PN4 PN4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AB VSS RESET PN5PN13 RFUaPN12 PN6PN7PN8PN9VSSAPLLVCCAPLLPN10 PN11
AC VSS PN5 PN13 RFUaPN12 PN6 PN7 PN8 PN9 FBDRES PLLTSTO PN10 PN11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Rev. 0.2 / Sep. 2008 15
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240pin Fully Buffered DDR2 SDRAM DIMMs
Right Side
NC= No Connect, RFU= Reserved for Future Use.
Note:
a. These pin positions are reserved for forwarded clocks to be used in future AMB implementations
16 17 18 19 20 21 22 23 24 25 26 27 28 29
A VDD TEST VDD DQ52 DQS15 VDD DQ49 DQS6 VDD DQ48 DQ38 VDD
B VDD TEST DDRC VSS DQS15 DQ53 VSS DQS6 DQ50 VSS DQS13 DQS13 VSS
CDQS17 VSS DDRC DQ54 VSS DQ55 DQ51 VSS DQS7 DQ56 VSS DQ46 DQS14 VDD
D CB6 CB7 VSS DQS16 DQ63 VSS DQ59 DQS7 VSS DQ36 DQ44 VSS DQS14 DQ47
EVSSCB5DQS16 VSS DQ61 DQ57 VSS DQ58 DQ39 VSS DQ33 DQ45 VSS DQ41
F CB4 VDD DQ62 DQ60 VSS TEST TEST VSS DQ37 DQ35 VSS DQS5DQ43 VSS
G TESTLO RFU RFU NC NC NC DQS4 DQS4 VSS NC NC NC DQS5 DQ40
H VSS VDD VSS NC NC NC VSS DQ34 DQ32 NC NC NC VSS DQ42
J VDD VSS VDD NC NC NC RASBVSS RFU NC NC NC CLK3VSS
K VSS VCC VSS NC NC NC ODT0B CS1B VSS NC NC NC CLK1CLK3
L VCC VSS VCC NC NC NC VSS CASBWEBNC NC NC VSSCLK1
M VSS VCC VSS NC NC NC CS0B VSS BA1B NC NC NC CKE0B VSS
N VCC VSS VCC NC NC NC A0B A2B VSS NC NC NC BA0B BA2B
P VSS VCC VSS NC NC NC VSS A4B A1B NC NC NC VSS CKE1B
R VCC VSS VCC NC NC NC A6B VSS A10B NC NC NC A3B VSS
T VSS VCC VSS NC NC NC A11B A9B VSS NC NC NC A7B A5B
U VSS VCCFBD RFU NC NC NC A8B A15B A14B SA0 SCL SDA PS8PS8
V VCCFBD VSS VCCFBD VSS VCCFBD RFUaRFUaVSS A13B A12B SA2 SA1 PS7PS7
W VSS SS0SS1SS2SS3SS4SS9SS5SS6SS7SS8VSSPS6PS6
Y VSS SS0 SS1 SS2 SS3 SS4 SS9 SS5 SS6 SS7 SS8 VSS PS5PS5
AA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PS9PS9VSS
AB VSS SN11 VSS SCK TESTLO PS0PS1PS2PS3PS4RFU
aVDDSPD VSS
AC RFU SN11 VSS SCK TESTLO PS0 PS1 PS2 PS3 PS4 RFUaVSS
16 17 18 19 20 21 22 23 24 25 26 27 28 29
Rev. 0.2 / Sep. 2008 16
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240pin Fully Buffered DDR2 SDRAM DIMMs
Advanced Memory Buffer(AMB) DRAM Interface Specifications
Please refer to the AMB Specification for all technical requirements
The following specifications for the AMB constitute the subset which is critical for proper operation of the
DDR2 SDRAM interface.
Note:
This list is not complete, more information will follow in later revisions of this specification.
Critical AMB Specifications
Note 1:
The timing numbers are for example only. Design should be based on the latest component specifications
Symbol Parameter Type VDDQ =1.8V +/-0.1V Units Notes
Min. Max
tSU DQ to DQS / DQS setup time (read) Input 245 ps 1
tH DQ to DQS / DQS hold time (read) Input 245 ps 1
tDVBamb AMB Data Valid Before DQS Output 470 ps 1
tDVAamb AMB Data Valid After DQS Output 470 ps 1
tCVBamb C/A/CNTL Valid Before Clock Output 1030 ps 1
tCVAamb C/A/CNTL Valid After Clock Output 890 ps 1
tDQSCKamb DQS/DQS-to-CK/CK output skew Output -240 240 ps 1
CIN Input Capacitance(DQ/DQS/DQS)2.02.5pF1
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240pin Fully Buffered DDR2 SDRAM DIMMs
Basic Functionality
1. Advanced Memory Buffer Overview
The Advanced Memory Buffer reference design complies with the JEDEC FB-DIMM Architecture and Proto-
col
Specification.
2. Advanced Memory Buffer Functionality
2.1 Advanced Memory Buffer
• Supports channel initialization procedures as defined in the initialization chapter of the FB-DIMM Archi-
tecture and Protocol Specification to align the clocks and the frame boundaries verify channel connec-
tivity and identify AMB DIMM position.
• Supports the forwarding of southbound an d nort hbound frames, servicing requests directed to DIMM,
as defined in the protocol chapter, and merging the return data into the northbound frames.
• If the AMB resides on the last DIMM in the channel, the AMB initializes northbound frames.
• Detects errors on the channel a nd reports them to the host memory controller.
• Acts as DRAM memory buffer for all read, write and configuration accesses addressed to the DIMM.
• Provides a read buffer FIFO and a write buffer FIFO.
• Supports an SMBus protocol interface for access to the AMB configuration registers.
• Provides logic to support MEMBIST and IBIST Design for Test functions.
• Provides a register interface for the thermal sensor and status indicator.
• Functions as a repeater to extend the maximum length of FBD Links.
2.2 Transparent Mode for DRAM Test Support
In this mode, the Advanced Memory Buffer will provide lower speed tester access to DRAM pins through
the FB-DIMM I/O pins. This allows the tester to send and arbitr ary test patt ern to the DRAMs. Transparent
mode only supports a maximum DRAM frequency equiva lent to DDR2 400.
Transparent mode functionality:
• Reconfigure FB-DIMM inputs from differential high speed link receivers to two single ended lower
speed receivers(~200 Mhz)
• These inputs directly control DDR2 Command/Address and input data that is replicated to all DRAMs
• Used low speed direct drive FB-DIMM outputs to bypass high speed Par allel/Serial circuitry and provide
test results back to tester
2.3 DDR2 SDRAM
• Supports DDR2 at speeds of 533,667 and 800 MT/s
• Supports 512Mb devices in x4 and x8 configurations
• 72 bit DDR2 SDRAM memory array
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240pin Fully Buffered DDR2 SDRAM DIMMs
3. Advanced Memory Buffer Block Diagram
PISO
Re-synch
Demux
Re-Time
Data Mer ge
Data Merge
Re-synch
Demux PISO
Re-Time
Link init SM &
Control & CSRs
Failover
IBIST - RX
LAI Logic
IBIST - RX
MUX
Init
patterns
MUX MUX
36 Deep
Write
Data
FIFO
DDR State
Controller
& CSRs
Command
Decoder &
CRC Check
External MEMBIST
DDR Calibration &
DDR IOBIST/DFX
Failover
MUX
Data CRC Gen
& Read FIFO Sync & Idle
Pattern Generator
IBIST - TX IBISt - RX
NB LAI
Buffer
Link init SM &
Control & CSRs
Core Control
& CSRs
Thermal
Sensor
LAI
Controller
SMbus
Controller
SMbus
Reset
Control
Reset#
PLL
1x2
I0*12 I0*12
14*6*2 14*12
Data In
Data
Out
Cmd
Out
DDR
IO’s
DRAMclock
DRAMclock#
DRAM Address
/CommandCopy1
DRAM Address
/CommandCopy2
DRAM Address
Data/Strobe
South bound
Data in South bound
Data out
Northbound
DataOut Northbound
DataIn
14x2
DRAM Cmd
14x2
10x2 10x2
Advanced Memory Buffer Block Diagram
Ref Clock
4
4
29
29
72+18X2
Rev. 0.2 / Sep. 2008 19
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240pin Fully Buffered DDR2 SDRAM DIMMs
4. Interfaces
Below Figure illustrates the AMB and all of its interfaces.They consists of two FB-DIMM links, one DDR2 channel and
an SMBus interface. Each FB-DIMM link connects the AMB to a host memory controller or an adjacent FB-DIMM.
The DDR2 channel supports direct connection to the DDR2 SDRAMs on a Fully Buffered DIMM.
4.1 FBD High-Speed Differential Point-to-Point Link (at 1.5V) Interfaces
The Advanced Memory Buffer supports one FBD channel consisting of two bidirectional link interfaces
using high speed differential point- to-point electrical signaling.
The southbound input link is 10 lanes wid and carries commands and write data from the host memory
controller or the adjacent DIMM in the host direction. The southbound output link forw ards this same data
to the next FBD.
The northbound input link is 13 to 14 lanes wide and carries read return data or status information from
the next FB-DIMM in the chain back towards the host. The northbound output link forwards this informa-
tion back towards the host and multiplexes in any read return data or status information that is generated
internally.
4.2 DDR2 Channel
The DDR2 channel on the Advanced Memory Buffer supports direct connection to DDR2 SDRAMs. The
DDR2 channel supports two ranks of eight banks with 16 row/column request, 64 data signals, and eight
check-bit signals.
There are two copies of address and command signals to support DIMM routing and electrical require-
ments.
Four transfer bursts are driven on the data and check-bit lines at 800 MHz. Propagation delays between
read data/check-bit strobe lanes on a given channel can differ. Each strobe can be calibrated by hardware
state machines using write/read trial and error. Hardware aligns the read data and check-bits to a single
core clock. The Advanced Memory Buffer provides four copies of the command clock phase refer-
ences(CLK[3:0]) and write data/check-bit strobes(DQSs) for each DRAM nibble.
AMB
SMBus
Mem ory Interface
DDR2
Channel
NB FBD
In Link
SB FBD
Out Link
NB FBD
Out Link
SB FBD
In Lin k
Primary or Host
Direction
Secondary or to
optional next FBD
Advanced M em ory Buffer Interfaces
Rev. 0.2 / Sep. 2008 20
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240pin Fully Buffered DDR2 SDRAM DIMMs
4.3 SMBus Slave Interface
The Advanced Memory Buffer supports an SMBus interface to allow system access to configuration regis-
ters independent of the FB-DIMM link. The Advanced Memory Buffer will never be a master on the SMBus,
only a slave. Serial SMBus data transfer is supported at 100 kHz. SMBus access to the Advanced Memory
Buffer may be a requirement to boot and to set link strength, frequency and other parameters needed to
insure robust configurations. It is also required for diagnostic support when the link is down. The SMBus
address straps located on the DIMM connector are used by the unique ID.
4.4 FBD Channel Latency
FB-DIMM channel latency is measured from the time a read request is driven on the FB-DIMM channel pins
to the time when the first 16 bytes (2nd chunk) of read completion data is sampled by the memory con-
troller. When not using the Variable Read Latency capability, the latency for a specific DIMM on a channel
is always equal to the latency f or any other DIMM on that channel. Howev er, the latency for each DIMM in
a specific configuration with some number of DIMMs installed. As more DIMMs are added to the channel,
additional latency is required to read from each DIMM on the channel. Because the channel is based on
the point to point interconnection of buff er components between DIMMs, memory requests are required to
travel through N-1 buffers before reaching the Nth buffer. The result is that a 4 DIMM channel configura-
tion will have greater idle read latency compared to a 1DIMM channel configuration.The Variable Read
Latency capability can be used to reduce latency for DIMMs closer to the host. The idle latencies listed in
this section are representative of what might be achieved in typical AMB designs. Actual implementations
with latencies less than the values listed will have higher application performance and vice versa.
4.5 Peak Theoretical Throughput
An FB-DIMM channel transfers read completion data on the FBD Northbound data connection. 144 bits of data are
transferred for every FBD Northbound data frame. This matches the 18-byte data transfer of an ECC DDR DRAM in a
single DRAM command clock. A DRAM burst of 8 from a single channel or a DRAM burst of four from two lock stepped
channels provides a total of 72 bytes of data(64 bytes plus 8 bytes ECC)
The FBD frame rate matches the DRAM command clock because of the fixed 6:1 ratio of the FBD channel clock to the
DRAM command clock. Therefore, the Northbound data connection will exhibit the same peak theoretical throughput
as a single DRAM channel. For example, when using DDR2 533 DRAMs, the peak theoretical throughput as a single
DRAM channel.For example, when using DDR2 533 DRAMs, the peak theoretical bandwidth of the Northbound data
connection is 4.276 GB/sec.
Write data is transferred on the FBD Southbound command and data connection, via Command+Wdata frames. 72
bits of data are transferred for every FBD Command+Wdata frame. Two Command+Wdata frames match the 18-byte
data transfer of and ECC DDR DRAM in a single DRAM command clock. A DRAM burst of 8 transfers from a single
channel, or a burst of 4 from two lock-step channels provides a total of 72 bytes of data(64 bytes plus & bytes ECC)
When the FBD frame rate matches the DRAM command clock, the Southbound command and data connection will
exhibit one half the peak theoretical throughput of a single DRAM channel. For example, when using DDR2 533
DRAMs, the peak theoretical bandwidth of the Southbound command and data connection is 2.133 GB/sec.
The total peak theoretical throughput for a single FBD channel is defined as the sum of the peak theoretical through-
put of the Northbound da ta connection and the Southb ound command and data con nection. When the FBD fr ame r ate
matches the DRAM command clock, this is equal to 1.5 times the peak theoretical throughput of a single DRAM chan-
nel. For example, when using DDR2 533 DRAMs, the peak theoretical throughput of a DDR2 533 channel would be
4.267 GB/sec, while the peak theoretical throughput of and FBD -/+533 channel would be 6.4 GB/sec.
Rev. 0.2 / Sep. 2008 21
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240pin Fully Buffered DDR2 SDRAM DIMMs
5 Hot-add
The FB-DIMM channel does not provide a mechanism to automatically detect and report the addition of a
new DIMM south of the current ly active last DIMM. It is assumed the system will be notified through some
means of the addition of one or more new DIMMs so that specific commands can be sent to the host con-
troller to initialize the newly added DIMM(s) and perform a Hot-add Reset to bring them into the channel
timing domain. It should be noted that the power to the DIMM socket must be removed bef ore a “hot- add”
DIMM is inserted or removed. Applying or removing the power to a DIMM socket is a system platform
function.
6 Hot-remove
In order to accomplish removal of DIMMs the host must perform a F ast Reset sequence targeted at the last
DIMM that will be retained on the channel. The Fast Reset re-establish the appropriate last DIMM so that
the Southbound
Tx outputs of the last DIMM and the Southbound and Northbound outputs of the DIMMs beyond the last
active DIMM are disabled. Once the appropriate output s ar e disabled the system can coor dinate the proce-
dure to remove power in preparation for physical removal of the DIMM if needed.
It should be noted that the power to the DIMM socket must be removed before a “hot-add” DIMM is
inserted or removed. Applying or removing the power to a DIMM socket is a system platform function.
7 Hot-replace
Hot replace of DIMM is accomplished through combing th Hot-Remove and Hot-Add process.
Rev. 0.2 / Sep. 2008 22
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240pin Fully Buffered DDR2 SDRAM DIMMs
Electrical Characteristics
ABSOLUTE MAXIMUM RATINGS
Note:
1. Stress greater than those listed may cause permanent dama ge to the device. This is a stress r ating only, and device
functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
OPERATING TEMPERATURE RANGE
Note:
1. Within the DRAM component Case Temperature range all DRAM specification will be supported.
2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced from 7.8us of
tREFI to 3.9us.
Supply Voltage Leve ls and DC Operating Conditions.
Note:
1. Applies for SMB and SPD bus Signals.
2. Applies for AMB CMOS Signal RESET.
3. for all other AMB related DC parameters, please refer to the High Speed Differential Link Interface Specifications
Parameter Symbol Value Unit Note
Voltage on any pins relative to Vss VIN, VOUT - 0.3 V ~ 1.75 V V 1
Voltage on VCC relative to Vss VCC - 0.3 V ~ 1.75 V V 1
Voltage on VDD relative to Vss VDD - 0.5 V ~ 2.3 V V 1
Voltage on VTT relative to Vss VTT - 0.5 V ~ 2.3 V V 1
Storage Temperature range TSTG - 55 oC ~ 100 oCoC1
Parameter Symbol Rating Units Notes
AMB Component Case temperature Range TCASE 0 ~ + 110 oC
DRAM Compone nt Case Temperature Range TCASE 0 ~ + 95 oC1,2
Parameter Symbol Min Nom Max Unit Note
AMB Supply Voltage VCC 1.455 1.5 1.575 V
DRAM Supply Voltage VDD 1.7 1.8 1.9 V
Termination Voltage VTT 0.48 x VDD 0.50 x VDD 0.52 x VDD V
EEPROM Supply Voltage VDDSPD 3.0 3.3 3.6 V
DC Input Logic High(SPD) VIH(DC) 2.1 - VDDSPD V1
DC Input Logic Low(SPD) VIL(DC) --0.8V1
DC Input Logic High(RESET) VIH(DC) 1.0 --V2
DC Input Logic Low(RESET) VIL(DC) --+0.5V2
Leakage Current (RESET) IL -90 - +90 uA 2
Leakage Cu rrent (Link) IL -5 - +5 uA 3
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240pin Fully Buffered DDR2 SDRAM DIMMs
Timing Parameters
Note:
1. Defined in FB-DIMM Architecture and Protocol Spec.
Environmental Parameters
Note:
1. The designer must meet the case temperature specifications for individual module components.
2. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and
device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating
conditions for extended periods
Parameter Symbol Min Typ Max Unit Note
EI Assertion Pass-Thru Timing tEI Propagad - 4 clks -
EI Deassertion Pass-Thru Timing tEID bit lock clks -
EI Assertion Duration tEI 100 clks 1
Bit Lock Interval tBitLock 119 frames 1
Frame Lock Interval tFr a meLock 154 frames 1
Symbol Parameter Rating Units Notes
TOPR Operating temperature See Note 1
HOPR Operating humidity(relative) 10 to 90 % 2
TSTG Storage temperature -50 to +100 oC2
HSTG Storage humidity(without condensation) 5 to 95 % 2
PBAR Barometric pre ssure(operating) 3050 m 2
PBAR Barometric pressure (storage) 15240 m 2
Rev. 0.2 / Sep. 2008 24
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240pin Fully Buffered DDR2 SDRAM DIMMs
IDD Specification and Conditions
IDD Measurement Conditions
Symbol Conditions
Idle_0 Idle Current, single or last DIMML0 state, idle (0 BW)Primary channel enabled, Sec-
ondary Channel Disabled CKE high. Command and address lines s table. DRAM clock
active.
Idle_1 Idle Current, first DIMML0 state, idle (0 BW)Primary and Secondary channels
enabled CKE high. Command and address lines stable. DRAM clock active.
Idle_2 Idle Current, DRAM power downL0 state, idle (0 BW)Primary and Secondary chan-
nels enabledCKE low. Command and address lines floated. DRAM clock active, ODT
and CKE driven low.
Active_1 Active PowerL0 state. 50% DRAM BW, 67% read, 33% write.
Primary and Secondary channels enabled. DRAM clock active, CKE high.
Active_2 Active P ower, data pass throughL0 state. 50% DRAM BW to downstream DIMM,
67% read, 33% write. Primary and Secondary channels enabled CKE high.
Command and address lines stable. DRAM clock active.
L0s Channel Standby A ver age powe r over 42 fr ames where the channel enters and exits
L0sDRAMs Idle (0 BW). CKE low. Command and address lines floated.
Dram clocks active, ODE and CKE driven low.
Training
(for AMB spec, not in
SPD)
Training Primary and Secondary channels enabled.100% toggle on all channels
lanes.DRAMs idle (0 BW).CKE high. Command and address lines stable.DRAM clock
active.
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240pin Fully Buffered DDR2 SDRAM DIMMs
IDD Power Supply Currents Specifications.
SAC Timing Parameters by Speed Grade
Note:
1) Assure that Primary channel Drive strength at 10 0% with De-emphas is at -6.5dB Secondary channel dr iv e streng th
at 60% with De-emphasis at -3dB when enabled. Address and Data fields ar e pseudo-random, which provides a 50%
toggle rate on DRAM data lines and link lanes when data is being transferred.
Assuming 1 activate command and 1 read/write command per BL=4 transferBL=4.10 lanes southbound and 14 lanes
northbound are enabled and acti ve (12 lanes NB if non-ECC DIMM).
SPD specific assumption:Number of devices on the specific DIMM assumed.Termination of command, address, and
control is actual value used on the DIMM. ECC or non-ECC as per the specific DIMM.
SPD specifies Delta TAMB power spec specific assumptions: Dual rank x8 ECC DIMM assumed (18 DRAM devices
present on DIMM)
Modeled with 27 ohm termination for command, address, and clocks, and 47 ohm termina tio n f o r contr o l.
ECC DIMM assumed (72 bit data, 14 lanes northbound). AMB specification specifies current for each rail.
Power Supply Max. Unit Note1)
Icc_Idle_0 @1.5V TBD mA
Idd_Idle_0 @1.8V TBD mA
Idle_0 Total P ower TBD W
Icc_Idle_1 @1.5V TBD mA
Idd_Idle_1 @1.8V TBD mA
Idle_1 Total P ower TBD W
Icc_Idle_2 @1.5V TBD mA
Idd_Idle_2 @1.8V TBD mA
Idle_2 Total P ower TBD W
Icc_Active_1 @1.5V TBD mA
Idd_Active_1 @1.8V TBD mA
Active_1 Total Power TBD W
Icc_Active_2 @1.5V TBD mA
Idd_Active_2 @1.8V TBD mA
Active_2 Total Power TBD W
Icc_L0s @1.5V TBD mA
Idd_L0s @1.8V TBD mA
L0s Total Power TBD W
Icc_Training @1.5V TBD mA
Idd_Training @1.8V TBD mA
Training Total Power TBD W
Rev. 0.2 / Sep. 2008 26
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240pin Fully Buffered DDR2 SDRAM DIMMs
Termination Current
Internal signals ar e terminated on the DIMM t hrough resistors to an external power supply VT T = VDD / 2.
Modeled with 30 Ohm termination for clocks, 39 ohm for command / address and 47 ohm for control.
The VTT power supply must be able to source and sink these currents:
VTT Currents table
Description Symbol Typ Max Unit
Idle Current, DRAM Power Down (Conditions TBD)
I
TT1 -700mA
Active Power, 50% DRAM BW (conditions TBD)
I
TT2 -700mA
Rev. 0.2 / Sep. 2008 27
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240pin Fully Buffered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
128Mx72, 1GB Module (1 rank of x8 based DDR2 SDRAMs)
HMP112F7EFR8C(N3, D3, D5)
Note 1: All dimensions are typical millimeter scale unless otherwise stated.
FRON T V IEW
BACK VIEW
FRONT VIEW W ITH HEAT SPREADER
Side
1.27±0.10
3.0 max
8.20 max
5.20 max
Chekbit
133.35 ±0.15
30.35
5.00
67.00 51.00
4.0 ±0.1
AMB
BACK VIEW WITH HEAT SPREADER
Rev. 0.2 / Sep. 2008 28
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240pin Fully Buffered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
256Mx72, 2GB Module (2 ranks of x8 based DDR2 SDRAMs)
HMP125F7EFR8C(N3, D3, D5)
Note 1: All dimensions are typical millimeter scale unless otherwise stated.
FRONT VIEW
BACK VIEW
FRONT VIEW W ITH HEAT SPR EAD ER
BACK VIEW W ITH HEAT SPREADE R
Side
1.27±0.10
3.0 max
8.20 max
5.20 max
ChekbitChekbit
133.35 ±0.15
30.35
5.00
67.00 51.00
4.0 ±0.1
AMB
Rev. 0.2 / Sep. 2008 29
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240pin Fully Buffered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
512Mx72, 4GB Module (2 ranks of x4 based DDR2 SDRAMs)
HMP151F7EFR4C(N3, D3, D5)
Note 1: All dimensions are typical millimeter scale unless otherwise stated.
FRONT VIEW
BACK VIEW
FRONT VIEW W ITH HEAT SPREADER
BACK VIEW WITH HE AT S PR E ADER
Side
1.27±0.10
3.0 max
8.20 max
5.20 max
133.35 ±0.15
30.35
5.00
67.00 51.00
4.0 ±0.1
Rev. 0.2 / Sep. 2008 30
1
240pin Fully Buffered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
512Mx72, 4GB Module (4 ranks of x8 based DDR2 SDRAMs)
HMP151F7EFR8D5
Note 1: All dimensions are typical millimeter scale unless otherwise stated.
FRONT VIEW
BACK VIEW
FRONT VIEW W ITH HEAT SPREADER
BACK VIEW WITH HE AT S PR E ADER
Side
1.27±0.10
3.0 max
8.20 max
5.20 max
133.35 ±0.15
30.35
5.00
67.00 51.00
4.0 ±0.1
Rev. 0.2 / Sep. 2008 31
1
240pin Fully Buffered DDR2 SDRAM DIMMs
PACKAGE OUTLINE
1Gx72, 8GB Module (4 ranks of x4 based DDR2 SDRAMs)
HMP31GF7EMR4D5
Note 1: All dimensions are typical millimeter scale unless otherwise stated.
FRONT VIEW
BACK VIEW
FRONT VIEW W ITH HEAT SPREADER
BACK VIEW WITH HE AT S PR E ADER
Side
1.27±0.10
3.0 max
8.20 max
5.20 max
133.35 ±0.15
30.35
5.00
67.00 51.00
4.0 ±0.1
Rev. 0.2 / Sep. 2008 32
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240pin Fully Buffered DDR2 SDRAM DIMMs
REVISION HISTORY
Revision History Date Remark
0.1 First Version Release July. 2008
0.2 Quad Rank FBDIMM Added Sep. 2008
