SRM2264LCT10/12 CMOS 64K-BIT STATIC RAM Industrial Temperature Range Low Supply Current Access Time 100ns/120ns 8,192 Words x 8 Bits, Asynchronous DESCRIPTION The SRM2264LCT10/12 is an 8,192-word x 8-bit asynchronous, static, random access memory on a monolithic CMOS chip. Its very low standby power requirement makes it ideal for applications requiring non-volatile storage with back-up batteries. The -40 to 85C operating temperature range is good for industrial use. The asynchronous and static nature of the memory requires no external clock or refreshing circuit. Both the input and output ports are TTL compatible, and the three-state output allows easy expansion of memory capacity. FEATURES * * * * * * * * * Industrial temperature range . . . . . . . . . . . . . -40 to 85C Fast access time . . . . . . . . . . . . . . . . . . . . . . SRM2264LCT10 . . . . . . . . . . . . . . . . . . .100ns (Max) SRM2264LCT12 . . . . . . . . . . . . . . . . . . .120ns (Max) Low supply current. . . . . . . . . . . . . . . . . . . . . Standby : 0.5A (Typ) Operation : 47mA (Typ) . . . . . . . . . . . . . . . 100ns 45mA (Typ) . . . . . . . . . . . . . . . 120ns Completely static . . . . . . . . . . . . . . . . . . . . . . No clock required Single power supply. . . . . . . . . . . . . . . . . . . . 5V 10% TTL compatible inputs and outputs Three-state output with wired-OR capability Non-volatile storage with back-up batteries Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRM2264LCT10/12 . . . . . . . . . . . 28-pin DIP (plastic) SRM2264LMT10/12 . . . . . . . . . . 28-pin SOP (plastic) 000-97-MEM-1.0 S-MOS Systems, Inc. * 150 River Oaks Parkway * San Jose, CA 95134 * Tel: (408) 922-0200 * Fax: (408) 922-0238 45 SRM2264LCT10/12 CS2 OE WE X Decoder 512 Memory Cell Array 512 x 16 x 8 Y 4 Decoder 16 x 8 16 Column Gate CS1, CS2 Chip Control CS1 9 8 OE, WE Chip Control A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 Address Buffer BLOCK DIAGRAM I/O Buffer I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 46 S-MOS Systems, Inc. * 150 River Oaks Parkway * San Jose, CA 95134 * Tel: (408) 922-0200 * Fax: (408) 922-0238 000-97-MEM-1.0 SRM2264LCT10/12 PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SRM2264LCT NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS PIN DESCRIPTION 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD WE CS2 A8 A9 A11 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 A0 to A12 Address Input WE Write Enable OE Output Enable CS1, CS2 Chip Select I/O1 to 8 Data Input/Output VDD Power Supply (+5V) VSS Logic Power Supply (0V) NC No Connection ABSOLUTE MAXIMUM RATINGS (VSS = 0V) Parameter Symbol Ratings Unit Supply voltage VDD -0.5 to 7.0 V Input voltage* VI -0.5 to 7.0 V Input/output voltage* VI/O -0.5 to VDD + 0.3 V Power dissipation PD 1.0 W Operating temperature TOPR -40 to 85 C Storage temperature TSTG -65 to 150 C Soldering temperature and time TSOL 260C, 10s (at lead) -- *VI, VI/O (Min) = -3.0V (Pulse width is 50ns) RECOMMENDED DC OPERATING CONDITIONS Parameter (VSS = 0V, Ta = -40 to 85C) Symbol Min Typ Max Unit VDD 4.5 5.0 5.5 V VSS 0 0 0 V VIH 2.2 3.5 VDD + 0.3 V VIL -0.3* 0 0.8 V Supply voltage Input voltage * If pulse width is less than 50ns, it is -1.0V 000-97-MEM-1.0 S-MOS Systems, Inc. * 150 River Oaks Parkway * San Jose, CA 95134 * Tel: (408) 922-0200 * Fax: (408) 922-0238 47 SRM2264LCT10/12 ELECTRICAL CHARACTERISTICS DC Electrical Characteristics (VDD = 5V 10%, VSS = 0V, Ta = -40 to 85C) SRM2264LCT10 Parameter Symbol Input leakage current SRM2264LCT12 Conditions Unit Min Typ* Max Min Typ* Max ILI VI = 0 to VDD -1 -- 1 -1 -- 1 A IDDS CS1 = VIH or CS2 = VIL -- 0.5 1.0 -- 0.5 1.0 mA IDDS1 CS1 = CS2 VDD - 0.2V or CS2 0.2V -- 0.5 30 -- 0.5 30 A Average operating current IDDA VI = VIL, VIH II/O = 0mA, tCYC = Min -- 47 82 -- 45 80 mA Operating supply current IDDO VI = VIL, VIH II/O = 0mA -- 35 60 -- 35 60 mA Output leakage ILO CS1 = VIH or CS2 = VIL or WE = VIL or OE = VIH, VI/O = 0 to VDD -1 -- 1 -1 -- 1 A High level output voltage VOH IOH = -1.0mA 2.4 VDD - 0.1 -- 2.4 VDD - 0.1 -- V Low level output voltage VOL IOL = 4.0mA -- 0.2 0.4 -- 0.2 0.4 V Standby supply current * Typical values are measured at Ta = 25C and VDD = 5.0V Terminal Capacitance Parameter Address capacitance Input capacitance I/O capacitance 48 (f = 1MHz, Ta = 25C) Symbol Conditions Min Typ Max Unit CADD VADD = 0V -- 3 5 pF CI VI = 0V -- 5 6 pF CI/O VI/O = 0V -- 6 7 pF S-MOS Systems, Inc. * 150 River Oaks Parkway * San Jose, CA 95134 * Tel: (408) 922-0200 * Fax: (408) 922-0238 000-97-MEM-1.0 SRM2264LCT10/12 AC Electrical Characteristics Read Cycle (VDD = 5V 10%, VSS = 0V, Ta = -40 to 85C) SRM2264LCT10 Parameter Symbol SRM2264LCT12 Conditions Unit Min Max Min Max Read cycle time tRC 100 -- 120 -- ns Address access time tACC -- 100 -- 120 ns CS1 access time tACS1 -- 100 -- 120 ns CS2 access time tACS2 -- 100 -- 120 ns OE access time *1 tOE -- 50 -- 60 ns CS1 output set time tCLZ1 10 -- 10 -- ns CS1 output floating time tCLZ1 -- 35 -- 40 ns CS2 output set time tCLZ2 10 -- 10 -- ns *2 CS2 output floating time tCLZ2 -- 35 -- 40 ns OE output set time tOLZ 5 -- 5 -- ns OE output floating time tOLZ -- 35 -- 40 ns Output hold time tOH 10 -- 10 -- ns *1 Write Cycle (VDD = 5V 10%, VSS = 0V, Ta = -40 to 85C) SRM2264LCT10 Parameter Symbol SRM2264LCT12 Conditions Unit Min Max Min Max Write cycle time tWC 100 -- 120 -- ns Chip select time 1 tCW1 80 -- 85 -- ns Chip select time 2 tCW2 80 -- 85 -- ns Address enable time tAW 80 -- 85 -- ns Address setup time tAS 0 -- 0 -- ns Write pulse width tWP 60 -- 70 -- ns Address hold time tWR 0 -- 0 -- ns Input data setup time tDW 50 -- 50 -- ns Input data hold time tDH 0 -- 0 -- ns -- 35 -- 40 ns 5 -- 5 -- ns WE output floating *1 tWHZ *3 WE output setup time 000-97-MEM-1.0 tOW S-MOS Systems, Inc. * 150 River Oaks Parkway * San Jose, CA 95134 * Tel: (408) 922-0200 * Fax: (408) 922-0238 49 SRM2264LCT10/12 *1 Read/Write Cycle Test Conditions 1. Input pulse level: 0.8V to 2.4V 2. tr = tf = 10ns 3. Input and output timing reference levels: 1.5V 4. Output load ITTL + CL = 100pF *2 Read Cycle Test Conditions 1. Input pulse level: 0.8V to 2.4V 2. tr = tf = 10ns 3. Test Circuit Test: tCHZ1, tCHZ2, tOHZ Both SW1 and SW2 are closed. Test: tCLZ1, tCLZ2, tOLZ Hi-Z"H" SW1 is open, SW2 is closed. Test: tCLZ1, tCLZ2, tOLZ Hi-Z"L" SW1 is closed, SW2 is open. Output turn-on turn-off times VDD To scope SW1 300 1.5V OE To output terminal 1.5V tOLZ I/O 1 k 5 pF Hi-Z tOHZ "H" "H" 1.5V "L" "L" 1.5V CS1 Hi-Z 0.5V 1.5V tCHZ1 tCLZ1 CS2 Include scope, test, tool capacity 1.5V SW2 VSS VSS 1.5V tCLZ2 I/O *3 Write Cycle Test Conditions 1. Input pulse level: 0.8V to 2.2V 2. tr = tf = 10ns 3. Test Circuit Hi-Z 1.5V "H" "H" 1.5V "L" "L" tCHZ2 0.5V Hi-Z 1.5V Test: tOW, tWHZ Hi-Z"H" and "H"Hi-Z SW is VDD side Test: tOW, tWHZ Hi-Z"L" and "L"Hi-Z SW is VSS side Output turn-on turn-off times VDD To scope 300 WE 1.5V 1.5V tOW To output terminal I/O SW Hi-Z H 0.1V 0.1V tWHZ 0.1V Hi-Z 0.1V L 1 k 5 pF Include scope, test, tool capacity VSS 50 VSS S-MOS Systems, Inc. * 150 River Oaks Parkway * San Jose, CA 95134 * Tel: (408) 922-0200 * Fax: (408) 922-0238 000-97-MEM-1.0 SRM2264LCT10/12 Timing Charts Read Cycle*1 tRC ADDRESS tOH tACC tACS1 CS1 CS2 tCLZ1 tCHZ1 tACS2 tCLZ2 tCHZ2 OE tOLZ Dout tOE tOHZ Note: *1. During the read cycle, WE must be "H". Write Cycle (1) (CS1 Control)*2 tWC ADDRESS tAW tWR tCW1 CS1 tAS CS2 WE Dout tDW tDH Din Note: *2. During write cycle (1) and (2), the Output Buffer is in high impedance regardless of the OE level. 000-97-MEM-1.0 S-MOS Systems, Inc. * 150 River Oaks Parkway * San Jose, CA 95134 * Tel: (408) 922-0200 * Fax: (408) 922-0238 51 SRM2264LCT10/12 Write Cycle (2) (CS2 Control)*2 tWC ADDRESS tAW tWR CS1 tAS CS2 tCW2 WE Dout tDW tDH Din Note: *2. During write cycle (1) and (2), the output buffer is in high impedance regardless of the OE level. Write Cycle (3) (WE Control)*3 tWC ADDRESS tAW tWR CS1 tAS CS2 tWP WE tWHZ tOW Dout tDW tDH Din Note: *3. During write cycle (3), the output buffer is in high impedance if the OE level is "H". 52 S-MOS Systems, Inc. * 150 River Oaks Parkway * San Jose, CA 95134 * Tel: (408) 922-0200 * Fax: (408) 922-0238 000-97-MEM-1.0 SRM2264LCT10/12 DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY (Ta = 0 to 70C) Parameter Symbol Conditions Min Typ Max Unit 2.0 -- 5.5 V -- -- 10 A Data retention supply voltage VDDR Data retention current IDDR Chip select data hold time tCDR 0 -- -- ns tR tRC* -- -- ns Operation recovery time VDD = 3V CS1 = CS2 VDD - 0.2V or CS2 0.2V * tRC = Read Cycle time Data Retention Timing (CS1 Control) Data hold mode VDD CS1 4.5V VDDR 2.0V tCDR 4.5V tR CS1 VDD - 0.2V 2.2V 2.2V Data Retention Timing (CS2 Control) Data hold mode VDD CS2 000-97-MEM-1.0 tCDR 0.4V 4.5V VDDR 2.0V 4.5V tR CS2 0.2V 0.4V S-MOS Systems, Inc. * 150 River Oaks Parkway * San Jose, CA 95134 * Tel: (408) 922-0200 * Fax: (408) 922-0238 53 SRM2264LCT10/12 FUNCTIONS Truth Table CS1 CS2 OE WE A0 to A12 Data I/O Mode IDD H X -- -- -- Hi-Z Unselected IDDS, IDDS1 -- L -- -- -- Hi-Z Unselected IDDS, IDDS1 L H X L Stable Input data Write IDDO L H L H Stable Output data Read IDDO L H H H Stable Hi-Z Output disable IDDO X: "H" or "L" --: "H", "L", or "Hi-Z" Read Data A read cycle begins with stable address data at the address port (A0 to A12), CS1 = "L", CS2 = "H", and OE = "L". Valid data is available at the data port (I/O1 to I/O8) within 100 or 120ns depending on the device. Write Data There are four ways of writing data into memory (see "Timing Charts", above): 1. 2. 3. 4. Write Cycle (1) -- CS1 control -- Write is accomplished by an active CS1 pulse. Write Cycle (2) -- CS2 control -- Write is accomplished by an active CS2 pulse. Write Cycle (3) -- WE control -- Write is accomplished by an active WE pulse. This method is a combination of the previous write cycles. Beginning with a stable address and all control signals in their non-active states (WE = "H", CS1 = "H" and CS2 = "L"), pulse all three control signals. The trailing edge of any of the write control signal pulses (WE, CS1, CS2) causes data on the data I/O pins to be latched into memory. Data bus contention is avoided since bringing CS1 and CS2 to their inactive states places the Data I/O pins in a high-impedance state. Standby Mode When CS1 and CS2 are in their inactive states, (CS1 = "H", CS2 = "L"), the SRM2264LCT10/12 is in standby mode. The only operation performed in standby mode is data retention. The data I/O pins are in a high impedance state. All other inputs can be either "H" or "L". This mode is maintained as long as the CS2 level is less than 0.2V and the CS1 level is greater than VDD - 0.2V. In this condition, the only current flow in the chip is caused by high-resistance paths in memory. 54 S-MOS Systems, Inc. * 150 River Oaks Parkway * San Jose, CA 95134 * Tel: (408) 922-0200 * Fax: (408) 922-0238 000-97-MEM-1.0 SRM2264LCT10/12 PACKAGE DIMENSIONS 28-pin DIP C28 1.472Max (37.4Max) Unit: Inches (mm) 1.445 0.004 (36.7 0.1) 15 1 14 0.100 0.010 (2.54 0.25) 0.600 (15.24) 0.010 0.0012 0.0004 (0.25 0.03 0.01) 0.600~0.655 (15.24~16.64) 0.130 0.002 (3.3 0.05) 0.059 (1.5 ) 0.024 0.004 (0.6 0.1) 0.181 0.004 (4.6 0.1) 0.528 0.004 (13.4 0.1) 28 0.018 0.004 (0.46 0.1) 28-pin SOP M28-2 0.713 Max (18.1 Max) 0.701 0.004 (17.8 0.1) 14 0.098 0.006 (2.5 0.15) 000-97-MEM-1.0 0.016 0.004 (0.4 0.1) 0.008 (0.2) 0.050 (1.27) 0.370 (9.4) 0.106 (2.7) 1 0.006 0.002 (0.15 0.05) 15 0.331 0.004 (8.4 0.1) 28 0.465 0.012 (11.8 0.3) Unit: Inches (mm) 0.039 (1.0) S-MOS Systems, Inc. * 150 River Oaks Parkway * San Jose, CA 95134 * Tel: (408) 922-0200 * Fax: (408) 922-0238 55 SRM2264LCT10/12 CHARACTERISTIC CURVES Normalized IDDA--tcycle Normalized IDDA--Ta VDD = 5.5V Ta = 25C 1.0 VDD = 5.5V Tcyc = Min 0.9 1.1 0.8 1.0 Normalized IDDA--VDD 1.2 1.0 0.7 0.8 0.6 0.9 0.6 0.5 0.8 0.4 0.7 0.4 Ta = 25C Tcyc = Min 0.3 0.2 0.2 -40 -20 0 20 40 60 80 (C) 100 Normalized IDDS1--Ta 200 300 500 700 1,000 (ns) 3 4 6 7 (V) Normalized IDDS1--VDD 100 IOH--VOH VDD = 5.5V CS = VDD - 0.2V 50 5 4.0 3.0 10 (mA) Ta = 25C CS = VDD - 0.2V 2.0 VDD = 4.5V Ta = 25C 10 5 1 1.0 0.5 5 0.1 0.05 0.4 0.01 0 Normalized tACC*tACS--Ta 56 4 5 6 1.1 0.9 1.0 0.8 0.9 0.7 0.8 0 20 40 60 80 (C) 1 2 3 4 5 (V) IOL--VOL Ta = 25C CL = 100pF 1.2 1.0 -20 0 7 (V) Normalized tACC*tACS--VDD VDD = 4.5V CL = 100pF 1.1 -40 3 -40 -20 0 20 40 60 80 (C) (mA) V DD = 4.5V Ta = 25C 10 5 0 4 5 6 6 (V) 0 0.5 S-MOS Systems, Inc. * 150 River Oaks Parkway * San Jose, CA 95134 * Tel: (408) 922-0200 * Fax: (408) 922-0238 1.0 (V) 000-97-MEM-1.0