000-97-MEM-1.0 45
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
SRM2264LCT
10/12
CMOS 64K-BIT STATIC RAM
●
Industrial Temperature Range
●
Low Supply Current
●
Access Time 100ns/120ns
●
8,192 Words
×
8 Bits, Asynchronous
■
DESCRIPTION
The SRM2264LCT
10/12
is an 8,192-word
×
8-bit asynchronous, static, random access memory on a
monolithic CMOS chip. Its very low standby power requirement makes it ideal for applications requir-
ing non-volatile storage with back-up batteries. The –40 to 85
°
C operating temperature range is good
for industrial use. The asynchronous and static nature of the memory requires no external clock or
refreshing circuit. Both the input and output ports are TTL compatible, and the three-state output al-
lows easy expansion of memory capacity.
■
FEATURES
•
Industrial temperature range . . . . . . . . . . . . . –40 to 85
°
C
•
Fast access time . . . . . . . . . . . . . . . . . . . . . . SRM2264LCT
10
. . . . . . . . . . . . . . . . . . .100ns (Max)
SRM2264LCT
12
. . . . . . . . . . . . . . . . . . .120ns (Max)
•
Low supply current. . . . . . . . . . . . . . . . . . . . . Standby : 0.5
µ
A (Typ)
Operation : 47mA (Typ) . . . . . . . . . . . . . . .100ns
45mA (Typ) . . . . . . . . . . . . . . .120ns
•
Completely static . . . . . . . . . . . . . . . . . . . . . . No clock required
•
Single power supply. . . . . . . . . . . . . . . . . . . . 5V
±
10%
•
TTL compatible inputs and outputs
•
Three-state output with wired-OR capability
•
Non-volatile storage with back-up batteries
•
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRM2264LCT
10/12
. . . . . . . . . . . 28-pin DIP (plastic)
SRM2264LMT
10/12
. . . . . . . . . . 28-pin SOP (plastic)
SRM2264LCT10/12
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 000-97-MEM-1.046
■
BLOCK DIAGRAM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
CS1
CS2
OE
WE I/O Buffer
Column Gate
Address Buffer
Memory Cell Array
512 x 16 x 8
X Decoder
Y
Decoder
CS1, CS2
Chip
Control
OE, WE
Chip
Control
4
9
16
512
16 x 8
8
SRM2264LCT10/12
000-97-MEM-1.0 47
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
■
PIN CONFIGURATION
■
PIN DESCRIPTION
■
ABSOLUTE MAXIMUM RATINGS
*V
I
, V
I/O
(Min) = –3.0V (Pulse width is 50ns)
■
RECOMMENDED DC OPERATING CONDITIONS
* If pulse width is less than 50ns, it is –1.0V
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
VDD
WE
CS2
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SRM2264LCT
A0 to A12 Address Input
WE Write Enable
OE Output Enable
CS1, CS2 Chip Select
I/O1 to 8 Data Input/Output
V
DD
Power Supply (+5V)
V
SS
Logic Power Supply (0V)
NC No Connection
(V
SS
= 0V)
Parameter Symbol Ratings Unit
Supply voltage V
DD
–0.5 to 7.0 V
Input voltage* V
I
–0.5 to 7.0 V
Input/output voltage* V
I/O
–0.5 to V
DD
+ 0.3 V
Power dissipation P
D
1.0 W
Operating temperature T
OPR
–40 to 85
°
C
Storage temperature T
STG
–65 to 150
°
C
Soldering temperature and time T
SOL
260
°
C, 10s (at lead) —
(V
SS
= 0V, T
a
= –40 to 85
°
C)
Parameter Symbol Min Typ Max Unit
Supply voltage V
DD
4.5 5.0 5.5 V
V
SS
000V
Input voltage V
IH
2.2 3.5 V
DD
+ 0.3 V
V
IL
–0.3* 0 0.8 V
SRM2264LCT10/12
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 000-97-MEM-1.048
■
ELECTRICAL CHARACTERISTICS
●
DC Electrical Characteristics
* Typical values are measured at T
a
= 25
°
C and V
DD
= 5.0V
●
Terminal Capacitance
(V
DD
= 5V
±
10%, V
SS
= 0V, T
a
= –40 to 85
°
C)
Parameter Symbol Conditions SRM2264LCT
10
SRM2264LCT
12
Unit
Min Typ* Max Min Typ* Max
Input leakage
current I
LI
V
I
= 0 to V
DD
–1 — 1 –1 — 1
µ
A
Standby supply
current
I
DDS
CS1 = V
IH
or CS2 = V
IL
— 0.5 1.0 — 0.5 1.0 mA
I
DDS1
CS1 = CS2
≥
V
DD
– 0.2V
or CS2
≤
0.2V — 0.5 30 — 0.5 30
µ
A
Average operating
current I
DDA
V
I
= V
IL
, V
IH
I
I/O
= 0mA, t
CYC
= Min —4782—4580mA
Operating supply
current I
DDO
V
I
= V
IL
, V
IH
I
I/O
= 0mA — 35 60 — 35 60 mA
Output leakage I
LO
CS1 = V
IH
or CS2 = V
IL
or WE = V
IL
or OE = V
IH
,
V
I/O
= 0 to V
DD
–1 — 1 –1 — 1
µ
A
High level output
voltage V
OH
I
OH
= –1.0mA 2.4 V
DD
– 0.1 — 2.4 V
DD
– 0.1 —V
Low level output
voltage V
OL
I
OL
= 4.0mA — 0.2 0.4 — 0.2 0.4 V
(f = 1MHz, T
a
= 25
°
C)
Parameter Symbol Conditions Min Typ Max Unit
Address capacitance C
ADD
V
ADD
= 0V — 3 5 pF
Input capacitance C
I
V
I
= 0V — 5 6 pF
I/O capacitance C
I/O
V
I/O
= 0V — 6 7 pF
SRM2264LCT10/12
000-97-MEM-1.0 49
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
●
AC Electrical Characteristics
°
Read Cycle
°
Write Cycle
(V
DD
= 5V
±
10%, V
SS
= 0V, T
a
= –40 to 85
°
C)
Parameter Symbol Conditions SRM2264LCT
10
SRM2264LCT12 Unit
Min Max Min Max
Read cycle time tRC
*1
100 — 120 — ns
Address access time tACC — 100 — 120 ns
CS1 access time tACS1 — 100 — 120 ns
CS2 access time tACS2 — 100 — 120 ns
OE access time tOE —50—60ns
CS1 output set time tCLZ1
*2
10—10—ns
CS1 output floating time tCLZ1 —35—40ns
CS2 output set time tCLZ2 10—10—ns
CS2 output floating time tCLZ2 —35—40ns
OE output set time tOLZ 5—5—ns
OE output floating time tOLZ —35—40ns
Output hold time tOH *1 10—10—ns
(VDD = 5V ± 10%, VSS = 0V, Ta = –40 to 85°C)
Parameter Symbol Conditions SRM2264LCT10 SRM2264LCT12 Unit
Min Max Min Max
Write cycle time tWC
*1
100 — 120 — ns
Chip select time 1 tCW1 80—85—ns
Chip select time 2 tCW2 80—85—ns
Address enable time tAW 80—85—ns
Address setup time tAS 0—0—ns
Write pulse width tWP 60—70—ns
Address hold time tWR 0—0—ns
Input data setup time tDW 50—50—ns
Input data hold time tDH 0—0—ns
WE output floating tWHZ *3 —35—40ns
WE output setup time tOW 5—5—ns
SRM2264LCT10/12
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 000-97-MEM-1.050
*1 Read/Write Cycle Test Conditions
1. Input pulse level: 0.8V to 2.4V
2. tr = tf = 10ns
3. Input and output timing reference levels: 1.5V
4. Output load ITTL + CL = 100pF
*2 Read Cycle Test Conditions
1. Input pulse level: 0.8V to 2.4V
2. tr = tf = 10ns
3. Test Circuit
Test: tCHZ1, tCHZ2, tOHZ
Both SW1 and SW2 are closed.
Test: tCLZ1, tCLZ2, tOLZ Hi-Z→“H”
SW1 is open, SW2 is closed.
Test: tCLZ1, tCLZ2, tOLZ Hi-Z→“L”
SW1 is closed, SW2 is open.
Output turn-on turn-off times
300Ω
VDD
To scope
1 kΩ
5 pF
To output terminal
VSS
VSS
Include scope,
test, tool capacity
SW1
SW2
tOHZ
tOLZ
OE
I/O 1.5V 0.5V Hi-Z
Hi-Z “H”
“L”
1.5V
“H”
“L” 1.5V
CS1
CS2
I/O
1.5V
tCHZ1
tCLZ1
1.5V 0.5V Hi-Z
Hi-Z “H”
“L”
1.5V
“H”
“L” 1.5V
1.5V
tCLZ2
1.5V
tCHZ2
1.5V
*3 Write Cycle Test Conditions
1. Input pulse level: 0.8V to 2.2V
2. tr = tf = 10ns
3. Test Circuit
Test: tOW, tWHZ Hi-Z→“H” and “H”→Hi-Z
SW is VDD side
Test: tOW, tWHZ Hi-Z→“L” and “L”→Hi-Z
SW is VSS side
Output turn-on turn-off times
300Ω
VDD
To scope
1 kΩ
SW
5 pF
To output terminal
VSS
VSS
Include scope,
test, tool capacity
tWHZ
tOW
WE
I/O 0.1V
0.1V 0.1V
0.1V Hi–ZHi–Z H
L
1.5V 1.5V
SRM2264LCT10/12
000-97-MEM-1.0 51
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
●Timing Charts
°Read Cycle*1
Note: *1. During the read cycle, WE must be “H”.
°Write Cycle (1) (CS1 Control)*2
Note: *2. During write cycle (1) and (2), the Output Buffer is in high impedance regardless of the OE level.
tRC
tACC
tACS1
tCLZ1
tACS2
tCLZ2
tOE
tOLZ tOHZ
tCHZ2
tOH
tCHZ1
ADDRESS
CS1
CS2
OE
Dout
tWC
tAW tCW1
tAS
tDW
tWR
tDH
ADDRESS
CS1
CS2
WE
Dout
Din
SRM2264LCT10/12
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 000-97-MEM-1.052
°Write Cycle (2) (CS2 Control)*2
Note: *2. During write cycle (1) and (2), the output buffer is in high impedance regardless of the OE level.
°Write Cycle (3) (WE Control)*3
Note: *3. During write cycle (3), the output buffer is in high impedance if the OE level is “H”.
tWC
tAW
tCW2
tAS
tWR
ADDRESS
CS1
CS2
WE
Dout
Din
tDW tDH
tWC
tAW
tOW
tAS
ADDRESS
CS1
CS2
WE
Dout
Din
tWP
tWHZ
tDW tDH
tWR
SRM2264LCT10/12
000-97-MEM-1.0 53
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
■DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY
*tRC = Read Cycle time
●Data Retention Timing (CS1 Control)
●Data Retention Timing (CS2 Control)
(Ta = 0 to 70°C)
Parameter Symbol Conditions Min Typ Max Unit
Data retention supply voltage VDDR 2.0 — 5.5 V
Data retention current IDDR VDD = 3V
CS1 = CS2 ≥ VDD – 0.2V
or CS2 ≤ 0.2V ——10µA
Chip select data hold time tCDR 0——ns
Operation recovery time tRtRC*— — ns
Data hold mode
tR
VDD
CS1
tCDR
2.2V
4.5V 4.5V
VDDR ≥ 2.0V
CS1 ≥ VDD – 0.2V 2.2V
VDD
CS2
Data hold mode
tR
tCDR
0.4V
4.5V 4.5V
VDDR ≥ 2.0V
CS2 ≤ 0.2V
0.4V
SRM2264LCT10/12
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 000-97-MEM-1.054
■FUNCTIONS
●Truth Table
X: “H” or “L”
—: “H”, “L”, or “Hi-Z”
●Read Data
A read cycle begins with stable address data at the address port (A0 to A12), CS1 = “L”, CS2 = “H”,
and OE = “L”. Valid data is available at the data port (I/O1 to I/O8) within 100 or 120ns depending on
the device.
●Write Data
There are four ways of writing data into memory (see “Timing Charts”, above):
1. Write Cycle (1) — CS1 control — Write is accomplished by an active CS1 pulse.
2. Write Cycle (2) — CS2 control — Write is accomplished by an active CS2 pulse.
3. Write Cycle (3) — WE control — Write is accomplished by an active WE pulse.
4. This method is a combination of the previous write cycles. Beginning with a stable address
and all control signals in their non-active states (WE = “H”, CS1 = “H” and CS2 = “L”), pulse
all three control signals.
The trailing edge of any of the write control signal pulses (WE, CS1, CS2) causes data on the data
I/O pins to be latched into memory. Data bus contention is avoided since bringing CS1 and CS2 to
their inactive states places the Data I/O pins in a high-impedance state.
●Standby Mode
When CS1 and CS2 are in their inactive states, (CS1 = “H”, CS2 = “L”), the SRM2264LCT10/12 is in
standby mode. The only operation performed in standby mode is data retention. The data I/O pins are
in a high impedance state. All other inputs can be either “H” or “L”. This mode is maintained as long
as the CS2 level is less than 0.2V and the CS1 level is greater than VDD – 0.2V. In this condition, the
only current flow in the chip is caused by high-resistance paths in memory.
CS1 CS2 OE WE A0 to A12 Data I/O Mode IDD
H X — — — Hi-Z Unselected IDDS, IDDS1
— L — — — Hi-Z Unselected IDDS, IDDS1
L H X L Stable Input data Write IDDO
LHLH Stable Output data Read IDDO
L H H H Stable Hi-Z Output disable IDDO
SRM2264LCT10/12
000-97-MEM-1.0 55
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
■PACKAGE DIMENSIONS
0.010 ± 0.0012
(0.25 ± 0.03)
141
0.528 ± 0.004
(13.4 ± 0.1)
0.018 ± 0.004
(0.46 ± 0.1)
0.600~0.655
(15.24~16.64)
0.100 ± 0.010
(2.54 ± 0.25)
0.059
(1.5 )
1528
0.024 ± 0.004
(0.6 ± 0.1)
0.181 ± 0.004
(4.6 ± 0.1)
0.130 ± 0.002
(3.3 ± 0.05)
0.600
(15.24)
0.0004
0.01
1.472Max
(37.4Max)
1.445 ± 0.004
(36.7 ± 0.1)
C28 28-pin DIP
Unit: Inches (mm)
141
0.331 ± 0.004
(8.4 ± 0.1)
0.016 ± 0.004
(0.4 ± 0.1)
0.050
(1.27)
15
28
0.098 ± 0.006
(2.5 ± 0.15)
0.006 ± 0.002
(0.15 ± 0.05)
0.008
(0.2)
0.713 Max
(18.1 Max)
0.370
(9.4)
0.465 ± 0.012
(11.8 ± 0.3)
0.701 ± 0.004
(17.8 ± 0.1)
0.106
(2.7)
0.039
(1.0)
M28-2 28-pin SOP
Unit: Inches (mm)
SRM2264LCT10/12
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 000-97-MEM-1.056
■CHARACTERISTIC CURVES
1.1
1.0
0.9
0.8
0.7
0–20–40 20 40 60 80 (°C)
I
OL
—V
OL
10
5
0.5 1.0
(mA)
(V)
V
DD
= 4.5V
Ta = 25°C
Normalized t
ACC
·t
ACS
—Ta
1.1
1.0
0.9
0.8
0.7
0-20-40 20 40 60 80 (°C)
V
DD
= 4.5V
C
L
= 100pF
Normalized t
ACC
·t
ACS
—V
DD
1.2
1.1
1.0
0.9
0.8
4566(V)
Ta = 25°C
C
L
= 100pF
I
OH
—V
OH
10
5
V
DD
= 4.5V
Ta = 25°C
01234
(V)
(mA)
5
Normalized I
DDS1
—Ta
-40 -20 0 20 40 60 80 (°C)
100
50
10
5
1
0.5
0.1
0.05
0.01
V
DD
= 5.5V
CS = V
DD
– 0.2V
Normalized I
DDS1
—V
DD
4.0
3.0
2.0
1.0
0.4
34567
(V)
Ta = 25°C
CS = V
DD
– 0.2V
Normalized I
DDA
—t
cycle
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
V
DD
= 5.5V
Ta = 25°C
100 200 300 500700 1,000
(ns)
Normalized I
DDA
—T
a
V
DD
= 5.5V
T
cyc
= Min
Normalized I
DDA
—V
DD
1.2
1.0
0.8
0.6
0.4
0.2
Ta = 25°C
T
cyc
= Min
34567(V)
0
00
