5-1
March 1997
HD-6402
CMOS Universal Asynchronous
Receiver Transmitter (UART)
Features
• 8.0MHz Operating Frequency (HD-6402B)
• 2.0MHz Operating Frequency (HD-6402R)
• Low Power CMOS Design
• Programmable Word Length, Stop Bits and Parity
• Automatic Data Formatting and Status Generation
• Compatible with Industry Standard UARTs
• Single +5V Power Supply
• CMOS/TTL Compatible Inputs
Description
The HD-6402 is a CMOS UART for interfacing computers or
microprocessors to an asynchronous serial data channel.
The receiver conver ts serial star t, data, parity and stop bits.
The transmitter converts parallel data into serial form and
automatically adds star t, par ity and stop bits. The data word
length can be 5, 6, 7 or 8 bits. Parity may be odd or even.
Parity checking and generation can be inhibited. The stop
bits may be one or two or one and one-half when transmit-
ting 5-bit code.
The HD-6402 can be used in a wide range of applications
including modems, printers, peripherals and remote data
acquisition systems. Utilizing the Intersil advanced scaled
SAJI IV CMOS process permits operation clock frequencies
up to 8.0MHz (500K Baud). Pow er requirements , b y compar-
ison, are reduced from 300mW to 10mW. Status logic
increases flexibility and simplifies the user interface.
Pinout
HD-6402 (PDIP, CERDIP)
TOP VIEW
Ordering Information
PACKAGE TEMPERATURE RANGE 2MHz = 125K BAUD 8MHz = 500K BAUD PKG. NO.
Plastic DIP -40oC to +85oC HD3-6402R-9 HD3-6402B-9 E40.6
CERDIP -40oC to +85oC HD1-6402R-9 HD1-6402B-9 F40.6
SMD# -55oC to +125oC 5962-9052501MQA 5962-9052502MQA F40.6
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
VCC
NC
GND
RRD
RBR8
RBR7
RBR6
RBR5
RBR4
RBR3
RBR2
RBR1
PE
FE
OE
SFD
RRC
DRR
DR
RRI
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
TRC
EPE
CLS1
CLS2
SBS
PI
CRL
TBR8
TBR7
TBR6
TBR5
TBR4
TBR3
TBR2
TBR1
TRO
TRE
TBRL
TBRE
MR
File Number 2956.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
5-2
Functional Diagram
Control Definition
CONTROL WORD CHARACTER FORMAT
CLS 2 CLS 1 PI EPE SBS START BIT DATA BITS PARITY BIT STOP BITS
0 0 0 0 0 1 5 ODD 1
0 0 0 0 1 1 5 ODD 1.5
0 0 0 1 0 1 5 EVEN 1
0 0 0 1 1 1 5 EVEN 1.5
0 0 1 X 0 1 5 NONE 1
0 0 1 X 1 1 5 NONE 1.5
0 1 0 0 0 1 6 ODD 1
0 1 0 0 1 1 6 ODD 2
0 1 0 1 0 1 6 EVEN 1
0 1 0 1 1 1 6 EVEN 2
0 1 1 X 0 1 6 NONE 1
0 1 1 x 1 1 6 NONE 2
1 0 0 0 0 1 7 ODD 1
1 0 0 0 1 1 7 ODD 2
1 0 0 1 0 1 7 EVEN 1
1 0 0 1 1 1 7 EVEN 2
1 0 1 X 0 1 7 NONE 1
1 0 1 x 1 1 7 NONE 2
1 1 0 0 0 1 8 ODD 1
1 1 0 0 1 1 8 ODD 2
1 1 0 1 0 1 8 EVEN 1
1 1 0 1 1 1 8 EVEN 2
1 1 1 X 0 1 8 NONE 1
1 1 1 x 1 1 8 NONE 2
(24) TRE
(22) TBRE †
(23) TBRL
(40) TRC
(38) CLS1
(37) CLS2
(34) CRL
(21) MR
(17) RRC
(18) DRR
(19) DR †
(16) SFD
† OE † FE † PE
(15) (14) (13) (5) (6) (7)
† RBR8
3-STATE
BUFFERS
(8) (9) (10) (11) (12)† RBR1
RECEIVER BUFFER REGISTER
RECEIVER REGISTER
MULTIPLEXER
MULTIPLEXER
TRANSMITTER REGISTER
TRANSMITTER BUFFER REGISTER
START
STOP PARITY
LOGIC
PARITY
LOGIC
START
LOGIC
STOP
LOGIC
CONTROL
REGISTER
RECEIVER
TIMING AND
CONTROL
TRANSMITTER
TIMING AND
CONTROL
† THESE OUTPUTS ARE
THREE-STATE
(4) RRD
(20) RRI
(35) PI
(39) EPE
(16) SFD
(36) SBS
(25) TRO
(26) TBR1(27)
(30)(29)(28)
(31)
(32)
(33)TBR8
HD-6402
5-3
Pin Description
PIN TYPE SYMBOL DESCRIPTION
1V
CC †Positive Voltage Supply
2 NC No Connection
3 GND Ground
4 I RRD A high level on RECEIVER REGISTER DISABLE
forces the receiver holding out-puts RBR1-RBR8
to high impedance state.
5 O RBR8 The contents of the RECEIVER BUFFER REGIS-
TER appear on these three-state outputs. W ord f or-
mats less than 8 characters are right justified to
RBR1.
6 O RBR7 See Pin 5-RBR8
7 O RBR6 See Pin 5-RBR8
8 O RBR5 See Pin 5-RBR8
9 O RBR4 See Pin 5-RBR8
10 O RBR3 See Pin 5-RBR8
11 O RBR2 See Pin 5-RBR8
12 O RBR1 See Pin 5-RBR8
13 O PE A high lev el on PARITY ERROR indicates received
parity does not match parity programmed by control
bits. When parity is inhibited this output is low.
14 O FE A high level on FRAMING ERROR indicates the
first stop bit was invalid.
15 O OE A high level on OVERRUN ERROR indicates the
data received flag was not cleared before the last
character was transferred to the receiver buffer
register.
16 I SFD A high level on STATUS FLAGS DISABLE forces
the outputs PE, FE, OE, DR, TBRE to a high im-
pedance state.
17 I RRC The Receiver register clock is 16X the receiver
data rate.
18 I DRR A low level on DATA RECEIVED RESET clears
the data received output DR to a low level.
19 O DR A high level on DATA RECEIVED indicates a
character has been received and transferred to
the receiver buffer register.
20 I RRI Serial data on RECEIVER REGISTER INPUT is
clocked into the receiver register.
21 I MR A high level on MASTER RESET clears PE, FE,
OE and DR to a low level and sets the transmitter
register empty (TRE) to a high level 18 cloc k cycles
after MR falling edge. MR does not clear the receiv-
er buff er register. This input must be pulsed at least
once after power up . The HD-6402 must be master
reset after power up . The reset pulse should meet
VIH and tMR. W ait 18 cloc k cycles after the falling
edge of MR before beginning operation.
22 O TBRE A high lev el on TRANSMITTER B UFFER REGIS-
TER EMPTY indicates the transmitter buffer register
has transf erred its data to the transmitter register
and is ready for ne w data.
23 I TBRL A low level on TRANSMITTER BUFFER REGIS-
TER LOAD transfers data from inputs TBR1-
TBR8 into the transmitter buffer register. A low to
high transition on TBRL initiates data transfer to
the transmitter register. If busy, transfer is auto-
matically delayed so that the two characters are
transmitted end to end.
24 O TRE A high level on TRANSMITTER REGISTER EMP-
TY indicates completed transmission of a charac-
ter including stop bits.
25 O TRO Character data, start data and stop bits appear se-
rially at the TRANSMITTER REGISTER OUTPUT.
26 I TRB1 Character data is loaded into the TRANSMITTER
BUFFER REGISTER via inputs TBR1-TBR8. For
character formats less than 8 bits the TBR8, 7 and
6 inputs are ignored corresponding to their pro-
grammed word length.
27 I TBR2 See Pin 26-TBR1.
28 I TBR3 See Pin 26-TBR1.
29 I TBR4 See Pin 26-TBR1.
30 I TBR5 See Pin 26-TBR1.
31 I TBR6 See Pin 26-TBR1.
32 I TBR7 See Pin 26-TBR1.
33 I TBR8 See Pin 26-TBR1.
34 I CRL A high level on CONTROL REGISTER LOAD
loads the control register with the control word. The
control word is latched on the falling edge of CRL.
CRL may be tied high.
35 I PI A high level on PARITY INHIBIT inhibits parity gen-
eration, parity checking and forces PE output low.
36 I SBS A high level on STOP BIT SELECT selects 1.5
stop bits for 5 character format and 2 stop bits for
other lengths.
37 I CLS2 These inputs program the CHARACTER
LENGTH SELECTED (CLS1 low CLS2 low 5 bits)
(CLS1 high CLS2 low 6 bits) (CLS1 low CLS2
high 7 bits) (CLS1 high CLS2 high 8 bits.)
38 I CLS1 See Pin 37-CLS2.
39 I EPE When PI is low, a high level on EVEN PARITY
ENABLE generates and checks even parity. A low
level selects odd parity.
40 I TRC The TRANSMITTER REGISTER CLOCK is 16X
the transmit data rate.
†A 0.1µF decoupling capacitor from the VCC pin to the GND is rec-
ommended.
PIN TYPE SYMBOL DESCRIPTION
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
HD-6402
HD-6402
5-4
Transmitter Operation
The transmitter section accepts parallel data, formats the data
and transmits the data in serial form on the Transmitter Regis-
ter Output (TRO) terminal (See serial data format). Data is
loaded from the inputs TBR1-TBR8 into the Transmitter Buff er
Register by applying a logic low on the Transmitter Buffer
Register Load (TBRL) input (A). Valid data must be present at
least tset prior to and thold follo wing the rising edge of TBRL. If
words less than 8 bits are used, only the least significant bits
are transmitted. The character is right justified, so the least
significant bit corresponds to TBR1 (B).
The rising edge of TBRL clears Transmitter Buffer Register
Empty (TBRE). 0 to 1 Clock cycles later, data is transferred
to the transmitter register, the Transmitter Register Empty
(TRE) pin goes to a low state, TBRE is set high and serial
data inf ormation is transmitted. The output data is clocked b y
Transmitter Register Clock (TRC) at a cloc k r ate 16 times the
data rate. A second low level pulse on TBRL loads data into
the Transmitter Buffer Register (C). Data transfer to the
transmitter register is delayed until transmission of the cur-
rent data is complete (D). Data is automatically transf erred to
the transmitter register and transmission of that character
begins one clock cycle later.
Receiver Operation
Data is received in serial form at the Receiver Register Input
(RRI). When no data is being received, RRI must remain
high. The data is clocked through the Receiver Register
Clock (RRC). The clock rate is 16 times the data rate. A low
level on Data Received Reset (DRR) clears the Data
Receiver (DR) line (A). During the first stop bit data is trans-
ferred from the Receiver Register to the Receiver Buffer
Register (RBR) (B). If the word is less than 8 bits, the
unused most significant bits will be a logic low. The output
character is right justified to the least significant bit RBR1. A
logic high on Overrun Error (OE) indicates overruns. An
overrun occurs when DR has not been cleared before the
present character was transferred to the RBR. One clock
cycle later DR is reset to a logic high, and Framing Error
(FE) is evaluated (C). A logic high on FE indicates an invalid
stop bit was received, a framing error. A logic high on Parity
Error (PE) indicates a parity error.
A B C D END OF LAST STOP BIT
1/2 CLOCK
0 TO 1 CLOCK
DATA
TBRL
TBRE
TRE
TRO
1
FIGURE 1. TRANSMITTER TIMING (NOT TO SCALE)
FIGURE 2. RECEIVER TIMING (NOT TO SCALE)
A B C
BEGINNING OF FIRST STOP BIT
7 1/2 CLOCK CYCLES
1 CLOCK CYCLE
RRI
RBR1-8, OE, PE
DRR
DR
FE
FIGURE 3. SERIAL DATA FORMAT
LSB MSB †
START BIT
PARITY †IF ENABLED
1, 11/2 OR 2 STOP BITS
5-8 DATA BITS
HD-6402
5-5
Start Bit Detection
The receiver uses a 16X clock timing. The start bit could have
occurred as much as one clock cycle before it was detected,
as indicated by the shaded portion (A). The center of the start
bit is defined as clock count 7 1/2. If the receiver clock is a
symmetrical square wave, the center of the start bit will be
located within ±1/2 clock cycle, ±1/32 bit or 3.125% giving a
receiver margin of 46.875%. The receiver begins searching
f or the next start bit at the center of the first stop bit.
Interfacing with the HD-6402
CLOCK
RRI INPUT START
71/2 CLOCK CYCLES
81/2 CLOCK CYCLES
COUNT 71/2 DEFINED
CENTER OF START BIT
FIGURE 4.
A
FIGURE 5. TYPICAL SERIAL DATA LINK
DIGITAL
SYSTEM
TRANSMITTER
RECEIVER
RRI
TRO
TBR1
TBR8
CONTROL
HD-6402
CONTROL
RB1
RB8
DIGITAL
SYSTEM
TRANSMITTER
RECEIVER
RRI
TRO TBR1
TBR8
CONTROL
HD-6402
CONTROL
RB1
RB8
RS232
DRIVER
RS232
RECEIVER RS232
DRIVER
RS232
RECEIVER
HD-6402
5-6
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V
Input, Output or I/O Voltage Applied. . . . . GND -0.5V to VCC +0.5V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Typical Derating Factor. . . . . . . . . . . . 1mA/MHz Increase in ICCOP
Thermal Resistance (Typical) θJA θJC
CERDIP Package . . . . . . . . . . . . . . . . 50oC/W 12oC/W
PDIP Package . . . . . . . . . . . . . . . . . . . 50oC/W N/A
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1643 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause per manent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range
HD-6402R-9, HD6402B-9 . . . . . . . . . . . . . . . . . . .-40oC to +85oC
DC Electrical Specifications VCC = 5.0V ±10%, TA = -40oC to +85oC (HD-6402R-9, HD-6402B-9)
SYMBOL PARAMETER
LIMITS
UNITS CONDITIONSMIN MAX
VIH Logical ‘‘1’’ Input Voltage 2.0 - V VCC = 5.5V
VIL Logical ‘‘0’’ Input Voltage - 0.8 V VCC = 4.5V
II Input Leakage Current -1.0 1.0 µAV
IN = GND or VCC, VCC = 5.5V
VOH Logical ‘‘1’’ Output Voltage 3.0
VCC -0.4 -
-VI
OH = -2.5mA, VCC = 4.5V
IOH = -100µA
VOL Logical ‘‘0’’ Output Voltage - 0.4 V IOL = +2.5mA, VCC = 4.5V
IOOutput Leakage Current -1.0 1.0 µAV
O = GND or VCC, VCC = 5.5V
ICCSB Standby Supply Current - 100 µAV
IN = GND or VCC; VCC = 5.5V,
Output Open
ICCOP Operating Supply Current (See Note) - 2.0 mA VCC = 5.5V, Clock Freq. = 2MHz,
VIN = VCC or GND, Outputs Open
NOTE: Guaranteed, but not 100% tested
Capacitance TA = +25oC
PARAMETER SYMBOL CONDITIONS
LIMIT
UNITSTYPICAL
Input Capacitance CIN Freq. = 1MHz, all measurements are referenced to de-
vice GND 25 pF
Output Capacitance COUT 25 pF
AC Electrical Specifications VCC = 5.0V ±10%, TA = -40oC to +85oC (HD-6402R-9, HD6402B-9)
SYMBOL PARAMETER
LIMITS HD-6402R LIMITS HD-6402B
UNITS CONDITIONSMIN MAX MIN MAX
(1) fCLOCK Clock Frequency D.C. 2.0 D.C. 8.0 MHz CL = 50pF
See Switching Waveform
(2) tPW Pulse Widths, CRL, DRR, TBRL 150 - 75 - ns
(3) tMR Pulse Width MR 150 - 150 - ns
(4) tSET Input Data Setup Time 50 - 20 - ns
(5) tHOLD Input Data Hold Time 60 - 20 - ns
(6) tEN Output Enable Time - 160 - 35 ns
HD-6402
5-7
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information fur nished by Intersil is believed to be accurate
and reliable . Howe ver, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted b y implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
A.C. Testing Input, Output Waveform
Test Circuit
Switching Waveforms
FIGURE 6. DATA INPUT CYCLE FIGURE 7. CONTROL REGISTER LOAD
CYCLE FIGURE 8. ST ATUS FLAG OUTPUT
ENABLE TIME OR DATA OUT-
PUT ENABLE TIME
TBR1 - TBR8 VALID DATA
TBRL
(4)
tSET
(2)
tPW
(5)
tHOLD
(5)
tHOLD
(2)
tPW
(4)
tSET
VALID DATA
CLS1, CLS2, SBS, PI, EPE
CRL
(6)
tEN
SFD
RRD
STATUS OR
RBR1 - RBR8
FIGURE 9.
NOTE: A.C. Testing: All input signals must switch between VIL - 50% VIL and VIH + 20% VIH. Input rise and fall times are driven at 1ns/V.
INPUT
VIH + 20% VIH
VIL - 50% VIL
1.5V 1.5V
OUTPUT
VOH
VOL
FIGURE 10.
NOTE: Includes stray and jig capacitance, CL = 50pF.
OUT
CL
(SEE NOTE)
HD-6402
