© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 2 1Publication Order Number:
NCP1271/D
NCP1271
Soft−Skipt Mode Standby
PWM Controller with
Adjustable Skip Level and
External Latch
The NCP1271 represents a new, pin to pin compatible, generation
of the successful 7−pin current mode NCP12XX product series. The
controller allows for excellent stand by power consumption by use of
its adjustable Soft−Skip mode and integrated high voltage startup
FET. This proprietary Soft−Skip also dramatically reduces the risk of
acoustic noise. This allows the use of inexpensive transformers and
capacitors in the clamping network. Internal frequency jittering,
ramp compensation, timer−based fault detection and a latch input
make this controller an excellent candidate for converters where
ruggedness and component cost are the key constraints.
Features
•Fixed−Frequency Current−Mode Operation with Ramp
Compensation and Skip Cycle in Standby Condition
•Timer−Based Fault Protection for Improved Overload Detection
•“Soft−Skip Mode” Technique for Optimal Noise Control in Standby
•Internal High−Voltage Startup Current Source for Lossless Startup
•"5% Current Limit Accuracy over the Full Temperature Range
•Adjustable Skip Level
•Internal Latch for Easy Implementation of Overvoltage and
Overtemperature Protection
•Frequency Jittering for Softened EMI Signature
•+500 mA/−800 mA Peak Current Drive Capability
•Sub−100 mW Standby Power can be Achieved
•Pin−to−Pin Compatible with the Existing NCP120X Series
•This is a Pb−Free Device
Typical Applications
•AC−DC Adapters for Notebooks, LCD Monitors
•Offline Battery Chargers
•Consumer Electronic Appliances STB, DVD, DVDR
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
PIN CONNECTIONS
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MARKING
DIAGRAMS
(Top View)
1271x
ALYWG
G
x = A or B
A= 65 kHz
B= 100 kHz
A = Assembly Location
L = Wafer Lot
Y = Year
W = W ork Week
G= Pb−Free Package
1
8
(Note: Microdot may be in either location)
Skip/latch
FB
CS
GND
1
2
3
4
HV
VCC
Drv
8
6
5
SOIC−7
D SUFFIX
CASE 751U
SOIC−7
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
ORDERING INFORMATION
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Figure 1. Typical Application Circuit
skip/latch
FB
CS
Gnd
NCP1271
Voltage
+
−
AC
Input Output
Rramp
latch input*
EMI
Filter
Rskip
HV
Vcc
Drv
*
*Optional
MAXIMUM RATINGS (Notes 1 and 2)
Rating Symbol Value Unit
VCC Pin (Pin 6)
Maximum Voltage Range
Maximum Current Vmax
Imax
−0.3 to +20
100 V
mA
Skip/Latch, FB, CS Pin (Pins 1−3)
Maximum Voltage Range
Maximum Current Vmax
Imax
−0.3 to +10
100 V
mA
Drv Pin (Pin 5)
Maximum Voltage Range
Maximum Current Vmax
Imax
−0.3 to +20
−800 to +500 V
mA
HV Pin (Pin 8)
Maximum Voltage Range
Maximum Current Vmax
Imax
−0.3 to +500
100 V
mA
Power Dissipation and Thermal Characteristics
Thermal Resistance, Junction−to−Air, SO−7, Low Conductivity PCB (Note 3)
Thermal Resistance, Junction−to−Lead, SO−7, Low Conductivity PCB
Thermal Resistance, Junction−to−Air, SO−7, High Conductivity PCB (Note 4)
Thermal Resistance, Junction−to−Lead, SO−7, High Conductivity PCB
RqJA
RqJL
RqJA
RqJL
177
75
136
69
°C/W
°C/W
°C/W
°C/W
Operating Junction Temperature Range TJ−40 to +125 °C
Maximum Storage Temperature Range Tstg −60 to +125 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device contains ESD protection and exceeds the following tests:
Pins 1−6: Human Body Model 2000 V per Mil−Std−883, Method 3015
Machine Model Method 150 V (on Pins 5 and 6) and 200 V (all other pins)
Pin 8 is the HV startup of the device and is rated to the maximum rating of the part, or 500 V
This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
2. Guaranteed by design, not tested.
3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm2 of 2 oz copper traces and heat spreading area. As specified for
a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow .
4. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 650 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow.
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Figure 2. Functional Block Diagram
−
LEB
Skip/ latch
CS
FB
7.5% Jittering
65, 100 kHz
Oscillator
130ms
delay
HV
S
R
Drv
Gnd
PWM
skip
OR
4.8 V
8 V
Max duty
R
S
= 80%
180 ns
0&
+
−
+
−
+
−
+
soft−skip
8
2
3
4
1
6
5
Vss
VFB
latch−off, reset
when Vcc < 4V
jittered ramp
current source
I
V
short
circuit
fault
12.6/
5.8 V
9.1 V
turn off
UVLO
−
+
−
+
turn on internal bias
4.1 mA when Vcc > 0.6 V
driver:
+500 mA
/ −800 mA
10V
disable
soft
skip
skip
&
double
hiccup
S
Q
10V
10V 20V
VCS
VCC
VCC
0
100uA
0.2 mA when Vcc < 0.6 V
Soft start/ soft−skip
management
−TLD
+
soft
start
2.85 V
1 / 3
13 us filter
1 0
skip
Rskip
4 ms/ 300 us
RCS
Rramp
(1V max)
16.7k
75.3k
V / 3
FB
VPWM
VFB
Q
R
Q
B2
Counter
Vskip = Rskip * Iskip or
Vskip = 1.2 V when pin 1 is opened
1
PIN FUNCTION DESCRIPTION
Pin N o . Symbol Function Description
1 Skip/latch Skip Adjust or
Latchoff A resistor to ground provides the adjustable standby skip level. Additionally, if this pin is
pulled higher than 8.0 V (typical), the controller latches off the drive.
2 FB Feedback An optocoupler collector pulls this pin low during regulation. If this voltage is less than
the Skip pin voltage, then the driver is pulled low and Soft−Skip mode is activated. If this
pin is open (>3 V) for more than 130 ms, then the controller is placed in a fault mode.
3 CS Current Sense This pin senses the primary current for PWM regulation. The maximum primary current
is limited to 1.0 V / RCS where RCS is the current sense resistor. Additionally, a ramp
resistor Rramp between the current sense node and this pin sets the compensation ramp
for improved stability.
4 Gnd IC Ground −
5 Drv Driver Output The NCP1271’ s powerful output is capable of driving the gates of large Qg MOSFETs.
6 VCC Supply Voltage This is the positive supply of the device. The operating range is between 10 V (min) and
20 V (max) with a UVLO start threshold 12.6 V (typ).
8 HV High Voltage This pin provides (1) Lossless startup sequence (2) Double hiccup fault mode (3)
Memory for latch−of f shutdown and (4) Device protection if VCC is shorted to GND.
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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values, TJ = −40°C to +125°C, VCC = 14 V,
HV = open, skip = open, FB = 2 V, CS = Ground, DRV = 1 nF, unless otherwise noted.)
Characteristic Pin Symbol Min Typ Max Unit
OSCILLATOR
Oscillation Frequency (65 kHz Version, TJ = 25_C)
Oscillation Frequency (65 kHz Version, TJ = −40 to + 85_C)
Oscillation Frequency (65 kHz Version, TJ = −40 to + 125_C)
Oscillation Frequency (100 kHz Version, TJ = 25_C)
Oscillation Frequency (100 kHz Version, TJ = −40 to +85_C)
Oscillation Frequency (100 kHz Version, TJ = −40 to +125_C)
5 fosc 61.75
58
55
95
89
85
65
65
65
100
100
100
68.25
69
69
105
107
107
kHz
Oscillator Modulation Swing, in Percentage of fosc 5 − − "7.5 − %
Oscillator Modulation Swing Period 5 − − 6.0 − ms
Maximum Duty Cycle (VCS = 0 V, VFB = 2.0 V) 5 Dmax 75 80 85 %
GATE DRIVE
Gate Drive Resistance
Output High (VCC = 14 V, Drv = 300 W to Gnd)
Output Low (VCC = 14 V, Drv = 1.0 V)
5ROH
ROL
6.0
2.0 11
6.0 20
12
W
Rise Time from 10% to 90% (Drv = 1.0 nF to Gnd) 5 tr− 30 − ns
Fall Time from 90% to 10% (Drv = 1.0 nF to Gnd) 5 tf− 20 − ns
CURRENT SENSE
Maximum Current Threshold 3 ILimit 0.95 1.0 1.05 V
Soft−Start Duration − tSS − 4.0 − ms
Soft−Skip Duration − tSK − 300 − ms
Leading Edge Blanking Duration 3 tLEB 100 180 330 ns
Propagation Delay (Drv =1.0 nF to Gnd) − − − 50 150 ns
Ramp Current Source Peak 3 Iramp(H) − 100 − mA
Ramp Current Source Valley 3 Iramp(L) − 0 − mA
SKIP
Default Standby Skip Threshold (Pin 1 = Open) 2 Vskip − 1.2 − V
Skip Current (Pin 1 = 0 V, TJ = 25_C) 1 Iskip 26 43 56 mA
Skip Level Reset (Note 5) 1 Vskip−reset 5.0 5.7 6.5 V
Transient Load Detection Level to Disable Soft−Skip Mode 2 VTLD 2.6 2.85 3.15 V
EXTERNAL LATCH
Latch Protection Threshold 1 Vlatch 7.1 8.0 8.7 V
Latch Threshold Margin (Vlatch−m = VCC(off) − Vlatch) 1 Vlatch−m 0.6 1.2 − V
Noise Filtering Duration 1 − − 13 − ms
Propagation Delay (Drv = 1.0 nF to Gnd) 1 Tlatch − 100 − ns
SHORT−CIRCUIT FAULT PROTECTION
Time for Validating Short−Circuit Fault Condition 2 tprotect − 130 − ms
5. Please refer to Figure 39 for detailed description.
6. Guaranteed by design.
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ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25°C, for min/max values, TJ = −40°C to +125°C,
VCC = 14 V, HV = open, skip = open, FB = 2 V, CS = Ground, DRV = 1 nF, unless otherwise noted.)
Characteristic Pin Symbol Min Typ Max Unit
STARTUP CURRENT SOURCE
High−Voltage Current Source
Inhibit Voltage (ICC = 200 mA, HV = 50 V)
Inhibit Current (VCC = 0 V, HV = 50 V)
Startup (VCC = VCC(on) − 0.2 V, HV = 50 V)
Leakage (VCC = 14 V, HV = 500 V)
6
6
6
8
Vinhibit
Iinhibit
IHV
IHV−leak
190
80
3.0
10
600
200
4.1
25
800
350
6.0
50
mV
mA
mA
mA
Minimum Startup Voltage (VCC = VCC(on) – 0.2 V, ICC = 0.5 mA) 8 VHV(min) − 20 28 V
SUPPLY SECTION
VCC Regulation
Startup Threshold, VCC Increasing
Minimum Operating Voltage After Turn−On
VCC Operating Hysteresis
Undervoltage Lockout Threshold Voltage, VCC Decreasing
Logic Reset Level (VCC(latch) –VCC(reset) > 1.0 V) (Note 7)
6VCC(on)
VCC(off)
VCC(on) − VCC(off)
VCC(latch)
VCC(reset)
11.2
8.2
3.0
5.0
−
12.6
9.1
3.6
5.8
4.0
13.8
10
4.2
6.5
−
V
V
V
V
V
VCC Supply Current
Operating (VCC = 14 V, 1.0 nF Load, VFB = 2.0 V, 65 kHz Version)
Operating (VCC = 14 V, 1.0 nF Load, VFB = 2.0 V, 100 kHz Version)
Output Stays Low (VCC = 14 V, VFB = 0 V)
Latchoff Phase (VCC = 7.0 V, VFB = 2.0 V)
6ICC1
ICC1
ICC2
ICC3
−
−
−
−
2.3
3.1
1.3
500
3.0
3.5
2.0
720
mA
mA
mA
mA
7. Guaranteed by design.
TYPICAL CHARACTERISTICS
Figure 3. Oscillation Frequency vs.
Temperature Figure 4. Maximum Duty Cycle vs.
Temperature
TEMPERATURE (°C) TEMPERATURE (°C)
1251007550250−50
50
60
70
80
90
100
110
1251007550250−50
75
76
77
78
79
80
81
OSCILLATION FREQUENCY (kHz)
MAXIMUM DUTY CYCLE (%)
−25 −25
82
83
84
85
100 kHz
65 kHz
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TYPICAL CHARACTERISTICS
Figure 5. Output Gate Drive Resistance vs.
Temperature Figure 6. Current Limit vs. Temperature
Figure 7. Soft−Start Duration vs. Temperature Figure 8. Leading Edge Blanking Time vs.
Temperature
TEMPERATURE (°C) TEMPERATURE (°C)
1251007550250−50
0
2
4
6
8
10
12
5
1007550250−50
0.94
0.96
0.98
1.0
1.04
OUTPUT GATE DRIVE RESIST ANCE (
W
)
CURRENT LIMIT (V)
Figure 9. Default Skip Level vs. Temperature Figure 10. Skip Pin Current vs. Temperature
TEMPERATURE (°C)
1
25
1007550250−50
0
100
200
300
LEADING EDGE BLANKING TIME (ns)
TEMPERATURE (°C)
1251007550250−50
1.00
1.10
1.20
1.30
1.40
DEFAULT SKIP LEVEL (V)
50
150
250
350
−25 −25
−25
−25
12
14
16
ROH
ROL
1.02
TEMPERATURE (°C)
1251007550250−50
0
2
4
6
SOFT−START DURATION (ms)
1
3
5
8
−25
7
TEMPERATURE (°C)
12
5
1007550250−50
35
36
37
38
39
40
41
SKIP PIN CURRENT (mA)
−25
42
43
44
45
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TYPICAL CHARACTERISTICS
Figure 11. Skip Level Reset Threshold vs.
Temperature Figure 12. Transient Load Detection Level vs.
Temperature
TEMPERATURE (°C)
1251007550250−50
5.5
5.6
5.7
5.8
5.9
6.0
SKIP LEVEL RESET THRESHOLD (V)
Figure 13. Latch Protection Level vs.
Temperature Figure 14. Fault Validation Time vs.
Temperature
TEMPERATURE (°C)
TEMPERATURE (°C)
1
25
1007550250−50
2.5
2.6
2.7
2.8
2.9
3.0
1251007550250−50
7.5
7.6
7.7
7.8
7.9
TRANSIENT LOAD DETECT LEVEL (V
)
LATCH PROTECTION LEVEL (V)
Figure 15. Startup Inhibit Voltage vs.
Temperature Figure 16. Startup Inhibit Current vs.
Temperature
TEMPERATURE (°C)
1251007550250−50
0
0.2
0.4
0.6
0.8
1.0
STARTUP INHIBIT VOLTAGE (V)
TEMPERATURE (°C)
12
5
1007550250−50
0
50
100
150
200
250
STARTUP INHIBIT CURRENT (mA)
300
0.1
0.3
0.5
0.7
0.9
−25 −25
−25
−25 −25
8.0
8.1
8.2
8.3
8.4
8.5
VCC = 0 V
TEMPERATURE (°C)
12
5
1007550250−50
100
105
110
115
120
FAULT VALIDATION TIME (ms)
−25
125
130
135
140
145
150
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TYPICAL CHARACTERISTICS
Figure 17. High Voltage Startup Current vs.
Temperature Figure 18. Startup Current vs. VCC Voltage
TEMPERATURE (°C) VCC, SUPPLY VOLTAGE (V)
1251007550250−50
3.5
3.6
3.7
3.8
3.9
4.0
4.1
1
2
108640
0
1
2
3
4
5
6
STARTUP CURRENT (mA)
STARTUP CURRENT (mA)
Figure 19. Startup Leakage Current vs.
Temperature Figure 20. Minimum Startup Voltage vs.
Temperature
TEMPERATURE (°C)
TEMPERATURE (°C)
1
25
1007550250−50
15
17
19
21
23
25
1251007550250−50
0
2
4
6
8
MINIMUM STAR TUP VOLTAGE (V)
SUPPLY VOLTAGE THRESHOLD (V)
Figure 21. Supply Voltage Thresholds vs.
Temperature
TEMPERATURE (°C)
12
5
1007550250−50
0
0.5
1.0
1.5
2.0
2.5
SUPPLY CURRENT (mA)
−25 2
−25
−25 −25
VCC(reset)
VCC(on)
4.2
4.3
4.4
4.5
16
18
20
22
24
10
12
14
VCC(off)
VCC(latch)
VCC = VCC(on) − 0.2 V
3.0
3.5
Figure 22. Supply Currents vs. Temperature
TEMPERATURE (°C)
1251007550250−50
0
5
10
15
20
25
30
STARTUP LEAKAGE CURRENT (
m
A)
−25
35
40
125°C
−40°C
25°C
ICC1 (100 kHz)
ICC2
ICC3
ICC1 (65 kHz)
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OPERATING DESCRIPTION
Introduction
The NCP1271 represents a new generation of the
fixed−frequency PWM current−mode flyback controllers
from ON Semiconductor. The device features integrated
high−voltage startup and excellent standby performance.
The proprietary Soft−Skip Mode achieves extremely
low−standby power consumption while keeping power
supply acoustic noise to a minimum. The key features of
the NCP1271 are as follows:
•Timer−Based Fault Detection: In the event that an
abnormally large load is applied to the output for more
than 130 ms, the controller will safely shut the
application down. This allows accurate overload (OL)
or short−circuit (SC) detection which is not dependent
on the auxiliary winding.
•Soft−Skip Mode: This proprietary feature of the
NCP1271 minimizes the standby low−frequency
acoustic noise by ramping the peak current envelope
whenever skip is activated.
•Adjustable Skip Threshold: This feature allows the
power level at which the application enters skip to be
fully adjusted. Thus, the standby power for various
applications can be optimized. The default skip level
is 1.2 V (40% of the maximum peak current).
•500 V High−Voltage Startup Capability: This
AC−DC application friendly feature eliminates the
need for an external startup biasing circuit, minimizes
the standby power loss, and saves printed circuit board
(PCB) space.
•Dual High−Voltage Startup−Current Levels: The
NCP1271 uniquely provides the ability to reduce the
startup current supply when Vcc is low. This prevents
damage if Vcc is ever shorted to ground. After Vcc
rises above approximately 600 mV, the startup current
increases to its full value and rapidly charges the Vcc
capacitor.
•Latched Protection: The NCP1271 provi des a pin,
which if pulled high, places the part in a latched off
mode. The refore, overvol tage (OVP) and
overte mpera ture (OTP) protec tion can be easil y
implemented. A noise filter is provided on this function
to reduce the cha nces of fa lsely trigge ring the latc h. The
lat c h is re l ea se d whe n Vc c is cycl e d bel ow 4 V.
•Non−Latched Protection/ Shutdown Option: By
pulling the feedback pin below the skip threshold
level, a non−latching shutdown mode can be easily
implemented.
•4.0 ms Soft−Start: The soft start feature slowly ramps
up the drive duty cycle at startup. This forces the
primary current to also ramp up slowly and
dramatically reduces the stress on power components
during startup.
•Current−Mode Operation: The NCP1271 uses
current−mode control which provides better transient
response than voltage−mode control. Current−mode
control also inherently limits the cycle−by−cycle
primary current.
•Compensation Ramp: A drawback of current−mode
regulation is that the circuit may become unstable
when the operating duty cycle is too high. The
NCP1271 offers an adjustable compensation ramp to
solve this instability.
•80% Maximum Duty Cycle Protection: This feature
limits the maximum on time of the drive to protect the
power MOSFET from being continuously on.
•Frequency Jittering: Frequency jittering softens the
EMI signature by spreading out peak energy within a
band +/− 7.5% from the center frequency.
•Switching Frequency Options: The NCP1271 is
available in either 65 kHz or 100 kHz fixed frequency
options. Depending on the application, the designer
can pick the right device to help reduce magnetic
switching loss or improve the EMI signature before
reaching the 150 kHz starting point for more
restrictive EMI test limits.
NCP1271 Operating Conditions
There are 5 p oss ible operating conditions f or t he N CP1271:
1. Normal Operation – When VCC is above VCC(off)
(9.1 V typic al) and the feedback pin volta ge (V FB)
is within the normal operat ion range (i.e. ,V FB < 3.0
V), the NCP1271 operat es as a fixed−freque ncy
current −mode PWM cont rolle r.
2. Standby Operation (or Skip−Cycle Operation)
Whe n the loa d current drops, the compe nsat ion
network responds by reduc ing the prim ary pe ak
current. When the peak current reaches the skip
peak current leve l, the NCP1271 enters Soft−Skip
operat ion to reduc e the power consumpt ion. This
Soft−Skip feat ure offers a modi fied pe ak curre nt
envel ope and hence also reduce s the risk of audible
noise. In the event of a sudden load incre ase, the
transient load detector (TLD) disables Soft−Skip
and applie s ma ximum power to bring the output
into re gula ti on as fast as possible .
3. Fault Operation – When no feedba ck signal is
received for 130 ms or when VCC drops be low
VCC(off) (9.1 V typi cal ), the NCP1271 rec ogniz es it
as a faul t condit ion. In this fault mode , the Vcc
volta ge is forced to go through two cycles of slowly
discharging and charging. This is known as a
“double hiccup. ” The double hi ccup insures that
am ple tim e is allowe d betwe en rest arts to prev ent
overhea ting of the power devi ces. If the fault is
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cle ared after the double hi ccup, then the applic ati on
resta rts. If not, then the process is repeate d.
4. Latched Shutdown – Whe n the Skip/lat ch pin (Pi n
1) volta ge is pulled above 8.0 V for more than
13 ms, the NCP1271 goes into latchoff shutdown.
The output is held low and VCC stays in hiccup
mode unt il the la tch is reset . The rese t can only
occu r if Vcc is allowed to fa ll bel ow V CC(reset)
(4.0 V typi cal ). This is genera ll y acc ompl ished by
unplugging the ma in input AC source.
5. Non−La t ched Shutdown – If the FB pin is pull ed
below the skip le vel, then the devi ce wi ll enter a
non−lat che d shutdown mode. Thi s mode di sable s
the driver, but the controller automatically recovers
when the pulldown on FB is rele ased. Alterna tive ly,
Vcc can al so be pulled low (below 190 mV) to
shutdown the controlle r. This has the added benefit
of pla cing the part into a low curre nt consumpti on
mode for improved power savings.
Biasing the Controller
During startup, the Vcc bias voltage is supplied by the
HV Pin (Pin 8). This pin is capable of supporting up to
500 V, so it can be connected directly to the bulk capacitor.
Internally, the pin connects to a current source which
rapidly charges VCC to its VCC(on) threshold. After this
level is reached, the controller turns on and the transformer
auxiliary winding delivers the bias supply voltage to VCC.
The startup FET is then turned off, allowing the standby
power loss to be minimized. This in−chip startup circuit
minimizes the number of external components and Printed
Circuit Board (PCB) area. It also provides much lower
power dissipation and faster startup times when compared
to using startup resistors to VCC. The auxiliary winding
needs to be designed to supply a voltage above the VCC(off)
level but below the maximum VCC level of 20 V.
For added protection, the NCP1271 also include a dual
startup mode. Initially, when VCC is below the inhibit
voltage Vinhibit (600 m V typical), the startup current source
is small (200 uA typical). The current goes higher (4.1 mA
typical) when VCC goes above Vinhibit. This behavior is
illustrated in Figure 23. The dual startup feature protects
the device by limiting the maximum power dissipation
when the VCC pin (Pin 6) is accidentally grounded. This
slightly increases the total time to charge VCC, but it is
generally not noticeable.
Figure 23. Startup Current at Various VCC Levels
V
VCC(on) CC
4.1 mA
200 uA
Startup current
0.6 V VCC(latch)
VCC Double Hiccup Mode
Figure 24 illustrates the block diagram of the startup
circuit. An undervoltage lockout (UVLO) comparator
monitors the VCC supply voltage. If VCC falls below
VCC(off), then the controller enters “double hiccup mode.”
Figure 24. VCC Management
Vcc
HV
8
6
12.6/
5.8 V
9.1 V
turn off
UVLO
−
+
−
+
turn on internal bias
&
double
hiccup
Q
R
20V
4.1 mA when Vcc > 0.6 V
200 uA when Vcc < 0.6 V
10−to−20V biasing voltage
(available after startup)
B2
Counter
S
Vbulk
During double hiccup operation, the Vcc level falls to
VCC(latch) (5.8 V typical). At this point, the startup FET is
turned back on and char ges VCC to VCC(on) (12.6 V typical).
VCC then slowly collapses back to the VCC(latch) level. This
cycle is repeated twice to minimize power dissipation in
NCP1271
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11
external components during a fault event. After the second
cycle, the controller tries to restart the application. If the
restart is not successful, then the process is repeated.
During this mode, VCC never drops below the 4 V latch
reset level. Therefore, latched faults will not be cleared
unless the application is unplugged from the AC line (i.e.,
Vbulk discharges).
Figure 25 shows a timing diagram of the VCC double
hiccup operation. Note that at each restart attempt, a soft
start is issued to minimize stress.
Figure 25. VCC Double Hiccup Operation in a Fault
Condition
5.8 V
12.6 V
9.1 V
Dtstartup
time
CC
Supply voltage, V
time
Drain current, I
Switching is missing in
every two VCC hiccup cycles
featuring a “double−hiccup”
VCC Capacitor
As stated earlier, the NCP1271 enters a fault condition
when the feedback pin is open (i.e. FB is greater than 3 V)
for 130 ms or VCC drops below VCC(off) (9.1 V typical).
Therefore, to take advantage of these features, the VCC
capacitor needs to be sized so that operation can be
maintained in the absence of the auxiliary winding for at
least 130 ms.
The controller typically consumes 2.3 mA at a 65 kHz
frequency with a 1 nF switch gate capacitance. Therefore,
to ensure at least 130 ms of operation, equation 1 can be
used to calculate that at least an 85 mF capacitor would be
necessary.
tstartup +CVCCDV
ICC1 +85 mF · (12.6 V−9.1 V)
2.3 mA +130 ms
(eq. 1)
If the 130 ms timer feature will not be used, then the
capacitance value needs to at least be large enough for the
output to charge up to a point where the auxiliary winding
can supply VCC. Figure 26 describes different startup
scenarios with different VCC capacitor values. If the VCC
cap is too small, the application fails to start because the
bias supply voltage cannot be established before VCC is
reduced to the VCC(off) level.
Figure 26. Different Startup Scenarios of the
Circuits with Different VCC Capacitors
time
V
Vout
CC
time
VCC
out
V
9.1 V
12.6 V
5.8 V
9.1 V
12.6 V
tstartup
0.6 V
0.6 V
Output waveforms with a large enough VCC capacitor
Output waveforms with too small of a VCC capacitor
Desired level of Vout
It is highly recommended that the VCC capacitor be as
close as possible to the VCC and ground pins of the product
to reduce switching noise. A small bypass capacitor on this
pin is also recommended. If the switching noise is large
enough, it could potentially cause VCC to go below VCC(off)
and force a restart of the controller.
It is also recommended to have a margin between the
winding bias voltage and VCC(off) so that all possible
transient swings of the auxiliary winding are allowed. In
standby mode, the VCC voltage swing can be higher due to
the low−frequency skip−cycle operation. The VCC
capacitor also affects this swing. Figure 27 illustrates the
possible swings.
Figure 27. Timing Diagram of Standby Condition
V
FB
D
9.1 V
CC
skip
time
Supply voltage, V
time
Feedback pin voltage, V
time
Drain current, I
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Soft−Start Operation
Figures 28 and 29 show how the soft−start feature is
included in the pulse−width modulation (PWM)
comparator. When the NCP1271 starts up, a soft−start
voltage V SS begins at 0 V. VSS increases gradually from 0 V
to 1.0 V in 4.0 ms and stays at 1.0 V afterward. This voltage
VSS is compared with the divided−by−3 feedback pin
voltage ( V FB/3). The lesser of VSS and (VFB/3) becomes the
modulation voltage VPWM in the PWM duty cycle
generation. Initially, (VFB/3) is above 1.0 V because the
output voltage is low. As a result, VPWM is limited by the
soft start function and slowly ramps up the duty cycle (and
therefore the primary current) for the initial 4.0 ms. This
provides a greatly reduced stress on the power devices
during startup.
Figure 28. VPWM is the lesser of VSS and (VFB/3)
0 1
−
+
VSS
V / 3
FB
VPWM
Figure 29. Soft−Start (Time = 0 at VCC = VCC(on))
time
time
time
1 V
4 ms
1 V
1 V
4 ms
time must be less than130 ms
to prevent fault condition
time
4 ms
Feedback pin voltage divided−by−3, VFB/3
Pulse Width Modulation voltage, VPWM
Drain Current, ID
Soft−start voltage, VSS
Current−Mode Pulse−Width Modulation
The NCP1271 uses a current−mode fixed−frequency
PWM with internal ramp compensation. A pair of current
sense resistors RCS and Rramp sense the flyback drain
current ID. As the drain current ramps up through the
inductor and current sense resistor, a corresponding voltage
ramp is placed on the CS pin (pin 3). This voltage ranges
from very low to as high as the modulation voltage VPWM
(maximum of 1.0 V) before turning the drive off. If the
internal current ramp is ignored (i.e., Rramp ≈ 0) then the
maximum possible drain current ID(max) is shown in
Equation 2. This sets the primary current limit on a cycle
by cycle basis.
ID(max) +1V
RCS (eq. 2)
Figure 30. Current−Mode Implementation
LEB CS
PWM
Output
180ns
+
−
3
Vbulk
Rramp
(1V max. signal)
VPWM
QS
VCS
Clock 1 0 RCS
ID
80%
max duty
Iramp
R
Figure 31. Current−Mode Timing Diagram
PWM
Output
VPWM
CS
clock
V
The timing diagram of the PWM is in Figure 31. An
internal clock turns the Drive Output (Pin 5) high in each
switching cycle. The Drive Output goes low when the CS
(Pin 3) voltage VCS intersects with the modulation voltage
VPWM. This generates the pulse width (or duty cycle). The
maximum duty cycle is limited to 80% (typically) in the
output RS latch.
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Ramp Compensation
Ramp compensation is a known mean to cure
subharmonic oscillations. These oscillations take place at
half the switching frequency and occur only during
continuous conduction mode (CCM) with a duty−cycle
greater than 50%. To lower the current loop gain, one
usually injects between 50 and 75% of the inductor down
slope. The NCP1271 generates an internal current ramp
that is synchronized with the clock. This current ramp is
then routed to the CS pin. Figures 32 and 33 depict how the
ramp is generated and utilized. Ramp compensation is
simply formed by placing a resistor, R ramp, between the CS
pin and the sense resistor.
Figure 32. Internal Ramp Current Source
Ramp current, I
0
100uA
time
80% of period
ramp
100% of period
Figure 33. Inserting a R esistor in Series with th e
Current Sense Inform ation bri ngs Ramp Compensation
Clock
Current
Ramp
Oscillator
DRIVE
CS Rramp
Rsense
100 mA Peak
For the NCP1271, the current ramp features a swing of
100 mA. Over a 65 kHz frequency with an 80% max duty
cycle, that corresponds to an 8.1 mA/ms ramp. For a typical
flyback design, let’s assume that the primary inductance
(Lp) is 350 mH, the SMPS output is 19 V, the Vf of the
output diode is 1 V and the Np:Ns ratio is 10:1. The OFF
time primary current slope is given by:
(eq. 3)
(Vout)Vf)@Np
Ns
Lp +571 VńmH +571 mAńms
When projected over an Rsense of 0.1 W (for example),
this becomes or 57 mV/ms. If we select 75% of the
downslope as the required amount of ramp compensation,
then we shall inject 43 mV/ms. Therefore, Rramp is simply
equal to:
(eq. 4)
Rramp +43 mVńms
8.1 mAńms+5.3 kW
It is recommended that the value of Rramp be limited to
less then 10 kW. Values larger than this will begin to limit
the effective duty cycle of the controller and may result in
reduced transient response.
Frequency Jittering
Frequency jittering is a method used to soften the EMI
signature b y spreading the energy in the vicinity of the main
switching component. The NCP1271 switching frequency
ranges from +7.5% to −7.5% of the switching frequency in
a linear ramp with a typical period of 6 ms. Figure 34
demonstrates how the oscillation frequency changes.
Figure 34. Frequency Jittering
(The values are for the 100 kHz frequency option)
time
Oscillator Frequency
92.5 kHz
107.5 kHz
100 kHz
6 ms
Fault Detection
Figure 35 details the timer−based fault detection
circuitry. When an overload (or short circuit) event occurs,
the output voltage collapses and the optocoupler does not
conduct current. This opens the FB pin (pin 2) and VFB is
internally pulled higher than 3.0 V. Since (VFB/3) is greater
than 1 V, the controller activates an error flag and starts a
130 ms timer. If the output recovers during this time, the
timer is reset and the device continues to operate normally.
However, if the fault lasts for more than 130 ms, then the
driver turns off and the device enters the VCC Double
Hiccup mode discussed earlier. At the end of the double
hiccup, the controller tries to restart the application.
Figure 35. Block Diagram of Timer−Based Fault
Detection
Softstart
FB
130ms
delay
1V max
Fault
&
−
+
2
VSS
VFB
disable Drv
VFB
3
4.8V
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14
Besides the timer−based fault detection, the NCP1271
also enters fault condition when VCC drops below VCC(off)
(9.1 V typical). The device will again enter a double hiccup
mode and try to restart the application.
Operation in Standby Condition
During standby operation, or when the output has a light
load, the duty cycle on the controller can become very
small. At this point, a significant portion of the power
dissipation is related to the power MOSFET switching on
and off. To reduce this power dissipation, the NCP1271
“skips” pulses when the FB level (i.e. duty cycle) drops too
low. The level that this occurs at is completely adjustable
by setting a resistor on pin 1.
By discontinuing pulses, the output voltage slowly drops
and the FB voltage rises. When the FB voltage rises above
the Vskip level, the drive is turned back on. However, to
minimize the risk of acoustic noise, when the drive turns
back on the duty cycle of its pulses are also ramped up. This
is similar to the soft start function, except the period of the
Soft−Skip operation is only 300 ms instead of 4.0 ms for the
soft start function. This feature produces a timing diagram
shown in Figure 36.
Figure 36. Soft−Skip Operation
V
FB
ID
skip
Soft Skip
Skip Duty Cycle
Skip peak current, %Icsskip, is the percentage of the
maximum peak current at which the controller enters skip
mode. Icsskip can be any value from 0 to 100% as defined
by equation 5. However, the higher that %Icsskip is, the
greater the drain current when skip is entered. This
increases the risk of acoustic noise. Conversely, the lower
that %Icsskip is the larger the percentage of energy is
expended turning the switch on and off. Therefore it is
important to adjust %Icsskip to the optimal level for a given
application.
%Ics
skip +Vskip
3V · 100% (eq. 5)
Skip Adjustment
By default, when the Skip/latch Pin (Pin 1) is opened, the
skip level is 1.2 V (Vskip = 1.2 V). This corresponds to a
40% Icsskip (%Icsskip = 1.2 V / 3.0 V 100% = 40%).
Therefore, the controller will enter skip mode when the
peak current is less than 40% of the maximum peak current.
However, this level can be externally adjusted by placing
a resistor Rskip between skip/latch pin (Pin 1) and Ground
(Pin 4). The level will change according to equation 6.
Vskip +Rskip Iskip (eq. 6)
To operate in skip cycle mode, Vskip must be between
0 V and 3.0 V. Therefore, Rskip must be within the levels
given in Table 1.
Table 1. Skip Resistor Rskip Range for Dmax = 80% and Iskip = 43 mA
%Icsskip Vskip or Vpin1 Rskip Comment
0% 0 V 0 WNever skips.
12% 0.375 V 8.7 kW−
25% 0.75 V 17.4 kW−
40% 1.2 V 28 kW−
50% 1.5 V 34.8 kW−
100% 3.0 V 70 kWAlways skips.
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Recover from Standby
In the event that a large load is encountered during skip
cycle operation, the circuit automatically disables the
normal Soft−Skip procedure and delivers maximum power
to the load (Figure 37). This feature, the Transient Load
Detector (TLD), is initiated anytime a skip event is exited
and the FB pin is greater than 2.85 V, as would be the case
for a sudden increase in output load.
Figure 37. Transient Response from Standby
V
VFB
ID
skip
VTLD
load current
Maximum current available
when TLD level is hit
output voltage 300 ms max
External Latchoff Shutdown
When the Skip/Latch input (Pin 1) is pulled higher than
Vlatch (8.0 V typical), the drive output is latched off until
VCC drops below VCC(reset) (4.0 Vtypical). If Vbulk stays
above approximately 30 Vdc, then the HV FET ensure that
VCC remains above VCC(latch) (5.8 Vtypical). Therefore, the
controller is reset by unplugging the power supply from the
wall and allowing Vbulk to discharge. Figure 38 illustrates
the timing diagram of VCC in the latchoff condition.
Figure 38. Latchoff VCC Timing Diagram
5.8 V
12.6 V
Startup current source is
charging the VCC capacitor Startup current source is
of f when VCC is 12.6 V
Startup current source turns
on when VCC reaches 5.8 VCC
Figure 39 defines the different voltage regions of the
Skip/latch Pin (Pin 1) operation.
1. When the voltage is above Vlatch (7.1 V min,
8.7 V max), the circuit is i n latchoff and all drive
pulses are disabled until VCC cycles below 4.0 V
(typical).
2. When the voltage is between Vskip−reset (5.0 V
min, 6.5 V max) and Vlatch, the pin is considered
to be opened. T h e skip level Vskip is restored to
the default 1.2 V.
3. When the voltage is between about 3.0 V and
Vskip−reset, the Vskip level is above the no rm al
operating range of t h e feedback pin. Therefore,
the output does not switch.
4. When the voltage is between 0 V and 3.0 V, the
Vskip is within the operating range of the
feedback pin. Then the voltage on this pin sets
the skip level as explained earlier.
Figure 39. NCP1271 Pin 1 Operating Regions
Output is latched off here.
Adjustable V range.
0 V (no skip)
3.0 V (always skip)
Vpin1
8V (V )
10 V (max limit)
Output always low (skipped) here.
5.7 V (V )
Pin 1 considered to be opened.
skip−reset
latch
skip
Vskip is reset to default level 1.2 V.
The external latch feature allows the circuit designers to
implement different kinds of latching protection. The
NCP1271 applications note (AND8242/D) details several
simple circuits to implement overtemperature protection
(OTP) and overvoltage protection (OVP).
In order to prevent unexpected latchoff due to noise,
it is very important to put a noise decoupling capacitor
near Pin 1 to increase the noise immunity. It is also
recommended to always have a resistor from pin 1 to GND.
This further reduces the risk of premature latchoff. Also
note that if the additional latch−off circuitry has leakage,
it will modify the skip adjust setup.
External Non−Latched Shutdown
Figure 40 illustrates the Feedback (pin 2) operation. An
external non−latched shutdown can be easily implemented
by simply pulling FB below the skip level. This is an
inherent feature from the standby skip operation. Hence, it
allows the designer to implement additional non−latched
shutdown protection.
The device can also be shutdown by pulling the VCC pin
to GND (<190 mV). In addition to shutting off the output,
this method also places the part into a low current
consumption state.
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16
Figure 40. NCP1271 Operation Threshold
Fault operation when staying
in this region longer than 130 ms
PWM operation
Non−latched shutdown
3 V
VFB
0 V
Vskip
Figure 41. Non−Latchoff Shutdown
1
2
3
4
8
6
5
NCP1271
OFF
opto
coupler
Output Drive
The output stage of the device is designed to directly
drive a power MOSFET. It is capable of up to +500 mA and
−800 mA peak drive currents and has a typical rise and fall
time of 30 ns and 20 ns with a 1.0 nF load. This allows the
NCP1271 to drive a high−current power MOSFET directly
for medium−high power application.
Noise Decoupling Capacitors
There are three pins in the NCP1271 that may need
external decoupling capacitors.
1. Skip/Latch Pin (Pin 1) – If the voltage on
this pin is above 8.0 V, then the circuit enters
latchoff. Hence, a decoupling capacitor on this
pin is essential for improved noise immunity.
Additionally, a resistor should always be placed
from this pin to GND to prevent noise from
causing the pin 1 level to exceed the latchoff
level.
2. Feedback Pin (Pin 2) – The FB pin is a high
impedance point and is very easily polluted in a
noisy environment. This could effect the circuit
operation.
3. VCC Pin (Pin 6) – The circuit maintains normal
operati on whe n VCC is above VCC(off) (9. 1 V
typica l). But, if VCC drops be low VCC(off) because
of switchi ng noise, then the circui t can incorrec tly
recognize it as a fault condition. Hence, it is
import ant to locat e the VCC capa ci tor or an
addit ional dec oupling capa citor as close as possible
to the de vice .
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Figure 42. 57 W Example Circuit Using NCP1271
IC1 NCP1271A
+
−
85 to
265 Vac 19 V / 3 A
Common
Mode Choke
D8 MBR3100
R1 100k / 2W
R5 15.8k
E3506−A
D6 MRA4005T3
1N5406 x 4
D7 MURS160
R7 511
D9 1N5358B (22V@50mA)
IC2 SFH615AA−X007
R9 1.69k
C3 82uF / 400V
IC4 TL431
Q1 SPP06N80C3
0.2 / 1W
D5 MMSZ914
C4 100uF
R2 10
D10 MZP4746A (18V)
R10 8.87k C9 2200 uF
C10 2200 uF
R6 10
IC3 SFH615AA−X007
C5 10 nF
Flyback transformer :
Cooper CTX22−17179
Lp = 180uH, leakage 2.5uH max
np : ns : naux = 30 : 6 : 5
Hi−pot 3600Vac for 1 sec, primary to secondary
Hi−pot 8500Vac for 1 sec, winding to core
C12
0.15 uF
C7 1.2 nF
C6 1.2 nF
C2 0.1 uF
T1
C1 0.1 uF
D1 − D4
R12 2.37k R11 15.8k
R13 25
C11 1nF/ 1000V
R8
R3 200
Fuse 2A
C13 100uF
C14 100pF
Figure 42 shows a typical application circuit using the
NCP1271. The standby power consumption of the circuit
is 83 mW with 230 Vac input. The details of the application
circuit are described in application note AND8242/D. The
efficiency o f the circuit at light load up to full load is shown
in Figure 43.
Figure 43. Efficiency of the NCP1271 Demo
Board at Nominal Line Voltages
Pout (W)
60504030200
60
65
70
75
80
85
90
EFFICIENCY (%)
10
95
230 Vac
120 Vac
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ORDERING INFORMATION
Device Frequency Package Shipping†
NCP1271D65R2G 65kHz SOIC−7
(Pb−Free) 2500 Tape & Reel
NCP1271D100R2G 100 kHz SOIC−7
(Pb−Free) 2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
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PACKAGE DIMENSIONS
SOIC−7
D SUFFIX
CASE 751U−01
ISSUE C
SEATING
PLANE
14
58
R
J
X 45_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
S
D
H
C
DIM
AMIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−A−
−B−
G
M
B
M
0.25 (0.010)
−T−
B
M
0.25 (0.010) TSAS
M
7 PL
____
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
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SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
NCP1271/D
Soft−Skip is a trademark of Semiconductor Components Industries, LLC (SCILLC).
The product described herein (NCP1271), may be covered by the following U.S. patents: 6,271,735, 6,362,067, 6,385,060, 6,597,221, 6,633,193. There may
be other patents pending.
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