NCP1851BFCCT1G - ON Semiconductor

March, 2013 − Rev. 6

1Publication Order Number:

NCP1851/D

NCP1851, NCP1851A

Fully Integrated Li-Ion

Switching Battery Charger

with Power Path

Management and USB

On-The-Go Support

The NCP1851 is a fully programmable single cell Lithium−ion

switching battery charger optimized for charging from a USB

compliant input supply and AC adaptor power source. The device

integrates a synchronous PWM controller, power MOSFETs, and the

entire charge cycle monitoring including safety features under

software supervision. An optional battery FET can be placed between

the system and the battery in order to isolate and supply the system.

The NCP1851 junction temperature and battery temperature are

monitored during charge cycle, and both current and voltage can be

modified accordingly through I2C setting. The charger activity and

status are reported through a dedicated pin to the system. The input pin

is protected against overvoltages.

The NCP1851 also provides USB OTG support by boosting the

battery voltage as well as providing overvoltage protected power

supply for USB transceiver.

Features

•1.6 A Buck Converter with Integrated Pass Devices

•Input Current Limiting to Comply to USB Standard

•Automatic Charge Current for AC Adaptor Charging

•High Accuracy Voltage and Current Regulation

•Input Overvoltage Protection up to +28 V

•Factory Mode

•500 mA Boosted Supply for USB OTG Peripherals

•Reverse Leakage Protection Prevents Battery Discharge

•Protected USB Transceiver Supply Switch

•Dynamic Power Path with Optional Battery FET

•Battery Temperature Sensing for Safe Operation (JEITA)

•Silicon Temperature Supervision for Optimized Charge Cycle

•Safety Timers

•Flag Output for Charge Status and Interrupts

•I2C Control Bus up to 3.4 MHz

•Small Footprint 2.2 x 2.55 mm CSP Package

•These Devices are Pb−Free and are RoHS Compliant

Applications

•Smart Phone

•Handheld Devices

•Tablets

•PDAs

MARKING

DIAGRAM

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See detailed ordering and shipping information in the package

dimensions section on page 30 of this data sheet.

ORDERING INFORMATION

25 BUMP

FLIP−CHIP

CASE 499BN

XXXX = Specific Device Code

A = Assembly Location

Y = Year

WW = Work Week

G or G = Pb−Free Package

XXXX

AYWW

*Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

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Figure 1. Typical Application Circuit

FLAG

SCL

SDA

SPM

TRANS

CAP

NTC

BAT

FET

WEAK

SENSN

SENSP

CBOOT

USB PHY

ILIM1

AGND

PGND

OTG

NCP1851

CORE

SYSTEM

VBUS

D+

D−

GND

10 nF

ILIM2

QBAT(*)

CBOOT

CIN

1 mF

CCAP

4.7 mF

2.2 mF

CCORE

0.1 mF

CTRS

10 mF

COUT

LXRSNS

2.2 mH68 mW

*Optional Battery FET.

PIN CONNECTIONS

Figure 2. Package Outline CSP

(Top View)

CBOOTE TRANS CORE WEAK BAT

PGND PGND SENSP SENSN FETD

SW SW AGND ILIM1 NTCC

CAP CAP OTG ILIM2 FLAGB

IN IN SPM SDA SCLA

12345

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Table 1. PIN FUNCTION DESCRIPTION

Pin Name Type Description

A1 IN POWER Battery Charger Input. These two pins must be decoupled by at least 1 mF capacitor and

connected together.

A2 IN POWER

A3 SPM DIGITAL INPUT System Power Monitor input.

A4 SDA DIGITAL

BIDIRECTIONAL

I2C data line

A5 SCL DIGITAL INPUT I2C clock line

B1 CAP POWER CAP pin is the intermediate power supply input for all internal circuitry. Bypass with at

least 4.7 mF capacitor. Must be tied together.

B2 CAP POWER

B3 OTG DIGITAL INPUT Enables OTG boost mode.

OTG = 0, the boost is powered OFF

OTG = 1 turns boost converter ON

B4 ILIM2 DIGITAL INPUT Automatic charge current / Input current limiter level selection (can be defeated by I2C).

B5 FLAG OPEN DRAIN

OUTPUT

Charging state active low. This is an open drain pin that can either drive a status LED or

connect to interrupt pin of the system.

C1 SW ANALOG OUTPUT Connection from power MOSFET to the Inductor.

These pins must be connected together.

C2 SW ANALOG OUTPUT

C3 AGND ANALOG GROUND Analog ground / reference. This pin should be connected to the ground plane and must

be connected together.

C4 ILIM1 DIGITAL INPUT Input current limiter level selection (can be defeated by I2C).

C5 NTC ANALOG INPUT Input for the battery NTC (10 KW / B = 3900) or (4.7 KW / B = 3900) If not used, this pin

must be tied to GND to configure the NCP1851 and warn that NTC is not used.

D1 PGND POWER GND Power ground. These pins should be connected to the ground plane and must be connec-

ted together.

D2 PGND POWER GND

D3 SENSP ANALOG INPUT Current sense input. This pin is the positive current sense input. It should be connected to

the RSENSE resistor positive terminal.

D4 SENSN ANALOG INPUT Current sense input. This pin is the negative current sense input. It should be connected

to the RSENSE resistor negative terminal. This pin is also voltage sense input of the

voltage regulation loop when the FET is present and open.

D5 FET ANALOG OUTPUT Battery FET driver output. When not used, this pin must be directly tied to ground.

E1 CBOOT ANALOG IN/OUT Floating Bootstrap connection. A 10 nF capacitor must be connected between CBOOT

and SW.

E2 TRANS ANALOG OUTPUT Output supply to USB transceiver. This pin can source a maximum of 50 mA to the ex-

ternal USB PHY or any other IC that needs +5 V USB. This pin is Overvoltage protected

and will never be higher than 5.5 V. This pin should be bypassed by a 100 nF ceramic

capacitor.

E3 CORE ANALOG OUTPUT 5 V reference voltage of the IC. This pin should be bypassed by a 2.2 mF capacitor. No

load must be connected to this pin.

E4 WEAK ANALOG OUTPUT Weak battery charging current source input.

E5 BAT ANALOG INPUT Battery connection

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Table 2. MAXIMUM RATINGS

Rating Symbol Value Unit

IN (Note 1) VIN −0.3 to +28 V

CAP (Note 1) VCAP −0.3 to +28 V

Power balls: SW (Note 1) VSW −0.3 to +24 V

CBOOT (Note 1) VCBOOT −0.3 to VSW +7.0 V

Sense/Control balls: SENSP, SENSN, VBAT, FET, TRANS, CORE, NTC,

FLAG and WEAK. (Note 1)

VCTRL −0.3 to +7.0 V

Digital Input: SCL, SDA, SPM, OTG, ILIM1 and ILIM2 (Note 1)

Input Voltage

Input Current

VDG

IDG

−0.3 to +7.0 V

Storage Temperature Range TSTG −65 to +150 °C

Maximum Junction Temperature (Note 2) TJ−40 to +TSD °C

Moisture Sensitivity (Note 3) MSL Level 1

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

Table 3. OPERATING CONDITIONS

Symbol Parameter Conditions Min Typ Max Unit

VIN Operational Power Supply 3 VINOV V

VDG Digital input voltage level 0 5.5 V

TAAmbient Temperature Range −40 25 +85 °C

ISINK FLAG sink current 10 mA

CIN Decoupling input capacitor 1mF

CCAP Decoupling Switcher capacitor 4.7 mF

CCORE Decoupling core supply capacitor 2.2 mF

COUT Decoupling system capacitor 10 mF

LXSwitcher Inductor 2.2 mH

RSNS Current sense resistor 68 mW

RqJA Thermal Resistance Junction to Air (Notes 2 and 4) 60 °C/W

TJJunction Temperature Range −40 25 +125 °C

1. According to JEDEC standard JESD22−A108.

2. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation. See Electrical Characteristics.

3. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.

4. The RqJA is dependent on the PCB heat dissipation. Board used to drive this data was a 2s2p JEDEC PCB standard.

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Table 4. ELECTRICAL CHARACTERISTICS

Min & Max Limits apply for TA between −40°C to +85°C and TJ up to + 125°C for VIN between 3.6 V to 7 V (Unless otherwise noted).

Typical values are referenced to TA = + 25°C and VIN = 5 V (Unless otherwise noted).

Symbol Parameter Conditions Min Typ Max Unit

INPUT VOLTAGE

VINDET Valid input detection threshold VIN rising 3.55 3.6 3.65 V

VIN falling 2.95 3.0 3.05 V

VBUSUV USB under voltage detection VIN falling 4.3 4.4 4.5 V

Hysteresis 50 100 150 mV

VBUSOV USB over voltage detection VIN rising 5.55 5.65 5.75 V

Hysteresis 25 75 125 mV

VINOV Valid input high threshold VIN rising 7.1 7.2 7.3 V

Hysteresis 200 300 400 mV

INPUT CURRENT LIMITING

IINLIM Input current limit VIN = 5 V IINLIM set to 100 mA 70 85 100 mA

IINLIM set to 500 mA 425 460 500 mA

IINLIM set to 900 mA 800 850 900 mA

IINLIM set to 1500 mA 1.4 1.45 1.5 A

INPUT SUPPLY CURRENT

IQ_SW VBUS supply current No load, Charger active state 15 mA

IOFF Charger not active, NTC disable 500 mA

CHARGER DETECTION

VCHGDET Charger detection threshold

voltage

VIN – VSENSN, VIN rising 40 100 150 mV

VIN – VSENSN, VIN falling 20 30 50 mV

REVERVE BLOCKING CURRENT

ILEAK VBAT leakage current Battery leakage, VBAT = 4.2 V VIN = 0 V,

SDA = SCL = 0 V

5mA

RRBFET Input RBFET On resistance (Q1) Charger active state, Measured between

IN and CAP,VIN = 5 V

−100 200 mW

BATTERY AND SYSTEM VOLTAGE REGULATION

VCHG Output voltage range Programmable by I2C 3.3 4.5 V

Default value 3.6 V

Voltage regulation accuracy Constant voltage mode, TA = 25°C−0.5 0.5 %

−1 1 %

I2C Programmable granularity 25 mV

BATTERY VOLTAGE THRESHOLD

VSAFE Safe charge threshold voltage VBAT rising 2.1 2.15 2.2 V

VPRE Conditioning charge threshold

voltage

VBAT rising 2.75 2.8 2.85 V

VFET End of weak charge threshold

voltage

VBAT rising Voltage range 3.1 3.6 V

Default value 3.4

Accuracy −2 2 %

I2C Programmable

granularity

100 mV

VRECHG Recharge threshold voltage Relative to VCHG setting register 97 %

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Table 4. ELECTRICAL CHARACTERISTICS

Min & Max Limits apply for TA between −40°C to +85°C and TJ up to + 125°C for VIN between 3.6 V to 7 V (Unless otherwise noted).

Typical values are referenced to TA = + 25°C and VIN = 5 V (Unless otherwise noted).

Symbol UnitMaxTypMinConditionsParameter

BATTERY VOLTAGE THRESHOLD

VBUCKOV Overvoltage threshold voltage VBAT rising, relative to VCHG setting register,

measured on SENSN or SENSP, QBAT close or no

QBAT

115 %

QBAT open. 5 V

CHARGE CURRENT REGULATION

ICHG Charge current range Programmable by I2C 400 1600 mA

Default value 950 1000 1050 mA

Charge current accuracy −50 50 mA

I2C Programmable granularity 100 mA

IPRE Pre−charge current VBAT < VPRE 80 100 120 mA

ISAFE Safe charge current VBAT < VSAFE 8 10 12 mA

IWEAK Weak battery charge current BATFET

present,

VSAFE < VBAT <

VFET

IWEAK[1:0] = 01 80 100 120 mA

IWEAK[1:0] = 10 180 200 220

IWEAK[1:0] = 11 270 300 330

CHARGE TERMINATION

IEOC Charge current termination VBAT ≥ VRECHG Current range 100 275 mA

Default value 150

Accuracy, IEOC < 200 mA −25 25

I2C Programmable granularity 25

FLAG

VFOL FLAG output low voltage IFLAG = 10 mA 0.5 V

IFLEAK Off−state leakage VFLAG = 5 V 1mA

TFLGON Interrupt request pulse duration Single event 150 200 250 ms

DIGITAL INPUT (VDG)

VIH High−level input voltage 1.2 V

VIL Low−level input voltage 0.4 V

RDG Pull down resistor 500 kW

IDLEAKK Input current VDG = 0 V −0.5 0.5 mA

I2C

VSYSUV CAP pin supply voltage I2C registers available 2.5 V

VI2CINT*High level at SCL/SCA line 1.7 5 V

VI2CIL SCL, SDA low input voltage 0.4 V

VI2CIH SCL, SDA high input voltage 0.8*

VI2CI

VI2COL SCL, SDA low output voltage ISINK = 3 mA 0.3 V

FSCL I2C clock frequency 3.4 MHz

JUNCTION THERMAL MANAGEMENT

TSD Thermal shutdown Rising 125 140 150 °C

Falling 115 °C

TH2 Hot temp threshold 2 Relative to TSD −7°C

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Table 4. ELECTRICAL CHARACTERISTICS

Min & Max Limits apply for TA between −40°C to +85°C and TJ up to + 125°C for VIN between 3.6 V to 7 V (Unless otherwise noted).

Typical values are referenced to TA = + 25°C and VIN = 5 V (Unless otherwise noted).

Symbol UnitMaxTypMinConditionsParameter

JUNCTION THERMAL MANAGEMENT

TH1 Hot temp threshold 1 Relative to TSD −11 °C

TWARN Thermal warning Relative to TSD −15 °C

BATTERY THERMAL MANAGEMENT

VNTCRMV Battery removed threshold

voltage

VNTC Rising 2.3 2.325 2.35 V

VCOLD Battery cold temperature

corresponding voltage

threshold

Voltage range 1.425 1.95 V

Default 1.7 1.725 1.75 V

VHOT Battery hot temperature

corresponding voltage

threshold

Voltage range 375 900 mV

Default 500 525 550 mV

VCOLD and VHOT voltage

granularity

75 mV

VWARM Battery warm temperature

corresponding voltage

threshold

BATWARM = 0 VHOT+

0.15

BATWARM = 1 VHOT+

0.225

VCHILLY Battery chilly temperature

corresponding voltage

threshold

BATCHILLY= 0 VCOLD−

0.15

BATCHILLY = 1 VCOLD−

0.225

VNTCDIS NTC disable corresponding

voltage threshold

VNTC Falling 50 75 100 mV

VREG Internal voltage reference 2.35 2.4 2.45 V

RNTCPU Internal resistor pull up 9.8 10 10.2 kW

BUCK CONVERTER

FSWCHG Switching Frequency −3−MHz

Switching Frequency Accuracy −10 +10 %

TDTYC Max Duty Cycle Average 99.5 %

IPKMAX Maximum peak inductor current 2 A

RONLS Low side Buck MOSFET

RDSON (Q3)

Measured between PGND and SW, VIN = 5 V −130 260 mW

RONHS High side Buck MOSFET

RDSON(Q2)

Measured between CAP and SW, VIN = 5 V −100 200 mW

PROTECTED TRANSCEIVER SUPPLY

VTRANS Voltage on TRANS pin VIN ≥ 5 V 5 5.5 V

ITRMAX TRANS current capability 50 mA

ITROCP Short circuit protection 150 mA

TIMING

TWD Watchdog timer 32 s

TUSB USB timer 2048 s

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Table 4. ELECTRICAL CHARACTERISTICS

Min & Max Limits apply for TA between −40°C to +85°C and TJ up to + 125°C for VIN between 3.6 V to 7 V (Unless otherwise noted).

Typical values are referenced to TA = + 25°C and VIN = 5 V (Unless otherwise noted).

Symbol UnitMaxTypMinConditionsParameter

TIMING

TCHG1 Charge timer Safe−charge or pre−charge or weak−safe or

weak− charge state.

3 h

TCHG2 Full−charge state 2 h

TWU Wake−up timer 64 s

TST Charger state timer Minimum

transition time

from states to

states.

From Weak Charge to Full

Charge State

32 s

All others state 16 ms

TVRCHR Deglitch time for end of charge

voltage detection

VBAT rising 15 ms

VBAT falling 127 ms

TINDET Deglitch time for input voltage

detection

VIN rising 15 ms

TDGS1 Deglitch time for signal

crossing IEOC, VPRE, VSAFE,

VCHGDET

, VINEXT thresholds.

Rising and falling edge 15 ms

TDGS2 Deglitch time for signal

crossing VFET

, VBUSUV,

VBUSOV thresholds.

Rising and falling edge 1 ms

BOOST CONVERTER AND OTG MODE

VIBSTL Boost minimum input

operating range

Boost start−up 3.1 3.2 3.3 V

Boost running 2.9 3 3.1 V

VIBSTH Boost maximum input

operating range

4.4 4.5 4.6 V

VOBST Boost Output Voltage DC value measured on CAP pin, no load 5.00 5.1 5.15 V

VOBSTAC Boost Output Voltage accuracy Measured on CAP pin Including line and load

regulation

−3 3 %

IBSTMX Output current capability 500 mA

FSWBST Switching Frequency 1.5 MHz

Switching Frequency Accuracy −10 10 %

IBPKM Maximum peak inductor current 2 A

VOBSTOL Boost overload Boost running, voltage on IN pin 4.3 4.4 4.5 V

TOBSTOL Maximum capacitance on IN pin during start−up 10 mF

ROBSTOL Minimum load

resistance on IN

pin during

start−up

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VOBSTOV Overvoltage protection VIN rising 5.55 5.65 5.75 V

Hysteresis 25 75 125 mV

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BLOCK DIAGRAM

CBOOT

CAP

Charge

Pump

PGND

5 V

reference

CORE

Current,

Voltage,

and Clock

Reference

NTC

PWM generator

BAT

FET

WEAK

SENSN

SENSP

I2C &

DIGITAL

CONTROLER

TRANS

SCL

SDA

ILIM1

OTG

SPM

AGND

FLAG

−

Amp

Drv

−

Drv

BATFET

& Drive

Drv

−

ILIM2

−

Figure 3. Block Diagram

VCAP

VCORE

VREG

VTJ

TSD

TH2

TH1

TWARN

VBAT

VCHGDET

VINOV

VIN

VINDET

VBUSOV

VBUSUV

VCAP

VCORE

IINREG

ICHG

VCHG

ICHG

detection

RNTCPU

VREG

VBAT

IEOC

IBAT

VBATOV

VRECHG

VFET

VPRE

VSAFE

VRMOVED

VCOLD

VCHILLY

VWARM

VHOT

VNTCDIS

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TYPICAL APPLICATION CIRCUITS

FLAG

SCL

SDA

SPM

TRANS

CAP

NTC

BAT

FET

WEAK

SENSN

SENSP

CBOOT

USB PHY

ILIM1

AGND

PGND

OTG

NCP1851

CORE

SYSTEM

VBUS

D+

D−

GND

RSNS

10 nF

ILIM2

Figure 4. USB Charger with Battery External MOSFET

FLAG

SCL

SDA

SPM

TRANS

CAP

NTC

BAT

FET

WEAK

SENSN

SENSP

CBOOT

NCP1851

CORE

SYSTEM

VBUS

D+

D−

GND

10 nF

CCAP

USB PHY

ILIM1

AGND

PGND

OTG

ILIM2

Figure 5. USB Charger without Battery External MOSFET

10 mF

CSYS

QBAT(*)

CBOOT

68 mW

LX2.2 mH

0.1 mF

CTRS

2.2 mF

CCORE

4.7 mF

CCAP

1.0 mF

CIN

RSNS

CSYS

10 mF

68 mW

CBOOT

LX2.2 mF

0.1 mF

CTRS

2.2 mF

CCORE

CCAP

4.7 mF

1.0 mF

CIN

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TYPICAL CHARACTERISTICS

Figure 6. VBUS Insertion Figure 7. Charger Mode Efficiency

Figure 8. Automatic Charge Current Figure 9. Dynamic Power Path

Figure 10. Boost Mode: Power−up Figure 11. Over Voltage Protection

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CHARGE MODE OPERATION

Overview

The NCP1851 is a fully programmable single cell

Lithium−ion switching battery charger optimized for

charging from a USB compliant input supply. The device

integrates a synchronous PWM controller; power

MOSFETs, and monitoring the entire charge cycle including

safety features under software supervision. An optional

battery FET can be placed between the system and the

battery in order to isolate and supply the system in case of

weak battery. The NCP1851 junction temperature and

battery temperature are monitored during charge cycle and

current and voltage can be modified accordingly through

I2C setting. The charger activity and status are reported

through a dedicated pin to the system. The input pin is

protected against overvoltages.

The NCP1851 is fully programmable through I2C

interface (see Registers Map section for more details). All

registers can be programmed by the system controller at any

time during the charge process. The charge current (ICHG),

charge voltage (VCHG), and input current (IINLIM) are

controlled by a dynamic voltage and current scaling for

disturbance reduction. Is typically 10 ms for each step.

NCP1851 also provides USB OTG support by boosting

the battery voltage as well as an over voltage protected

power supply for USB transceiver.

Charge Profile

In case of application without QFET (see Figure 5), the

NCP1851 provides 4 main charging phases as described

below. Unexpected behaviour or limitations that can modify

the charge sequence are described further (see Charging

Process section).

Figure 12. Typical Charging Profile of NCP1851

VSAFE

VPRE

VRECHG

VCHG

VBAT

IBAT

ICHG

IPRE

IEOC

ISAFE

Safe

Charge

Pre

Charge

Constant

Current

Constant

Voltage

End of

Charge

Safe Charge:

With a disconnected battery or completely empty battery,

the charge process is in safe charge state, the charge current

is set to ISAFE in order to charge up the system’s capacitors

or the battery. When the battery voltage reaches VSAFE

threshold, the battery enters in pre−conditioning.

Pre Conditioning (pre−charge):

In preconditioning (pre charge state), the DC−DC

convertor is enabled and an IPRE current is delivered to the

battery. This current is much lower than the full charge

current. The battery stays in preconditioning until the VBAT

voltage is lower than VPRE threshold.

Constant Current (full charge):

In the constant current phase (full charge state), the

DC−DC convertor is enabled and an ICHG current is

delivered to the load. As battery voltage could be sufficient,

the system may be awake and sink an amount of current. In

this case the charger output load is composed of the battery

and the system. Thus ICHG current delivered by the

NCP1851 is shared between the battery and the system:

ICHG = ISYS + IBAT.

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System

awake

Figure 13. Typical Charging Profile of NCP1851 with System Awake

VSAFE

VPRE

VRECHG

VBAT

VCHG

VBAT

IBAT

ISYS

IBAT

ISAFE

IEOC

IPRE

ICHG

Safe

Charge

Pre

Charge

Constant

Current

Constant

Voltage

End of

Charge

ICHG current is programmable using I2C interface

(register IBAT_SET − bits ICHG[3:0]).

Constant Voltage (full charge):

The constant voltage phase is also a part of the full charge

state. When the battery voltage is close to its maximum

(VCHG), the charge circuit will transition from a constant

current to a constant voltage mode where the charge current

will slowly decrease (taper off). The battery is now voltage

controlled. VCHG voltage is programmable using I2C

interface (register VBAT_SET− bits CTRL_VBAT[5:0]).

End of Charge:

The charge is completed (end of charge state) when the

battery is above the VRECHG threshold and the charge current

below the IEOC level. The battery is considered fully charged

and the battery charge is halted. Charging is resumed in the

constant current phase when the battery voltage drops below

the VRECHG threshold. IEOC current is programmable using

I2C interface (register IBAT_SET− bits IEOC[2:0]).

Power Stage Control

NCP1851 provides a fully−integrated 3MHz step−down

DC−DC converter for high efficiency. For an optimized

charge control, 3 feedback signals controls the PWM duty

cycle. These 3 loops are: maximum input current (IINLIM),

maximum charge current (ICHG) and, maximum charge

voltage (VCHG). The switcher is regulated by the first loop

that reaches its corresponding threshold. Typically during

charge current phase (VPRE < VBAT < VRECHG), the

measured input current and output voltage are below the

programmed limit and asking for more power. But in the

same time, the measured output current is at the

programmed limit and thus regulates the DC−DC converter.

In order to prevent battery discharge and overvoltage

protection, Q1(reverse voltage protection) and Q2(high side

N−MOSFET of the DC−DC converter) are mounted in a

back−to−back common drain structure while Q3 is the low

side N MOSFET of the DC−DC converter. Q2 gate driver

circuitry required an external bootstrap capacitor connected

between CBOOT pin and SW pin.

An internal current sense monitors and limits the

maximum allowable current in the inductor to IPEAK value.

Charger Detection, Start−up Sequence and System Off

The start−up sequence begins upon an adaptor valid

voltage plug in detection: VIN > VINDET and VIN − VBAT >

VCHGDET (off state).

Then, the internal circuitry is powered up and the presence

of NTC and BATFET are reported (register STATUS – bit

BATFET and NTC). When the power−up sequence is done,

the charge cycle is automatically launched. At any time and

any state, the user can hold the charge process and transit to

fault state by setting CHG_EN to ‘0’ (register CTRL1) in the

I2C register. Furthermore, during fault state, NTC block can

be disabled for power saving (bit NTC_EN register CTRL1)

The I2C registers are accessible without valid voltage on

VIN if VCAP > VSYSUV (i.e. if VBAT is higher than VSYSUV

+ voltage drop across Q2 body diode).

At any time, the user can reset all register stack (register

CTRL1 – bit REG_RST).

Weak Battery Support

An optional battery FET (QBAT) can be placed between

the application and the battery. In this way, the battery can

be isolated from the application and so−called weak battery

operation is supported.

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Typically, when the battery is fully discharged, also

referred to as weak battery, its voltage is not sufficient to

supply the application. When applying a charger, the battery

first has to be pre−charged to a certain level before operation.

During this time; the application is supplied by the DC−DC

converter while integrated current sources will pre−charge

the battery to the sufficient level before reconnecting.

The pin FET can drive a PMOS switch (QBAT) connected

between BAT and WEAK pin. It is controlled by the charger

state machine (Charging process section). The basic

behaviour of the FET pin is that it is always low. Thus the

PMOS is conducting, except when the battery is too much

discharged at the time a charger is inserted under the

condition where the application is not powered on. The FET

pin is always low for BAT above the VFET threshold. Some

exceptions exist which are described in the Charging process

and Power Path Management section. The VFET threshold

is programmable (register MISC_SET – bit CTRL_VFET).

Batfet detection

The presence of a PMOS (QBAT) at the FET pin is verified

by the charging process during its config state. To distinguish

the two types of applications, in case of no battery FET the

pin FET is to be tied to ground. In the config state an attempt

will be made to raise the FET pin voltage slightly up to a

detection threshold. If this is successful it is considered that

a battery FET is present. The batfet detection is completed

for the whole charge cycle and will be done again upon

unplug condition (VBAT < VINDET or VIN − V

BAT <

VCHGDET) or register reset (register CTRL1– bit REG_RST).

Weak wait

Weak wait state is entered from wait state (see Charging

process section) in case of BATFET present, battery voltage

lower than VFET and host system in shutdown mode (SPM

= 0). The DCDC converter from VIN to SW is enabled and

set to VCHG while the battery FET QBAT is opened. The

system is now powered by the DC−DC. The internal current

source to the battery is disabled. In weak wait state, the state

machine verifies if the battery temperature is OK thanks to

the NTC sensor. If NTC OK or if NTC is not present (NTC

pin tied to 0), this state is left for weak safe state. In case of

no battery, the NCP1851 stay in weak wait state (the system

is powered by DC−DC).

Weak safe

The voltage at VBAT, is below the VSAFE threshold. In

weak safe state, the battery is charged with a linear current

source at a current of ISAFE. The DC−DC converter is

enabled and set to VCHG while the battery FET QBAT is

opened. In case the ILIM pin is not made high or the input

current limit defeated by I2C before timer expiration, the

state is left for the safe charge state after a certain amount of

time (see Wake up Timer section). Otherwise, the state

machine will transition to the weak charge state once the

battery is above VSAFE.

Weak charge

The voltage at VBAT, is above the VSAFE threshold. The

DC−DC converter is enabled and set to VCHG. The battery

is initially charged at a charge current of IWEAK supplied by

a linear current source from WEAK pin (i.e. DC−DC

converter) to BAT pin. IWEAK value is programmable

(register MISC_SET bits IWEAK). The weak charge timer

(see Wake up Timer section) is no longer running. When the

battery is above the VFET threshold (programmable), the

state machine transitions to the full charge state thus

BATFET QBAT is closed.

Figure 14. Weak Charge Profile

VSAFE

VFET

VCHG

IBAT

VBAT

Weak

Charge

Constant

Current

Constant

Voltage

End of

Charge

Weak

Safe

Weak

Wait

VRECHG

ISYS

VBAT

IBAT

VSYS

IOUT

ICHG

IWEAK

ISAFE

IEOC

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Weak Charge Exit

In some application cases, the system may not be able to

start in weak charge states due to current capability

limitation or/and configuration of the system. If so, in order

to avoid unexpected “drop and retry” sequence of the buck

output, the charge state machine allows only 3 system

power−up sequences based on SPM pin level: If SPM pin

level is toggled 3 times during weak charge states, the

system goes directly to safe charge state and a full charge

mode sequence is initiated (“Power fail” condition in

Charging process section).

Power Path Management

Power path management can be supported when a battery

FET (QBAT) is placed between the application and the

battery. When the battery is fully charged (end of charge

state), power path management disconnects the battery from

the system by opening QBAT, while the DC−DC remains

active. This will keep the battery in a fully charged state with

the system being supplied from the DC−DC. If a load

transient appears exceeding the DC−DC output current and

thus causing VSENSEN to fall below VRECHG, the FET QBAT

is instantaneously closed to reconnect the battery in order to

provide enough current to the application. The FET QBAT

remains closed until the end of charge state conditions are

reached again. The power path management function is

enabled through the I2C interface (register CRTL2 bit

PWR_PATH=1).

Safety Timer Description

The safety timer ensures proper and safe operation during

charge process. The set and reset condition of the different

safety timer (Watchdog timer, Charge timer, Wakeup timer

and USB timer) are detailed below. When a timer expires

(condition “timeout” in Charging process section), the

charge process is halted.

Watchdog Timer

Watchdog timer ensures software remains alive once it

has programmed the IC. The watchdog timer is no longer

running since I2C interface is not available. Upon an I2C

write, automatically a watchdog timer TWD is started. The

watchdog timer is running during charger active states and

fault state. Another I2C write will reset the watchdog timer.

When the watchdog times out, the state machine reverts to

fault state and reported through I2C interface (register

CHINT2– bit WDTO). Also used to time out the fault state.

This timer can be disabled (Register CTRL2 bit

WDTO_DIS).

Charge Timer

A charge timer TCHG is running that will make that the

overall charge to the battery will not exceed a certain amount

of energy. The charge timer is running during charger active

states and halted during charger not active states (see

Charging process section). The timer can also be cleared any

time through I2C (register CTRL1 – bit TCHG_RST). The

state machine transitions to fault state when the timer

expires. This timer can be disabled (Register CTRL2 bit

CHGTO_DIS).

USB Timer

A USB charge timer TUSB is running in the charger active

states while halted in the charger non active states. The timer

keeps running as long as the lowest input current limit

remains selected either by ILIM pin or I2C (register I_SET

– bit IINLIM and IINLIM_EN). This will avoid exceeding

the maximum allowed USB charge time for un−configured

connections. When expiring, the state machine will

transition to fault state. The timer is cleared in the off state

or by I2C command (register CTRL1 – bit TCHG_RST).

Wake up Timer

Before entering weak charge state, NCP1851 verifies if

the input current available is enough to supply both the

application and the charge of the battery. A wake−up timer

TWU verifies if ILIM pin is raised fast enough or application

powered up (by monitoring register I_SET – bit IINLIM and

IINLIM_EN level) after a USB attachment. The wake up

timer is running in weak wait state and weak safe state and

clears when the input current limit is higher than 100 mA.

Input Current Limitation

In order to be USB specification compliant, the input

current at VIN is monitored and could be limited to the

IINLIM threshold. The input current limit threshold is

selectable through the ILIMx pin. When low, the one unit

USB current is selected (IIN ≤ 100 mA), where when made

high 5 units are selected (IIN ≤ 500 mA). In addition, this

current limit can be programmed through I2C (register

MISC_SET bits IINLIM) therefore defeating the state of the

ILIMx pin. In case of non−limited input source, current limit

can be disabled (register CTRL2 bit IINLIM_EN). The

current limit is also disabled in case the input voltage

exceeds the VBUSOV threshold.

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Figure 15. Typical Charging Profile of NCP1851 with Input Current Limit

End of

Charge

Constant

Voltage

VSAFE

VPRE

VRECHG

VCHG

VBAT

Constant

Current

Safe

Charge

Pre

Charge

IBAT

ISAFE

IEOC

IPRE

ICHG

Input Voltage Based Automatic Charge Current

If the input power source capability is unknown,

automatic charge current will automatically increase the

charge current step by step until the VIN drops to VBUSUV

Upon VBUSUV being triggered, the charge current ICHG is

immediately reduced by 1 step and stays constant until VIN

drops again to VBUSUV

. The ICHG current is clamped to the

I2C register value (register IBAT_SET, bits ICHG). This

unique feature is enabled when the pins ILIM1 = 0 and

ILIM2 = 1 or through I2C register (register CRTL2 bit

AICL_EN).

ILIM1 ILIM2 Input Current Limit

0 0 100 mA

0 1 Automatic Charge Current

1 0 500 mA

1 1 900 mA

Junction Temperature Management

During the charge process, NCP1851 monitors the

temperature of the chip. If this temperature increases to

TWAR N, an interrupt request (described in section Charge

status reporting ) is generated and bit TWARN_SNS is set

to ‘1’ (register NTC_TH_SENSE). Knowing this, the user

is free to halt the charge (register CTRL − bit CHG_EN) or

reduce the charge current (register I_SET − bits ICHG).

When chip temperature reaches TSD value, the charge

process is automatically halt.

Between TWARN and TSD threshold, a junction

temperature management option is available by setting 1 to

TJ_WARN_OPT bit (register CONTROL). In this case, if

the die temperature hits TM1 threshold, an interrupt is

generated again but NCP1851 will also reduce the charge

current ICHG by two steps or 200 mA. This should in most

cases stabilize the die temperature because the power

dissipation will be reduced by approximately 50 mW. If the

die temperature increases further to hit TM2, an interrupt is

generated and the charge current is reduced to its lowest

level or 400 mA. The initial charge current will be

re−established when the die temperature falls below the

TWAR N again.

If bit TJ_WARN_OPT = 0 (register CTRL1), the charge

current is not automatically reduced, no current changes

actions are taken by the chip until TSD.

Battery Temperature Management

For battery safety, charging is not allowed for too cold or

too hot batteries. The battery temperature is monitored

through a negative temperature coefficient (NTC)

thermistor mounted in the battery pack or on the phone PCB

close to the battery pack. In some cases the NTC is handled

by the platform and will not be connected to the charger IC.

NCP1851 provides a NTC pin for monitoring an external

NTC thermistor. NTC pin is connected to an internal voltage

VREG through pull−up resistor (RNTCPU). By connecting a

NTC thermistor between NTC pin and GND, internal

comparators can monitors voltage variation and provides

temperature information to the state machine.

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−

−+

NTC

−

NCP1851

−

Figure 16. NTC Monitoring Circuit

RNTCPU

VREG

VRMOVED

VCOLD

VCHILLY

VWARM

VHOT

VNTCDIS

Four thresholds ‘cold’, ‘chilly’, ‘warm’ and ‘hot’ are

provided those are all programmable. The corresponding

voltage levels of these thresholds are respectively VCOLD,

VCHILLY

, VWARM and VHOT. Interrupts (describe in section

Charge status reporting) are generated when crossing either

threshold. Two charging schemes are available through I2C

using these four thresholds. The default scheme (bit

JEITA_OPT = 0 in CTRL1 register) will halt charging

outside the cold−warm window. A second extended

temperature scheme (bit JEITA_OPT = 1 in CTRL1

while reducing the charge voltage and current in the

warm−hot and chilly−cold window with VCHGRED

(register NTC_SET1) and ICHGRED (register NTC_SET1).

The state machine (see Charging process section), takes the

chilly−warm respectively the cold−hot window for not out

of temp detection. This boils down into selecting between

ICHGRED or no current for the warm−hot and cold−chilly

window. In both cases, the charge voltage and charge current

can be reprogrammed while in the warm−hot and

cold−chilly window. Together with the programmable

thresholds this effectively allows the use of different

charging schemes at different temperatures as well as to

accommodate to different NTC characteristics. Cold, chilly,

warm and hot threshold can be set respectively with bits

BATCOLD, BATCHILLY, BATWARM and BATHOT of

NTC_SET2 register.

In addition to the above, comparators monitor the NTC

presence. When the NTC is removed (VNTC > VNTCRMV),

no more charge current is supplied to the battery and an

interrupt is generated (describe in section Charge status

reporting). This functionality can be disabled through

programming (bit NTC_EN in register CTRL1). When the

NTC is not used in the application the NTC pin can be tied

to ground (VNTC < VNTCDIS) which will disable the battery

temperature monitoring function.

Battery

Temperature

Figure 17. Charge Voltage and Current versus Battery Temperature (JEITA_OPT)

ICHGRED

ICHG

IBAT

VBAT

IBAT

VCHG − VCHGRED

VCHG

VBAT

THOT

TWARM

TCHILLY

TCOLD

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Use Case of Current and Voltage Charge

If configured, charge current and voltage is automatically modified by the input current limit, chip temperature and battery

temperature.

1.5 A

1 A

0.5 A

Constant current charge mode

ICHG = 1.5 A, VCHG = 4.2 V, VCHGRED = 0.2 V, ICHGRED = 0.7 A

IIINLIM = 500 mA

4.2 V

4 V

Chip temperature::Battery temperature: t

1.3 A

0.4 A

0.6 A

0.7 A

Figure 18. Use Case Charge Voltage and Current

VBAT

IBAT

VBAT

IBAT

TJ > TH1 TJ > TH2 TBAT <

TCOLD

USB 5 units charge:

TBAT

: OK TBAT >

TWARM

TBAT >

THOT

Regulated Power Supply (Trans pin)

NCP1851 has embedded a linear voltage regulator

(VTRANS) able to supply up to ITRMAX to external loads.

This output can be used to power USB transceiver. Trans pin

is enabled if a VBUS valid is connected on input pin

(VBUSUV < VIN < VBUSOV) and can be disabled through I2C

(bit TRANS_EN_REG register CTRL2).

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Charge Status Reporting

FLAG pin

FLAG pin is to used to report charge status to the system

processor and for interruption request.

During charger active states and wait state, the pin FLAG

is low in order to indicate that the charge of the battery is in

progress. When charge is completed or disabled or a fault

occurs, the FLAG pin is high as the charge is halted.

STATUS and CONTROL Registers

The status register contains the current charge state, NTC

and BATFET connection as well as fault and status interrupt

(bits FAULTINT and STATINT in register STATUS). The

charge state (bits STATE in register STATUS) is updated on

the fly and corresponds to the charging state describe in

Charging process section. An interruption (see description

below) is generated upon a state change. In the config state,

hardware detection is performed on BAFTET and NTC

pins. From wait state, their statuses are available (bit

BATFET and NTC in register STATUS). STATINT bit is set

to 1 if an interruption appears on STAT_INT register (see

description below). FAULTINT bit is set to 1 if an

interruption appears on registers CH1_INT, CH1_INT or

BST_INT. Thanks to this register, the system controller

knows the chip status with only one I2C read operation. If a

fault appears or a status change (STATINT bits and

FAULTINT), the controller can read corresponding

registers for more details.

Interruption

Upon a state or status change, the system controller is

informed by sensing FLAG pin. A TFLAGON pulse is

generated on this pin in order to signalize an event. The level

of this pulse depends on the state of the charger (see

Charging process section):

•When charger in is charger active states and wait state

the FLAG is low and consequently the pulse level on

FLAG pin is high.

•In the others states, the pulse level is low as the FLAG

stable level is high.

Charge state transition even and all bits of register

STAT_INT, CH1_INT, CH2_INT, BST_INT generate an

interrupt request on FLAG pin and can be masked with the

corresponding mask bits in registers STAT_MSK,

CH1_MSK, CH2_MSK and BST_MSK. All interrupt

signals can be masked with the global interrupt mask bit (bit

INT_MASK register CTRL1). All these bits are read to

clear. The register map (see REGISTERS MAP section)

indicated the active transition of each bits (column “TYPE”

in see REGISTERS MAP section).

If more than 1 interrupt appears, only 1 pulse is generated

while interrupt registers (STAT_INT, CH1_INT, CH2_INT,

BST_INT) will not fully clear.

Sense and Status Registers

At any time the system processor can know the status of

all the comparators inside the chip by reading VIN_SNS,

VBAT_SNS, and TEMP_SNS registers (read only). These

bits give to the system controller the real time values of all

the corresponding comparators outputs (see BLOCK

DIAGRAM).

Battery Removal and No Battery Operation

During normal charge operation the battery may bounce

or be removed. The state transition of the state machine only

occurs upon deglitched signals which allow bridging any

battery bounce. True battery removal will last longer than

the debounce times. The NCP1851 responses depend on

NTC and BATFET presence:

If the battery is equipped with an NTC its removal is

detected (VNTC > VNTCRMV) and the state machine transits

to fault state and an interrupt is generated (bit BATRMV

BATFET, the state machine will end up in weak wait state so

the system is powered by the DC−DC converter (see Weak

wait section) without battery. In case of application without

BATFET, the state machine will end up in fault state

(DC−DC off) so the system is not powered.

With a battery pack without NTC support, the voltage at

VBAT will rapidly reach the DCDC converter setting VCHG

and then transition to end of charge state causing DC−DC

off. Thus VBAT falls (“Battery fail” condition in Charging

process section).

Factory Mode

During factory testing no battery is present in the

application and a supply could be applied through the

bottom connector to power the application. The state

machine will support this mode of operation under the

condition that the application includes a battery FET and

uses batteries with NTC support (similar as no battery

operation). In this case, the state machine will end up in weak

wait state (see Weak wait section). The application is

supplied while the absence of the battery pack is interpreted

as a battery pack out of temperature (VNTC > VCOLD).

Through I2C the device is entirely programmable so the

controller can configure appropriate current and voltage

threshold for handle factory testing. Factory regulation

mode (Register CTRL2 Bit FCTRY_MOD_REG) is

accessible for factory testing purpose. In this mode, input

and charge current loops are disabled, allowing full power

to the system.

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CHARGING PROCESS

Timeout

Fault removed

and CHR_EN = 1

Start Charging:

Halt Charging:

CHARGER ACTIVE:

WEAK CHARGE MODE

CHARGER ACTIVE:

FULL CHARGE MODE

Power−up and

detection done

CHARGER NOT ACTIVE MODE

REG_RST = 1

FAULT

WEAK WAIT

WEAK SAFE

WEAK CHARGE

FULL CHARGE

PRE CHARGE

SAFE CHARGE

OFF

END OF CHARGE

− Power−up

− NTC and BATFET detection

− Q1: ON

CONFIG

WAIT

ANY STATE

− BUCK: OFF

− IWEAK: OFF

− ISAFE: ON

− FLAG: LOW

− QFET: ON

DPP

− BUCK: ON

− IWEAK: OFF

− ISAFE: OFF

− FLAG: HIGH

− QFET: ON

Figure 19. Detailed Charging Process

(*) see Power Path Management section

− BUCK: ON (precharge)

− IWEAK: OFF

− ISAFE: OFF

− FLAG: LOW

− QFET: ON

− BUCK: ON

− IWEAK: OFF

− ISAFE: OFF

− FLAG: LOW

− QFET: ON

− BUCK: ON

− IWEAK: ON

− ISAFE: OFF

− FLAG: LOW

− QFET: OFF

− BUCK: ON

− IWEAK: OFF

− ISAFE: ON

− FLAG: LOW

− QFET: OFF

− BUCK: ON

− IWEAK: OFF

− ISAFE: OFF

− FLAG: LOW

− QFET: OFF

VBAT > VFET

VBAT > VPRE

VBAT < VPRE

VBAT > VSAFE

VBAT < VSAFE

VBAT > VSAFE and

IINLIM ≥ 500 mA

VNTC > VCOLD or

VNTC < VWARM or

VBAT > VSAFE

VNTC > VCOLD or

VNTC < VWARM

VNTC < VCOLD or

VNTC > VWARM

VCAP > VSYSUV

− Charger OFF IQ < IOFF

− I2C available

−VIN < VINDET or

−VIN − VBAT < VCHGDET

−VIN > VINDET and

−VIN − VBAT > VCHGDET

Batfet present

and VBAT < VFET

and SPM = 0

Start Charging:

VCOLD > VNTC > VWARM

Halt Charging:

VNTC > VCOLD or

VNTC < VWARM or

Battery fail

−VBAT > VRECHG and

−IBAT < IEOC

−VSENSN > VRECHG and

−pwr_path = 1

−VBAT > VRECHG and

−IBAT < IEOC

− BUCK: OFF*

− IWEAK: OFF

− ISAFE: OFF

− FLAG: HIGH

− QFET: ON*

− BUCK: OFF

− IWEAK: OFF

− ISAFE: OFF

− FLAG: LOW

− QFET: ON

− BUCK: OFF

− IWEAK: OFF

− ISAFE: OFF

− FLAG: HIGH

− QFET: ON

−TJ > TSD or

−VIN > VINOV or

−VNTC > VNTCRMV or

−CHR_EN = 0

−Timeout

−TJ > TSD or

−VIN > VINOV or

−VBAT > VBATOV or

−CHR_EN = 0

−VIN > VINOV or

−VBAT > VBUCKOV or

−Timeout or

−Power fail or

−TJ > TSD or

−CHR_EN = 0

−Timeout

−TJ > TSD or

−VIN > VINOV or

−VBAT > VBUCKOV or

−VNTC > VNTCRMV or

−CHR_EN = 0

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BOOST MODE OPERATION

The DC−DC Converter can also be operated in a Boost

mode where the application voltage is stepped up to the input

VIN for USB OTG supply. The converter operates in a

1.5 MHz fixed frequency PWM mode or in pulse skipping

mode under low load condition. In this mode, where CAP is

the regulated output voltage, Q3 is the main switch and Q2

is the synchronous rectifier switch. While the boost

converter is running, the Q1 MOSFET is fully turned ON.

Boost Start−up

The boost mode is enabled through the OTG pin or I2C

(register CTRL1 − bit OTG_EN). Upon a turn on request, the

converter regulates CAP pin, and the output voltage is present

on IN pin through the Q1 MOSFET which is maintained

close unless OVLO event. During start−up phase, if the IN

pin cannot reach voltage higher than VBUSUV within 16 ms,

then a fault is indicated to the system controller (bit

VBUSILIM register BST_INT) and the boost is turns−off.

VIN Over−Voltage Protection

The NCP1851 contains integrated over−voltage protection

on the VIN line. During boost operation (VIN supplied), if an

over−voltage condition is detected (VIN > VBUSOV), the

controller turns off the PWM converter. OTG_EN bit

(register CTRL1) is set to 0 and a fault is indicated to the

system controller (bit VBUSOV register BST_INT)

VIN Over−Current Protection

The NCP1851 contains over current protection to prevent

the device and battery damage when VIN is overloaded.

When the IN voltage drops down to VBUSUV

, NCP1851

determine an over−current condition is met, so Q1 MOSFET

and PWM converter are turned off. A fault is indicated to the

system controller (bit VBUSILIM register BST_INT).

Battery Under−Voltage Protection

During boost mode, when the battery voltage is lower than

the battery under voltage threshold (VBAT < VIBSTL), the IC

turns off the PWM converter. A fault is indicated to the

system controller (bit VBATLO register BST_INT)

A toggle on OTG pin or OTG_EN bit (register CTRL1) is

needed to start again a boost operation.

Boost Status Reporting

STATUS and CTRL registers

The status register contains the boost status. Bits STATE

in register STATUS gives the boost state to the system

controller. Bits FAULTINT and STATINT in register

STATUS are also available in boost mode. If a fault appears

or a status changes (STATINT bits and FAULTINT) the

processor can read corresponding registers for more details.

Interruption

In boost mode, valid interrupt registers are STAT_INT and

BST_INT while CH1_INT and CH2_INT are tied to their

reset value. Upon a state or status changes, the system

controller is informed by sensing FLAG pin. Like in charge

mode, TFLAGON pulse is generated on this pin in order to

signalize the event. The pulse level is low as the FLAG level

is high in boost mode. Charge state transition even and all

signals of register BST_INT can generate an interrupt

request on FLAG pin and can be masked with the

corresponding mask bits in register BST_MSK. All these

bits are read to clear. The register map (see Registers Map

section) indicates the active transition of each bits (column

“TYPE” in see Registers Map section). If more than 1

interrupt appears, only 1 pulse is generated while interrupt

registers (listed just above) will not fully clear.

Sense and Status Registers

At any time the system controller can know the status of

all the comparator inside the chip by reading VIN_SNS and

TEMP_SNS registers (read only). These bits give to the

controller the real time values of all the corresponding

comparators outputs (see Block Diagram).

I2C DESCRIPTION

NCP1851 can support a subset of I2C protocol, below are detailed introduction for I2C programming.

START IC ADRESS 1

1à READ

ACK DATA 1 ACK DATA n /ACK STOP

START ACK

IC ADRESS 0

0à WRITE

DATA 1 ACK DATA n

ACK

/ACK

STOP

FROM MCU to NCPxxxx

FROM NCPxxxx to MCU

READ OUT

WRITE INSIDE PART

If PART does not Acknowledge, the /NACK will be followed by a STOP or Sr.

If PART Acknowledges, the ACK can be followed by another data or Stop or Sr

Figure 20. General Protocol Description

FROM PART

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The first byte transmitted is the Chip address (with LSB

bit sets to 1 for a read operation, or sets to 0 for a Write

operation). Then the following data will be:

•In case of a Write operation, the register address

(@REG) we want to write in followed by the data we

will write in the chip. The writing process is incremental.

So the first data will be written in @REG, the second

one in @REG + 1…. The data are optional.

•In case of read operation, the NCP1851 will output the

data out from the last register that has been accessed by

the last write operation. Like writing process, reading

process is an incremental process.

Read Out from Part

The Master will first make a “Pseudo Write” transaction

with no data to set the internal address register. Then, a stop

then start or a Repeated Start will initiate the read transaction

from the register address the initial write transaction has set:

STOP

IC ADRESS 1

1à READ

ACKSTART IC ADRESS 0

0à WRITE

START ACK DATA 1 DATA n

ACK /ACK STOP

STETS INTERNAL

VALUE

n REGISTERS READ

FROM MCU to NCPxxxx

FROM NCPxxxx to MCU

Figure 21. Read Out from Part

The first WRITE sequence will set the internal pointer on the register we want access to. Then the read transaction will start

at the address the write transaction has initiated.

Write in Part:

Write operation will be achieved by only one transaction. After chip address, the MCU first data will be the internal register

we want access to, then following data will be the data we want to write in Reg, Reg + 1, Reg + 2,…., Reg +n.

Write n Registers:

Figure 22. Write in n Registers

REG + (n − 1) VALUE ACK STOP

FROM MCU to NCPxxxx

FROM NCPxxxx to MCU

START IC ADRESS 0

0à WRITE

ACK REGISTER REG0 ADRESS ACK REG VALUE ACK

SETS INTERNAL

WRITE VALUE IN

n REGISTERS WRITE

I2C Address

NCP1851 has fixed I2C but different I2C address (0$10, 7 bit address, see below table A7~A1), NCP1851 supports 7−bit

address only.

Table 5. NCP1851 I2C ADDRESS

I2C Address (Note 5) Hex A7 A6 A5 A4 A3 A2 A1 A0

Default $6C / $6D 0 1 1 0 1 1 0 X

5. Other addresses are available upon request.

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Table 6. REGISTERS MAP

Bit Type Reset Name

RST

Value Function

STATUS REGISTER − Memory location : 00

7−4R No_Reset STATE[3:0] 0000 Charge mode:

−0000 : OFF

−0001 : WAIT + STBY

−0010 : SAFE CHARGE

−0011 : PRE CHARGE

−0100 : FULL CHARGE

−0101 : VOLTAGE CHARGE

−0110 : CHARGE DONE

−0111 : DPP

−1000 : WEAK WAIT

−1001 : WEAK SAFE

−1010 : WEAK CHARGE

−1011 : FAULT

Boost mode:

−1100 : BOOST WAIT(s_WAIT)

−1101 : BOOST MODE (s_ON)

−1110 : BOOST FAULT( s_FAULT)

−1111 : BOOST OVER LOAD (s_OL))

3 R No_Reset BATFET 0 Indicate if a batfet is connected:

0 : No BATFET is connected

1 : BATFET is connected.

2 R No_Reset NTC 0 Indicate if a ntc resistor is present:

0 : No NTC connected

1: NTC connected

1 R No_Reset STATINT 0 Status interrupt:

0 : No status interrupt

1 : Interruption flagged on STAT_INT register

0 R No_Reset FAULTINT 0 Fault interrupt:

0 : No status interrupt

1 : interruption flagged on CHRIN1, CHRIN2

or BST_INT register

CTRL1 REGISTER − Memory location : 01

7RW OFF STATE, POR,

REG_RST

REG_RST 0 Reset:

0 : No reset

1 : Reset all registers

6RW OFF STATE, POR,

REG_RST

CHG_EN 1 Charge control:

0 : Halt charging (go to fault state) or OTG operation

1 : Charge enabled / Charge resume

5RW OFF STATE, POR,

REG_RST, CHGMODE

OTG_EN 0 On the go enable:

0 : no OTG operation

1 : OTG operation (set by I2C or OTG pin)

4RW OFF STATE, POR,

REG_RST

NTC_EN 1 ntc pin operation enable:

0 :Battery temperature igniore,

1 : Battery temperature modify the charge profile.

3RW OFF STATE, POR,

REG_RST

TJ_WARN_OPT 0 Enable charge current vs Junction temperature

0: No current change versus junction temperature

1: Charge current is reduced when TJ is too high.

2RW OFF STATE, POR,

REG_RST, OTGMODE

JEITA_OPT 0 NTC warning operation enable:

0 : Hold the charge when VNTC > VWARM.

1 : Reduced the charge when VNTC > VWARM.

1RW OFF STATE, POR,

REG_RST, TRM_RST

TCHG_RST 0 Charge timer reset:

0 : no reset

1 : Reset and resume charge timer(tchg timer)

(self clearing)

0RW OFF STATE, POR,

REG_RST

INT_MASK 1 global interrupt mask

0 : All Interrupts can be active.

1 : All interrupts are not active

NCP1851, NCP1851A

http://onsemi.com

Table 6. REGISTERS MAP

Bit Function

RST

Value

NameResetType

CTRL2 REGISTER − Memory location : 02

7RW OFF STATE, POR,

REG_RST, OTGMODE

WDTO_DIS 0 Disable watchdog timer

0: Watchdog timer enable

1: Watchdog timer disable

6RW OFF STATE, POR,

REG_RST, OTGMODE

CHGTO_DIS 0 Disable charge timer

0: Charge timer enable

1: Charge timer disable

5RW OFF STATE, POR,

REG_RST, OTGMODE

PWR_PATH 0 Power Path Management:

0: Power Path disable

1: Power Path enable

4RW OFF STATE, POR,

REG_RST

TRANS_EN_REG 1 Trans pin operation enable:

0 : Trans pin is still off

1 : Trans pin is supply

3RW OFF STATE, POR,

REG_RST, OTGMODE

FCTRY_MOD_REG 0 Factory mode:

0: Factory mode disable

1: Enable factory mode.

2RW OFF STATE, POR,

REG_RST, OTGMODE

IINSET_PIN_EN 1 Enable input current set pin:

0: Input current limit and AICL control by I2C

1: Input current limit and AICL control by pins ILIMx

1RW OFF STATE, POR,

REG_RST, OTGMODE

IINLIM_EN 1 Enable input current limit:

0: No input current limit

1: Input current limit is IINLIM[3:0]

0RW OFF STATE, POR,

REG_RST, OTGMODE

AICL_EN 0 Enable automatic charge current:

0: No AICL

1: AICL

STAT_INT REGISTER − Memory location : 03

7−6R No_Reset RESERVED

5 RCDual OFF STATE, POR,

REG_RST

TWARN 0 0 : Silicon temperature is below TWARN threshold

1 : Silicon temperature is above TWARN threshold

4 RCDual OFF STATE, POR,

REG_RST

TM1 0 0 : Silicon temperature is below T1 threshold

1 : Silicon temperature is above T1 threshold

3 RCDual OFF STATE, POR,

REG_RST

TM2 0 0 : Silicon temperature is below T2 threshold

1 : Silicon temperature is above T2 threshold

2 RCDual OFF STATE, POR,

REG_RST

TSD 0 0 : Silicon temperature is below TSD threshold

1 : Silicon temperature is above TSD threshold

1 RCDual OFF STATE,

REG_RST,

POR, OTGMODE

CHGEX 0 0: Input voltage is lower than VINEXT

1: charger in extended range, VIN is higher than

VINEXT

0 RCDual OFF STATE,

REG_RST,

POR, OTGMODE

VBUSOK 0 0: changer not in USB range

1: charger in USB charging range VBUSUV < VIN

< VBUSOV

CH1_INT REGISTER − Memory location : 04

7−5R No_Reset RESERVED 0

4 RCDual OFF STATE,

REG_RST,

POR, OTGMODE

VINLO 0 VIN changer detection interrupt:

1: VIN - VBAT > VCHGDET and VIN < VINDET

3 RCDual OFF STATE,

REG_RST,

POR, OTGMODE

VINHI 0 VIN over voltage lock out interrupt:

1: VIN > VINOV

2 RCDual OFF STATE,

REG_RST,

POR, OTGMODE

BATRMV 0 battery temp out of range interrupt:

1: VNTC > VNTCRMV

NCP1851, NCP1851A

http://onsemi.com

Table 6. REGISTERS MAP

Bit Function

RST

Value

NameResetType

CH1_INT REGISTER − Memory location : 04

1RCDual OFF STATE,

REG_RST,

POR, OTGMODE

BUCKOVP 0 VBAT over voltage interrupt:

1: VBAT > VOVP

0 R No_Reset CHINT2 0 charger related interrupt (CH2_INT register)

CH2_INT REGISTER − Memory location : 05

7RCDual OFF STATE,

REG_RST,

POR, OTGMODE

NTCHOT 0 Battery Temperature exceeds NTC HOT threshold

6 RCDual OFF STATE,

REG_RST,

POR, OTGMODE

NTCWARM 0 Battery Temperature exceeds NTC WARM

threshold

5 RCDual OFF STATE,

REG_RST,

POR, OTGMODE

NTCCHILLY 0 Battery Temperature is lower than NTC CHILLY

threshold

4 RCDual OFF STATE,

REG_RST,

POR, OTGMODE

NTCCOLD 0 Battery Temperature is lower than NTC COLD

threshold

3 RCSingle OFF STATE, POR,

REG_RST, TRM_RST,

OTGMODE

WDTO 0 watchdog timeout expires interrupt:

1: 32s timer expired.

2 RCSingle OFF STATE, POR,

REG_RST, TRM_RST,

OTGMODE

USBTO 0 usb timeout expires initerrupt:

1: 2048s timer expired

1 RCSingle OFF STATE, POR,

REG_RST, TRM_RST,

OTGMODE

CHGTO 0 charge timeout expires interrupt:

1: 3600s timer expired

0 R No_Reset CHINT1 0 charger related interrupt (CH1_INT register)

BST_INT REGISTER − Memory location : 06

7−3R No_Reset RESERVED 00000

2 RCDual OFF STATE, POR,

REG_RST, CHGMODE

VBUSILIM 0 vbus overload interrupt:

1: Vbus voltage < VBUSUV

1 RCDual OFF STATE, POR,

REG_RST, CHGMODE

VBUSOV 0 vbus overvoltage interrupt:

1: Vbus voltage < VBUSOV

0 RCDual OFF STATE, POR,

REG_RST, CHGMODE

VBATLO 0 vbat overvoltage interrupt:

1: Vbat voltage < VIBSTL

VIN_SNS REGISTER − Memory location : 07

7R No_Reset VINOVLO_SNS 0 VIN over voltage lock out comparator

1: VIN > VINOV

6 R No_Reset CHEXTD7V_SNS 0 VIN extended range comparator

1: VIN > VINEXT

5 R No_Reset VBUSOV_SNS 0 VIN not is USB range comparator

1: VIN > VBUSOV

4 R No_Reset VBUSUV_SNS 0 VIN not is USB range comparator

1: VIN < VBUSUV

3 R No_Reset VINDET_SNS 0 VIN voltage detection comparator

1: VIN > VINDET

2 R No_Reset VCHGDET_SNS 0 VIN changer detection comparator

1: VIN − VBAT > VCHGDET

1 R No_Reset VBOOST_UV_SNS 0 VIN OTG under voltage comparator

1: VIN < VBUSUV

NCP1851, NCP1851A

http://onsemi.com

Table 6. REGISTERS MAP

Bit Function

RST

Value

NameResetType

VIN_SNS REGISTER − Memory location : 07

0R No_Reset RESERVED 0

VBAT_SNS REGISTER − Memory location : 08

7R No_Reset NTC_REMOVAL_SNS 0 NTC removal comparator:

1: Battery removal, VNTC > VNTCRMV

6 R No_Reset VBAT_OV_SNS 0 VBAT over voltage comparator

1: VBAT > VOVP

5 R No_Reset VRECHG_OK_SNS 0 VBAT recharge comparator

1: VBAT > VRECHG

4 R No_Reset VFET_OK_SNS 0 VBAT weak charge comparator

1: VBAT > VFET

3 R No_Reset VPRE_OK_SNS 0 VBAT precharge comparator

1: VBAT > VPRE

2 R No_Reset VSAFE_OK_SNS 0 VBAT safe comparator

1: VBAT > VSAFE

1 R No_Reset IEOC_OK_SNS 0 End of charge current comparator

1: ICHARGE > IEOC

0 R No_Reset RESERVED 0

TEMP_SNS REGISTER − Memory location : 09

7R No_Reset NTC_COLD_SNS 0 NTC cold comparator :

1: VNTC < VCOLD

6 R No_Reset NTC_CHILLY_SNS 0 NTC warm comparator :

1: VNTC > VCHILLY

5 R No_Reset NTC_WARM_SNS 0 NTC hot comparator :

1: VNTC > VHOT

4 R No_Reset NTC_HOT_SNS 0 NTC disable comparator :

1: VNTC > VNTCDIS

3 R No_Reset TSD_SNS 0 Chip thermal shut down comparator

1: Chip Temp > TSD

2 R No_Reset TM2_SNS 0 Chip thermal shut down comparator

1: Chip Temp > tm2

1 R No_Reset TM1_SNS 0 Chip thermal shut down comparator

1: Chip Temp > tm1

0 R No_Reset TWARN 0 Chip thermal shut down comparator

1: Chip Temp > twarn

STAT_MSK REGISTER − Memory location : 0A

7R No_Reset RESERVED 0

6 R No_Reset RESERVED 0

5RW OFF STATE,

POR, REG_RST

TWARN_MASK 0 TWARN interruption mask bit.

4RW OFF STATE,

POR, REG_RST

TM1_MASK 0 TM1 interruption mask bit.

3RW OFF STATE,

POR, REG_RST

TM2_MASK 0 TM2 interruption mask bit.

2RW OFF STATE,

POR, REG_RST

TSD_MASK 0 TSD interruption mask bit.

1 R No_Reset RESERVED 0

0RW OFF STATE, POR,

REG_RST, OTGMODE

VBUSOK_MASK 0 VBUSOK interruption mask bit.

NCP1851, NCP1851A

http://onsemi.com

Table 6. REGISTERS MAP

Bit Function

RST

Value

NameResetType

CH1_MSK REGISTER − Memory location : 0B

7−5R No_Reset RESERVED 0

4RW OFF STATE, POR,

REG_RST, OTGMODE

VINLO_MASK 0 VINLO interruption mask bit.

3RW OFF STATE, POR,

REG_RST, OTGMODE

VINHI_MASK 0 VINHI interruption mask bit.

2RW OFF STATE, POR,

REG_RST, OTGMODE

BATRMV_MASK 0 BATRMV interruption mask bit.

1RW OFF STATE, POR,

REG_RST, OTGMODE

BUCKOVP_MASK 0 BUCKOVP interruption mask bit.

0RW OFF STATE, POR,

REG_RST, OTGMODE

STATECHG_MASK 0 State transition interruption mask bit.

CH2_MSK REGISTER − Memory location : 0C

7RW OFF STATE, POR,

REG_RST, OTGMODE

NTCHOT_MASK 0 NTCHOT interruption mask bit.

6RW OFF STATE, POR,

REG_RST, OTGMODE

NTCWARM_MASK 0 NTCWARM interruption mask bit.

5RW OFF STATE, POR,

REG_RST, OTGMODE

NTCCHILLY_MASK 0 NTCCHILLY interruption mask bit.

4RW OFF STATE, POR,

REG_RST, OTGMODE

NTCCOLD_MASK 0 NTCCOLD interruption mask bit.

3RW OFF STATE, POR,

REG_RST, OTGMODE

WDTO_MASK 1 WDTO interruption mask bit.

2RW OFF STATE, POR,

REG_RST, OTGMODE

USBTO_MASK 1 USBTO interruption mask bit.

1RW OFF STATE, POR,

REG_RST, OTGMODE

CHGTO_MASK 1 CHGTO interruption mask bit.

0 R No_Reset RESERVED 0

BST_MSK REGISTER − Memory location : 0D

7−4R No_Reset RESERVED 0

3RW OFF STATE, POR,

REG_RST, OTGMODE

VBUSILIM_MASK 1 VBUSILIM interruption mask bit.

2RW OFF STATE, POR,

REG_RST, OTGMODE

VBUSOV_MASK 1 VBUSOV interruption mask bit.

1RW OFF STATE, POR,

REG_RST, OTGMODE

VBATLO_MASK 1 VBATLO interruption mask bit.

0RW OFF STATE, POR,

REG_RST, OTGMODE

STATEOTG_MASK 1 STATEOTG interruption mask bit.

VBAT_SET REGISTER − Memory location : 0E

7−6R No_Reset RESERVED 00

0−5RW OFF STATE, POR,

REG_RST, OTGMODE

CTRL_VBAT [5:0] 001100 000000: 3.3 V

001100: 3.6 V

110000: 4.5 V

Step: 0.025 V

IBAT_SET REGISTER − Memory location : 0F

7R No_Reset RESERVED 0

6−4RW OFF STATE, POR,

REG_RST, OTGMODE

IEOC[2:0] 010 000: 100 mA

010: 150 mA

111: 275 mA

Step: 25 mA

NCP1851, NCP1851A

http://onsemi.com

Table 6. REGISTERS MAP

Bit Function

RST

Value

NameResetType

IBAT_SET REGISTER − Memory location : 0F

3−0RW OFF STATE, POR,

REG_RST, OTGMODE

ICHG[3:0] 0110 Output range current programmable range:

0000: 400 mA

1100: 1.6 A

Step: 100 mA

MISC_SET REGISTER − Memory location : 10

7R No_Reset RESERVED 0

6−5RW OFF STATE, POR,

REG_RST, OTGMODE

IWEAK[1:0] 01 Charge current during weak battery states:

00: Disable

01: 100 mA

10: 200 mA

11: 300 mA

4−2RW OFF STATE, POR,

REG_RST, OTGMODE

CTRL_VFET[2:0] 011 Battery to system re−conection threshold:

000: 3.1 V

001: 3.2 V

010: 3.3 V

011: 3.4 V

100: 3.5 V

101: 3.6 V

1−0RW OFF STATE, POR,

REG_RST, OTGMODE

IINLIM[2:0] 00 Input current limit range:

00: 100 mA

01: 500 mA

10: 900 mA

11: 1500 mA

NTC_SET1 REGISTER − Memory location : 11

7−4R No_Reset RESERVED 000

3−2RW OFF STATE, POR,

REG_RST, OTGMODE

VCHRED[1:0] 10 Charge voltage reduction according to

battery temperature:

00: 000 mV

01: 100 mV

10: 200 mV

11: 300 mV

1−0RW OFF STATE, POR,

REG_RST, OTGMODE

ICHRED[1:0] 00 Charge current reduction according to

battery temperature:

00: 400 mA

01: 500 mA

10: 600 mA

11: 700 mA

NTC_SET2 REGISTER − Memory location : 12

7−5RW OFF STATE, POR,

REG_RST, OTGMODE

BATCOLD[2:0] 101 Cold battery temperature threshold:

101: 1.725 V

Step: 0.146 V

4−2RW OFF STATE, POR,

REG_RST, OTGMODE

BATHOT[2:0] 011 Hot battery temperature threshold:

011: 0.525 V

Step: 0.146 V

1OFF STATE, POR,

REG_RST, OTGMODE

BATCHILLY 0 Chilly battery temperature threshold:

0: VCHILLY + 0.146 V

1: VCHILLY + 0.219 V

0RW OFF STATE, POR,

REG_RST, OTGMODE

BATWARM 0 Warm battery temperature threshold:

0: VWARM – 0.146 V

1: VWARM – 0.219 V

NCP1851, NCP1851A

http://onsemi.com

APPLICATION INFORMATION

Components Selection

Inductor L1

NCP1851 is recommended to be used with 2.2 mH

inductor. Below will give inductor ripple and maximum

current for 2 different application cases knowing the

following relation:

DIL+VBAT ǒ1*VBAT

VIN Ǔ 1

L1 FSWCHG

The worst case is when VBAT *VBAT 2

VIN

is maximum

DILMAX +VIN

4@1

L1 @FSWCHG

;IPEAKMAX +ICHG )DILMAX

so when VBAT +VIN

Capacitor C6

A 10 mF output capacitor is recommended for proper

operation and design stability. The bandwidth of the system

is defined by the following relation:

FBW +1

2p L1 C6

Ǹ+33 kHz

The bandwidth is recommended to be high enough in case

of application with a BATFET because the system can be

directly connected to the buck output. And in this case, the

battery does not play any role upon a load transient as it’s

disconnected from the buck converter.

USB dedicated charge

VIN = 5 V

VCHG = 4.2 V

ICHG = 1.5 A

L1 = 2.2 mH

DIL1 = 0.189 A

IPEAKMAX = 1.59 A

AC adaptor charge

VIN = 16 V

VCHG = 4.2 V

ICHG = 1.5 A

L1 = 2.2 mH

DIL1 = 0.6 A

IPEAKMAX = 1.8 A

Resistance R1

R1 (charge current sense resistor) resistor is determined by

considering thermal constrain as its value is 68 mW typical.

The power dissipation is given by:

PR1 +R1 (ICHG)2

The worst case is ICHG = 1.5 A so PR1 = 0.153 W.

BILL OF MATERIAL

FLAG

SCL

SDA

SPM

TRANS

CAP

NTC

BAT

FET

WEAK

SENSN

SENSP

CBOOT

USB PHY

ILIM1

AGND

PGND

OTG

NCP1851

CORE

SYSTEM

VBUS

D+

D−

GND

10 nF

ILIM2

Figure 23. NCP1851 Typical Application Example

1 mF

CIN

4.7 mF

2.2 mF

CCORE

0.1 mF

CCAP

CTRS

QBAT (*)

CBOOT

68 mW

RSNS

CSYS

10 mF

LX2.2 mF

NCP1851, NCP1851A

http://onsemi.com

Item Part Description Ref Value

PCB

Footprint Manufacturer

Manufacturer

Reference

1Ceramic Capacitor 25 V X5R CIN 1 mF0603 MURATA GRM188R61E105K

2Ceramic Capacitor 25 V X5R CCAP 4.7 mF0805 MURATA GRM21BR61E475KA12L

3Ceramic Capacitor 6.3 V X5R CCORE 2.2 mF0402 MURATA GRM155R60J225M

4Ceramic Capacitor 6.3 V X5R CTRS 0.1 mF0402 MURATA GRM155R60J104K

5Ceramic Capacitor 10 V X5R CBOOT 10 nF 0402 MURATA GRM155R60J103K

6Ceramic Capacitor 6.3 V X5R COUT 10 mF0603 MURATA GRM188R60J106M

7SMD Inductor LX2.2 mH3012 TDK VLS3012T−2R2M1R5

8SMD Resistor 0.25 W, 1% RSNS 68 mW0603 PANASONIC ERJ3BWFR068V

9Power channel P−MOSFET QBAT 30 mWUDFN 2*2mm ONSEMI NTLUS3A40PZ

PCB Layout Consideration

Particular attention must be paid with CCORE capacitor as

it’s decoupling the supply of internal circuitry including gate

driver. This capacitor must be placed between CORE pin

and PGND pin with a minimum track length.

The high speed operation of the NCP1851 demands

careful attention to board layout and component placement.

To prevent electromagnetic interference (EMI) problems,

attention should be paid specially with components CIN, LX,

CCAP

, and COUT as they constitute a high frequency current

loop area. The power input capacitor CIN, connected from

IN to PGND, should be placed as close as possible to the

NCP1851. The output inductor LX and the output capacitor

COUT connected between RSNS and PGND should be placed

close to the IC. CCAP capacitor should also be place as close

as possible to CAP and PGND pin.

The high current charge path through IN, CAP, SW,

inductor L1, Resistor R1, optional BAFTET, and battery

pack must be sized appropriately for the maximum charge

current in order to avoid voltage drops in these traces. An

IWEAK current can flow through WEAK and BAT traces

witch defines the appropriate track width.

It’s suggested to keep as complete ground plane under

NCP1851 as possible. PGND and AGND pin connection

must be connected to the ground plane.

Care should be taken to avoid noise interference between

PGND and AGND. Finally it is always good practice to keep

the sensitive tracks such as feedbacks connections (SENSP,

SENSN, BAT) away from switching signal connections by

laying the tracks on the other side or inner layer of PCB.

CAP

PGND

CORE

Power path

NCP1851

Noise sensitive path

Figure 24. NCP1851 Power Path

CSYS

10 mF

68 mW

RSNS

LX2.2 mF

CIN

1 mF

2.2 mF

CCORE

4.7 mF

CCAP

ORDERING INFORMATION

Part Number Specific Device Code VSYSOV ROBSTOL RNTCPU I2C address

NCP1851FCCT1G 1851 7 V 170 W10 kW$6C

NCP1851AFCCT1G 1851A 7 V 50 W10 kW$6C

NCP1851, NCP1851A

http://onsemi.com

PACKAGE DIMENSIONS

25 Pin Flip−Chip, 2.55x2.20

CASE 499BN

ISSUE A

SEATING

PLANE

0.10 C

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. COPLANARITY APPLIES TO SPHERICAL

CROWNS OF SOLDER BALLS.

DIM

MIN MAX

−−−

MILLIMETERS

D2.55 BSC

b0.24 0.29

e0.40 BSC

0.60

PIN A1

REFERENCE

A0.05 BC

0.03 C

0.05 C

25X b

0.10 C

0.17 0.23

2.20 BSC

0.25

25X

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.40

0.10 C

2X TOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 3

A3 0.04 REF

RECOMMENDED

PACKAGE

OUTLINE

123

PITCH

EPITCH

DETAIL A

A2 0.36 REF

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,

copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC

reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC

does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where

personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and

its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,

any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture

of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

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USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

NCP1851/D

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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

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For additional information, please contact your local

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Authorized Distributor

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NCP1851AFCCT1G NCP1851BFCCT1G