1. General description
The HEF4094B-Q100 is an 8-stage serial shift register. It has a storage latch associated
with each stage for strobing data from the serial input to parallel buffered 3-state outputs
QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is
shifted on positive-going clock transitions. The data in each shift register stage is
transferred to the sto ra g e re gis ter whe n the strobe (STR) input is HIGH. Data in the
storage register appears at the outputs whenever the output enable (OE) signa l is HIGH.
Two serial outputs (QS1 and QS2) are available for cascading a number of
HEF4094B-Q100 devices. Serial data is available at QS1 on positive-going clock edges to
allow high-speed operation in cascaded systems with a fast clock rise time. The same
serial data is available at QS2 on the next negative going clock edge. This is used for
cascading HEF4094B-Q100 devices when the clock has a slow rise time.
It operates over a recommended VDD power supply r ange of 3 V to 15 V referenced to VSS
(usually ground). Connect unused inputs to VDD, VSS, or another input.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
ESD protection:
MIL-STD-833, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Complies with JEDEC standard JESD 13-B
HEF4094B-Q100
8-stage shift-and-store register
Rev. 3 — 4 July 2013 Product data sheet
HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 2 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-store register
3. Ordering information
4. Functional diagram
Table 1. Ordering information
All types operate from
40
C to +125
C.
Type number Package
Name Description Version
HEF4094BT-Q100 SO16 plastic small outline package ; 16 leads; body width 3.9 mm SOT109-1
HEF4094BTT-Q100 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
Fig 1. Functional di agram Fig 2. Logic symbol
001aaf119
8-STAGE SHIFT
REGISTER
8-BIT STORAGE
REGISTER
3-STATE OUTPUTS
D
2QS2 10
QS1
QP0
4 5 6 7 14 13 12 11
QP1 QP2 QP3 QP4 QP5 QP6 QP7
9
CP
3
STR
1
OE
15
15
2
OE
D
CP STR
31
QP0
QP1
QP2
QP3
QP4
QP5
QP6
QP7
QS1
QS2
9
10
4
5
6
7
14
13
12
11
001aaf111
HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 3 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-store register
5. Pinning information
5.1 Pinning
Fig 3. Logic diag ram
001aag799
DD
CP
CP
Q
FF 0
D
LE
Q
LATCH 0
D
CP
Q
FF 7
D
LE
Q
LATCH 7
D
CP
Q
STAGES 1 TO 6STAGE 0 STAGE 7
QP2
QP0
D QS2
QS1
LE
Q
LATCH
QP1 QP4
QP3 QP6
QP5 QP7
STR
OE
Fig 4. Pin configuration SOT109-1 Fig 5. Pin co nfiguration SOT403-1
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HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 4 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-store register
5.2 Pin description
6. Functional description
[1] At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs.
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= positive-going transition; = negative-going transition;
Z = HIGH-impedance OFF-state; NC = no change;
Q6S = the data in register stage 6 before the LOW to HIGH clock transition;
Q7S = the data in register stage 7 before the HIGH to LOW clock transition.
Table 2. Pin description
Symbol Pin Description
STR 1 strobe input
D 2 data input
CP 3 clock input
QP0 to QP7 4, 5, 6, 7, 14, 13, 12, 11 parallel output
VSS 8 ground supply voltage
QS1 9 serial ou tp u t
QS2 10 serial output
OE 15 output enable input
VDD 16 supply voltage
Table 3. Function table[1]
Inputs Parallel outputs Serial outputs
CP OE STR DQP0 QPn QS1 QS2
LXXZZQ6SNC
LXXZZNCQ7S
HLXNCNCQ6SNC
HHLLQPn 1Q6S NC
HHHHQPn 1Q6S NC
H H H NCNCNCQ7S
HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 5 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-store register
7. Limiting values
[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
Fig 6. Timing diagram
001aaf117
CLOCK INPUT
DATA INPUT
STROBE INPUT
OUTPUT ENABLE INPUT
INTERNAL Q0S (FF 0)
OUTPUT QP0
INTERNAL Q6S (FF 6)
OUTPUT QP6
SERIAL OUTPUT QS1
SERIAL OUTPUT QS2
Z-state
Z-state
Table 4. L imiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +18 V
IIK input clamping current VI<0.5 V or VI>V
DD + 0.5 V - 10 mA
VIinput voltage 0.5 VDD + 0.5 V
IOK output clamping curre nt VO<0.5 V or VO>V
DD + 0.5 V - 10 mA
II/O input/output current - 10 mA
IDD supply current - 50 mA
Tstg storage temperature 65 +150 C
Tamb ambient temperature 40 +125 C
Ptot total power dissipation [1] - 500 mW
P power dissipation per output - 100 mW
Table 5. Recommended operating con ditions
Symbol Parameter Conditions Min Typ Max Unit
VDD supply voltage 3 - 15 V
VIinput voltage 0 - VDD V
Tamb ambient temperature in free air 40 - +125 C
t/V input transition rise and fall rate VDD = 5 V --3.75s/V
VDD = 10 V --0.5s/V
VDD = 15 V --0.08s/V
HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 6 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-store register
9. Static characteristics
Table 6. Static characteristics
VSS = 0 V; VI=V
SS or VDD; unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 CUnit
Min Max Min Max Min Max Min Max
VIH HIGH-level
input voltage IO < 1 A 5 V 3.5 - 3.5 - 3.5 - 3.5 - V
10 V7.0-7.0-7.0-7.0 -V
15 V 11.0 - 11.0 - 11.0 - 11.0 - V
VIL LOW-level
input voltage IO < 1 A 5 V - 1.5 - 1.5 - 1.5 - 1.5 V
10 V - 3.0 - 3.0 - 3.0 - 3 .0 V
15 V - 4.0 - 4.0 - 4.0 - 4 .0 V
VOH HIGH-level
output voltage IO < 1 A 5 V 4.95 - 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - 14.95 - V
VOL LOW-level
output voltage IO < 1 A 5 V - 0.05 - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 - 0.05 V
IOH HIGH-level
output current VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 - 1.1 mA
VO = 4.6 V 5 V - 0.64 - 0.5 - 0.36 - 0.36 mA
VO = 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA
VO = 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA
IOL LOW-level
output current VO = 0.4 V 5 V 0.64 - 0.5 - 0.36 - 0.36 - mA
VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA
VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA
IOZ OFF-state
output current QPn output
is HIGH;
VO=15V
15 V - 0.4 - 0.4 - 12 - 12 A
IIinput leakage
current 15 V - 0.1 - 0.1 - 1.0 - 1.0 A
IDD supply current al l valid input
combinations;
IO=0A
5 V - 5 - 5 - 150 - 150 A
10 V - 10 - 10 - 300 - 300 A
15 V - 20 - 20 - 600 - 600 A
CIinput
capacitance ---7.5-- - -pF
HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 7 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-store register
10. Dynamic characteristics
Table 7. Dynamic characteristics
VSS = 0 V; Tamb = 25
C; for test circuit see Figure 11; unless otherwise specified.
Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit
tPHL HIGH to LOW
propagation delay CP to QS1;
see Figure 7 5 V [1] 108 ns + (0.55 ns/pF)CL- 135 270 ns
10 V 54 ns + (0.23 ns/pF)CL- 65 130 ns
15 V 42 ns + (0.16 ns/pF)CL- 50 100 ns
CP to QS2;
see Figure 7 5 V 78 ns + (0.55 ns/pF)CL- 105 210 ns
10 V 39 ns + (0.23 ns/pF)CL- 50 100 ns
15 V 32 ns + (0.16 ns/pF)CL-4080ns
CP to QPn;
see Figure 7 5 V 138 ns + (0.55 ns/pF)CL- 165 330 ns
10 V 64 ns + (0.23 ns/pF)CL- 75 150 ns
15 V 47 ns + (0.16 ns/pF)CL- 55 110 ns
STR to QPn;
see Figure 8 5 V 83 ns + (0.55 ns/pF)CL- 110 220 ns
10 V 39 ns + (0.23 ns/pF)CL- 50 100 ns
15 V 27 ns + (0.16 ns/pF)CL-3570ns
tPLH LOW to HIGH
propagation delay CP to QS1;
see Figure 7 5 V [1] 78 ns + (0.55 ns/pF)CL- 105 210 ns
10 V 39 ns + (0.23 ns/pF)CL- 50 100 ns
15 V 32 ns + (0.16 ns/pF)CL-4080ns
CP to QS2;
see Figure 7 5 V 78 ns + (0.55 ns/pF)CL- 105 210 ns
10 V 39 ns + (0.23 ns/pF)CL- 50 100 ns
15 V 32 ns + (0.16 ns/pF)CL-4080ns
CP to QPn;
see Figure 7 5 V 123 ns + (0.55 ns/pF)CL- 150 300 ns
10 V 59 ns + (0.23 ns/pF)CL- 70 140 ns
15 V 47 ns + (0.16 ns/pF)CL- 55 110 ns
STR to QPn;
see Figure 8 5 V 73 ns + (0.55 ns/pF)CL- 100 200 ns
10 V 34 ns + (0.23 ns/pF)CL-4590ns
15 V 27 ns + (0.16 ns/pF)CL-3570ns
tttransition time 5 V [1] 10 ns + (1.00 ns/pF)CL- 60 120 ns
10 V 9 ns + (0.42 ns/pF)CL-3060ns
15 V 6 ns + (0.28 ns/pF)CL-2040ns
tPZH OFF-state to HIGH
propagation delay OE to QPn;
see Figure 9 5 V - 40 80 ns
10 V - 25 5 0 ns
15 V - 20 4 0 ns
tPZL OFF-state to LOW
propagation delay OE to QPn;
see Figure 9 5 V - 40 80 ns
10 V - 25 5 0 ns
15 V - 20 4 0 ns
tPHZ HIGH to OFF-state
propagation delay OE to QPn;
see Figure 9 5 V - 75 150 ns
10 V - 40 8 0 ns
15 V - 30 6 0 ns
HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 8 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-store register
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
tPLZ LOW to OFF-state
propagation delay OE to QPn;
see Figure 9 5 V - 80 160 ns
10 V - 40 8 0 ns
15 V - 30 6 0 ns
tsu set-up time D to CP;
see Figure 10 5 V 6030- ns
10 V 20 10 - ns
15 V 15 5 - ns
thhold time D to CP;
see Figure 10 5 V +5 15 - ns
10 V 20 5 - ns
15 V 20 5 - ns
tWpulse width minimum LOW
clock pulse;
see Figure 7
5 V 6030- ns
10 V 30 15 - ns
15 V 24 12 - ns
minimum HIGH
strobe pulse;
see Figure 8
5 V 4020- ns
10 V 30 15 - ns
15 V 24 12 - ns
fmax maximum frequency see Figure 7 5 V 5 10 - MHz
10 V 11 22 - MHz
15 V 1428- MHz
Table 7. Dynamic characteristics …continued
VSS = 0 V; Tamb = 25
C; for test circuit see Figure 11; unless otherwise specified.
Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit
Table 8. Dynamic power dissipation
VSS = 0 V; tr = tf
20 ns; Tamb = 25
C.
Symbol Parameter VDD Typical formula for PD (W) where:
PDdynamic power
dissipation 5 V PD = 2100 fi + (fo CL) VDD2fi = input frequency in MHz,
fo = output frequency in MHz,
CL = output load capacitance in pF,
VDD = supply voltage in V,
(fo CL) = sum of the outputs.
10 V PD = 9700 fi + (fo CL) VDD2
15 V PD = 26000 fi + (fo CL) VDD2
HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 9 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-store register
11. Waveforms
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. Clock to outputs propagation delays, and clock pulse width and maximum frequency
1/f
max
t
W
t
PHL
t
PLH
V
I
GND
V
OH
V
OL
QPn, QS1 output
CP input V
M
V
M
001aaf113
t
PHL
t
PLH
V
OH
V
OL
QS2 output V
M
Table 9. Mea surement points
Supply voltage Input Output
VDD VMVMVXVY
5 V to 15 V 0.5VDD 0.5VDD 0.1VDD 0.9VDD
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. Strobe to output propagation delays, and strobe pulse width, set up and hold times
HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 10 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-store register
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9. 3-state output enable and disable times for OE input
001aai545
tPLZ
tPHZ
outputs
disabled outputs
enabled
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input VM
VI
VOL
VOH
GND
VY
VX
tPZL
tPZH
VM
VM
VDD
GND
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 10. Data input data set up and hold times
001aaf115
GND
GND
th
tsu th
tsu
VM
VM
VM
VI
VOH
VOL
VI
QPn, QS1, QS2 output
CP input
D input
HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 11 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-store register
a. Input waveform
b. Test circuit
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL= load capacitance including jig and probe capacitance.
RL = load resistance.
RT= termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 11. Test circuit
V
M
V
M
t
W
t
W
10 %
90 %
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
90 %
10 %
t
f
t
r
t
r
t
f
001aaj781
001aaj915
VEXT
VDD
VIVO
DUT
CL
RT
RL
G
Table 10. Test data
Supply voltage Input VEXT Load
VDD VItr, tftPHL, tPLH tPHZ, tPZH tPLZ, tPZL CLRL
5 V to 15 V VSS or VDD 20 ns open VSS VDD 50 pF 1 k
HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 12 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-store register
12. Application information
Some examples of applications for the HEF4094B-Q100 are:
Serial-to-parallel data conversion
Remote control holding register
Fig 12. Remote control holding register
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HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 13 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-store register
13. Package outline
Fig 13. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
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Lp
Q
detail X
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y
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max. A1A2A3bpcD
(1) E(1) (1)
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REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 10.0
9.8 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.39
0.38 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.020 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 14 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-store register
Fig 14. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
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e
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18
16 9
θ
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A1
A2
Lp
Q
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L
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c
vMA
X
A
y
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scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 15 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-store register
14. Abbreviations
15. Revision history
Table 11. Ab br eviations
Acronym Description
HBM Human Body Model
ESD ElectroStatic Discharge
MM Machine Model
MIL Military
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
HEF4094B_Q100 v.3 20130704 Product data sheet - HEF4094B_Q100 v.2
Modifications: Figure 3 corrected (errata).
HEF4094B_Q100 v.2 20130606 Product data sheet - HEF4094B_Q100 v.1
Modifications: added type number HEF4094BTT-Q100.
HEF4094B_Q100 v. 1 201 20807 Product data sheet - -
HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 16 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-sto r e reg is te r
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specification The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyon d those described in the
Product data sheet.
16.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability t owards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descripti ons, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, t he product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associate d with t heir
applications and products.
NXP Semiconductors does not accept any liabil ity related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the appl ication or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress rating s only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Te rms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly ob jects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specificati on for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.
Product [short] dat a sheet Production This document contains the product specification.
HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 17 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-sto r e reg is te r
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) versio n of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-sto r e reg is te r
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 July 2013
Document identifier: HEF4094B_Q100
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12 Application information. . . . . . . . . . . . . . . . . . 12
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
17 Contact information. . . . . . . . . . . . . . . . . . . . . 17
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18