24LC08B/P202 - Microchip Technology, Inc.

 2001 Microchip Technology Inc. DS21051H-page 1

M24LC04B/08B

FEATURES

• Single supply with operation down to 2.5V

• Low power CMOS technology

- 1 mA active current typical

-10 µA standby current typical at 5.5V

-5 µA standby current typical at 3.0V

• Organized as two or four blocks of 256 bytes

(2 x 256 x 8) and (4 x 256 x 8)

• 2-wire serial interface bus, I2C™ compatible

• Schmitt trigger, filtered inputs for noise

suppression

• Output slope control to eliminate ground bounce

• 100 kHz (E-temp) and 400 kHz (C/I-temp.)

compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 16 bytes

• 2 ms typical write cycle time for page-write

• Hardware write protect for entire memory

• Can be operated as a serial ROM

• Factory programming (QTP) available

• ESD protection > 4,000V

• 1,000,000 erase/write cycles ensured

• Data retention > 20 0 years

• 8-pin DIP, 8-lead SOIC, 8-pin TSSOP packages

• Available temperature ranges:

DESCRIPTION

The Microchip Technology Inc. 24LC04B/08B is a 4

Kbit or 8 Kbit Electrically Erasable PROM (EEPROM).

The device is organized as two or four blocks of 256 x

8-bit memory with a 2-wire serial in terface. L ow vol tage

design permits operation down to 2.5 volts with typical

standby and active currents of only 5 µA and 1 mA

respectively. The 24LC04B/08B also has a page-write

cap abilit y for up to 16 by tes o f dat a. T he 24L C04B/08B

is available in the standard 8-pin DIP, 8-lead surface

mount SOIC, MSOP a nd TSSOP packages.

PACKAGE TYPES

BLOCK DIAGRAM

- Commercial (C): 0°C to +70°C

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

24LC04B/08B

Vss

VCC

SCL

SDA

PDIP, SOIC

TSSOP

24LC04B/08B

VSS

VCC

SCL

SDA

VCC

SCL

SDA

24LC04B/08B

VSS

MSOP

Note: A0, A1 and A2 are not used

HV GENERATOR

EEPROM ARRAY

(2 x 256 x 8) or

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA SCL

VCC

VSS

(4 x 256 x 8)

4K/8K 2.5 I2C™ Serial EEPROMs

24LC04B/08B

DS21051H-page 2  2001 Microchip Technology Inc.

1.0 ELECTRICAL

CHARACTERISTICS

1.1 Maximum Ratings*

VCC........................................................................7.0V

All inputs and outputs w.r.t. VSS ....-0.3V to VCC + 1.0V

Storage temperature ..........................-65°C to +150°C

Ambient temp. with powe r appli ed.....-65°C to +125°C

Soldering temperature of leads (10 seconds)..+300°C

ESD protection on all pins .....................................≥ 4 KV

TABLE 1-1: PIN FUNCTION TABLE

TABLE 1-2: DC CHARACTERISTICS

FIGURE 1-1: BUS TIMING START/STOP

*Notice: Stresses above those listed under “Maximum

ratings” may cause permanent damage to the

device. This is a stress rating only and functional

operation of the device at those or any other

conditions above those indicated in the opera-

tional listings of this specification is not implied.

Exposure to maximum rating conditions for

extended periods may affect device reliability.

Name Function

VSS Ground

SDA Serial Address/Data I/O

SCL Serial Clock

WP Write Protect Input

VCC +2.5V to 5.5V Power Supply

A0, A1, A2 No Internal Connection

VCC = +2.5V to +5.5V Commercial (C): TAMB = 0°C to +70°C

Industrial (I): TAMB = -40°C to +85°C

Automotive (E): TAMB = -40°C to +125°C

Parameter Symbol Min. Max. Units Conditions

WP, SCL and SDA pins:

High level input voltage

Low level input voltage

Hysteresis of Schmitt trigger

Inputs

Low level outp ut voltage

VIH

VIL

VHYS

VOL

.7 VCC

—

.05 VCC

—

.3 VCC

—

.40

—

(Note)

IOL = 3.0mA, VCC = 2.5V

Input leakage current ILI -10 10 µAVIN = 0.1V to VCC

Output lea kage curre nt ILO -10 10 µAVOUT = 0.1V to VCC

Pin capacitance

(all inputs/outpu ts) CIN, COUT —10 pF VCC = 5.0V (Note)

TAMB = 25°C, FCLK = 1 MHz

Operati ng current ICC Write

ICC Read —

—3

1mA

mA VCC = 5.5V, SCL = 400 k Hz

—

Standby current ICCS —

—30

100 µA

µAVCC = 3.0V, SDA = SCL = VCC

VCC = 5.5V, SDA = SCL = VCC

WP = VSS

Note: This parameter is periodically sampled and not 100% tested.

TSU:STA THD:STA

VHYS

TSU:STO

START STOP

SCL

SDA

 2001 Microchip Technology Inc. DS21051H-page 3
24LC04B/08B
TABLE 1-3: AC CHARACTERISTICS
VCC = +2.5V to 5.5V Commercial (C): TAMB =    0°C to +70°C
Industrial (I): TAMB = -40°C to +85°C
Automotive (E): TAMB = -40°C to +125°C
Parameter Symbol Min Max Units Conditions
Clock frequency FCLK —
—400
100 kHz 4.5V ≤ VCC ≤  5.5V
2.5V ≤  VCC ≤  5.5V (E-temp. range)
Clock high time THIGH 600
4000 —
—ns 4.5V ≤  VCC ≤ 5.5V
2.5V ≤  VCC ≤  5.5V (E-temp. range)
Clock low time TLOW 1300
4700 —
—ns 4.5V ≤  VCC ≤  5.5V
2.5V ≤  VCC ≤  5.5V (E-temp. range)
SDA and SCL rise time
(Note 1) TR—
—300
1000 ns 4.5V ≤  VCC ≤  5.5V (Note 1)
2.5V ≤  VCC ≤  5.5V (E-temp. range) (Note 1)
SDA and SCL fall time TF—300 ns (Note 1)
START condition hold time THD:STA 600
4000 —
—ns 4.5V ≤  VCC ≤  5.5V
2.5V ≤  VCC ≤  5.5V (E-temp. range)
START condition setup time TSU:STA 600
4700 —
—ns 4.5V ≤  VCC ≤  5.5V
2.5V ≤  VCC ≤  5.5V (E-temp. range)
Data input hold time THD:DAT 0—ns (Note 2)
Data input setup time TSU:DAT 100
250 —
—ns 4.5V ≤  VCC ≤  5.5V
2.5V ≤  VCC ≤  5.5V (E-temp. range)
STOP condition setup time TSU:STO 600
4000 —
—ns 4.5V ≤  VCC ≤  5.5V
2.5V ≤  VCC ≤  5.5V (E-temp. range)
Output valid from clock
(Note 2) TAA —
—900
3500 ns 4.5V ≤  VCC ≤  5.5V
2.5V ≤  VCC ≤  5.5V (E-temp. range)
Bus free time: Time the bus must be 
free before a new transmission can 
start
TBUF 1300
4700 —
—ns 4.5V ≤  VCC ≤  5.5V
2.5V ≤  VCC ≤  5.5V (E-temp. range)
Output fall time from VIH
minimum to VIL maximum TOF 20+0.1CB
—250
250 ns 4.5V ≤  VCC ≤  5.5V (Note 1)
2.5V ≤  VCC ≤  5.5V (E-temp. range) (Note 1)
Input filter spike suppression
(SDA and SCL pins) TSP —50 ns (Notes 1 and 3)
Write cycle time (byte or page) TWC —5ms
—
Endurance 1M —cycles 25°C, VCC = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 
300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined Tsp and Vhys specifications are due to new Schmitt trigger inputs which provide improved noise spike 
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please 
consult the Total Endurance Model which can be obtained on Microchip’s website:  www.microchip.com.

24LC04B/08B

DS21051H-page 4  2001 Microchip Technology Inc.

FIGURE 1-2: BUS TIMING DATA

2.0 FUNCTIONAL DESCRIPTION

The 24LC04B/08B supports a bi-directional 2-wire bus

and data transmission protocol. A device that sends

data onto the bu s is defi ned as trans mitter and if receiv-

ing dat a, as rece iver. The bus ha s to be co ntroll ed by a

master device which generates the serial clock (SCL),

controls the bus access an d genera tes the START and

STOP conditions, while the 24LC04B/08B works as

slave. Both master and slave can operate as transmit-

ter or rece iver, but th e ma ster d evic e dete rmines which

mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

•Data transfer may be initiated only when the bus

is not busy

•During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in th e dat a line whi le the clock line i s HI GH w ill be

interpreted as a START or STOP condition

Accordingly, the following bus conditions have been

defined (Figure 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL ) is HIGH determine s a ST ART c ondition. All

commands must be preceded by a START condition.

3.3 S top Data Transfer (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operati ons must be ende d with a STOP c ondition.

3.4 Data Valid (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited, although only the last 16

will be stored when doing a write operation. When an

overwri te d oes oc c ur it will repl ac e da t a i n a firs t in firs t

out fashion.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The mast er device mus t ge nera te a n ext ra c lock

pulse which is associated with this acknowledge bit.

The device that acknowledges, has to pull down the

SDA line d uring th e ackn owledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an acknowledge bit on the last

byte that has been clocked out of the slave. In this

case, the slave must leave the data line HIGH to enable

the master to generate the STOP condition.

TSU:STA

TLOW

THIGH

THD:DAT TSU:DAT TSU:STO

THD:STA TBUF

TAA

TSP

THD:STA

SCL

SDA

OUT

Note: The 24LC04B/08B does not generate

any acknowledge bits if an internal pro-

gramming cycle is in progress.

 2001 Microchip Technology Inc. DS21051H-page 5

24LC04B/08B

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A) (B) (D) (D) (A)(C)

START

CONDITION ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

24LC04B/08B

DS21051H-page 6  2001 Microchip Technology Inc.

3.6 Device Addressing

A control byte is the first byte received following the

start conditi on from t he mast er devic e. The c ontrol by te

consists of a 4-bit control code, for the 24LC04B/08B

this is set as 1010 binary for read and write operations .

The next three bits of the control byte are the block

select bits (B2, B1, B0). B2 is a ‘don' t c are ’ fo r bo th th e

24LC04B and 24LC08B; B1 is a ‘don't care’ for the

24LC04B. They are used by the master device to select

which of the two or four 256 word b locks of memory are

to be ac cessed. These bit s are in effec t the mos t signif-

icant bits of the word address.

The last bit of the control byte defines the operation to

be performed. When set to ‘1’, a read operation is

selected and when set to ‘0’, a write operation is

selected. Following the start condition, the 24LC04B/

08B monitors the SDA bus checking the device type

identifier being transmitted. Upon a 1010 code, the

slave device outputs an acknowledge signal on the

SDA line. Depending on the state of the R/W bit, the

24LC04B/08B will select a read or write operation.

FIGURE 3-2: CONTROL BYTE

ALLOCATION

Operation Control

Code Block Select R/W

Read 1010 Block Address 1

Write 1010 Block Address 0

X = ’Don’t care’. B1 is ‘don’t care’ for 24LC0 4B .

1010XB1B0

R/W A

START READ/WRITE

SLAVE ADDRESS

 2001 Microchip Technology Inc. DS21051H-page 7

24LC04B/08B

4.0 WRITE OPERATION

4.1 Byte Write

Following the start condition from the master, the

dev ice code (4 bits), th e block address (3 bits) and the

R/W bit, which is a logic LOW is placed onto the bus by

the master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will fol-

low after it has generated an acknowledge bit during

the nint h clock cycl e. Therefor e, the next byt e transmit-

ted by the master is the word address and will be writ-

ten into the address pointer of the 24LC04B/08B. After

receiving another acknowledge signal from the

24LC0 4B/0 8B, the ma ster device will tran sm it the da ta

word to be wr itten into the addressed mem ory locatio n.

The 24LC04B/08B acknowledges again and the mas-

ter gen erates a s top conditi on. This i nitiates th e internal

write cycle. During this time, the 24LC04B/08B will not

generate acknowledge signals (Figure 4-1).

4.2 Page Write

The write control byte, word address and the first data

byte are transmitted to the 24LC04B/08B in the same

way as in a b yte w ri te. But instead of g ene rati ng a stop

condition, the master transmits up to 16 data bytes to

the 24LC04B/08B which are temporarily stored in the

on-chip page buffer and will be written into the memory

after the master has transmitted a stop condition. After

the receipt of each word, the four lower order address

pointer bits are internally incremented by one. The

higher order seven bits of the word address remains

constant. If the master should transmit more than 16

words prior to generating the stop condition, the

address counter will roll over and the previously

receive d dat a will be overwri tten. As w ith the byte w rite

operation, once the stop condition is received an inter-

nal write cycle will begin (Figure 4-2).

FIGURE 4-1: BYTE WRITE

FIGURE 4-2: PAGE WRITE

Note: Page write operations are limited to

writing bytes within a single physical

page, regardless of the number of

bytes actually being written. Physical

page boundaries start at addresses

that are integer multiples of the page

buffer size (or ‘page size’) and end at

addresses that are integer multiples of

[page size - 1]. If a page write com-

mand atte mp ts to write a cro ss a phy si -

cal page boundary , the result is that the

data wraps around to the beginning of

the current page (overwriting data pre-

viously stored there), instead of being

written to the next page as might be

expected. It is therefore necessary for

the application software to prevent

page write operations that would

attempt to cross a page boundary.

S P

BUS ACTIVITY

MASTER

SDA LINE

BUS ACT IV IT Y

CONTROL

BYTE WORD

ADDRESS DATA

S P

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE WORD

ADDRESS (n) DATA (n) DATA (n + 15) S

DATA (n + 1)

24LC04B/08B

DS21051H-page 8  2001 Microchip Technology Inc.

5.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the master, the device ini-

tiates the internally timed write cycle. ACK polling can

be initi ated immediately . This involves the master send-

ing a start condition followed by the control byte for a

write co mmand (R/W = 0). If the device is still bu sy with

the write cycle, then no ACK will be returned. If the

cycle is complete, then the device will return the ACK

and the master can then proceed with the next read or

write command. See Figure 5-1 for flow diagram.

FIGURE 5-1: ACKNOWLEDGE

POLLING FLOW

6.0 WRITE PROTECTION

The 24LC 04B/ 08B ca n be us ed as a seria l ROM whe n

the WP pin is connected to VCC. Prog rammi ng wil l be

inhibit ed and the en tire m emory will b e write-p rote cted.

7.0 READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to a ’1’. There are three basic type s

of read operations: current address read, random read

and sequential read.

7.1 Current Address Read

The 24LC04B/08B contains an address counter that

maintains the address of the last word accessed, inter-

nally incremented by one. Therefore, if the previous

access (either a read or write operation) was to

address n, the next current address read operation

would access dat a from add ress n + 1. Upo n receip t of

the slav e add res s wi th R /W bi t s et to ’1’, the 24LC04 B/

08B issues an acknowledge and transmits the 8-bit

data word. The master will not acknowledge the trans-

fer but does generate a stop condition and the

24LC04B/08B discontinues transmission (Figure 7-1).

7.2 Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this typ e of re ad o peration, first the word ad dres s m us t

be set. This is done b y sending the word address to the

24LC04B/08B as part of a write operation. After the

word addr ess is sent, the ma ster generates a st art con-

dition following the acknowledge. This terminates the

write operation, but not before the internal address

pointer is set. Then the master issues the control byte

again but with the R/W bit set to a ’1’. The 24LC04B/

08B will then issue an acknowledge and transmits the

8-bit data word. The master will not acknowledge the

transfer but does generate a stop condition and the

24LC04B/08B discontinues transmission (Figure 7-2).

7.3 Sequentia l Read

Sequential reads are initiated in the same way as a ran-

dom read exc ept that af ter the 24L C04B/ 08B transm it s

the first data byte, the master issues an acknowledge

as opposed to a stop condition in a random read. This

directs the 24LC04B/08B to transmit the next sequen-

tially add res sed 8-bit word (Figu re 7-3).

To provide sequential reads the 24LC04B/08B contains

an internal address pointer which is incremented by

one at the completion of each operation. This address

pointer all ows the entire memor y contents to be seriall y

read during one operation.

7.4 Noise Protection

The 24LC04B/08B employs a VCC threshold detector

circuit which disables the internal erase/write logic if the

VCC is below 1.5 vo lt s at nomin al condition s.

The SCL and SDA input s have Schmitt trig ger and filter

circuits which suppress noise spikes to assure proper

device operation even on a noisy bus.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Devic e

Acknowledge

(ACK = 0)?

Operation

Yes

 2001 Microchip Technology Inc. DS21051H-page 9

24LC04B/08B

FIGURE 7-1: CURRENT ADDRESS READ

FIGURE 7-2: RANDOM READ

FIGURE 7-3: SEQUENTIAL READ

8.0 PIN DESCRIPTIONS

8.1 SDA Serial Address/Data Input/

Output

This is a bi-directional pin used to transfer addresses

and data into and data out of the device. It is an open

drain te rminal. Therefore, the SDA bus requires a pull-

up resistor to VCC (typical 10KΩ for 10 0 kHz, 2 KΩ for

400 kHz).

For normal data transfer, SDA is allowed to change

only dur i ng SCL LO W. Cha nge s du r i ng SC L HI GH ar e

reserved for indicating the START and STOP condi-

tions.

8.2 SCL Serial Clock

This i nput is u sed t o sy nchron ize the d ata trans fer fro m

and to the device.

8.3 WP

This pin must be connected to either VSS or VCC.

If tied to VSS, normal memory operation is enabled

(read/wri te the ent ire memory ).

If tied to VCC, WRITE operations are inhibited. The

entire m emory will be write -protect ed. R ead operati ons

are not affected.

This feature allows the user to use the 24LC04B/08B

as a serial ROM when WP is enabled (tied to VCC).

8.4 A0, A1, A2

These pins are not used by the 24LC04B/08B. They

may be left floating or tied to either VSS or VCC.

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE DATA (n)

S P

BUS ACT I VITY

MASTER

SDA LINE

BUS ACT I VITY

CONTROL

BYTE

WORD

ADDRESS (n) CONTROL

BYTE

TDATA (n)

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA (n) DATA (n + 1) DATA (n + 2) DATA (n + X)

24LC04B/08B

DS21051H-page 10  2001 Microchip Technology Inc.

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

XXXXXXXX

XXXXXNNN

YYWW

8-Lead PDIP (300 mil) Example

24LC04B

XXXXXNNN

8-Lead SOIC (150 mil) Example

Legend: XX...X Customer specific information*

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Note: In the even t the full Microc hip par t numbe r cannot b e marke d on one l ine, it w ill

be carried over to the next line thus limiting the number of available characters

for cust omer speci fic informati on.

*Standard PICmicro device marking consists of Microchip part number, year code, week code and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

XXXXXXXX

XXXXYYWW

NNN

24LC04B

XXXX0025

8-Lead TSSOP Example

XXXX

XYWW

NNN

0025

4L04

IYWW

NNN

8-Lead MSOP Example

XXXXX

YWWNNN

4L4BI

YWWNNN

 2001 Microchip Technology Inc. DS21051H-page 11

24LC04B/08B

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

Units INCHES* MILLIMETERS

Dime nsion Limits MIN NOM MAX MIN NOM MAX

Number of Pins n88

Pitch p.100 2.54

Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32

Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68

Base to Seating Plane A1 .015 0.38

Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26

Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60

Overall Length D .360 .373 .385 9.14 9.46 9.78

Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43

Lead Thickness c.008 .012 .015 0.20 0.29 0.38

Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78

Lower Lead Width B .014 .018 .022 0.36 0.46 0.56

Overall Row S pacing §eB .310 .370 .430 7.87 9.40 10.92

Mold Draft Angle Top α51015 51015

Mold Draft Angle Bottom β51015 51015

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

JEDEC Equivalent: MS-001

Drawing No. C04-018

.010” (0.254mm) per side.

§ Significant Characteristic

24LC04B/08B

DS21051H-page 12  2001 Microchip Technology Inc.

8-Lead Plastic Small Outline (SN) –Narrow, 150 mil (SOIC)

Foot A ngle f048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008

Lead Thickness

0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Pa ckag e Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004

Standoff §1.551.421.32.061.056.052A2Molded Packag e Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050

Pitch 88

Numb er of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units

45×

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equiva lent : MS- 012

Drawing No. C04-057

§ Significant Characteristic

 2001 Microchip Technology Inc. DS21051H-page 13

24LC04B/08B

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

10501050

Mold Draft Angle Bottom 10501050

Mold Draft Angle Top 0.300.250.19.012.010.007BLead Width 0.200.150.09.008.006.004

Lead Thickness

0.700.600.50.028.024.020LFoot Length 3.103.002.90.122.118.114DMolded Package Length 4.504.404.30.177.173.169E1Mold ed Pa ckag e Width 6.506.386.25.256.251.246EOverall Width 0.150.100.05.006.004.002

Standoff §0.950.900.85.037.035.033A2Mold ed Packag e Thick ness 1.10.043AOverall Height 0.65.026

Pitch 88

Number of Pins MAXNOMMINMAXNOMMINDimension Limi ts MILLIMETERS*INCHESUnits

Foot A ngle f048048

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.005” (0.127mm) per side.

JEDEC Equivalent: MO-153

Drawing No. C04-086

§ Significant Characteristic

24LC04B/08B

DS21051H-page 14  2001 Microchip Technology Inc.

8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not

.037.035FFootprint (Reference)

exceed .010" (0.254mm) per side.

Notes:

Drawing No. C04-111

*Cont ro l l ing Paramet er

Mold Draft Angle Top

Mold Draft Angle Bottom

Foot Angle

Lead Width

Lead Thickness

.004

.010

0.006

.012

(F)

Di mensio n Limits

Overall Height

Molded Package Thickness

Molded Package Width

Overal l Len gt h

Foot Length

Standoff §

Overall Width

Num ber of Pi ns

Pitch A

.016

.114

.114 .022

.118

.002

.030

.193

.034

MIN

Units

.026

NOM 8

INCHES

1.000.950.90.039

0.15

0.30

.008

.016

60.10

0.25

0.20

0.40

MILLIMETERS*

0.65

0.86

3.00

0.55

4.90

.044

.122

.028

.122

.038

.006

0.40

2.90

0.05

0.76

MINMAX NOM

1.18

0.70

3.10

0.15

0.97

MAX

Bn 1

§ Significant Characteristic

.184 .200 4.67 .5.08

 2001 Microchip Technology Inc. DS21051H-page 15

24LC04B/08B

ON-LINE SUPPORT

Microchip provides on-line support on the Microchip

World Wide Web (WWW) site.

The web site is used b y Micr ochip as a me ans to mak e

files and information easily available to customers. To

view t he site, the user must have acce ss to the In ternet

and a web browser, such as Netscape® or Microsoft®

Explorer. Files are also available for FTP download

from our FTP site.

Connecting to the Microchip Internet Web Site

The Microchip web site is available by using your

fa vorite Internet browser to attach to:

www.microchip.com

The file transfer site is available by using an FTP ser-

vice to connect to:

ftp://ftp.microchip.com

The web site and file transfer site provide a variety of

services. Users may download files for the latest

Development Tools, Data Sheets, Application Notes,

User’s Guides, Articles and Sample Programs. A v ari-

ety of Microchip specific business information is also

available, including listings of Microchip sales offices,

distributors and factory representatives. Other data

available for consideration is:

•Latest Microchip Press Releases

•Technical Support Section with Frequently Asked

Questions

•Design Tips

•Device Errata

•Job Postin gs

•Microchip Consultant Program Member Listing

•Links to other useful web sites related to

Microchip Products

•Confere nces for prod ucts, Dev elopment Systems,

technical information and more

•Listing of seminars and events

Systems Information and Upgrade Hot Line

The Systems Information and Upgrade Line provides

system users a listing of the latest versions of all of

Microchip's development systems software products.

Plus, this line provides information on how customers

can receive any currently available upgrade kits.The

Hot Line Numbers are:

1-800-755-2345 for U.S. and most of Canada, and

1-480-792-7302 for the rest of the world.

24LC04B/08B

DS21051H-page 16  2001 Microchip Technology Inc.

READER RESPONSE

It is ou r intentio n t o p rov ide you wi th the bes t document ati on possible to en su re s uc cess ful us e of y our Micr ochip prod-

uct. If you w ish to pro vide your comm ents on org aniza tion, c lar ity, s ubjec t matter, and ways in whi ch ou r doc umenta tion

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-7578.

Please list the following information, and use this outline to provide us with your comments about this Data Sheet.

To: Technical Publications Manager

RE: Reader Response Total Pages Sent

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Num ber:

Questions:

FAX: (______) _________ - _________

DS21051H

24LC04B/08B

1. What are the be st fe atures of t his document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this data sheet easy to follow? If not, why?

4. What additions to the data sheet do you think would enhance the structure and subject?

5. What deleti ons fr om the data sheet co uld be made without aff ecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

8. How would you improve our software, systems, and silicon products?

 2001 Microchip Technology Inc. DS21051H-page 17

24LC04B/08B

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Sales and Support

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device: 24LC04B: VDD range 1.8V to 5.5V

24LC04BT: (Tape and Reel)

24LC08B: VDD range 2.5V to 5.5V

24LC08BT: (Tape and Reel)

Temperature

Range: -= 0°C to+70°C

I=-40°C to+85°C

E= -40°C to+125°C

Package: P = Plastic DIP (300 mil body), 8-lead

SN = Plastic SOIC (150 mil body),

8-lead

ST = Plastic TSSOP (4.4mm body),

8-lead

MS = MSOP, 8-le ad

Examples:

a) 24LC04B–I/P Industrial Temp,

PDIP package, normal VDD limits.

b) 24LC08B/SN Commercial Temp.,

SOIC package, normal VDD limits.

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences

and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of

the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

24LC04B/08B

DS21051H-page 18  2001 Microchip Technology Inc.

NOTES:

 2001 Microchip Technology Inc. DS21051H-page 19

24LC04B/08B

Technology Incorporated, USA. Information contained

in this publication regard ing device ap plications and the

like is intended through suggestion only and may be

superse ded by updates . No repr esent ati on or warrant y

is given and no liabil ity is assume d by Microchip

Technology Incorporated with respect to the accuracy

or use of such information, or infringement of paten ts or

other intellectual property rights arising from such use

or otherwise. Use of Microchip’s products as critical

components in life support systems is not authorized

except with express written approval by Microchip. No

licenses are conveyed, implicitly or otherwise, under

any int ell ectual pro per ty righ ts. The Mi croch ip log o and

name are registered trademarks of Microchip

Technology Inc. in the U.S.A. and other countries. All

rights rese rve d. Al l ot her t r ade ma rks m enti one d h erei n

are the property of their respective companies. No

licenses are conveyed, implicitly or otherwise, under

any intellectual property rights.”

Trademarks

The Microchip name, logo, PIC, PICmicro,

PICMASTER, PICSTART, PRO MATE, KEELOQ,

SEEVAL, MPLAB and The Embedd ed Control

Solutions Company are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and

other countries.

Total Endurance, ICSP, In-Circuit Serial Programming,

FilterLab, MXDEV, microID, FlexROM, fuzzyLAB,

MPASM, MPLINK, MPLIB, PICDEM, ICEPIC,

Migratable Memory, FanSense, ECONOMONITOR,

Select Mode and microPort are trademarks of

Microchip Technology Incorporated in the U.S.A.

Serializ ed Q ui ck Term Programm in g (SQ TP) is a

service mark of Microchip Technology Incorporated in

the U.S.A.

All other trademarks mentioned herein are property of

their respec tiv e com p a ni es.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and T empe, Arizona in July 1999. The

Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro® 8- bi t MC Us , KEELOQ® code hopping

devices, Serial EEPROMs and microperipheral

products. In addition, Microchip’s quality

system for the design and manufacture of

development systems is ISO 9001 certified.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by

update s. It i s your respo nsibilit y to en sure t hat you r app licatio n mee ts with y our sp ecifica tions. N o re presen tation or warra nty is given and n o liability is

assumed by M icroc hip Techno log y Incor porate d with respe ct t o the accuracy or u se of such infor mation, or infrin gemen t of patents or other in tellectua l

property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with

express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec-

tual p roperty rights. The M icrochip logo an d name are reg istered tradema rks of Microchip Technolo gy Inc. in the U.S.A . and other countries. All rights

reserved. All other trademarks mentioned herein are the property of their respective companies.

DS21051H-page 20  2001 Microchip Technology Inc.

AMERICAS

Corporate Office

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ASIA/PACIFIC (continued)

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01/30/01

WORLDWIDE SALES AND SERVICE