3-Axis, 1g/2g/4g/8g Digital Accelerometer ADXL350 Data Sheet FEATURES GENERAL DESCRIPTION Excellent zero-g bias accuracy and stability with minimum/maximum specifications Ultralow power: as low as 45 A in measurement mode and 0.1 A in standby mode at VS = 2.5 V (typical) Power consumption scales automatically with bandwidth User-selectable resolution Fixed 10-bit resolution Full resolution, where resolution increases with g range, up to 13-bit resolution at 8 g (maintains 2 mg/LSB scale factor in all g ranges) Embedded, 32-level FIFO buffer minimizes host processor load Tap/double tap detection and free-fall detection Activity/inactivity monitoring Supply voltage range: 2.0 V to 3.6 V I/O voltage range: 1.7 V to VS SPI (3- and 4-wire) and I2C digital interfaces Flexible interrupt modes mappable to either interrupt pin Measurement ranges selectable via serial command Bandwidth selectable via serial command Wide temperature range (-40C to +85C) 10,000 g shock survival Pb-free/RoHS compliant Small and thin: 4 mm x 3 mm x 1.2 mm cavity LGA package The high performance ADXL350 is a small, thin, low power, 3-axis accelerometer with high resolution (13-bit) and selectable measurement ranges up to 8 g. The ADXL350 offers industryleading noise and temperature performance for application robustness with minimal calibration. Digital output data is formatted as 16-bit twos complement and is accessible through either a SPI (3- or 4-wire) or I2C digital interface. The ADXL350 is well suited for high performance portable applications. It measures the static acceleration of gravity in tiltsensing applications, as well as dynamic acceleration resulting from motion or shock. Its high resolution (2 mg/LSB) enables measurement of inclination changes of less than 1.0. Several special sensing functions are provided. Activity and inactivity sensing detect the presence or lack of motion and if the acceleration on any axis exceeds a user-set level. Tap sensing detects single and double taps. Free-fall sensing detects if the device is falling. These functions can be mapped to one of two interrupt output pins. Low power modes enable intelligent motion-based power management with threshold sensing and active acceleration measurement at extremely low power dissipation. The ADXL350 is supplied in a small, thin, 3 mm x 4 mm x 1.2 mm, 16-lead cavity laminate package. APPLICATIONS Portable consumer devices High performance medical and industrial applications FUNCTIONAL BLOCK DIAGRAM VS ADXL350 VDD I/O POWER MANAGEMENT ADC 3-AXIS SENSOR DIGITAL FILTER CONTROL AND INTERRUPT LOGIC 32 LEVEL FIFO SERIAL I/O INT1 INT2 SDA/SDI/SDIO SDO/ALT ADDRESS SCL/SCLK CS GND 10271-001 SENSE ELECTRONICS Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com ADXL350 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interrupts ..................................................................................... 21 Applications ....................................................................................... 1 FIFO ............................................................................................. 21 General Description ......................................................................... 1 Self-Test ....................................................................................... 22 Functional Block Diagram .............................................................. 1 Register Map ................................................................................... 23 Revision History ............................................................................... 2 Register Definitions ................................................................... 24 Specifications..................................................................................... 3 Applications Information .............................................................. 28 Absolute Maximum Ratings ............................................................ 4 Power Supply Decoupling ......................................................... 28 Thermal Resistance ...................................................................... 4 Mechanical Considerations for Mounting .............................. 28 Package Information .................................................................... 4 Tap Detection .............................................................................. 28 ESD Caution .................................................................................. 4 Threshold .................................................................................... 29 Pin Configuration and Function Descriptions ............................. 5 Link Mode ................................................................................... 29 Typical Performance Characteristics ............................................. 6 Sleep Mode vs. Low Power Mode............................................. 29 Theory of Operation ...................................................................... 14 Offset Calibration ....................................................................... 29 Power Sequencing ...................................................................... 14 Using Self-Test ............................................................................ 30 Power Savings.............................................................................. 15 Axes of Acceleration Sensitivity ............................................... 32 Serial Communications ................................................................. 16 Layout and Design Recommendations ................................... 33 SPI ................................................................................................. 16 Outline Dimensions ....................................................................... 34 I2C ................................................................................................. 19 Ordering Guide .......................................................................... 34 REVISION HISTORY 9/12--Revision 0: Initial Version Rev. 0 | Page 2 of 36 Data Sheet ADXL350 SPECIFICATIONS TA = 25C, VS = 2.5 V, VDD I/O = 2.5 V, acceleration = 0 g, and CIO = 0.1 F, unless otherwise noted. All minimum and maximum specifications are guaranteed. Typical specifications are not guaranteed. Table 1. Parameter SENSOR INPUT Measurement Range Nonlinearity Inter-Axis Alignment Error Cross-Axis Sensitivity 1 OUTPUT RESOLUTION All g Ranges 1 g Range 2 g Range 4 g Range 8 g Range SENSITIVITY Sensitivity at XOUT, YOUT, ZOUT Scale Factor at XOUT, YOUT, ZOUT Sensitivity at XOUT, YOUT, ZOUT Scale Factor at XOUT, YOUT, ZOUT Sensitivity at XOUT, YOUT, ZOUT Scale Factor at XOUT, YOUT, ZOUT Sensitivity at XOUT, YOUT, ZOUT Scale Factor at XOUT, YOUT, ZOUT Sensitivity at XOUT, YOUT, ZOUT Scale Factor at XOUT, YOUT, ZOUT Sensitivity Change Due to Temperature 0 g BIAS LEVEL 0 g Output for XOUT, YOUT 0 g Output for ZOUT 0 g Offset vs. Temperature (X Axis and Y Axis) 2 0 g Offset vs. Temperature (Z Axis)2 NOISE PERFORMANCE Noise (X-Axis and Y-Axis) Noise (Z-Axis) OUTPUT DATA RATE AND BANDWIDTH Measurement Rate 3 SELF-TEST 4 Output Change in X-Axis Output Change in Y-Axis Output Change in Z-Axis POWER SUPPLY Operating Voltage Range (VS) Interface Voltage Range (VDD I/O) Supply Current Standby Mode Leakage Current Turn-On Time 5 OPERATING TEMPERATURE RANGE Test Conditions Each axis User selectable Percentage of full scale Each axis 10-bit resolution Full resolution Full resolution Full resolution Full resolution Each axis Any g-range, full resolution Any g-range, full resolution 1 g, 10-bit resolution 1 g, 10-bit resolution 2 g, 10-bit resolution 2 g, 10-bit resolution 4 g, 10-bit resolution 4 g, 10-bit resolution 8 g, 10-bit resolution 8 g, 10-bit resolution Min Typ Max Unit 1, 2, 4, 8 0.5 0.1 3 g % Degrees % 10 10 11 12 13 Bits Bits Bits Bits Bits 473.6 1.80 473.6 1.80 236.8 3.61 118.4 7.22 59.2 14.45 512 1.95 512 1.95 256 3.91 128 7.81 64 15.63 0.01 550.4 2.10 550.4 2.10 275.2 4.21 137.6 8.40 68.8 16.80 LSB/g mg/LSB LSB/g mg/LSB LSB/g mg/LSB LSB/g mg/LSB LSB/g mg/LSB %/C -150 -250 -0.31 -0.49 50 75 0.17 0.24 +150 +250 +0.31 +0.49 Mg Mg mg/C mg/C Each axis 100 Hz data rate, full resolution 100 Hz data rate, full resolution User selectable 1.1 1.7 LSB rms LSB rms 6.25 3200 Hz 0.2 -2.1 0.3 2.1 -0.2 3.4 g g g 3.6 VS V V A A A ms o C Data rate 100 Hz, 2.0 V VS 3.6 V 2.0 1.7 Data rate > 100 Hz Data rate < 10 Hz Data rate = 3200 Hz -40 1 2.5 1.8 166 45 0.1 1.4 2 +85 Cross-axis sensitivity is defined as coupling between any two axes. Offset vs. temperature minimum/maximum specifications are guaranteed by characterization and represent a mean 3 distribution. 3 Bandwidth is half the output data rate. 4 Self-test change is defined as the output (g) when the SELF_TEST bit = 1 (in the DATA_FORMAT register) minus the output (g) when the SELF_TEST bit = 0 (in the DATA_FORMAT register). Due to device filtering, the output reaches its final value after 4 x when enabling or disabling self-test, where = 1/(data rate). 5 Turn-on and wake-up times are determined by the user-defined bandwidth. At a 100 Hz data rate, the turn-on and wake-up times are each approximately 11.1 ms. For other data rates, the turn-on and wake-up times are each approximately + 1.1 in milliseconds, where = 1/(data rate). 2 Rev. 0 | Page 3 of 36 ADXL350 Data Sheet ABSOLUTE MAXIMUM RATINGS PACKAGE INFORMATION Parameter Acceleration Any Axis, Unpowered Any Axis, Powered VS VDD I/O Digital Pins Rating All Other Pins Output Short-Circuit Duration (Any Pin to Ground) Temperature Range Powered Storage 10,000 g 10,000 g -0.3 V to +3.6 V -0.3 V to +3.6 V -0.3 V to VDD I/O + 0.3 V or 3.6 V, whichever is less -0.3 V to +3.6 V Indefinite The information in Figure 2 and Table 4 provide details about the package branding for the ADXL350. For a complete listing of product availability, see the Ordering Guide section. XL350B ywVVVV Figure 2. Product Information on Package (Top View) Table 4. Package Branding Information -40C to +105C -40C to +105C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Branding Key XL350B yw VVVV ESD CAUTION THERMAL RESISTANCE Table 3. Package Characteristics Package Type 16-Terminal LGA_CAV JA 150C/W 10271-202 Table 2. JC 85C/W Device Weight 20 mg Rev. 0 | Page 4 of 36 Field Description Part identifier for ADXL350 Date code Factory lot code Data Sheet ADXL350 VDD I/O GND RESERVED VS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 16 15 14 1 NC 2 13 ADXL350 GND 12 RESERVED 11 INT1 10 RESERVED +X 5 NC = NO INTERNAL CONNECTION +Z 9 6 7 8 TOP VIEW (Not to Scale) INT2 10271-002 NC +Y CS 4 SDO/ ALT ADDRESS SCL/SCLK SDA/SDI/SDIO NC 3 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic VDD I/O NC NC SCL/SCLK NC SDA/SDI/SDIO SDO/ALT ADDRESS CS INT2 RESERVED INT1 RESERVED GND VS RESERVED GND Description Digital Interface Supply Voltage. Not Internally Connected. Not Internally Connected. Serial Communications Clock. Not Internally Connected. Serial Data (I2C)/Serial Data Input (SPI 4-Wire)/Serial Data Input and Output (SPI 3-Wire). Serial Data Output/Alternate I2C Address Select. Chip Select. Interrupt 2 Output. Reserved. This pin must be connected to ground or left open. Interrupt 1 Output. Reserved. This pin must be connected to ground. This pin must be connected to ground. Supply Voltage. Reserved. This pin must be connected to VS or left open. This pin must be connected to ground. Rev. 0 | Page 5 of 36 ADXL350 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS N = 460 for all typical performance characteristics plots, unless otherwise noted. 30 20 10 0 -100 -80 -60 -40 -20 0 20 40 60 80 100 ZERO g OFFSET (mg) 20 10 0 -100 -40 -20 0 20 40 60 80 100 Figure 7. X-Axis Zero g Offset at 25C, VS = 3.0 V 30 30 20 10 -80 -60 -40 -20 0 20 40 60 80 100 ZERO g OFFSET (mg) 10 0 -100 10271-104 0 -100 20 -80 -60 -40 -20 0 20 40 60 80 100 ZERO g OFFSET (mg) 10271-107 PERCENT OF POPULATION (%) 40 Figure 8. Y-Axis Zero g Offset at 25C, VS = 3.0 V Figure 5. Y-Axis Zero g Offset at 25C, VS = 2.5 V 30 PERCENT OF POPULATION (%) 30 20 10 0 20 10 Figure 9. Z-Axis Zero g Offset at 25C, VS = 3.0 V Figure 6. Z-Axis Zero g Offset at 25C, VS = 2.5 V Rev. 0 | Page 6 of 36 70 10271-108 ZERO g OFFSET (mg) 50 30 10 -10 -30 -50 -70 -90 -110 -130 -150 -170 -190 -230 95 10271-105 ZERO g OFFSET (mg) 115 75 55 35 15 -5 -25 -45 -65 -85 -105 -125 0 -210 PERCENT OF POPULATION (%) -60 ZERO g OFFSET (mg) Figure 4. X-Axis Zero g Offset at 25C, VS = 2.5 V PERCENT OF POPULATION (%) -80 10271-106 PERCENT OF POPULATION (%) 30 10271-103 PERCENT OF POPULATION (%) 40 Data Sheet ADXL350 100 30 75 N = 16 VS = VDD I/O = 2.5V 50 20 OUTPUT (mg) PERCENT OF POPULATION (%) -40C TO +25C +25C TO +85C 10 25 0 -25 -50 0.5 ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/C) -100 -60 10271-109 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 -20 0 20 40 60 80 100 TEMPERATURE (C) Figure 13. X-Axis Zero g Offset vs. Temperature-- 16 Parts Soldered to PCB, VS = 2.5 V Figure 10. X-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V 100 30 -40C TO +25C +25C TO +85C 75 N = 16 VS = VDD I/O = 2.5V 50 20 OUTPUT (mg) PERCENT OF POPULATION (%) -40 10271-112 -75 25 0 -25 10 -50 -100 -60 0.5 ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/C) -20 0 20 40 60 80 100 TEMPERATURE (C) Figure 14. Y-Axis Zero g Offset vs. Temperature-- 16 Parts Soldered to PCB, VS = 2.5 V Figure 11. Y-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V 150 20 -40C TO +25C +25C TO +85C 100 N = 16 VS = VDD I/O = 2.5V 15 50 OUTPUT (mg) 10 0 -50 5 -100 -150 -60 ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/C) 0.5 10271-111 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 -40 -20 0 20 40 60 80 TEMPERATURE (C) Figure 12. Z-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V Figure 15. Z-Axis Zero g Offset vs. Temperature-- 16 Parts Soldered to PCB, VS = 2.5 V Rev. 0 | Page 7 of 36 100 10271-114 PERCENT OF POPULATION (%) -40 10271-110 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 10271-113 -75 ADXL350 Data Sheet 100 30 75 N = 16 VS = VDD I/O = 3.0V 50 20 OUTPUT (mg) PERCENT OF POPULATION (%) -40C TO +25C +25C TO +85C 25 0 -25 10 -50 0.6 ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/C) -100 -60 10271-115 0.5 0.4 0.3 0.2 0 0.1 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 0 -20 0 20 40 60 80 100 TEMPERATURE (C) Figure 16. X-Axis Zero g Offset Temperature Coefficient, VS = 3.0 V Figure 19. X-Axis Zero g Offset vs. Temperature-- 16 Parts Soldered to PCB, VS = 3.0 V 100 30 -40C TO +25C +25C TO +85C 75 N = 16 VS = VDD I/O = 3.0V 50 20 OUTPUT (mg) PERCENT OF POPULATION (%) -40 10271-118 -75 25 0 -25 10 -50 -100 -60 ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/C) 10271-116 0.6 0.5 0.4 0.3 0.2 0 0.1 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 0 -20 0 20 40 60 80 100 TEMPERATURE (C) Figure 20. Y-Axis Zero g Offset vs. Temperature-- 16 Parts Soldered to PCB, VS = 3.0 V Figure 17. Y-Axis Zero g Offset Temperature Coefficient, VS = 3.0 V 150 20 N = 16 VS = VDD I/O = 3.0V -40C TO +25C +25C TO +85C 100 15 50 OUTPUT (mg) PERCENT OF POPULATION (%) -40 10271-119 -75 10 0 -50 5 -150 -60 10271-117 ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/C) 0.6 0.5 0.4 0.3 0.2 0 0.1 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 0 -40 -20 0 20 40 60 TEMPERATURE (C) Figure 21. Z-Axis Zero g Offset vs. Temperature-- 16 Parts Soldered to PCB, VS = 3.0 V Figure 18. Z-Axis Zero g Offset Temperature Coefficient, VS = 3.0 V Rev. 0 | Page 8 of 36 80 10271-120 -100 Data Sheet ADXL350 80 60 PERCENT OF POPULATION (%) 40 20 0 60 40 20 0.010 SENSITIVITY TEMPERATURE COEFFICIENT (%/C) Figure 22. X-Axis Sensitivity at 25C, VS = 2.5 V, Full Resolution 10271-124 0.008 0.006 0.004 0.002 0 -0.002 -0.004 -0.006 -0.010 550 SENSITIVITY (LSB/g) 10721-121 545 540 535 530 525 520 515 510 505 500 495 490 485 480 475 470 0 -0.008 PERCENT OF POPULATION (%) -40C TO +25C +25C TO +85C Figure 25. X-Axis Sensitivity Temperature Coefficient, VS = 2.5 V 80 60 PERCENT OF POPULATION (%) 40 20 10721-122 40 20 0.010 SENSITIVITY TEMPERATURE COEFFICIENT (%/C) Figure 23. Y-Axis Sensitivity at 25C, VS = 2.5 V, Full Resolution 10271-125 0.008 0.006 0.004 0.002 0 -0.002 -0.004 -0.006 SENSITIVITY (LSB/g) -0.008 0 550 545 540 535 530 525 520 515 510 505 500 495 490 485 480 475 470 0 60 -0.010 PERCENT OF POPULATION (%) -40C TO +25C +25C TO +85C Figure 26. Y-Axis Sensitivity Temperature Coefficient, VS = 2.5 V 40 60 PERCENT OF POPULATION (%) 40 20 30 20 10 0.010 SENSITIVITY TEMPERATURE COEFFICIENT (%/C) Figure 27. Z-Axis Sensitivity Temperature Coefficient, VS = 2.5 V Figure 24. Z-Axis Sensitivity at 25C, VS = 2.5 V, Full Resolution Rev. 0 | Page 9 of 36 10271-126 0.008 0.006 0.004 0.002 0 -0.002 -0.004 -0.006 -0.010 10721-123 550 545 540 535 530 525 520 515 510 505 500 495 490 485 480 475 SENSITIVITY (LSB/g) -0.008 0 0 470 PERCENT OF POPULATION (%) -40C TO +25C +25C TO +85C ADXL350 Data Sheet 80 40 PERCENT OF POPULATION (%) 30 20 10 60 40 20 0.010 10271-130 0.008 0.006 0.004 0.002 0 -0.002 SENSITIVITY TEMPERATURE COEFFICIENT (%/C) Figure 28. X-Axis Sensitivity, VS = 3.0 V, Full Resolution Figure 31. X-Axis Sensitivity Temperature Coefficient, VS = 3.0 V 70 60 -40C TO +25C +25C TO +85C PERCENT OF POPULATION (%) 60 PERCENT OF POPULATION (%) -0.004 -0.010 575 10721-127 570 565 560 555 550 545 540 535 530 525 520 515 510 505 500 495 SENSITIVITY (LSB/g) -0.006 0 0 -0.008 PERCENT OF POPULATION (%) -40C TO +25C +25C TO +85C 40 20 50 40 30 20 10 0.010 SENSITIVITY TEMPERATURE COEFFICIENT (%/C) 10271-131 0.008 0.006 0.004 0.002 0 -0.002 -0.004 -0.006 -0.010 10721-128 575 570 565 560 555 550 545 540 535 530 525 520 515 510 505 500 495 SENSITIVITY (LSB/g) -0.008 0 0 Figure 32. Y-Axis Sensitivity Temperature Coefficient, VS = 3.0 V Figure 29. Y-Axis Sensitivity, VS = 3.0 V, Full Resolution 50 60 PERCENT OF POPULATION (%) 40 20 40 30 20 10 0.010 SENSITIVITY TEMPERATURE COEFFICIENT (%/C) Figure 30. Z-Axis Sensitivity, VS = 3.0 V, Full Resolution Figure 33. Z-Axis Sensitivity Temperature Coefficient, VS = 3.0 V Rev. 0 | Page 10 of 36 10271-132 0.008 0.006 0.004 0.002 0 -0.002 -0.004 -0.006 -0.010 10721-129 550 545 540 535 530 525 520 515 510 505 500 495 490 485 480 475 SENSITIVITY (LSB/g) -0.008 0 0 470 PERCENT OF POPULATION (%) -40C TO +25C +25C TO +85C Data Sheet ADXL350 540 545 540 525 535 520 515 510 505 530 525 520 515 500 510 495 505 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) 500 -60 40 60 80 100 545 535 SENSITIVITY (LSB/g) 540 525 520 515 510 505 530 525 520 515 500 510 495 505 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) 500 -60 10271-134 SENSITIVITY (LSB/g) 20 550 N = 16 VS = VDD I/O = 2.5V 530 N = 16 VS = VDD I/O = 3.0V -40 -20 0 20 40 60 80 100 TEMPERATURE (C) Figure 35. Y-Axis Sensitivity vs. Temperature-- 16 Parts Soldered to PCB, VS = 2.5 V, Full Resolution Figure 38. Y-Axis Sensitivity vs. Temperature-- 16 Parts Soldered to PCB, VS = 3.0 V, Full Resolution 540 535 0 Figure 37. X-Axis Sensitivity vs. Temperature-- 16 Parts Soldered to PCB, VS = 3.0 V, Full Resolution 540 490 -60 -20 TEMPERATURE (C) Figure 34. X-Axis Sensitivity vs. Temperature-- 16 Parts Soldered to PCB, VS = 2.5 V, Full Resolution 535 -40 10271-137 490 -60 N = 16 VS = VDD I/O = 3.0V 10271-136 SENSITIVITY (LSB/g) 530 10271-133 SENSITIVITY (LSB/g) 535 550 N = 16 VS = VDD I/O = 2.5V 550 N = 16 VS = VDD I/O = 2.5V 545 540 530 SENSITIVITY (LSB/g) 525 520 515 510 505 530 525 520 515 510 505 500 500 490 -60 495 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 490 -60 N = 16 VS = VDD I/O = 3.0V -40 -20 0 20 40 60 80 TEMPERATURE (C) Figure 39. Z-Axis Sensitivity vs. Temperature-- 16 Parts Soldered to PCB, VS = 3.0 V, Full Resolution Figure 36. Z-Axis Sensitivity vs. Temperature-- 16 Parts Soldered to PCB, VS = 2.5 V, Full Resolution Rev. 0 | Page 11 of 36 100 10271-138 495 10271-135 SENSITIVITY (LSB/g) 535 ADXL350 Data Sheet 80 40 20 0 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 OUTPUT (g) 60 40 20 0 0.80 0.95 1.00 1.05 1.10 1.15 1.20 Figure 43. X-Axis Self-Test Response at 25C, VS = 3.0 V 60 40 20 0 -1.00 -0.95 -0.90 -0.85 -0.80 -0.75 -0.70 -0.65 -0.60 OUTPUT (g) 80 60 40 20 0 -1.20 -1.15 -1.10 -1.05 -1.00 -0.95 -0.90 -0.85 -0.80 OUTPUT (g) 10271-143 PERCENT OF POPULATION (%) 100 10271-140 Figure 44. Y-Axis Self-Test Response at 25C, VS = 3.0 V Figure 41. Y-Axis Self-Test Response at 25C, VS = 2.5 V 50 PERCENT OF POPULATION (%) 60 40 20 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 OUTPUT (g) 30 20 10 0 10271-141 0 40 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 OUTPUT (g) Figure 45. Z-Axis Self-Test Response at 25C, VS = 3.0 V Figure 42. Z-Axis Self-Test Response at 25C, VS = 2.5 V Rev. 0 | Page 12 of 36 10271-144 PERCENTAGE OF POPULATION (%) 0.90 OUTPUT (g) Figure 40. X-Axis Self-Test Response at 25C, VS = 2.5 V PERCENT OF POPULATION (%) 0.85 10271-142 PERCENT OF POPULATION (%) 60 10271-139 PERCENT OF POPULATION (%) 80 Data Sheet ADXL350 220 200 40 CURRENT (A) PERCENT OF POPULATION (%) 60 20 180 160 140 100 110 120 130 140 150 160 170 180 CURRENT CONSUMPTION (A) 190 200 100 10271-145 0 2 180 160 120 100 80 60 40 20 10 100 1k 10k OUTPUT DATA RATE (Hz) 10271-146 CURRENT (A) 140 1 4 Figure 48. Supply Current vs. Supply Voltage, VS at 25C, 10 Parts Figure 46. Current Consumption at 25C, 100 Hz Output Data Rate, VS = 2.5 V, 31 Parts 0 3 SUPPLY VOLTAGE (V) Figure 47. Current Consumption vs. Output Data Rate at 25C VS = 2.5 V, 10 Parts Rev. 0 | Page 13 of 36 10271-147 120 ADXL350 Data Sheet THEORY OF OPERATION POWER SEQUENCING The ADXL350 is a complete 3-axis acceleration measurement system with a selectable measurement range of 1 g, 2 g, 4 g, or 8 g. It measures both dynamic acceleration resulting from motion or shock and static acceleration, such as gravity, which allows the device to be used as a tilt sensor. Power can be applied to VS or VDD I/O in any sequence without damaging the ADXL350. All possible power-on modes are summarized in Table 6. The sensor is a polysilicon surface-micromachined structure built on top of a silicon wafer. Polysilicon springs suspend the structure over the surface of the wafer and provide a resistance against acceleration forces. Deflection of the structure is measured using differential capacitors that consist of independent fixed plates and plates attached to the moving mass. Acceleration deflects the beam and unbalances the differential capacitor, resulting in a sensor output whose amplitude is proportional to acceleration. Phase-sensitive demodulation is used to determine the magnitude and polarity of the acceleration. The interface voltage level is set with the interface supply voltage, VDD I/O, which must be present to ensure that the ADXL350 does not create a conflict on the communication bus. For single-supply operation, VDD I/O can be the same as the main supply, VS. In a dual-supply application, however, VDD I/O can differ from VS to accommodate the desired interface voltage, as long as VS is greater than VDD I/O. After VS is applied, the device enters standby mode, where power consumption is minimized and the device waits for VDD I/O to be applied and for the command to enter measurement mode to be received. (This command can be initiated by setting the measure bit in the POWER_CTL register (Address 0x2D).) In addition, any register can be written to or read from to configure the part while the device is in standby mode. It is recommended to configure the device in standby mode and then to enable measurement mode. Clearing the measure bit returns the device to the standby mode. Table 6. Power Sequencing Condition Power Off VS Off VDD I/O Off Bus Disabled On Off Bus Enabled Off On Standby or Measurement On On Description The device is completely off, but there is the potential for a communication bus conflict. The device is on in standby mode, but communication is unavailable and creates a conflict on the communication bus. The duration of this state should be minimized during power-up to prevent a conflict. No functions are available, but the device does not create a conflict on the communication bus. At power-up, the device is in standby mode, awaiting a command to enter measurement mode, and all sensor functions are off. After the device is instructed to enter measurement mode, all sensor functions are available. Rev. 0 | Page 14 of 36 Data Sheet ADXL350 Table 8. Current Consumption vs. Data Rate, Low Power Mode (TA = 25C, VS = 2.5 V, VDD I/O = 1.8 V) POWER SAVINGS Power Modes The ADXL350 automatically modulates its power consumption in proportion to its output data rate, as outlined in Table 7. If additional power savings is desired, a lower power mode is available. In this mode, the internal sampling rate is reduced, allowing for power savings in the 12.5 Hz to 400 Hz data rate range but at the expense of slightly greater noise. To enter lower power mode, set the LOW_POWER bit (Bit 4) in the BW_RATE register (Address 0x2C). The current consumption in low power mode is shown in Table 8 for cases where there is an advantage for using low power mode. The current consumption values shown in Table 7 and Table 8 are for a VS of 2.5 V. Current scales linearly with VS. Table 7. Current Consumption vs. Data Rate (TA = 25C, VS = 2.5 V, VDD I/O = 1.8 V) Output Data Rate (Hz) 3200 1600 800 400 200 100 50 25 12.5 6.25 Bandwidth (Hz) 1600 800 400 200 100 50 25 12.5 6.25 3.125 Rate Code 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 IDD (A) 145 100 145 145 145 145 100 65 55 40 Output Data Rate (Hz) 400 200 100 50 25 12.5 Bandwidth (Hz) 200 100 50 25 12.5 6.25 Rate Code 1100 1011 1010 1001 1000 0111 IDD (A) 100 65 55 50 40 40 Auto Sleep Mode Additional power can be saved if the ADXL350 automatically switches to sleep mode during periods of inactivity. To enable this feature, set the THRESH_INACT register (Address 0x25) and the TIME_INACT register (Address 0x26) each to a value that signifies inactivity (the appropriate value depends on the application), and then set the AUTO_SLEEP bit and the link bit in the POWER_CTL register (Address 0x2D). Current consumption at the sub-8 Hz data rates used in this mode is typically 40 A for a VS of 2.5 V. Standby Mode For even lower power operation, standby mode can be used. In standby mode, current consumption is reduced to 0.1 A (typical). In this mode, no measurements are made. Standby mode is entered by clearing the measure bit (Bit 3) in the POWER_CTL register (Address 0x2D). Placing the device into standby mode preserves the contents of FIFO. Rev. 0 | Page 15 of 36 ADXL350 Data Sheet SERIAL COMMUNICATIONS I2C and SPI digital communications are possible and regardless, the ADXL350 always operates as a slave. I2C mode is enabled if the CS pin is tied high to VDD I/O. The CS pin should always be tied high to VDD I/O or be driven by an external controller because there is no default mode if the CS pin is left unconnected. Not taking this precaution may result in an inability to communicate with the part. In SPI mode, the CS pin is controlled by the bus master. In both SPI and I2C modes of operation, data transmitted from the ADXL350 to the master device should be ignored during writes to the ADXL350. SPI For SPI, either 3- or 4-wire configuration is possible, as shown in the connection diagrams in Figure 49 and Figure 50. Clearing the SPI bit in the DATA_FORMAT register (Address 0x31) selects 4-wire mode, whereas setting the SPI bit selects 3-wire mode. The maximum SPI clock speed is 5 MHz with 100 pF maximum loading, and the timing scheme follows clock polarity (CPOL) = 1 and clock phase (CPHA) = 1. CS is the serial port enable line and is controlled by the SPI master. This line must go low at the start of a transmission and high at the end of a transmission, as shown in Figure 52. SCLK is the serial port clock and is supplied by the SPI master. It is stopped high when CS is high during a period of no transmission. SDI and SDO are the serial data input and output, respectively. Data should be sampled at the rising edge of SCLK. SDIO PROCESSOR ADXL350 ADXL350 D OUT CS D IN/OUT SDIO SDO SCLK D OUT Figure 49. 3-Wire SPI Connection Diagram PROCESSOR CS D OUT SDI D OUT SDO SCLK D IN D OUT PROCESSOR D OUT D IN/OUT SDO SCLK D OUT Figure 51. Recommended SPI Connection Diagram when Using Multiple SPI Devices on a Single Bus 10271-003 ADXL350 ADXL350 The ADXL350 CS pin is used both for initiating SPI transacttions, and for enabling I2C mode. When the ADXL350 is used on an SPI bus with multiple devices, its CS pin is held high while the master communicates with the other devices. There may be conditions where an SPI command transmitted to another device looks like a valid I2C command. In this case, the ADXL350 would interpret this as an attempt to communicate in I2C mode, and could interfere with other bus traffic. Unless bus traffic can be adequately controlled to assure such a condition never occurs, it is recommended to add a logic gate in front of the SDI pin as shown in Figure 51. This OR gate will hold the SDA line high when CS is high to prevent SPI bus traffic at the ADXL350 from appearing as an I2C start command. 10271-151 CS Preventing Bus Traffic Errors 10271-004 ADXL350 ADXL350 To read or write multiple bytes in a single transmission, the multiple-byte bit, located after the R/W bit in the first byte transfer (MB in Figure 52 to Figure 54), must be set. After the register addressing and the first byte of data, each subsequent set of clock pulses (eight clock pulses) causes the ADXL350 to point to the next register for a read or write. This shifting continues until the clock pulses cease and CS is deasserted. To perform reads or writes on different, nonsequential registers, CS must be deasserted between transmissions and the new register must be addressed separately. The timing diagram for 3-wire SPI reads or writes is shown in Figure 54. The 4-wire equivalents for SPI writes and reads are shown in Figure 52 and Figure 53, respectively. Figure 50. 4-Wire SPI Connection Diagram Rev. 0 | Page 16 of 36 Data Sheet ADXL350 Table 9. SPI Digital Input/Output Voltage Parameter Digital Input Low Level Input Voltage (VIL) High Level Input Voltage (VIH) Low Level Input Current (IIL) High Level Input Current (IIH) Digital Output Low Level Output Voltage (VOL) High Level Output Voltage (VOH) Low Level Output Current (IOL) High Level Output Current (IOH) Pin Capacitance 1 Test Conditions Min Limit 1 Max 0.3 x VDD I/O 0.7 x VDD I/O VIN = VDD I/O VIN = 0 V IOL = 10 mA IOH = -4 mA VOL = VOL, max VOH = VOH, min fIN = 1 MHz, VIN = 2.5 V 0.1 -0.1 0.2 x VDD I/O 0.8 x VDD I/O 10 -4 8 Unit V V A A V V mA mA pF Limits based on characterization results, not production tested. Table 10. SPI Timing (TA = 25C, VS = 2.5 V, VDD I/O = 1.8 V) 1 Parameter fSCLK tSCLK tDELAY tQUIET tDIS tCS,DIS tS tM tSDO tSETUP tHOLD Min Limit 2, 3 Max 5 200 10 10 100 250 0.4 x tSCLK 0.4 x tSCLK 95 10 10 Unit MHz ns ns ns ns ns ns ns ns ns ns Description SPI clock frequency 1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40 CS falling edge to SCLK falling edge SCLK rising edge to CS rising edge CS rising edge to SDO disabled CS deassertion between SPI communications SCLK low pulse width (space) SCLK high pulse width (mark) SCLK falling edge to SDO transition SDI valid before SCLK rising edge SDI valid after SCLK rising edge The CS, SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation. Limits are based on characterization results, characterized with fSCLK = 5 MHz and bus load capacitance of 100 pF; not production tested. 3 The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 9. 1 2 Rev. 0 | Page 17 of 36 ADXL350 Data Sheet CS tM tSCLK tDELAY tS tQUIET tCS,DIS SCLK tHOLD W SDI MB A5 tSDO X SDO A0 D7 ADDRESS BITS X D0 tDIS DATA BITS X X X 10271-017 tSETUP X Figure 52. SPI 4-Wire Write CS tM tSCLK tDELAY tS tCS,DIS tQUIET SCLK tHOLD R SDI MB A5 tSDO X SDO A0 X X tDIS ADDRESS BITS X X D7 X D0 10271-018 tSETUP DATA BITS Figure 53. SPI 4-Wire Read CS tDELAY tM tSCLK tS tQUIET tCS,DIS SCLK tSETUP SDIO tSDO tHOLD R/W MB A0 A5 ADDRESS BITS D7 D0 DATA BITS 10271-019 SDO NOTES 1. tSDO IS ONLY PRESENT DURING READS. Figure 54. SPI 3-Wire Read/Write Rev. 0 | Page 18 of 36 Data Sheet ADXL350 I2C If other devices are connected to the same I2C bus, the nominal operating voltage level of these other devices cannot exceed VDD I/O by more than 0.3 V. External pull-up resistors, RP, are necessary for proper I2C operation. Refer to the UM10204 I2C-Bus Specification and User Manual, Rev. 03--19 June 2007, when selecting pull-up resistor values to ensure proper operation. With CS tied high to VDD I/O, the ADXL350 is in I2C mode, requiring a simple 2-wire connection as shown in Figure 55. The ADXL350 conforms to the UM10204 I2C-Bus Specification and User Manual, Rev. 03--19 June 2007, available from NXP Semiconductor. It supports standard (100 kHz) and fast (400 kHz) data transfer modes if the timing parameters given in Table 12 and Figure 57 are met. Table 11. I2C Digital Input/Output Voltage Parameter Digital Input Voltage Low Level Input Voltage (VIL) High Level Input Voltage (VIH) Digital Output Voltage Low Level Output Voltage (VOL) 2 Single-byte or multiple-byte reads/writes are supported, as shown in Figure 56. With the SDO/ALT ADDRESS pin (Pin 7) high, the 7-bit I2C address for the device is 0x1D, followed by the R/W bit. This translates to 0x3A for a write and 0x3B for a read. An alternate I2C address of 0x53 (followed by the R/W bit) can be chosen by grounding the SDO/ALT ADDRESS pin (Pin 7). This translates to 0xA6 for a write and 0xA7 for a read. 1 2 Limit 1 Unit 0.25 x VDD I/O 0.75 x VDD I/O V max V min 0.2 x VDD I/O V max Limits are based on characterization results; not production tested. The limit given is only for VDD I/O < 2 V. When VDD I/O > 2 V, the limit is 0.4 V maximum. VDD I/O ADXL350 ADXL350 RP RP PROCESSOR CS SDA D IN/OUT ALT ADDRESS SCL 10271-008 D OUT Figure 55. I2C Connection Diagram (Address 0x53) SINGLE-BYTE WRITE MASTER START SLAVE ADDRESS + WRITE SLAVE DATA REGISTER ADDRESS ACK ACK STOP ACK MULTIPLE-BYTE WRITE MASTER START SLAVE ADDRESS + WRITE SLAVE DATA REGISTER ADDRESS ACK ACK DATA STOP ACK ACK SINGLE-BYTE READ MASTER START SLAVE ADDRESS + WRITE SLAVE START1 REGISTER ADDRESS ACK SLAVE ADDRESS + READ ACK NACK ACK DATA ACK DATA STOP MULTIPLE-BYTE READ SLAVE SLAVE ADDRESS + WRITE START1 REGISTER ADDRESS ACK ACK SLAVE ADDRESS + READ ACK NOTES 1. THIS START IS EITHER A RESTART OR A STOP FOLLOWED BY A START. 2. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING. Figure 56. I2C Device Addressing Rev. 0 | Page 19 of 36 NACK STOP DATA 10271-009 MASTER START ADXL350 Data Sheet Table 12. I2C Timing (TA = 25C, VS = 2.5 V, VDD I/O = 1.8 V) Parameter fSCL t1 t2 t3 t4 t5 t6 3, 4, 5, 6 t7 t8 t9 t10 Limit 1, 2 Max 400 Min 2.5 0.6 1.3 0.6 350 0 0.6 0.6 1.3 Unit kHz s s s s ns s s s s ns ns ns ns ns pF 0.65 300 0 t11 250 300 20 + 0.1 Cb 7 Cb 400 Description SCL clock frequency SCL cycle time tHIGH, SCL high time tLOW, SCL low time tHD, STA, start/repeated start condition hold time tSU, DAT, data setup time tHD, DAT, data hold time tSU, STA, setup time for repeated start tSU, STO, stop condition setup time tBUF, bus-free time between a stop condition and a start condition tR, rise time of both SCL and SDA when receiving tR, rise time of both SCL and SDA when receiving or transmitting tF, fall time of SDA when receiving tF, fall time of both SCL and SDA when transmitting tF, fall time of both SCL and SDA when transmitting or receiveing Capacitive load for each bus line 1 Limits are based on characterization results, with fSCL = 400 kHz and a 3 mA sink current; not production tested. All values are referred to the VIH and the VIL levels given in Table 11. 3 t6 is the data hold time that is measured from the falling edge of SCL. It applies to data in transmission and acknowledge times. 4 A transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with respect to VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. 5 The maximum t6 value must be met only if the device does not stretch the low period (t3) of the SCL signal. 6 The maximum value for t6 is a function of the clock low time (t3), the clock rise time (t10), and the minimum data setup time (t5(min)). This value is calculated as t6(max) = t3 - t10 - t5(min). 7 Cb is the total capacitance of one bus line in picofarads. 2 SDA t3 t9 t4 t11 t10 SCL t6 t2 t5 t7 REPEATED START CONDITION Figure 57. I2C Timing Diagram Rev. 0 | Page 20 of 36 t1 t8 STOP CONDITION 10271-020 t4 START CONDITION Data Sheet ADXL350 INTERRUPTS The ADXL350 provides two output pins for driving interrupts: INT1 and INT2. Each interrupt function is described in detail in this section. All functions can be used simultaneously, with the only limiting feature being that some functions may need to share interrupt pins. Interrupts are enabled by setting the appropriate bit in the INT_ENABLE register (Address 0x2E) and are mapped to either the INT1 or INT2 pin based on the contents of the INT_MAP register (Address 0x2F). It is recommended that interrupt bits be configured with the interrupts disabled, preventing interrupts from being accidentally triggered during configuration. This can be done by writing a value of 0x00 to the INT_ENABLE register. Clearing interrupts is performed either by reading the data registers (Address 0x32 to Address 0x37) until the interrupt condition is no longer valid for the data-related interrupts or by reading the INT_SOURCE register (Address 0x30) for the remaining interrupts. This section describes the interrupts that can be set in the INT_ENABLE register and monitored in the INT_SOURCE register. DATA_READY The DATA_READY bit is set when new data is available and is cleared when no new data is available. SINGLE_TAP The SINGLE_TAP bit is set when a single acceleration event that is greater than the value in the THRESH_TAP register (Address 0x1D) occurs for less time than is specified in the DUR register (Address 0x21). register (Address 0x29). The FREE_FALL interrupt differs from the inactivity interrupt as follows: all axes always participate, the timer period is much smaller (1.28 sec maximum), and the mode of operation is always dc-coupled. Watermark The watermark bit is set when the number of samples in FIFO equals the value stored in the samples bits (Register FIFO_CTL, Address 0x38). The watermark bit is cleared automatically when FIFO is read, and the content returns to a value below the value stored in the samples bits. Overrun The overrun bit is set when new data replaces unread data. The precise operation of the overrun function depends on the FIFO mode. In bypass mode, the overrun bit is set when new data replaces unread data in the DATAX, DATAY, and DATAZ registers (Address 0x32 to Address 0x37). In all other modes, the overrun bit is set when FIFO is filled. The overrun bit is automatically cleared when the contents of FIFO are read. FIFO The ADXL350 contains patent pending technology for an embedded 32-level FIFO that can be used to minimize host processor burden. This buffer has four modes: bypass, FIFO, stream, and trigger (see Table 20). Each mode is selected by the settings of the FIFO_MODE bits in the FIFO_CTL register (Address 0x38). Bypass Mode In bypass mode, FIFO is not operational and, therefore, remains empty. DOUBLE_TAP The DOUBLE_TAP bit is set when two acceleration events that are greater than the value in the THRESH_TAP register (Address 0x1D) occur for less time than is specified in the DUR register (Address 0x21), with the second tap starting after the time specified by the latent register (Address 0x22) but within the time specified in the window register (Address 0x23). See the Tap Detection section for more details. FIFO Mode The activity bit is set when acceleration greater than the value stored in the THRESH_ACT register (Address 0x24) is experienced. In FIFO mode, data from measurements of the x-, y-, and zaxes are stored in FIFO. When the number of samples in FIFO equals the level specified in the samples bits of the FIFO_CTL register (Address 0x38), the watermark interrupt is set. FIFO continues accumulating samples until it is full (32 samples from measurements of the x-, y-, and z-axes) and then stops collecting data. After FIFO stops collecting data, the device continues to operate; therefore, features such as tap detection can be used after FIFO is full. The watermark interrupt continues to occur until the number of samples in FIFO is less than the value stored in the samples bits of the FIFO_CTL register. Inactivity Stream Mode The inactivity bit is set when acceleration of less than the value stored in the THRESH_INACT register (Address 0x25) is experienced for more time than is specified in the TIME_INACT register (Address 0x26). The maximum value for TIME_INACT is 255 sec. In stream mode, data from measurements of the x-, y-, and z-axes are stored in FIFO. When the number of samples in FIFO equals the level specified in the samples bits of the FIFO_CTL register (Address 0x38), the watermark interrupt is set. FIFO continues accumulating samples and holds the latest 32 samples from measurements of the x-, y-, and z-axes, discarding older data as new data arrives. The watermark interrupt continues occurring until the number of samples in FIFO is less than the value stored in the samples bits of the FIFO_CTL register. Activity FREE_FALL The FREE_FALL bit is set when acceleration of less than the value stored in the THRESH_FF register (Address 0x28) is experienced for more time than is specified in the TIME_FF Rev. 0 | Page 21 of 36 ADXL350 Data Sheet Trigger Mode SELF-TEST In trigger mode, FIFO accumulates samples, holding the latest 32 samples from measurements of the x-, y-, and z-axes. After a trigger event occurs and an interrupt is sent to the INT1 or INT2 pin (determined by the trigger bit in the FIFO_CTL register), FIFO keeps the last n samples (where n is the value specified by the samples bits in the FIFO_CTL register) and then operates in FIFO mode, collecting new samples only when FIFO is not full. The ADXL350 incorporates a self-test feature that effectively tests its mechanical and electronic systems simultaneously. When the self-test function is enabled (via the SELF_TEST bit in the DATA_FORMAT register, Address 0x31), an electrostatic force is exerted on the mechanical sensor. This electrostatic force moves the mechanical sensing element in the same manner as acceleration, and it is additive to the acceleration experienced by the device. This added electrostatic force results in an output change in the x-, y-, and z-axes. Because the electrostatic force is proportional to VS2, the output change varies with VS. A delay of at least 5 s should be present between the trigger event occurring and the start of reading data from the FIFO to allow the FIFO to discard and retain the necessary samples. Additional trigger events cannot be recognized until the trigger mode is reset. To reset the trigger mode, set the device to bypass mode and then set the device back to trigger mode. Note that the FIFO data should be read first because placing the device into bypass mode clears FIFO. Retrieving Data from FIFO The FIFO data is read through the DATAX, DATAY, and DATAZ registers (Address 0x32 to Address 0x37). When the FIFO is in FIFO, stream, or trigger mode, reads to the DATAX, DATAY, and DATAZ registers read data stored in the FIFO. Each time data is read from the FIFO, the oldest x-, y-, and z-axes data are placed into the DATAX, DATAY, and DATAZ registers. If a single-byte read operation is performed, the remaining bytes of data for the current FIFO sample are lost. Therefore, all axes of interest should be read in a burst (or multiple-byte) read operation. To ensure that the FIFO has completely popped (that is, that new data has completely moved into the DATAX, DATAY, and DATAZ registers), there must be at least 5 s between the end of reading the data registers and the start of a new read of the FIFO or a read of the FIFO_STATUS register (Address 0x39). The end of reading a data register is signified by the transition from Register 0x37 to Register 0x38 or by the CS pin going high. For SPI operation at 1.6 MHz or less, the register addressing portion of the transmission is a sufficient delay to ensure that the FIFO has completely popped. For SPI operation greater than 1.6 MHz, it is necessary to deassert the CS pin to ensure a total delay of 5 s; otherwise, the delay will not be sufficient. The total delay necessary for 5 MHz operation is at most 3.4 s. This is not a concern when using I2C mode because the communication rate is low enough to ensure a sufficient delay between FIFO reads. The self-test feature of the ADXL350 also exhibits a bimodal behavior that depends on which phase of the clock self-test is enabled. However, the limits shown in Table 1 and Table 13 to Table 16 are valid for all potential self-test values across the entire allowable voltage range. Use of the self-test feature at data rates less than 100 Hz may yield values outside these limits. Therefore, the part should be placed into a data rate of 100 Hz or greater when using self-test. Table 13. Self-Test Output in LSB for 1 g, 10-bit Resolution or any g-Range, Full Resolution Axis X Y Z Min 100 -1180 150 Max 1180 -100 1850 Unit LSB LSB LSB Table 14. Self-Test Output in LSB for 2 g, 10-Bit Resolution Axis X Y Z Min 50 -590 75 Max 590 -50 925 Unit LSB LSB LSB Table 15. Self-Test Output in LSB for 4 g, 10-Bit Resolution Axis X Y Z Min 25 -295 38 Max 295 -25 463 Unit LSB LSB LSB Table 16. Self-Test Output in LSB for 8 g, 10-Bit Resolution Axis X Y Z Rev. 0 | Page 22 of 36 Min 12 -148 19 Max 148 -12 232 Unit LSB LSB LSB Data Sheet ADXL350 REGISTER MAP Table 17. Register Map Address Hex Dec 0x00 0 0x01 to 0x01C 1 to 28 0x1D 29 0x1E 30 0x1F 31 0x20 32 0x21 33 0x22 34 0x23 35 0x24 36 0x25 37 0x26 38 0x27 39 0x28 40 0x29 41 0x2A 42 0x2B 43 0x2C 44 0x2D 45 0x2E 46 0x2F 47 0x30 48 0x31 49 0x32 50 0x33 51 0x34 52 0x35 53 0x36 54 0x37 55 0x38 56 0x39 57 Name DEVID Reserved THRESH_TAP OFSX OFSY OFSZ DUR Latent Window THRESH_ACT THRESH_INACT TIME_INACT ACT_INACT_CTL THRESH_FF TIME_FF TAP_AXES ACT_TAP_STATUS BW_RATE POWER_CTL INT_ENABLE INT_MAP INT_SOURCE DATA_FORMAT DATAX0 DATAX1 DATAY0 DATAY1 DATAZ0 DATAZ1 FIFO_CTL FIFO_STATUS Type R Reset Value 11100101 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R/W R R R R R R R/W R 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00001010 00000000 00000000 00000000 00000010 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Rev. 0 | Page 23 of 36 Description Device ID. Reserved. Do not access. Tap threshold. X-axis offset. Y-axis offset. Z-axis offset. Tap duration. Tap latency. Tap window. Activity threshold. Inactivity threshold. Inactivity time. Axis enable control for activity and inactivity detection. Free-fall threshold. Free-fall time. Axis control for tap/double tap. Source of tap/double tap. Data rate and power mode control. Power-saving features control. Interrupt enable control. Interrupt mapping control. Source of interrupts. Data format control. X-Axis Data 0. X-Axis Data 1. Y-Axis Data 0. Y-Axis Data 1. Z-Axis Data 0. Z-Axis Data 1. FIFO control. FIFO status. ADXL350 Data Sheet REGISTER DEFINITIONS A value of 0 mg may result in undesirable behavior if the inactivity interrupt is enabled. Register 0x00--DEVID (Read Only) D7 1 D6 1 D5 1 D4 0 D3 0 D2 1 D1 0 D0 1 The DEVID register holds a fixed device ID code of 0xE5 (345 octal). Register 0x1D--THRESH_TAP (Read/Write) The THRESH_TAP register is eight bits and holds the threshold value for tap interrupts. The data format is unsigned, so the magnitude of the tap event is compared with the value in THRESH_TAP. The scale factor is 31.2 mg/LSB (that is, 0xFF = +8 g). A value of 0 may result in undesirable behavior if tap/ double tap interrupts are enabled. Register 0x1E, Register 0x1F, Register 0x20--OFSX, OFSY, OFSZ (Read/Write) Register 0x26--TIME_INACT (Read/Write) The TIME_INACT register is eight bits and contains an unsigned time value representing the amount of time that acceleration must be less than the value in the THRESH_INACT register for inactivity to be declared. The scale factor is 1 sec/LSB. Unlike the other interrupt functions, which use unfiltered data (see the Threshold section), the inactivity function uses filtered output data. At least one output sample must be generated for the inactivity interrupt to be triggered. This results in the function appearing unresponsive if the TIME_INACT register is set to a value less than the time constant of the output data rate. A value of 0 results in an interrupt when the output data is less than the value in the THRESH_INACT register. Register 0x27--ACT_INACT_CTL (Read/Write) The OFSX, OFSY, and OFSZ registers are each eight bits and offer user-set offset adjustments in twos complement format with a scale factor of 7.8 mg/LSB (that is, 0x7F = +1 g). Register 0x21--DUR (Read/Write) The DUR register is eight bits and contains an unsigned time value representing the maximum time that an event must be above the THRESH_TAP threshold to qualify as a tap event. The scale factor is 625 s/LSB. A value of 0 disables the tap/double tap functions. Register 0x22--Latent (Read/Write) The latent register is eight bits and contains an unsigned time value representing the wait time from the detection of a tap event to the start of the time window (defined by the window register) during which a possible second tap event can be detected. The scale factor is 1.25 ms/LSB. A value of 0 disables the double tap function. Register 0x23--Window (Read/Write) The window register is eight bits and contains an unsigned time value representing the amount of time after the expiration of the latency time (determined by the latent register) during which a second valid tap can begin. The scale factor is 1.25 ms/LSB. A value of 0 disables the double tap function. Register 0x24--THRESH_ACT (Read/Write) The THRESH_ACT register is eight bits and holds the threshold value for detecting activity. The data format is unsigned, so the magnitude of the activity event is compared with the value in the THRESH_ACT register. The scale factor is 31.2 mg/LSB. A value of 0 may result in undesirable behavior if the activity interrupt is enabled. Register 0x25--THRESH_INACT (Read/Write) The THRESH_INACT register is eight bits and holds the threshold value for detecting inactivity. The data format is unsigned, so the magnitude of the inactivity event is compared with the value in the THRESH_INACT register. The scale factor is 31.2 mg/LSB. D7 ACT ac/dc D3 INACT ac/dc D6 ACT_X enable D2 INACT_X enable D5 ACT_Y enable D1 INACT_Y enable D4 ACT_Z enable D0 INACT_Z enable ACT AC/DC and INACT AC/DC Bits A setting of 0 selects dc-coupled operation, and a setting of 1 enables ac-coupled operation. In dc-coupled operation, the current acceleration magnitude is compared directly with THRESH_ACT and THRESH_INACT to determine whether activity or inactivity is detected. In ac-coupled operation for activity detection, the acceleration value at the start of activity detection is taken as a reference value. New samples of acceleration are then compared to this reference value, and if the magnitude of the difference exceeds the THRESH_ACT value, the device triggers an activity interrupt. Similarly, in ac-coupled operation for inactivity detection, a reference value is used for comparison and is updated whenever the device exceeds the inactivity threshold. After the reference value is selected, the device compares the magnitude of the difference between the reference value and the current acceleration with THRESH_INACT. If the difference is less than the value in THRESH_INACT for the time in TIME_INACT, the device is considered inactive and the inactivity interrupt is triggered. ACT_x Enable Bits and INACT_x Enable Bits A setting of 1 enables x-, y-, or z-axis participation in detecting activity or inactivity. A setting of 0 excludes the selected axis from participation. If all axes are excluded, the function is disabled. Register 0x28--THRESH_FF (Read/Write) The THRESH_FF register is eight bits and holds the threshold value, in unsigned format, for free-fall detection. The root-sumsquare (RSS) value of all axes is calculated and compared with the value in THRESH_FF to determine if a free-fall event occurred. The scale factor is 31.2 mg/LSB. Note that a value of 0 mg may Rev. 0 | Page 24 of 36 Data Sheet ADXL350 result in undesirable behavior if the free-fall interrupt is enabled. Values between 300 mg and 600 mg (0x0A to 0x13) are recommended. Register 0x29--TIME_FF (Read/Write) The TIME_FF register is eight bits and stores an unsigned time value representing the minimum time that the RSS value of all axes must be less than THRESH_FF to generate a free-fall interrupt. The scale factor is 5 ms/LSB. A value of 0 may result in undesirable behavior if the free-fall interrupt is enabled. Values between 100 ms and 350 ms (0x14 to 0x46) are recommended. Register 0x2A--TAP_AXES (Read/Write) D7 0 D6 0 D5 0 D4 0 D3 Suppress D2 TAP_X enable D1 TAP_Y enable D0 TAP_Z enable Suppress Bit Setting the suppress bit suppresses double tap detection if acceleration greater than the value in THRESH_TAP is present between taps. See the Tap Detection section for more details. TAP_x Enable Bits A setting of 1 in the TAP_X enable, TAP_Y enable, or TAP_Z enable bit enables x-, y-, or z-axis participation in tap detection. A setting of 0 excludes the selected axis from participation in tap detection. Register 0x2B--ACT_TAP_STATUS (Read Only) D7 0 D6 ACT_X source D5 ACT_Y source D4 ACT_Z source D3 Asleep D2 TAP_X source D1 TAP_Y source D0 TAP_Z source ACT_x Source and TAP_x Source Bits These bits indicate the first axis involved in a tap or activity event. A setting of 1 corresponds to involvement in the event, and a setting of 0 corresponds to no involvement. When new data is available, these bits are not cleared but are overwritten by the new data. The ACT_TAP_STATUS register should be read before clearing the interrupt. Disabling an axis from participation clears the corresponding source bit when the next activity or tap/double tap event occurs. Asleep Bit A setting of 1 in the asleep bit indicates that the part is asleep, and a setting of 0 indicates that the part is not asleep. See the Register 0x2D--POWER_CTL (Read/Write) section for more information on autosleep mode. Register 0x2C--BW_RATE (Read/Write) D7 0 D6 0 D5 0 D4 LOW_POWER D3 D2 D1 Rate D0 Rate Bits These bits select the device bandwidth and output data rate (see Table 7 and Table 8 for details). The default value is 0x0A, which translates to a 100 Hz output data rate. An output data rate should be selected that is appropriate for the communication protocol and frequency selected. Selecting too high of an output data rate with a low communication speed results in samples being discarded. Register 0x2D--POWER_CTL (Read/Write) D7 0 D6 0 D5 Link D4 AUTO_SLEEP D3 Measure D2 Sleep D1 D0 Wakeup Link Bit A setting of 1 in the link bit with both the activity and inactivity functions enabled delays the start of the activity function until inactivity is detected. After activity is detected, inactivity detection begins, preventing the detection of activity. This bit serially links the activity and inactivity functions. When this bit is set to 0, the inactivity and activity functions are concurrent. Additional information can be found in the Link Mode section. When clearing the link bit, it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write. This is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the link bit is cleared may have additional noise, especially if the device was asleep when the bit was cleared. AUTO_SLEEP Bit If the link bit is set, a setting of 1 in the AUTO_SLEEP bit sets the ADXL350 to switch to sleep mode when inactivity is detected (that is, when acceleration has been below the THRESH_INACT value for at least the time indicated by TIME_INACT). A setting of 0 disables automatic switching to sleep mode. See the description of the sleep bit in this section for more information. When clearing the AUTO_SLEEP bit, it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write. This is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the AUTO_SLEEP bit is cleared may have additional noise, especially if the device was asleep when the bit was cleared. Measure Bit A setting of 0 in the measure bit places the part into standby mode, and a setting of 1 places the part into measurement mode. The ADXL350 powers up in standby mode with minimum power consumption. LOW_POWER Bit Sleep Bit A setting of 0 in the LOW_POWER bit selects normal operation, and a setting of 1 selects reduced power operation, which has somewhat higher noise (see the Power Modes section for details). A setting of 0 in the sleep bit puts the part into the normal mode of operation, and a setting of 1 places the part into sleep mode. Sleep mode suppresses DATA_READY, stops transmission of data Rev. 0 | Page 25 of 36 ADXL350 Data Sheet to FIFO, and switches the sampling rate to one specified by the wakeup bits. In sleep mode, only the activity function can be used. When clearing the sleep bit, it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write. This is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the sleep bit is cleared may have additional noise, especially if the device was asleep when the bit was cleared. Wakeup Bits These bits control the frequency of readings in sleep mode as described in Table 18. Table 18. Frequency of Readings in Sleep Mode D1 0 0 1 1 Setting D0 0 1 0 1 Frequency (Hz) 8 4 2 1 D6 SINGLE_TAP D2 FREE_FALL D5 DOUBLE_TAP D1 Watermark D5 DOUBLE_TAP D1 Watermark D4 Activity D0 Overrun D4 Activity D0 Overrun Any bits set to 0 in this register send their respective interrupts to the INT1 pin, whereas bits set to 1 send their respective interrupts to the INT2 pin. All selected interrupts for a given pin are OR'ed. Register 0x30--INT_SOURCE (Read Only) D7 DATA_READY D3 Inactivity D6 SINGLE_TAP D2 FREE_FALL D5 DOUBLE_TAP D1 Watermark D6 SPI D5 INT_INVERT D4 0 D3 FULL_RES D2 Justify D1 D0 Range A setting of 1 in the SELF_TEST bit applies a self-test force to the sensor, causing a shift in the output data. A value of 0 disables the self-test force. Register 0x2F--INT_MAP (Read/Write) D6 SINGLE_TAP D2 FREE_FALL D7 SELF_TEST SELF_TEST Bit Setting bits in this register to a value of 1 enables their respective functions to generate interrupts, whereas a value of 0 prevents the functions from generating interrupts. The DATA_READY, watermark, and overrun bits enable only the interrupt output; the functions are always enabled. It is recommended that interrupts be configured before enabling their outputs. D7 DATA_READY D3 Inactivity Register 0x31--DATA_FORMAT (Read/Write) The DATA_FORMAT register controls the presentation of data to Register 0x32 through Register 0x37. All data, except that for the 8 g range, is clipped internally to avoid rollover. Register 0x2E--INT_ENABLE (Read/Write) D7 DATA_READY D3 Inactivity Bits set to 1 in this register indicate that their respective functions have triggered an event, whereas a value of 0 indicates that the corresponding event has not occurred. The DATA_READY, watermark, and overrun bits are always set if the corresponding events occur, regardless of the INT_ENABLE register settings, and are cleared by reading data from the DATAX, DATAY, and DATAZ registers. The DATA_READY and watermark bits may require multiple reads, as indicated in the FIFO mode descriptions in the FIFO section. Other bits, and the corresponding interrupts, are cleared by reading the INT_SOURCE register. D4 Activity D0 Overrun SPI Bit A value of 1 in the SPI bit sets the device to 3-wire SPI mode, and a value of 0 sets the device to 4-wire SPI mode. INT_INVERT Bit A value of 0 in the INT_INVERT bit sets the interrupts to active high, and a value of 1 sets the interrupts to active low. FULL_RES Bit When this bit is set to a value of 1, the device is in full resolution mode, where the output resolution increases with the g range set by the range bits to maintain a 2 mg/LSB scale factor. When the FULL_RES bit is set to 0, the device is in 10-bit mode, and the range bits determine the maximum g range and scale factor. Justify Bit A setting of 1 in the Justify bit selects left (MSB) justified mode, and a setting of 0 selects right justified mode with sign extension. Range Bits These bits set the g range as described in Table 19. Table 19. g Range Setting D1 0 0 1 1 Rev. 0 | Page 26 of 36 Setting D0 0 1 0 1 g Range 1 g 2 g 4 g 8 g Data Sheet ADXL350 Register 0x32 to Register 0x37--DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Samples Bits These six bytes (Register 0x32 to Register 0x37) are eight bits each and hold the output data for each axis. Register 0x32 and Register 0x33 hold the output data for the x-axis, Register 0x34 and Register 0x35 hold the output data for the y-axis, and Register 0x36 and Register 0x37 hold the output data for the z-axis. The output data is twos complement, with DATAx0 as the least significant byte and DATAx1 as the most significant byte, where x represent X, Y, or Z. The DATA_FORMAT register (Address 0x31) controls the format of the data. It is recommended that a multiple-byte read of all registers be performed to prevent a change in data between reads of sequential registers. Register 0x38--FIFO_CTL (Read/Write) D7 D6 FIFO_MODE D5 Trigger D4 D3 D2 D1 Samples D0 FIFO_MODE Bits 1 0 Stream 1 1 Trigger Stream Trigger D7 FIFO_TRIG Table 20. FIFO Modes Mode Bypass FIFO Table 21. Samples Bits Functions FIFO Mode Bypass FIFO Samples Bits Function None. Specifies how many FIFO entries are needed to trigger a watermark interrupt. Specifies how many FIFO entries are needed to trigger a watermark interrupt. Specifies how many FIFO samples are retained in the FIFO buffer before a trigger event. 0x39--FIFO_STATUS (Read Only) These bits set the FIFO mode, as described in Table 20. Setting D7 D6 0 0 0 1 The function of these bits depends on the FIFO mode selected (see Table 21). Entering a value of 0 in the samples bits immediately sets the watermark status bit in the INT_SOURCE register, regardless of which FIFO mode is selected. Undesirable operation may occur if a value of 0 is used for the samples bits when trigger mode is used. Function FIFO is bypassed. FIFO collects up to 32 values and then stops collecting data, collecting new data only when FIFO is not full. FIFO holds the last 32 data values. When FIFO is full, the oldest data is overwritten with newer data. When triggered by the trigger bit, FIFO holds the last data samples before the trigger event and then continues to collect data until full. New data is collected only when FIFO is not full. D6 0 D5 D4 D3 D2 Entries D1 D0 FIFO_TRIG Bit A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring, and a 0 means that a FIFO trigger event has not occurred. Entries Bits These bits report how many data values are stored in FIFO. Access to collect the data from FIFO is provided through the DATAX, DATAY, and DATAZ registers. FIFO reads must be done in burst or multiple-byte mode because each FIFO level is cleared after any read (single- or multiple-byte) of FIFO. FIFO stores a maximum of 32 entries, which equates to a maximum of 33 entries available at any given time because an additional entry is available at the output filter of the device. Trigger Bit A value of 0 in the trigger bit links the trigger event of trigger mode to INT1, and a value of 1 links the trigger event to INT2. Rev. 0 | Page 27 of 36 ADXL350 Data Sheet APPLICATIONS INFORMATION * POWER SUPPLY DECOUPLING A 1 F tantalum capacitor (CS) at VS and a 0.1 F ceramic capacitor (CIO) at VDD I/O placed close to the ADXL350 supply pins is used for testing and is recommended to adequately decouple the accelerometer from noise on the power supply. If additional decoupling is necessary, a resistor or ferrite bead, no larger than 100 , in series with VS may be helpful. Additionally, increasing the bypass capacitance on VS to a 10 F tantalum capacitor in parallel with a 0.1 F ceramic capacitor may also improve noise. * * Care should be taken to ensure that the connection from the ADXL350 ground to the power supply ground has low impedance because noise transmitted through ground has an effect similar to noise transmitted through VS. It is recommended that VS and VDD I/O be separate supplies to minimize digital clocking noise on the VS supply. If this is not possible, additional filtering of the supplies as previously mentioned may be necessary. VS SECOND TAP XHI BW FIRST TAP THRESHOLD (THRESH_TAP) VDD I/O TIME LIMIT FOR TAPS (DUR) CIO VS LATENCY TIME (LATENT) VDD I/O INTERRUPTS ADXL350 SDA/SDI/SDIO INT1 SDO/ALT ADDRESS SCL/SCLK INT2 CS 10271-016 GND 3- OR 4-WIRE SPI OR I2C INTERFACE Figure 58. Application Diagram MECHANICAL CONSIDERATIONS FOR MOUNTING The ADXL350 should be mounted on the PCB in a location close to a hard mounting point of the PCB to the case. Mounting the ADXL350 at an unsupported PCB location, as shown in Figure 59, may result in large, apparent measurement errors due to undampened PCB vibration. Locating the accelerometer near a hard mounting point ensures that any PCB vibration at the accelerometer is above the accelerometer's mechanical sensor resonant frequency and, therefore, effectively invisible to the accelerometer. TIME WINDOW FOR SECOND TAP (WINDOW) SINGLE TAP INTERRUPT DOUBLE TAP INTERRUPT 10271-011 CS INTERRUPT CONTROL The maximum tap duration time is defined by the DUR register (Address 0x21). The tap latency time is defined by the latent register (Address 0x22) and is the waiting period from the end of the first tap until the start of the time window, when a second tap can be detected, which is determined by the value in the window register (Address 0x23). The interval after the latency time (set by the latent register) is defined by the window register. Although a second tap must begin after the latency time has expired, it need not finish before the end of the time defined by the window register. Figure 60. Tap Interrupt Function with Valid Single and Double Taps If only the single tap function is in use, the single tap interrupt is triggered when the acceleration goes below the threshold, as long as DUR has not been exceeded. If both single and double tap functions are in use, the single tap interrupt is triggered when the double tap event has been either validated or invalidated. Several events can occur to invalidate the second tap of a double tap event. First, if the suppress bit in the TAP_AXES register (Address 0x2A) is set, any acceleration spike above the threshold during the latency time (set by the latent register) invalidates the double tap detection, as shown in Figure 61. INVALIDATES DOUBLE TAP IF SUPRESS BIT SET ACCELEROMETERS Figure 59. Incorrectly Placed Accelerometers TIME LIMIT FOR TAPS (DUR) TAP DETECTION The tap interrupt function is capable of detecting either single or double taps. The following parameters are shown in Figure 60 for a valid single and valid double tap event: * The tap detection threshold is defined by the THRESH_TAP register (Address 0x1D). Rev. 0 | Page 28 of 36 LATENCY TIME (LATENT) TIME WINDOW FOR SECOND TAP (WINDOW) Figure 61. Double Tap Event Invalid Due to High g Event When the Suppress Bit Is Set 10271-012 MOUNTING POINTS 10271-010 XHI BW PCB Data Sheet ADXL350 A double tap event can also be invalidated if acceleration above the threshold is detected at the start of the time window for the second tap (set by the window register). This results in an invalid double tap at the start of this window, as shown in Figure 62. Additionally, a double tap event can be invalidated if an acceleration exceeds the time limit for taps (set by the DUR register), resulting in an invalid double tap at the end of the DUR time limit for the second tap event, also shown in Figure 62. XHI BW INVALIDATES DOUBLE TAP AT START OF WINDOW THRESHOLD The lower output data rates are achieved by decimating a common sampling frequency inside the device. The activity, free-fall, and single tap/double tap detection functions are performed using unfiltered data. Since the output data is filtered, the high frequency and high g data that is used to determine activity, free-fall, and single tap/double tap events may not be present if the output of the accelerometer is examined. This may result in trigger events being detected when acceleration does not appear to trigger an event because the unfiltered data may have exceeded a threshold or remained below a threshold for a certain period of time while the filtered output data has not exceeded such a threshold. LINK MODE The function of the link bit is to reduce the number of activity interrupts that the processor must service by setting the device to look for activity only after inactivity. For proper operation of this feature, the processor must still respond to the activity and inactivity interrupts by reading the INT_SOURCE register (Address 0x30) and, therefore, clearing the interrupts. If an activity interrupt is not cleared, the part cannot go into autosleep mode. The asleep bit in the ACT_TAP_STATUS register (Address 0x2B) indicates if the part is asleep. TIME LIMIT FOR TAPS (DUR) TIME LIMIT FOR TAPS (DUR) LATENCY TIME (LATENT) TIME WINDOW FOR SECOND TAP (WINDOW) TIME LIMIT FOR TAPS (DUR) XHI BW SLEEP MODE VS. LOW POWER MODE 10271-013 INVALIDATES DOUBLE TAP AT END OF DUR Figure 62. Tap Interrupt Function with Invalid Double Taps Single taps, double taps, or both can be detected by setting the respective bits in the INT_ENABLE register (Address 0x2E). Control over participation of each of the three axes in single tap/ double tap detection is exerted by setting the appropriate bits in the TAP_AXES register (Address 0x2A). For the double tap function to operate, both the latent and window registers must be set to a nonzero value. Every mechanical system has somewhat different single tap/double tap responses based on the mechanical characteristics of the system. Therefore, some experimentation with values for the latent, window, and THRESH_TAP registers is required. In general, a good starting point is to set the latent register to a value greater than 0x10, to set the window register to a value greater than 0x10, and to set the THRESH_TAP register to be greater than 3 g. Setting a very low value in the latent, window, or THRESH_TAP register may result in an unpredictable response due to the accelerometer picking up echoes of the tap inputs. After a tap interrupt has been received, the first axis to exceed the THRESH_TAP level is reported in the ACT_TAP_STATUS register (Address 0x2B). This register is never cleared, but is overwritten with new data. In applications where a low data rate is sufficient and low power consumption is desired, it is recommended that the low power mode be used in conjunction with the FIFO. The sleep mode, while offering a low data rate and low average current consumption, suppresses the DATA_READY interrupt, preventing the accelerometer from sending an interrupt signal to the host processor when data is ready to be collected. In this application, setting the part into low power mode (by setting the LOW_POWER bit in the BW_RATE register) and enabling the FIFO in FIFO mode to collect a large value of samples reduces the power consumption of the ADXL350 and allows the host processor to go to sleep while the FIFO is filling up. OFFSET CALIBRATION Accelerometers are mechanical structures containing elements that are free to move. These moving parts can be very sensitive to mechanical stresses, much more so than solid-state electronics. The 0 g bias or offset is an important accelerometer metric because it defines the baseline for measuring acceleration. Additional stresses can be applied during assembly of a system containing an accelerometer. These stresses can come from, but are not limited to, component soldering, board stress during mounting, and application of any compounds on or over the component. If calibration is deemed necessary, it is recommended that calibration be performed after system assembly to compensate for these effects. A simple method of calibration is to measure the offset while assuming that the sensitivity of the ADXL350 is as specified in Table 1. The offset can then be automatically accounted for by Rev. 0 | Page 29 of 36 ADXL350 Data Sheet using the built-in offset registers. This results in the data acquired from the DATA registers already compensating for any offset. In a no-turn or single-point calibration scheme, the part is oriented such that one axis, typically the z-axis, is in the 1 g field of gravity and the remaining axes, typically the x-axis and y-axis, are in a 0 g field. The output is then measured by taking the average of a series of samples. The number of samples averaged is a choice of the system designer, but a recommended starting point is 0.1 sec worth of data for data rates of 100 Hz or greater. This corresponds to 10 samples at the 100 Hz data rate. For data rates less than 100 Hz, it is recommended that at least 10 samples be averaged together. These values are stored as X0g, Y0g, and Z+1g for the 0 g measurements on the x-axis and y-axis and the 1 g measurement on the z-axis, respectively. The values measured for X0g and Y0g correspond to the x- and y-axis offset, and compensation is done by subtracting those values from the output of the accelerometer to obtain the actual acceleration. XACTUAL = XMEAS - X0g YACTUAL = YMEAS - Y0g Because the z-axis measurement was done in a +1 g field, a no-turn or single-point calibration scheme assumes an ideal sensitivity, SZ for the z-axis. This is subtracted from Z+1g to attain the z-axis offset, which is then subtracted from future measured values to obtain the actual value: Z0g = Z+1g - SZ ZACTUAL = ZMEAS - Z0g The ADXL350 can automatically compensate the output for offset by using the offset registers (Register 0x1E, Register 0x1F, and Register 0x20). These registers contain an 8-bit, twos complement value that is automatically added to all measured acceleration values, and the result is then placed into the DATA registers. Because the value placed in an offset register is additive, a negative value is placed into the register to eliminate a positive offset and vice versa for a negative offset. The register has a scale factor of 7.8 mg/LSB and is independent of the selected g-range. As an example, assume that the ADXL350 is placed into fullresolution mode with a sensitivity of typically 512 LSB/g. The part is oriented such that the z-axis is in the field of gravity and x-, y-, and z-axis outputs are measured as +10 LSB, -13 LSB, and +9 LSB, respectively. Using the previous equations, X0g is +10 LSB, Y0g is -13 LSB, and Z0g is +9 LSB. Each LSB of output in full-resolution is 1.95 mg or one-quarter of an LSB of the offset register. Because the offset register is additive, the 0 g values are negated and rounded to the nearest LSB of the offset register: XOFFSET = -Round(10/4) = -3 LSB YOFFSET = -Round(-13/4) = 3 LSB registers in the ADXL350, the offset registers do not retain the value written into them when power is removed from the part. Power cycling the ADXL350 returns the offset registers to their default value of 0x00. Because the no-turn or single-point calibration method assumes an ideal sensitivity in the z-axis, any error in the sensitivity results in offset error. To help minimize this error, an additional measurement point can be used with the z-axis in a 0 g field and the 0 g measurement can be used in the ZACTUAL equation. USING SELF-TEST The self-test change is defined as the difference between the acceleration output of an axis with self-test enabled and the acceleration output of the same axis with self-test disabled (see Endnote 4 of Table 1). This definition assumes that the sensor does not move between these two measurements, because if the sensor moves, a non-self-test related shift corrupts the test. Proper configuration of the ADXL350 is also necessary for an accurate self-test measurement. The part should be set with a data rate that is greater than or equal to 100 Hz. This is done by ensuring that a value greater than or equal to 0x0A is written into the rate bits (Bit D3 through Bit D0) in the BW_RATE register (Address 0x2C). It is also recommended that the part be set to 8 g mode to ensure that there is sufficient dynamic range for the entire self-test shift. This is done by setting Bit D3 of the DATA_FORMAT register (Address 0x31) and writing a value of 0x03 to the range bits (Bit D1 and Bit D0) of the DATA_FORMAT register (Address 0x31). This results in a high dynamic range for measurement and a 2 mg/LSB scale factor. After the part is configured for accurate self-test measurement, several samples of x-, y-, and z-axis acceleration data should be retrieved from the sensor and averaged together. The number of samples averaged is a choice of the system designer, but a recommended starting point is 0.1 sec worth of data, which corresponds to 10 samples at 100 Hz data rate. The averaged values should be stored and labeled appropriately as the self-test disabled data, that is, XST_OFF, YST_OFF, and ZST_OFF. Next, self-test should be enabled by setting Bit D7 of the DATA_FORMAT register (Address 0x31). The output needs some time (about four samples) to settle after enabling self-test. After allowing the output to settle, several samples of the x-, y-, and z-axis acceleration data should be taken again and averaged. It is recommended that the same number of samples be taken for this average as was previously taken. These averaged values should again be stored and labeled appropriately as the value with selftest enabled, that is, XST_ON, YST_ON, and ZST_ON. Self-test can then be disabled by clearing Bit D7 of the DATA_FORMAT register (Address 0x31). ZOFFSET = -Round(9/4) = -2 LSB These values are programmed into the OFSX, OFSY, and OFXZ registers, respectively, as 0xFD, 0x03, and 0xFE. As with all Rev. 0 | Page 30 of 36 Data Sheet ADXL350 With the stored values for self-test enabled and disabled, the self-test change is as follows: XST = XST_ON - XST_OFF YST = YST_ON - YST_OFF ZST = ZST_ON - ZST_OFF Because the measured output for each axis is expressed in LSBs, XST, YST, and ZST are also expressed in LSBs. These values can be converted to g's of acceleration by multiplying each value by the 2 mg/LSB scale factor, if configured for full-resolution, 8 g mode. Additionally, Table 13 through Table 16 correspond to the selftest range converted to LSBs and can be compared with the measured self-test change. If the part was placed into fullresolution, 8 g mode, the values listed in Table 13 should be used. Although the fixed 10-bit mode or a range other than 8 g can be used, a different set of values, as indicated in Table 14 through Table 16, would need to be used. Using a range below 8 g may result in insufficient dynamic range and should be considered when selecting the range of operation for measuring self-test. In addition, note that the range in Table 1 and the values in Table 13 through Table 16 take into account all possible supply voltages, VS, and no additional conversion due to VS is necessary. If the self-test change is within the valid range, the test is considered successful. Generally, a part is considered to pass if the minimum magnitude of change is achieved. However, a part that changes by more than the maximum magnitude is not necessarily a failure. Rev. 0 | Page 31 of 36 ADXL350 Data Sheet AXES OF ACCELERATION SENSITIVITY AZ AX 10271-021 AY Figure 63. Axes of Acceleration Sensitivity (Corresponding Output Voltage Increases When Accelerated Along the Sensitive Axis) XOUT = 0g YOUT = 1g ZOUT = 0g GRAVITY XOUT = 1g YOUT = 0g ZOUT = 0g XOUT = 0g YOUT = -1g ZOUT = 0g XOUT = 0g YOUT = 0g ZOUT = 1g Figure 64. Output Response vs. Orientation to Gravity Rev. 0 | Page 32 of 36 XOUT = 0g YOUT = 0g ZOUT = -1g 10271-022 XOUT = -1g YOUT = 0g ZOUT = 0g Data Sheet ADXL350 LAYOUT AND DESIGN RECOMMENDATIONS Figure 65 shows the recommended printed wiring board land pattern. Figure 66 and Table 22 provide details about the recommended soldering profile. 0.3mm 0.8mm 3.35mm 10271-044 0.5mm 3.53mm Figure 65. Recommended Printed Wiring Board Land Pattern (Dimensions shown in millimeters) CRITICAL ZONE TL TO TP tP TP tL TSMAX TSMIN tS RAMP-DOWN PREHEAT 10271-015 TEMPERATURE RAMP-UP TL t25C TO PEAK TIME Figure 66. Recommended Soldering Profile Table 22. Recommended Soldering Profile 1, 2 Profile Feature Average Ramp Rate from Liquid Temperature (TL) to Peak Temperature (TP) Preheat Minimum Temperature (TSMIN) Maximum Temperature (TSMAX) Time from TSMIN to TSMAX (tS) TSMAX to TL Ramp-Up Rate Liquid Temperature (TL) Time Maintained Above TL (tL) Peak Temperature (TP) Time of Actual TP - 5C (tP) Ramp-Down Rate Time 25C to Peak Temperature 1 2 Sn63/Pb37 3C/sec max Condition Pb-Free 3C/sec max 100C 150C 60 sec to 120 sec 3C/sec max 183C 60 sec to 150 sec 240 + 0/-5C 10 sec to 30 sec 6C/sec max 6 minutes max Based on JEDEC Standard J-STD-020D.1. For best results, the soldering profile should be in accordance with the recommendations of the manufacturer of the solder paste used. Rev. 0 | Page 33 of 36 150C 200C 60 sec to 180 sec 3C/sec max 217C 60 sec to 150 sec 260 + 0/-5C 20 sec to 40 sec 6C/sec max 8 minutes max ADXL350 Data Sheet OUTLINE DIMENSIONS 4.10 4.00 3.90 3.40 REF REFERENCE CORNER 0.25 REF 0.50 BSC 0.86 BSC R 0.10 REF 0.22 BSC 3.10 3.00 2.90 0.62 x 0.25 (PINS 1-5, 9-13) 13 14 2.40 REF TOP VIEW 8 6 5 0.13 0.50 REF 0.64 REF 07-13-2012-B 0.25 x 0.35 (PINS 6-8, 14-16) 0.50 BSC 0.25 REF BOTTOM VIEW R 0.18 REF 1.30 1.20 1.10 1 0.10 DIA. (Vent Hole) 9 R 0.60 REF 16 SIDE VIEW 0.24 REF Figure 67. 16-Terminal Chip Array, Small Outline, No Lead Cavity [LGA_CAV] 4.00 mm x 3.00 mm x 1.2 mm Body (CE-16-3) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADXL350BCEZ-RL ADXL350BCEZ-RL7 EVAL-ADXL350Z EVAL-ADXL350Z-M Measurement Range (g) 1, 2, 4, 8 1, 2, 4, 8 Specified Voltage (V) 2.5 2.5 Temperature Range -40C to +85C -40C to +85C EVAL-ADXL350Z-S 1 Z = RoHS Compliant Part. Rev. 0 | Page 34 of 36 Package Description 16-Terminal [LGA_CAV] 16-Terminal [LGA_CAV] Evaluation Board Analog Devices Inertial Sensor Evaluation System, Includes ADXL350 Satellite ADXL350 Satellite, Standalone Package Option CE-16-3 CE-16-3 Data Sheet ADXL350 NOTES Rev. 0 | Page 35 of 36 ADXL350 Data Sheet NOTES (c)2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10271-0-9/12(0) Rev. 0 | Page 36 of 36 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: ADXL350BCEZ-RL ADXL350BCEZ-RL7 EVAL-ADXL350Z-S EVAL-ADXL350Z