DS04-27707-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP for Power Supply Applications (For Secondary Battery)
Li-Ion Battery Protection IC
MB3836
■DESCRIPTION
The MB3836 is a lithium-ion battery protection IC for three cells series lithium-ion batter y pack in a notebook
PC’ s. This IC supports charging at 12.6 V and detects an over-charge, ov er-discharge, and ov er-current to control
charging and discharging.
The IC has a built-in function that mak es the battery rechargeable even when the battery voltage has decreased
to 0 V.
Upon detection of an over-discharge from the lithium-ion battery, the IC outputs a preliminary signal to stop
discharging. This f eature allo ws the notebook PC to sa v e its memory data to hard disk. In addition, the IC allows
the battery to be used up to the over-discharge level of each cell, increasing the operating time.
After detecting an over-discharge, the IC disconnects all of its biases so that its current consumption becomes
0 µA. The IC can theref ore make the battery pac k rechargeable e v en when it has been left for an e xtended period
of time with the output disconnected due to over-discharging.
The batter y can also be set into a quasi-over-discharged state even when the cell voltage is equal to or greater
than the ov er-discharge detection voltage . When the notebook PC is shipped, the IC can prev ent the battery pack
from being discharged and turn off its bias sources, allowing the battery pack to be stored for a long time.
The IC’s remote on/off function can tur n off the output from the detached batter y pack without the need for an
external logic circuit or an y mechanism on the notebook PC. This prevents the output from being short-circuited
by a malfunction and facilitates the handling of the battery pack itself.
The MB3836 is the best IC for protecting the lithium-ion battery pack used for a notebook PC.
■PACKAGE 20-pin plastic SSOP
(FPT-20P-M03)
MB3836
2
■FEATURES
• Power supply voltage range : 6 V to 13.5 V
• High-precision over-charge detection voltage : 4.325 V ± 0.025 V
• Circuit power consumption after detecting over-discharge : 0 µA (Typ)
• Built-in quasi-over-discharge function
• Built-in pre-alarm function before shutting down of over-discharge
• Built-in remoting ON/OFF function
• Built-in over-discharge current detecting function with 2-step delay time : Vth = 300 mV→7 ms (Typ)
: Vth = 600 mV→500 µs (Typ)
• Built-in charge recovery function for 0 V cell
■PIN ASSIGNMENT
(TOP VIEW)
(FPT-20P-M03)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OCV :
COUT :
DOUT :
N.C. :
VS :
VCC :
BATH :
BATM :
BATL :
GND :
: OUTON
: PF
: PDWN
: MSW2
: MSW1
: VMON
: COVT
: COCT
: CUVT
: CPDT
MB3836
3
■PIN DESCRIPTIONS
Pin no. Pin name I/O Description
1 OCV I Over-current state and discharging/charging state detection terminal
2 COUT O Pch MOS control output terminal for charging control switch
3 DOUT O Pch MOS control output terminal for discharging control switch
4N.C.No connection
5 VS O “H” level output terminal for remoting ON function
6VCCPower supply terminal
7 BATH I Battery connection terminal
8 BATM I Battery connection terminal
9 BATL I Battery connection terminal
10 GND GND terminal
11 CPDT Capacitor connection terminal for setting power-down delay time
12 CUVT Capacitor connection terminal for setting PF output delay time
13 COCT Capacitor connection terminal for setting over-current detection time
14 COVT Capacitor connection terminal for setting over-charge detection time
15 VMON O Output terminal of monitoring cell voltage
16 MSW1 I
Switching signal of monitoring cell voltage input terminal
17 MSW2 I
18 PDWN I
Power down signal input terminal
After input “H” level, Latch 3 will be set, DOUT=”H” level, and OCV=”L” level.
At this time, all battery connecting terminal will be released, and all bias will be
set OFF.
19 PF O PF signal output terminal
20 OUTON I Remoting ON signal input terminal
After input “L” level, the bias of over-charge detection block will be set OFF. At
this time, DOUT and COUT value will be equal to “H” level.
MSW1 MSW2 VMON output Cell voltage input block SW
LL Depend on over-charge detection block
L H H cell voltage Off
H L M cell voltage Off
H H L cell voltage Off
MB3836
4
■BLOCK DIAGRAM
−
+
×1
×1
×1
+
−
+
−
+
−
−
−
−
+
6
7
8
9
10 15 16 17 13 14 11 12
18
19
20
5
1
2
3
VCC
bias
ON/OFF
100 kΩ
100 kΩ
100 kΩ
BATH
BATM
BATL
GND VMON MSW1 MSW2 COCT COVT CPDT CUVT
PDWN
PF
OUTON
VS
OCV
COUTDOUT
300 mV
600 mV
4.325 V
(± 0.6%)
2.75 V
(±2%)
Latch2
Latch1
Latch3
bias
ON/OFF 600 Ω
−
+
(7 ms)
(500 µs)
PF output
time (2 s)
[Cell voltage
input block]
[Over-discharge detection,
and power fail circuit block]
[Remote ON
circuit block]
Delay
circuit [Over-current
detection block]
Delay
circuit
(23 ms)
Reset
Decoder
Reference
voltage block
Power down
delay time
(20 s)
[Cell voltage moni-
toring block] [Over-charge
detection block]
Reset
Reset
MB3836
5
■ABSOLUTE MAXIMUM RATINGS
* : When mounted on a 10 cm square double-sided epoxy board.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■RECOMMENDED OPERATING CONDITIONS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Conditions Rating Unit
Min Max
Power supply voltage VCC 20 V
Input voltage VIBATH, OCV, PDWN, OUTON, PF,
MSW1, MSW2 terminals 20 V
Collector output voltage VOCOUT terminal 25 V
Output current IODOUT, COUT terminals (DC) 2mA
Peak output current IODOUT, COUT terminals
Duty = tON / t 2 / Duty mA
Power dissipation PDTa ≤ + 25 °C540 * mW
Operating temperature Ta −30 + 85 °C
Storage temperature Tstg −55 + 125 °C
Parameter Symbol Conditions Value Unit
Min Typ Max
Power supply voltage VCC 6.0 12.6 13.5 V
Input voltage VIOCV, PDWN, OUTON,
MSW1, MSW2 terminals 018 V
Output current IOVS terminal −10 0mA
External OCV terminal resistor ROCV 10 Ω
Capacitor for setting delay time
COVT 220 10000 pF
CUVT 0.001 0.15 µF
CPDT 0.001 1.5 µF
COCT 220 560 pF
MB3836
6
■ELECTRICAL CHARACTERISTICS (VCC = 12.6 V, Ta = + 25 °C)
*: Standard design value
(Continued)
Parameter Sym-
bol Pin
No. Conditions Value Unit
Min Typ Max
Over-charge
detection
block
Detection voltage VTH 2, 7,
8, 9
Ta = + 25 °C,
Each cell voltage 4.300 4.325 4.350 V
Ta = 0 °C to + 70 °C,
Each cell voltage 4.280 4.325 4.370 V
Hysteresis width VH2, 7,
8, 9 0.14 0.20 0.26 V
Input current IIN 7, 8, 9 Each cell voltage = 4.2 V 0.1 0.5 µA
Delay time tD2COVT = 0.01 µF 11.5 23 34.5 ms
Output voltage VOL 2COUT = 1 mA 0.75 1.0 V
Output leakage
current ILEAK 2COUT = 13.5 V 00.5µA
Over-
discharge
detection,
power-fail
circuit block
Detection voltage VTH 7, 8,
9, 19 2.695 2.75 2.805 V
PF output delay time tD1 19 CUVT = 0.15 µF, VCC = 8.5 V 1 2 3 s
PF Min pulse width tP19 CUVT = 0.15 µF, VCC = 8.5 V 7 * ms
Output voltage VOL 19 PF = 1 mA 0.75 1.0 V
Output leakage
current ILEAK 19 PF = 13.5 V 00.5µA
Input threshold
voltage VTH 3, 18 Each cell voltage = 2 V 2.0 3.5 5.0 V
Input current IIN 18 PDWN = 5 V 50 100 µA
Power-down delay
time tD2 3CPDT = 1.5 µF, VCC = 8.5 V 10 20 30 s
Over-
current
detection
block
Detection voltage VTH1 1, 3,
13 Voltage between VCC
terminal and OCV terminal 0.22 0.30 0.38 V
VTH2 1, 3,
13 Voltage between VCC
terminal and OCV terminal 0.45 0.60 0.75 V
Delay time tD1 3COCT = 560 pF
VTH2 > VCC−OCV > VTH1 4710ms
tD2 3COCT = 560 pF
VCC−OCV > VTH2 250 500 750 µs
Output voltage VOL 3DOUT = 1 mA 1.0 V
VOH 3DOUT = −0.4 mA VCC−
0.4 V
Cell voltage
input block
Input current at
over-charge IIN 7, 8, 9 Each cell voltage = 4.5 V 22.5 45 67.5 µA
Short cell detection
voltage VTH 7, 8, 9 Cell voltage without
measuring cell = 3.6 V
at COUT = “L”→“H” 0.6 * V
MB3836
7
(Continued)
(VCC = 12.6 V, Ta = + 25 °C)
* : Standard design value.
Parameter Sym-
bol Pin
No. Conditions Value Unit
Min Typ Max
Remoting
ON circuit
block
Input thereshold
voltage VTLH 1, 2 0.8 1.4 2.0 V
Input current IIN 1OCV = 13.5 V 10 20 µA
Input resistance at
power-down RI1480 600 720 Ω
Input thereshold
voltage VTH 20 0.8 1.4 2.0 V
Input current IIN 20 OUTON = 13.5 V 13 17 µA
Output voltage VOH 5VS = −4 mA VCC−0.5 VCC−0.2 V
Output current IO5VS = 0 V −30 −11 mA
Output leakage
current ILEAK 5VS = 0 V,
Each cell voltage = 2 V −0.5 0 µA
Cell voltage
monitoring
block
Voltage gain AV15 Cell voltage = 2.9 V to 4.2 V 0.98 1.0 1.02 V/V
Input thereshold
voltage VTH 16, 17 0.8 1.4 2.0 V
Input current IIN 16, 17 MSW1 = MSW2 = 5 V 50 100 µA
Output source
current IOH 15 Each cell voltage = 2.9 V,
MON = 1.9 V −350 −180 µA
Output sink
current IOL 15 Each cell voltage = 2.9 V,
MON = 3.9 V 40 80 µA
All device Power supply
current
ICC1 6VCC = 12.6 V, normal state,
OUTON = 5 V 75 110 µA
ICC2 6VCC = 8.7 V, normal state,
OUTON = 5 V 65 95 µA
ICC3 6VCC = 12.6 V,
Cell voltage monitoring state 130 200 µA
ICC4 6VCC = 6 V,
Shutting over-discharge state 0 * µA
MB3836
8
■TYPICAL CHARACTERISTICS
(Continued)
1000
100
10
1
0.1
0.01
0.0001 0.001 0.01 0.1 1 10
Ta = +25 °C
200
180
160
140
120
100
80
60
40
20
01614121086420
4.40
4.38
4.36
4.34
4.32
4.30
4.28
4.26
4.24
4.22
4.20
−40 −20 0 20 40 60 80 100
1000
100
10
1
0.1
100 1000 10000 100000
Ta = +25 °C100
10
1
0.1
0.01
0.0001 0.001 0.01 0.1 1 10
Ta = +25 °C
100
10
1
0.1
100 1000 10000
Ta = +25 °C
tD1
VCC − OCV = 0.5 V
tD2
VCC − OCV = 1 V
Power Supply Current
vs.Power Supply Voltage
Power supply current ICC (µ
µµ
µA)
Power supply voltage VCC (V)
Over-charge Detection Voltage
vs. Ambient Temperature
Ambient temperature Ta (°
°°
°C)
Over-charge detection voltage VTH (V)
Delay Time on Over-charge Detection Block
Delay time tD (ms)
Capacitor for setting delay time COVT (pF)
Delay Time on Over-discharge Detection Block
Delay time of alarm output tD (s)
Capacitor for setting alarm output time CUVT (µ
µµ
µF)
Delay Time on Over-discharge Detection
Block
Power failure permission signal wait time tD (s)
Capacitor for setting power failure permission
signal wait time CPDT (µ
µµ
µF) Capacitor for setting delay time COCT (pF)
Delay Time of Over-current Detection
Delay time tD1, tD2 (ms)
Ta = +25 °CBATH
= VCC
H cell voltage = M cell voltage = L cell voltage
OUTON = 5 V
Cell voltage monitoring
state
MSW1 = OPEN
MSW2 = 5 V
Normal state
MSW1 = MSW2 = OPEN
Typical H cell
OUTON = 5 V
BATH = VCC
BATM = 8.4 V
BATL = 4.2 V
MB3836
9
(Continued)
−40
600
540
500
400
300
200
100
00−20 4020 8060 100
Power Dissipation vs. Ambient Temperature
Characteristics
Ambient temperature Ta (°
°°
°C)
Power dissipation PD (mW)
MB3836
10
■FUNCTIONAL DESCRIPTION
(1) Over-charge Detection Block
When the battery is being charged, the over-charge detection block monitors each cell voltage. If any cell voltage
reaches or exceeds the over-charge detection voltage (4.325 V T yp) as in Figure 1 (see "1. Over-charge detection
block and cell voltage input block " in "■OPERATION TIMING CHART"), the COUT ter minal (pin 2) goes “H”
level, after a delay time (23 ms Typ) managed by the capacitor (COVT) connected between the COVT ter minal
(pin 14) and GND , to turn off the Pch MOS FET for external charge control, thereby stopping charging the battery.
When all the cell vo ltages in the over-charge detected state become the over-charge release voltage (4.125 V
Typ) or less, the COUT terminal (pin 2) goes “L” level to turn on the Pch MOS FET for external charge control.
Ev en when a cell voltage reaches or exceeds the ov er-charge detection voltage as in Figure 2, the cell voltage
does not enter the ov er-charge detected state if it falls below the over-charge detection voltage within the delay
time (23 ms Typ).
(2) Cell Voltage Input Block
If any cell voltage reaches or exceeds the over-charge detection voltage (4.325 V Typ) as in Figures 1 and 2
(see "1. Over-charge detection block and cell voltage input block" in "■OPERATION TIMING CHART"), the
COUT terminal (pin 2) goes high to turn off the Pch MOS FET for external charge control after a delay time
(23 ms Typ) managed by the capacitor (COVT) connected between the COVT terminal (pin 14) and GND. At the
same time, the cell voltage input block switch for the cell exceeding the over-charge detection value is tur ned
on to supply the cell voltage input current to that cell so that high-voltage cells are lowered in voltage.
When the cell voltage in the over-charge detected state becomes the o ver-charge release v oltage ( 4.125 V Typ)
or less, the cell voltage input block switch is turned off.
(3) Over-discharge Detection/Power Fail Circuit Block
When the batter y is being discharged, the over-discharge detection/power fa il circuit block monitors each cell
voltage. If any cell voltage becomes the over-discharge detection voltage (2.75 V Typ) as in Figure 5 (see "3.
Over-discharge detection/power fail circuit" in "■OPERA TION TIMING CHART"), the PF terminal (pin 19) outputs
a “L” le vel PF signal to the notebook PC after a PF output dela y time (2 s Typ) managed b y the capacitor (CUVT)
connected between the CUVT terminal (pin 12) and GND. At the same time, after a power-down delay time
(20 s Typ) managed by the capacitor (CPDT) connected between the CPDT terminal (pin 11) and GND , the DOUT
terminal (pin 3) goes “H” level to turn off the Pch MOS FET for external discharge control, thereby stopping
discharging the battery.
(4) Over-current Detection Block
The over-current detection block monitors the discharge current from the batter y. It detects an over-current if
the potential difference between the VCC and OCV terminals by RON of Pch MOS FET for external charge
control becomes 300 mV or more as in Figure 6 (see "4. Over-current detection block 1" in "■OPERATION
TIMING CHART"). After a delay time (7 ms Typ) managed by the capacitor (COCT) connected between the COCT
ter minal (pin 13) and GND, the DOUT terminal (pin 3) goes “H” level to tur n off the Pch MOS FET for exter nal
discharge control, thereby stopping discharging the battery.
When the discharge current is large, if the potential difference between the VCC and OCV terminals becomes
600 mV or more as in Figure 7 (see "5. Over-current detection block 2" in "■OPERATION TIMING CHART"),
the DOUT ter minal (pin 3) goes “H” level to turn off the Pch MOS FET fo r exter nal discharge control, thereby
stopping discharging the battery, after a power-down delay time (500 µs Typ) managed by the capacitor (COCT)
connected between the COCT terminal (pin 13) and GND.
Note that, if an ov er-current is detected, the VS terminal (pin 5) goes “L” le vel in the same wa y as when the ov er-
discharge detection function works. As discharging is stopped, the OCV terminal (pin 1) goes “L” level to
MB3836
11
completely tur n off the bias source of this IC, so that the batter y pack enters the power-dow n state. To return
from that state, perform recharging operation, or set the OCV terminal (pin 1) to “H” level.
(5) Remote ON Circuit Block
When the batter y pack is detached from the notebook PC, the OUTON ter minal (pin 20) pulled up to the VS
ter minal (pin 5) on the notebook PC side goes “L” level to turn off the bias of the over-current detection block.
At the same time, the COUT terminal (pin 2) and DOUT ter minal (pin 3) go “H” level to turn off the Pch MOS
FET for external charge/discharge control.
Even when the OUTON terminal (pin 20) is “L” level with charging/discharging off, the IC is operating and the
over-discharge detection function is working to protect the battery. If the VS terminal (pin 5) is “H” level, connecting
the battery pack to the main unit makes it readily available.
(6) Cell Voltage Monitor Block
The cell to be monitored can be selected depending on the voltage levels at the MSW1 ter minal (pin 16) and
MSW2 ter minal (pin 17). When the monitor function is operating, the cell voltage input block switch does not
work even when an over-charge is detected.
Condition of monitoring cell voltage
Voltage level at
MSW1 terminal Voltage level at
MSW2 terminal VMON output SW at cell voltage input block
LLDepend on over-charge detection block
L H H cell voltage Off
H L M cell voltage Off
H H L cell voltage Off
MB3836
12
■SETTING DELAY TIME for OVER-CHARGE DETECTION BLOCK
F or ov er-charge detection, y ou can set the dela y time from when charging the capacitor (COVT) connected to the
COVT terminal (pin 14) is started and the COVT terminal voltage increases until the COUT terminal (pin 2)
voltage goes “H” level (with the open-collector output off) with the COVT terminal at the threshold voltage.
Over-charge detection block delay time : tD (s) := 2.3 × COVT (µF)
■SETTING PF OUTPUT DELAY TIME
For over-discharge detection, you can set the delay time from charging the capacitor (CUVT) connected to the
CUVT terminal (pin 12) is started and the CUVT terminal v oltage increases until the PF terminal (pin 19) voltage
goes “L” level with the CUVT terminal at the threshold voltage.
PF output delay time : tD1 (s) := 13.3 × CUVT (µF)
■SETTING POWER-DOWN DELAY TIME
You can set the dela y time from charging the capacitor (CPDT) connected to the CPDT terminal (pin 11) is started
after “L” level output to the PF terminal (pin 19) at over-discharge detection and the CPDT terminal voltage
increases until the DOUT terminal (pin 3) voltage goes high with the CPDT terminal at the threshold voltage.
Power-down delay time : tD2 (s) := 13.3 × CPDT (µF)
After the DOUT ter m inal goes “H” level to stop overdischarging, the OCV terminal (pin 1) goes “L” level to turn
off the entire internal circuitry of the IC so that the circuit current becomes 0 µA. Considering the time constant
based on the notebook PC’s capacitor connected to the OCV ter minal, the discharge time constant of CPDT
ter minal is used to prevent recover y (retur n) and shutdown (power-down) from being repeated in response to
var iations in battery voltage. The capacitor connected to the OCV ter minal on the notebook PC side requires
the restriction expressed below based on the value of the capacitor (CPDT) connected to the CPDT terminal.
OCV terminal external capacitor : COCV (µF) < 1790 × CPDT (µF)
■SETTING DELAY TIME for OVER-CURRENT DETECTION BLOCK
For over-current detection when 0.6 V (Typ) > VCC - OCV > 0.3 V (Typ), you can set the delay time from when
charging the capacitor (COCT) connected to the COCT terminal (pin 13) is started and the COCT terminal voltage
increases until the DOUT terminal (pin 3) voltage goes “H” level with the COUT terminal at the threshold voltage.
Over-current detection block delay time : tD1 (s) := 12.5 × COCT (µF)
For over-current detection when VCC - OCV > 0.6 V (Typ), you can set the delay time from when charging the
capacitor (COCT) connected to the COCT ter minal (pin 13) is started and the COCT terminal voltage increases
until the DOUT terminal (pin 3) voltage goes “H” level with the COCT terminal at the threshold voltage.
Over-current detection block delay time : tD2 (s) := 0.9 × COCT (µF)
MB3836
13
■OPERATION at LOW VOLTAGE
If cell v oltages cause e xtreme imbalance or one or more cells enter the short-circuited state (0.6 V Typ) or less,
the short-circuit cell detection function sets the COUT terminal (pin 2) to “H” le vel (with the open-collector output
off). If the VCC terminal (pin 6) voltage becomes 4.2 V (Typ) or less, however, the shor t-circuit cell detection
function is disabled, the COUT terminal (pin 2) goes “L” le v el, enabling 0 V cell charging, with the OCV terminal
(pin 1) at a voltage of 1.4 V (Typ) or higher.
When VCC is less than 4.2 V, the DOUT ter m inal (pin 3) is fixed at “H” level.
MB3836
14
■OPERATION TIMING CHART
1. Over-charge Detection Block and Cell Voltage Input Block
(1) When cell 3 does not exceed VTH and cells 1 and 2 are lowered in voltage by cell voltage input current
and self-discharging
If any cell voltage reaches or e xceeds the o v er-charge detection voltage (4.325 V Typ), the COUT terminal (pin
2) goes “H” level to turn off the Pch MOS FET for e xternal charge control, after a delay time (23 ms Typ) managed
by the capacitor (C OVT) connected between the COVT terminal (pin 14) and GND, thereby stopping charging the
battery. At this time, the cell v oltage input bloc k s witch is turned on to supply the cell voltage input current to that
cell so that high-voltage cells are lowered in voltage.
When all the cell vo ltages in the over-charge detected state become the over-charge release voltage (4.125 V
Typ) or less, the COVT terminal (pin 14) and COUT terminal (pin 2) go “L” lev el to turn on the Pch MOS FET f or
external charge control.
When any cell v oltage in the ov er-charge detected state becomes the over-charge release voltage (4.125 V Typ)
or less, the cell voltage input block switch is turned off.
tD (23 ms)
VH (0.2 V)
VTH (4.325 V)
(4.125 V)
(6.26 V)
(45 µA)
(0 µA)
(45 µA)
(0 µA)
Cell voltage
Cell voltage input
current
COVT terminal
COUT terminal
Cell 2
Cell 1
Cell 1
Cell 2
Figure 1
MB3836
15
(2) When the voltage is lowered by cell voltage input current and self-discharge after pulsed charge
Even when a cell voltage reaches or exceeds the over-charge detection voltage (4.325 V Typ), the cell voltage
does not enter the over-charge detected state if it fa lls below the over-charge detection voltage (4.325 V Typ)
within the delay time (23 ms Typ) managed by the capacitor (COVT) connected between the COVT terminal (pin
14) and GND.
If a cell v oltage reaches or e xceeds the o v er-charge detection voltage (4.325 V Typ), the COUT terminal (pin 2)
goes “H” level to turn off the Pch MOS FET for exter nal charge control, stopping charging the battery, after a
delay time (23 ms Typ) managed by the capacitor (COVT) connected between the COVT terminal (pin 14) and
GND. At this time, the cell voltage input block switch is turned on to supply the cell voltage input current to that
cell so that high-voltage cells are lowered in voltage.
When all the cell vo ltages in the over-charge detected state become the over-charge release voltage (4.125 V
Typ) or less, the COVT terminal (pin 14) and COUT terminal (pin 2) go “L” lev el to turn on the Pch MOS FET f or
external charge control.
When any cell v oltage in the ov er-charge detected state becomes the over-charge release voltage (4.125 V Typ)
or less, the cell voltage input block switch is turned off.
tD (23 ms)
VH (0.2 V)
VTH (4.325 V)
(4.125 V)
(6.26 V)
(45 µA)
(0 µA)
Cell voltage
Cell voltage
input current
COVT terminal
COUT terminal
Figure 2
MB3836
16
(3) When the OUTON terminal changes "H"→
→→
→"L"→
→→
→"H" after detection of an over-charge
When the OUTON ter minal (pin 20) changes from “H” level to “L” level after detection of an over-charge, the
DOUT terminal (pin 3) goes “H” le vel to turn off the Pch MOS FET for e xternal discharge control, thereby setting
the OCV terminal (pin 1) to “L” level.
When the OUTON terminal (pin 20) changes from “H” level to “L” level after all the cell voltages in the over-
charge detected state become the over-charge release voltage (4.125 V Typ) or less, the COUT ter minal (pin
2) goes “L” level to turn on the Pch MOS FET for external charge control. When the OCV terminal (pin 1) changes
from “L” level to “H” level at this time, the DOUT terminal (pin 3) goes “L” level to turn on the Pch MOS FET for
external discharge control.
VTH (4.325 V)
VH (0.2 V)
(4.125 V)
(45 µA)
(0 µA)
(6.26 V)
(0 V)
(0 V)
tD (23 ms)
Cell voltage
Cell voltage
input current
COVT terminal
COUT terminal
OUTON terminal
DOUT terminal
OCV terminal
VS terminal
Figure 3
MB3836
17
2. Over-charge Detection Block, Discharge Detection Block, and Cell Voltage Input Block
•When battery is discharged after detection of an ov er-charge or re-discharged after detection of an o v er-charge
by recharging
If a cell v oltage reaches or e xceeds the o v er-charge detection voltage (4.325 V Typ), the COUT terminal (pin 2)
goes “H” le vel to turn off the Pch MOS FET f or external charge control after a dela y time (23 ms Typ) managed
by the capacitor (COVT) connected between the CO VT terminal (pin 14) and GND . This stops charging the battery
and puts it into the over-charge detected state.
When a discharge is started in the over-charge detected state , the OCV terminal v oltage is lowered b y the body
diode v oltage of the Pch MOS FET f or e xternal charge control. When the potential diff erence between the VCC
ter minal and OCV ter minal (pin 1) becomes 300 mV or more, the COUT ter minal (pin 2) goes “L” level to tur n
on the Pch MOS FET f or e xternal charge control and the cell voltage input b lock s witch is turned off at the same
time.
An ov er-charge caused b y recharging can be detected e ven with cell v oltages remaining abov e the o ver-charge
release voltage (4.125 V Typ).
tD (23 ms)tD (23 ms)
VH (0.2 V)
VTH (4.325 V)
(4.125 V)
(6.26 V)
(VCC)
VTH (VCC − 0.3 V)
(45 µA)
(0 µA)
Discharge start↓
Cell voltage
input current
COVT terminal
COUT terminal
OCV terminal
↓Charge start ↓Discharge start
Cell voltage
Figure 4
MB3836
18
3. Over-discharge Detection/Power Fail Circuit
•When no “H” level signal is input to the PDWN terminal after over-discharge detection
If any cell voltage becomes the over-discharge detection voltage (2.75 V Typ), the PF terminal (pin 19) outputs
a “L” le vel PF signal to the notebook PC after a PF output dela y time (2 s Typ) managed b y the capacitor (CUVT)
connected between the CUVT terminal (pin 12) and GND. At the same time, after a power-down delay time
(20 s Typ) managed by the capacitor (CPDT) connected between the CPDT terminal (pin 11) and GND , the DOUT
terminal (pin 3) goes “H” level to turn off the Pch MOS FET for external discharge control, thereby stopping
discharging the battery. The VS terminal (pin 5) goes “L” le vel at this time. As discharging is stopped, the OCV
terminal (pin 1) goes “L” level to completely turn off the bias source in the IC.
That is, an o ver-discharge state is detected when a cell voltage does not return to the ov er-discharge detection
voltage (2.75 V Typ) or more within the pow er-down delay time (20 s Typ), an over-discharge state is detected.
When the OCV terminal (pin 1) goes “H” le v el, the DOUT terminal (pin 3) goes “L” le v el to turn on the Pch MOS
FET for external discharge control and the VS terminal (pin 5) goes “H” level. If the cell voltage remains not
exceeding the over-discharge detection voltage (2.75 V Typ) at this time, the PF terminal (pin 19) outputs a “L”
le v el PF signal to the notebook PC again after a PF output delay time (2 s Typ) managed b y the capacitor (CUVT)
connected between the CUVT terminal (pin 12) and GND. If the cell voltage reaches or exceeds the over-
discharge detection v oltage (2.75 V Typ) within the power-do wn dela y time (20 s Typ), ho we v er, the PF terminal
goes “H” level and an over-discharge state is not detected.
MB3836
19
VTH (2.75 V)
(4.9 V)
(4.9 V)
0 V
0 V
0 V
0 V
tD1 (2 s) tD2 (20 s) tD1 (2 s)
Cell voltage
CUVT terminal
PF terminal
CPDT terminal
PDWN terminal
DOUT terminal
OCV terminal
OUTON terminal
Internal bias : Off
VS terminal
Figure 5
↓Charge start
MB3836
20
4. Over-current Detection Block 1
When a discharge current is relatively small as an over-current, if the potential difference between the VCC
ter minal and OCV terminal (pin 1) by RON of the Pch MOS FET for external charge control becomes 300 mV
or more, the capacitor (COCT) connected between the COCT ter minal (pin 13) and GND is charged. No over-
current is detected if the OCV ter minal voltage retur ns to the batter y voltage level within the delay time (7 ms
Typ). If the potential difference between the VCC ter minal and OCV ter minal (pin 1) by RON of the Pch MOS
FET for external charge control becomes 300 mV or more again, an over-current is detected after a delay time
(7 ms Typ) managed by the capacitor (COCT) connected between the COCT ter minal (pin 13) and GND. At this
time, the DOUT terminal (pin 3) goes “H” level to tur n off the Pch MOS FET for exter n al discharge control and
the bias source in the IC is completely turned off as well.
Recharging can be restarted by setting the OCV terminal (pin 1) to “H” le v el to set the DOUT terminal (pin 3) to
“L” level and VS terminal (pin 5) to “H” level, respectively.
(VCC)
VTH (VCC - 0.3 V)
VTH (VCC - 0.6 V)
0 V
(5.8 V)
0 V
tD (7 ms)
OCV terminal
COCT terminal
DOUT terminal
VS terminal
↓Charge start
Internal bias : Off
Figure 6
MB3836
21
5. Over-current Detection Block 2
When a discharge current is relatively large as an over-current, if the potential difference between the VCC
ter minal and OCV terminal (pin 1) by RON of the Pch MOS FET for external charge control becomes 300 mV
or more, the capacitor (COCT) connected between the COCT ter minal (pin 13) and GND is charged. No over-
current is detected if the OCV ter minal voltage retur ns to the batter y voltage level within the delay time (7 ms
Typ). If the potential difference between the VCC ter minal and OCV terminal (pin 1) of the Pch MOS FET for
external charge control becomes 600 mV or more, an over-current is detected after a delay time (500 ms Typ)
managed by the capacitor (COCT) connected between the COCT ter minal (pin 13) and GND. At this time, the
DOUT terminal (pin 3) goes “H” le v el to turn off the Pch MOS FET f or e xternal discharge control, both of the VS
terminal (pin 5) and OCV terminal (pin 1) go “L” level, and the bias source in the IC is completely turned off as well.
Recharging can be restarted by setting the OCV terminal (pin 1) to “H” le v el to set the DOUT terminal (pin 3) to
“L” level and VS terminal (pin 5) to “H” level, respectively.
(VCC)
VTH (VCC - 0.3 V)
VTH (VCC - 0.6 V)
0 V
(5.8 V)
0 V
tD (500 µs)
OCV terminal
COCT terminal
DOUT terminal
VS terminal
↓Charge start
Internal bias : Off
Figure 7
MB3836
22
■TREATMENT WHEN VOLTAGE MONITOR FUNCTION IS NOT USED
When the voltage monitor function is not used, connect the MSW1 ter minal (pin 16) and MSW2 ter minal (pin
17) to GND by taking their shortest ways and leave the VMON terminal (pin 15) open.
■NOTE ON VS TERMINAL
If the battery is charged through the body diode of the internal Pch MOS FET connected to the VS terminal (pin
5), the over-charge protection function cannot be disabled. Be careful not to apply a voltage equal to or higher
than the VCC terminal voltage to the VS terminal.
■NOTE ON ELECTROSTATIC APPLICATION
This IC has a built-in function to set ICC to 0 µA in power-down mode to extend the battery lif e . As a charger is
required to return the IC from power -down mode , use meticulous care not to let it malfunction, f or example , with
applied static electricity. To prevent electrostatic noise from coming into each input pin of the IC, it is advisable
to lower impedance, for example, by adding a capacitor. The capacitor used for this purpose should be placed
as close to the IC as possible.
17
16
15
MSW2
MSW1
VMON “Open”
When voltage monitor function is not used
MB3836
23
■I/O TERMINAL EQUIVALE CIRCUIT
VCC
GND
OCV
COCT
2 kΩ
300 kΩ300 kΩ
6
10
1
3
13
VCC
GND
CUVT
PF CPDT
PDWN
2 kΩ
500 kΩ
2 kΩ
1 kΩ100 kΩ
20 kΩ
12
19 11
18 VCC
GND
COVT
COUT
2 kΩ
1
4
2
GND
BATL
BATM X1
X1
100 kΩ
100 kΩ
BATH X1
100 kΩ
7
8
9
GND
VS
OCV
OUTON
600 Ω50 Ω
VCC
5
2
0
5
700 kΩ
1 MΩ
VCC
GND
VMON
100 kΩ
1
7
15
100 kΩ
100 kΩ
100 kΩ
1
6
MSW2 MSW1
[Over-current detection block]
ESD
protection
element
[Over-discharge detection/power fail circuit block] [Over-charge detection block]
[Cell voltage input block] [Remote ON circuit block]
[Cell voltage monitor block]
MB3836
24
■APPLICATION EXAMPLE
600 mV
−
+
−
+
×1
×1
×1
+
−
+
−
+
−
−
−
−
+
6
7
8
9
10 15 16 17 13 14 11 12
18
19
20
5
1
VCC
bias
ON/OFF
100 kΩ
100 kΩ
BATH
C1
R1
0.1 µF
BATM
BATL
GND VMON
C9
4700 pF
MSW1
C10
4700 pF
MSW2
C11
4700 pF
COCT COVT CPDT CUVT
PDWN
PF
VS
OCV
COUTDOUT
M2M1
300 mV
4.325 V
(±0.6%)
2.75 V
(±2%)
Latch2
Latch1
Latch3
bias
ON/OFF 600 Ω
2
3
C6
560 pF C7
0.01µFC2
1.5 µF
C12
0.22 µF
C5
0.15 µF
R7
100 Ω
R8
R4
1 MΩ
ZD1
18 V
C14
0.1 µFC15
C13
R6
10 Ω
R5
1 MΩ
R14
10 kΩ
R13
10 kΩ
R9
1 MΩ
0.1 µF(+)
(G)
OUTON
100 kΩ
0.1 µF
1 kΩ
1 kΩ
1 kΩ
R2
R3
100 kΩ
(7 ms)
(500 µs)
PF output time
(2 s)
[Cell voltage
input block]
[Over-discharge detection/
power fail circuit block]
[Remote ON
circuit block]
Delay
circuit
Pch MOS FET for discharge control
Delay circuit
(23 ms)
Reset
Decoder
Reference volt-
age source
Power down
delay time
(20 s)
[Over-current de-
tection block]
Pch MOS FET for charge control
H cell
M cell
L cell
Litium-Ion battery
[Over-charge
detection block]
[Cell voltage
monitor block]
Reset
Reset
Note PC side
MB3836
25
■PARTS LIST
Note: VISHAY SILICONIX : VISHAY Intertechnology, Inc.
TOSHIBA : TOSHIBA CORPORATION
■USAGE PRECAUTION
•Printed circuit board ground lines should be set up with consideration for common impedance.
•Take appropriate static electricity measures.
• Containers f or semiconductor materials should have anti-static protection or be made of conductiv e material.
• After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
• Work platforms, tools, and instruments should be properly grounded.
• Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and gr ound.
COMPONENT ITEM SPECIFICATION VENDOR PARTS No.
M1, M2 FET VDS = −30 V VISHAY
SILICONIX Si4425DY
ZD1 Diode 200 mW, 18 V ± 7% TOSHIBA 02CZ18-Y
C1
C2
C5
C6
C7
C9, C10, C11
C12
C13, C14, C15
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
0.1 µF
1.5 µF
0.15 µF
560 pF
0.01 µF
4700 pF
0.22 µF
0.1 µF
25 V (10%)
16 V (10%)
16 V (10%)
50 V (5%)
25 V (10%)
25 V (10%)
25 V (10%)
25 V (10%)
R1, R2, R3
R4, R5, R9
R6
R7
R8
R13, R14
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
1 kΩ
1 MΩ
10 Ω
100 Ω
100 kΩ
10 kΩ
1/16 W, 5%
1/16 W, 5%
1/16 W, 5%
1/16 W, 5%
1/16 W, 5%
1/16 W, 5%
MB3836
26
■ORDERING INFORMATION
Part number Package Remarks
MB3836PFV 20-pin plastic SSOP
(FPT-20P-M03)
MB3836
27
■PACKAGE DIMENSION
20-pin plastic SSOP
(FPT-20P-M03)
Note 1) *1: Resin protrusion. (Each side: +0.15 (.006) Max).
Note 2) *2: These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2003 FUJITSU LIMITED F20012S-c-4-6
6.50±0.10(.256±.004)
4.40±0.10 6.40±0.20
(.252±.008)(.173±.004)
.049 –.004
+.008
–0.10
+0.20
1.25 (Mounting height)
0.10(.004)
0.65(.026) 0.24±0.08
(.009±.003)
1 10
20 11
"A"
0.10±0.10 (Stand off)
0.17±0.03
(.007±.001)
M
0.13(.005)
(.004±.004)
Details of "A" part
0~8˚
(.024±.006)
0.60±0.15
(.020±.008)
0.50±0.20
0.25(.010)
LEAD No.
INDEX
*1
*2
MB3836
FUJITSU LIMITED
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Fujitsu semiconductor device; Fujitsu does not warrant proper
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have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
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Please note that Fujitsu will not be liable against you and/or any
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Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
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If any products described in this document represent goods or
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F0310
FUJITSU LIMITED Printed in Japan
