intel. 8253/8253-5 PROGRAMMABLE INTERVAL TIMER m MCS-85T Compatible 8253-5 m Count Binary or BCD . @ 3 Independent 16-Bit Counters @ Single +5V Supply m DC to 2.6 MHz m Available in EXPRESS Standard Temperature Range w Programmable Counter Modes Extended Temperature Range The Intel 8253 is a programmable counter/timer device designed for use as an intel microcomputer peripher- al. It uses NMOS technology with a single + 5V supply and is packaged in a 24-pin plastic DIP. It is organized as 3 independent 16-bit counters, each with a count rate of up to 2.6 MHz. All modes of operation are software programmable. mo -e--- CLK 0 DATA 0,0, 8 3 ps K 4 K COUNTER Fs Gate STH] opurrer | 0 |____ OUT 0 | ! 0,1 ou v, 7 cc RD --+q _ cLK1 oC] 2 23 1 WA ReaD) COUNTER 0,3 22 AD A Vocie 1 fF cates 0,4 apes __+| . /+ 0uT! p,(}5 20a, 0,46 8253 19a, t o,Q)7 18 DciK 2 cs id Do Ly 8 17D out 2 ctKo] 9 16 LIGATE 2 CLK? OuT o[] 10 1sPcek 1 r>+ CLK CONTROL Gateot} 11 14. GaTe1 word K COUNTER Fe careo GnoC] 12 13 Dour 1 REGISTER =2 }- OUT 2 231306-2 Figure 2. Pin Configuration INTERNAL BUS / || Figure 1. Block Diagram 231306-1 November 1986 3-51 Order Number: 231306-001intel. 8253/8253-5 FUNCTIONAL DESCRIPTION General The 8253 is programmable interval timer/counter specifically designed for use with the Intel Micro- computer systems. Its function is that of a general purpose, multi-timing element that can be treated as an array of |/O ports in the system software. The 8253 solves one of the most common problems in any microcomputer system, the generation of ac- curate time delays under software control. Instead of setting up timing loops in systems software, the pro- grammer configures the 8253 to match his require- ments, initializes one of the counters of the 8253 with the desired quantity, then upon command the 8253 will count out the delay and interrupt the CPU when it has completed its tasks. It is easy to see that the software overhead is minimal and that multiple delays can easily be maintained by assignment of priority levels. Other counter/timer functions that are non-delay in nature but also common to most microcomputers can be implemented with the 8253. * Programmable Rate Generator Event Counter Binary Rate Multiplier Real Time Clock Digital One-Shot Complex Motor Controller Data Bus Buffer The 3-state, bi-directional, 8-bit buffer is used to in- terface the 8253 to the system data bus. Data is transmitted or received by the buffer upon execution of INput or OUTput CPU instructions. The Data Bus Buffer has three basic functions. 1. Programming the MODES of the 8253. 2. Loading the count registers. 3. Reading the count values. Read/Write Logic The Read/Write Logic accepts inputs from the sys- tem bus and in turn generates control signals for overall device operation. !t is enabled or disabled by CS so that no operation can occur to change the function unless the device has been selected by the system logic. 3-52 RD (Read) A low on this input informs the 8253 that the CPU is inputting data in the form of a counters value. WR (Write) A low on this input informs the 8253 that the CPU is outputting data in the form of mode information or loading counters. AO, Al These inputs are normally connected to the address bus. Their function is to select one of the three coun- ters to be operated on and to address the control word register for mode selection. CS (Chip Select) A low on this input enables the 8253. No reading or writing will occur unless the device is selected. The CS input has no effect upon the actual opera- tion of the counters. Led CLK 0 Dy- DATA aS COUNTER L._ GaTEo Do a 20 SUFFER i+ ouT 0 #6 +q aR be CLK t qd READY: COUNTER NATE 21 r+ GATET Ag +] OGG. + ouT t Ay & | | P cLK2 CONTROL worD KK COUNTER 1. Gate 2 REGISTER b+ OUT 2 INTERNAL BUS J es 231306-3 Figure 3. Block Diagram Showing Data Bus Buffer and Read/Write Logic Functions8253/8253-5 intel. CS | RD | WR Aj | Ap 0 1 0 0 | O | Load Counter No. 0 0 1 0 0 1. | Load Counter No. 1 0 1 0 1 0 | Load Counter No. 2 0 1 0 1 1 | Write Mode Word 0 0 1 O | O | Read Counter No. 0 0 0 1 0 1 | Read Counter No. 1 0 0 1 1 0 | Read Counter No. 2 0 0 1 1 1_| No-Operation 3-State 1 x xX X | X | Disable 3-State 0 1 1 X {| X | No-Operation 3-State Control Word Register The Control Word Register is selected when AO, A1 are 11. It then accepts information from the data bus buffer and stores it in a register. The information stored in this register controls the operation MODE of each counter, selection of binary or BCD counting and the loading of each count register. The Control Word Register can only be written into; no read operation of its contents is available. Counter #0, Counter #1, Counter #2 These three functional blocks are identical in opera- tion so only a single counter will be described. Each Counter consists of a single, 16-bit, pre-settable, DOWN counter. The counter can operate in either binary or BCD and its input, gate and output are con- figured by the selection of MODES stored in the Control Word Register. The counters are fully independent and each can have separate MODE configuration and counting op- eration, binary or BCD. Also, there are special fea- tures in the control word that handle the loading of the count value so that software overhead can be minimized for these functions. The reading of the contents of each counter is avail- able to the programmer with simple READ opera- tions for event counting applications and special commands and logic are included in the 8253 so that the contents of each counter can be read on the fly without having to inhibit the clock input. 8253 SYSTEM INTERFACE The 8253 is a component of the Intel Microcom- puter systems and interfaces in the same manner as all other peripherals of the family. It is treated by the systems software as an array of peripheral I/O ports; three are counters and the fourth is a contro! register for MODE programming. Basically, the select inputs AO, A1 connect to the AO, A1 address bus signals of the CPU. The CS can be derived directly from the address bus using a lin- ear select method. Or it can be connected to the output of a decoder, such as an Intel 8205 for larger systems. Fe CLK O ge GATED Dy- DATA nC 8 aus BUFFER ae uags crk 1 we ~___-q | he Gated ~ ouTl CLK 2 GATE2 OurT2 INTERNAL BUS / 231306-4 Figure 4. Block Diagram Showing Control Word Register and Counter Functions ADDRESS BUS (16) 3 A, [Ag | | CONTROL BUS to { 4 DATA BUS (a) 3 | . a, =>) COUNTER 0 L 5 ae out care cix! our cate cix our Gare ciK! MP TT) 7] 231306-5 Figure 5. 8253 System Interfaceintel. 8253/8253-5 OPERATIONAL DESCRIPTION General The complete functional definition of the 8253 is programmed by the systems software. A set of con- trol words must be sent out by the CPU to initialize each counter of the 8253 with the desired MODE and quantity information. Prior to initialization, the MODE, count, and output of all counters is unde- fined. These control words program the MODE, Loading sequence and selection of binary or BCD counting. : Once programmed, the 8253 is ready to perform whatever timing tasks it is assigned to accomplish. The actual counting operation of each counter is completely independent and additional logic is pro- vided on-chip so that the usual problems associated with efficient monitoring and management of exter- nal, asynchronous events or rates to the microcom- puter system have been eliminated. Programming the 8253 All of the MODES for each counter are programmed by the systems software by simple 1/O operations. Each counter of the 8253 is individually programmed by writing a control word into the Control Word Reg- ister. (AO, A1 = 11) Control Word Format D7 De Ds Dg D3 Do OD Do [sc1 | sco | Att | Rio | m2] mt | Mo | Bco | Definition Of Control SCSELECT COUNTER: Sci sco 0 0 Select Counter 0 0 1 Seiect Counter 1 1 0 Select Counter 2 1 1 lilegal 3-54 RLREAD/LOAD: RL1 ALO . 0 0 | Counter Latching operation (see READ/WRITE Procedure Section). 1 0 | Read/Load most significant byte only. 0 Read/Load least significant byte only. 1 1 | Read/Load least significant byte first, then most significant byte. MMODE: M2 M1 MO 0 0 0 Mode 0 0 0 1 Mode 1 x 1 0 Mode 2 x 1 1 Mode 3 1 0 0 Mode 4 1 0 1 Mode 5 BCD: 0 Binary Counter 16-Bits Binary Coded Decimal (BCD) Counter (4 Decades) Counter Loading The count register is not foaded until the count value is written (one or two bytes, depending on the mode selected by the RL bits), followed by a rising edge and a falling edge of the clock. Any read of the coun- ter prior to that falling clock edge may yield invalid data. MODE DEFINITION MODE 0: interrupt on Terminal Count. The output will be initially low after the mode set operation. After the count is loaded into the selected count register, the output will remain low and the counter will count. When termina! count is reached, the output will go high and remain high until the selected count regis- ter is reloaded with the mode or a new count is load- ed. The counter continues to decrement after termi- nal count has been reached. Rewriting a counter register during counting results in the following: (1) Write 1st byte stops the current counting. (2) Write 2nd byte starts the new count.intel. 8253/8253-5 MODE 1: Programmable One-Shot. The output will go low on the count following the rising edge of the gate input. The output will go high on the terminal count. If a new count value is loaded while the output is low it will not affect the duration of the one-shot pulse until the succeeding trigger. The current count can be read at any time without affecting the one-shot pulse. The one-shot is retriggerable, hence the output will remain low for the full count after any rising edge of the gate input. MODE 2: Rate Generator. Divide by N counter. The output will be low for one period of the input clock. The period from one output pulse to the next equals the number of input counts in the count register. if the count register is reloaded between output pulses the present period will not be affected, but the sub- sequent period will reflect the new value. The gate input, when low, will force the output high. When the gate input goes high, the counter will start from the initiat count. Thus, the gate input can be used to synchronize the counter. When this mode is set, the output will remain high until after the count register is loaded. The output then can also be synchronized by software. MODE 3: Square Wave Rate Generator. Similar to MODE 2 except that the output will remain high until one half the count has been completed (or even numbers) and go low for the other half of the count. This is accomplished by decrementing the counter by two on the falling edge of each clock pulse. When the counter reaches terminal count, the state of the output is changed and the counter is reloaded with the full count and the whole process is repeated. If the count is odd and the output is high, the first clock pulse (after the count is loaded) decrements the count by 1. Subsequent clock pulses decrement the clock by 2. After timeout, the output goes low and the full count is reloaded. The first clock pulse (following the reload) decrements the counter by 3. Subsequent clock pulses decrement the count by 2 until timeout. Then the whole process is repeated. In this way, if the count is odd, the output will be high for (N + 1)/2 counts and low for (N 1)/2 counts. 3-55 In Modes 2 and 3, if a CLK source other than the system clock is used, GATE should be pulsed imme- diately following WR of a new count value: MODE 4: Software Triggered Strobe. After the mode is set, the output will be high. When the count is loaded, the counter will begin counting. On termi- nal count, the output will go low for one input clock period, then will go high again. If the count register is reloaded during counting, the new count will be loaded on the next CLK pulse. The count will be inhibited while the GATE input is low. MODE 5: Hardware Triggered Strobe. The counter will start counting after the rising edge of the trigger input and will go iow for one clock period when the terminal count is reached. The counter is retriggera- ble. The output will not go low until the full count after the rising edge of any trigger. Signal Low Status| Or Going Rising High Modes Low 0 Disables _ Enables counting counting 1 1) Initiates _ counting 2) Resets output after next clock 2 1) Disables 1) Reloads Enables counting counter counting 2) Sets output | 2) Initiates immediately} counting high 3 1) Disables 1) Reloads Enables counting counter counting 2) Sets output | 2) Initiates immediately} counting high 4 Disables _ Enables counting counting 5 _ Initiates _ counting Figure 6. Gate Pin Operations Summaryintel. 8253/8253-5 MODE 0: INTERRUPT ON TERMINAL COUNT cock SLPLPUP LLL ' t Win | I 1 ' 4321 9 OUTPUT (INTERRUPT) (n= 4) bo} - +} I ' Win LS t i GATE ; 1 5 4 3921 6 oureuranrenrueT) im = 8) A B A+B=m 231306-6 MODE 1: PROGRAMMABLE ONE-SHOT ctock PUPAL Lee Wi TLS TRIGGER j 4 3 2 1 0 ouTPuT Lr in= 4) TRIGGER 43 2 4 3 2 1 90 231306-7 MODE 2: RATE GENERATOR clock LULL Ler, Win n@ o 3 ouTeut 4 3 2 1 OM 3 2 = 1 O72 1 ~0 OUTPUT Os 3.2 4 ON 2 1 O12 1 Ww LU ee SS~S OUTPUT {n= 3} RESET 231306-8 MODE 3: SQUARE WAVE GENERATOR cteck PUPUP UPL ULL LP. 4 24 2 4 2.4 2 4 2 4a 2 4 output ine) 5 4 2 5 2 5 4 2 5 2 a 2 OUTPUT {n = 5) d tl j l J 231306-9 MODE 4: SOFTWARE TRIGGERED STROBE cvoek PLP LL WR n=4 4 3 2 1 90 OUTPUT 1 } LOAD n n=4 GATE lt J 4 4 3 2 #1 =90 OUTPUT LJ 231306-10 MODE 5: HARDWARE TRIGGERED STROBE ctoek TUPLE . GATE OUTPUT (n = 4) l J GATE _ LS 434 3 2 #1 0 OUTPUT (n = 4) | 231306-11 Figure 7. 8253 Timing Diagrams 3-56intel. 8253/8253-5 8253 READ/WRITE PROCEDURE Write Operations The systems software must program each counter of the 8253 with the mode and quantity desired. The programmer must write out to the 8253 a MODE control word and the programmed number of count register bytes (1 or 2) prior to actually using the se- lected counter. The actual order of the programming is quite flexible. Writing out of the MODE control word can be in any sequence of counter selection, e.g., counter #0 does not have to be first or counter #2 last. Each counters MODE contro! word register has a sepa- rate address so that its loading is completely se- quence independent. (SCO, SC1). The loading of the Count Register with the actual count vaiue, however, must be done in exactly the sequence programmed in the MODE control word (RLO, RL1). This loading of the counters count reg- ister is still sequence independent like the MODE control word loading, but when a selected count reg- ister is to be loaded it must be loaded with the num- ber of bytes programmed in the MODE control word (RLO, RL1). The one or two bytes to be loaded in the count register do not have to follow the associated MODE control word. They can be programmed at any time following the MODE control word loading as long as the correct number of bytes is loaded in order. All counters are down counters. Thus, the value loaded into the count register will actually be decre- mented. Loading all zeros into a count register will result in the maximum count (216 for Binary or 104 for BCD). In MODE 0 the new count will not restart until the load has been completed. It will accept one of two bytes depending on how the MODE control words (RLO, RL1) are programmed. Then proceed with the restart operation. 3-57 MODE Control Word Counter n LSB Counter Register byte Counter n MSB Counter Register byte Counter n NOTE: Format shown is a simple example of loading the 8253 and does not imply that it is the only format that can be used. Figure 8. Programming Format A1| AO MODE Control Word Not Counter 0 1] 1 MODE Control Word , No.2 Counter 1 1) 1 MODE Control Word No.8 Counter 2 1] 1 Count Register Byte No.4) LSB Counter 1 Oo} 1 Count Register Byte No.8 | MSB Counter 1 o|1 No.6 | LSB Count Register Byte | , | | Counter 2 Count Register Byte No.7) MSB Counter 2 1] 0 Count Register Byte No.8 | LSB Counter 0 0 0 No.9 | MSB Count Register Byte o | o Counter 0 NOTE: The exclusive addresses of each counters count regis- ter make the task of programming the 8253 a very sim- ple matter, and maximum effective use of the device will result if this feature is fully initilized. Figure 9. Alternate Programming Formatsintel. 8253/8253-5 Read Operations in most counter applications it becomes necessary to read the value of the count in progress and make a computational decision based on this quantity. Event counters are probably the most common ap- plication that uses this function. The 8253 contains logic that will allow the programmer to easily read the contents of any of the three counters without disturbing the actual count in progress. There are two methods that the programmer can use to read the value of the counters. The first meth- od involves the use of simple |/O read operations of the selected counter. By controlling the AO, A1 in- puts to the 8253 the programmer can select the counter to be read (remember that no read opera- tion of the mode register is allowed AO, A1-11). The only requirement with this method is that in order to assure a stable count reading the actual operation of the selected counter must be inhibited either by con- trolling the Gate input or by external logic that inhibits the clock input. The contents of the counter selected will be available as follows: First |/O Read contains the least significant byt (LSB). Second |/O Read contains the most significant byte (MSB). Due to the internal logic of the 8253 it is absolutely necessary to complete the entire reading procedure. If two bytes are programmed to be read, then two bytes must be read before any loading WR com- mand can be sent to the same counter. Read Operation Chart Al AO RD 0 0 0 Read Counter No. 0 0 1 0 Read Counter No. 1 1 0 0 Read Counter No. 2 1 1 0 INegal Reading While Counting In order for the programmer to read the contents of any counter without effecting or disturbing the count- ing operation the 8253 has special internal logic that can be accessed using simple WR commands to the MODE register. Basically, when the programmer wishes to read the contents of a selected counter on the fly he loads the MODE register with a spe- cial code which latches the present count value into a storage register so that its contents contain an accurate, stable quantity. The programmer then is- sues a normal read command to the selected coun- ter and the contents of the latched register is available. MODE Register for Latching Count AO, A1 = 11 07 D6 | DS | D4} 03 | D2; 01 | DO Sci | SCO | 0 0 X X x X SC1, SCO specify counter to be latched. D5,D4 00 designates counter latching opera- tion. X dont care. The same limitation applies to this mode of reading the counter as the previous method. That is, it is mandatory to complete the entire read operation as programmed. This command has no effect on the counters mode. 3MHz CLK * 1.5MHz CLK 8085 8253-5 231306-12 *tf an 8085 clock output is to drive an 8253-5 clock input, it must be reduced to 2 MHz or less. Figure 10. MCS-85T Clock interface* 3-58intel. 8253/8253-5 ABSOLUTE MAXIMUM RATINGS* Ambient Temperature Under Bias ...... 0C to 70C Storage Temperature .......... 65C to + 150C Voltage On Any Pin with Respect to Ground............ 0.5V to 7V Power Dissipation ...................-.005 1 Watt NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and ex- tended exposure beyond the Operating Conditions may affect device reliability. D.C. CHARACTERISTICS Ta, = 0C to 70C, Voc = 5V + 10%* Symbol Parameter Min Max Unit Test Conditions Vit input Low Voltage -0.5 0.8 Vv Vin - Input High Voltage 2.2 Voc + .5V v VoL Output Low Voltage 0.45 Vv (Note 1) Vou Output High Voltage 2.4 Vv (Note 2) Iie input Load Current , +10 pA Vin = Vcc to OV loFL Output Float Leakage +10 pA Vout = Vcc to 0.45V loc Voc Supply Current 140 mA CAPACITANCE Ta = 28C, Vcc = GND = OV Symbol! Parameter Min Typ Max Unit Test Conditions Cin Input Capacitance 10 pF fc = 1 MHz Cio 1/O Capacitance 20 pF Unmeasured pins returned to Vss A.C. CHARACTERISTICS Ty, = 0C to 70C, Vcc = 5.0V +10%, GND = OV* Bus Parameters(3) READ CYCLE 8253 8253-5 Symbol Parameter Unit Min Max Min Max tar Address Stable before READ 50 30 ns tra Address Hold Time for READ 5 5 ns tar READ Pulse Width 400 300 ns tap Data Delay from READ(4) 300 200 ns tor READ to Data Floating 25 125 25 100 ns tay Recovery Time between READ 1 1 ps and Any Other Control Signal 3-59intel. 8253/8253-5 A.C. CHARACTERISTICS (Continued) WRITE CYCLE Symbol Parameter 8258 82535 Unit Min Max Min Max taw Address Stable before WRITE 50 30 ns twa Address Hold Time for WRITE 30 30 ns tww WATTE Pulse Width 400 300 ns tow Data Set Up Time for WRITE 300 250 ns two Data Hold Time for WRITE 40 30 ns try - Recovery Time between WRITE 1 1 ps and Any Other Control Signal CLOCK AND GATE TIMING Symbol Parameter e208 82535 Unit , Min Max Min Max tcLk Clock Period 380 de 380 de ns tpWH High Pulse Width 230 230 ns tpwe Low Pulse Width 150 150 ns tew Gate Width High 150 150 ns tet Gate Width Low 100 100 ns tes Gate Set Up Time to CLK T 100 100 ns igu Gate Hold Time after CLK T 50 50 ns top Output Delay from CLK J (4) 400 400 ns tone Output Delay from Gate | (4) 300 300 ns NOTES: 1. lo, = 2.2 mA. 2. lon = 400 pA. 3. AC timings measured at Voy 2.2, VoL = 0.8. 4.C, = 150 pF. *For Extended Temperature EXPRESS, use M8253 electrical parameters. A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT 24 2.2 2.2V > TEST POINTS < 0.8 . 0.45 oe 231306-13 A.C. Testing: Inputs are driven at 2.4V for a Logic "1" and 0.45V for a Logic 0. Timing measurements are made at 2.2V for a Logic 1 and 0.8V for a Logic 0. DEVICE UNDER Test T = 150 pF 231306-14 Cy, Includes Jig Capacitance 3-60intel. 8253/8253-5 WAVEFORMS WRITE TIMING READ TIMING ] Ag-1. C8 Ao-1. CS j+-- tape - 4 +i jeter a tan DATA BUS AD tap tore wR DATA ws fY HIGH IMPEDANCE VALID [HIGH IMPEDANCE ww 231306-16 231306~15 CLOCK AND GATE TIMING asl tev - | tes > GATEG J tow be te, | be tog o| OUTPUT O 231306-17 3-61