Am2102 /Am2102-1/Am2102- 1024-Bit Static N-Channel RAM | Distinctive Characteristics Operates from single 5 V_ power supply @ Three speed selections: tyusec, 650ns, 500ns | @ All inputs and outputs directly TTL compatible @ No clocks required @ 100% reliability testing in accordance with MIL-STD-883 The Am2102 is a static N-channel 1024-bit random access memory. The device operates from a single +5 volt power supply and all inputs and outputs are directly TTL com- patible with no external components required. The memory is addressed for reading or writing one bit by applying a binary code to the 10 address inputs AgAg. Writing is accomplished by lowering the write enable (WE) and the chip select (CE); the data on the data input (Dj,) will be stored in the addressed location. If the chip select is low- ered while write enable is HIGH, then the data stored in the addressed location will be read out on the data output (Dour). Any time the chip select is HIGH, the entire chip is dis- abled. Data cannot be written into the memory and the FUNCTIONAL DESCRIPTION output will go to a high impedance OFF state. When chip select is LOW, the output will drive at least one TTL load in both the HIGH and LOW states. During the write opera- tion, the data output follows the data input. The chip select function and the(fhree-state outpuD ake the construction of a large array using Am2102 chips very easy. Am2102 inputs and outputs can be tied together and chips selected by a standard TTL decoder such as the Am9321 or Am9301. The Am2102 is available in three different cycle time selections. The Am21Q2 operates with a lusec minimum read or write cycle, the Am2102-1 requires a 500ns min- imum read or write cycle, and the Am2102-2 requires a 650ns minimum read or write cycie. LOGIC SYMBOL AZ Ay mM As As a? Ly Ms ce Voc = Pin 10 GND = Pin? BLOCK DIAGRAM x Ay 3 a2 = a3 z 3 NM 2 at we o Dine Ay Me Ar Ag As Am2102 ORDERING INFORMATION Ambient Tysec 500ns 650ns Package Temperature Order Order Order Type Range Number Number Number Molded DIP.) -OC to +70C_)-- P2102 P2102-1 P2102-2 Hermetic DIP OC to +70C ~C2102 C2102-1 C2102-2 CONNECTION DiAGRAM Top View Ar Me AS CE our Din tec 38D Note Pin 11s marked tor onentationMAXIMUM kh. ; iNGS (Above which the useful life may be impaired) Storage Temperature 66C to +150C Temperature (Ambient) Under Bias 0C to +70C Supply Voltage to Ground Potential (Pin 10 to Pin 9) Continuous -0.5V to +7V OC Voltage Applied to Outputs -0.5V to +7V OC input Voltage O.5V to +7V OPERATING RANGE Pert Number Vee Ambient Temperature am2102, AM2102-1, AM2102-2 6.0V 25% OC 10 +70C ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Untess Otherwise Noted) Py Description Test Conditions Min. Typ.iNove 1) Max. Units Vou Output HIGH Voltage Voc = MIN., lon -100uA 2.2 Volts Voi Output LOW Voltage Voc * MIN, Io, = 1.9mA 0.45 Volts Guaranteed input logical HIGH Vin input HIGH Level voltage for all inputs 2.2 Voc Volts Guaranteed input logical LOW Vin Input LOW Levet voltage for atl inputs 05 0.65 Votts tu Input Loed Current Vec * MAX.. Vin = OV to 5.25 V 10 uA t All inputs = Voc - cel Power Supply Current Dete out open Ta = 25C Sad 6 mA loe2 Veo = MAX. Tas OC to +70C 30 70 Vout = 4.0V 10 . Cu . lio Output Leskage Current VE" 2.2V Vout = 046V =100 nA Nowe 1. Typicst limits are at Voc 8.0V and Ta = 28C CAPACITANCE (Ta = 25C} Parameters Description Test Conditions Min. Typ. Max. Units { cin [input Capacitance, Any input | Vin OV, f= TMHz | | 3 s | oF [Sour ]_ Output Capacitance [Your = OV, f= 1MHz T I 10 | OF | Am2102 SWITCHING CHARACTERISTICS AND OPERATING REQUIREMENTS (Ta = 0C to 70C, Vcc = 5V 25%) Load = 1 TTL Gate and 100 pF, Vj, = 0.68, Ving 22V, t= t= 20n8 Typ. (Note 1) Paramaters Description Test Conditions Reed Cycle Time Access Time LOW to Output Previous Read Deta Valid with to Address Previous Reed Data Valid with to Select Write Cycle Time Write Width Max. 1000 Units no ns 500 na ne Ria gs Rl alzl2_4m2102-1 SWITCHING CHARACTERISTICS AND OPERATING REQUIREMENTS (Ta =0C to 70 C= 5Vt5%) Load = 1 TTL Gate end 100 pF, Vi_ = 0.65V, Vip * 2.2V, tr = tf = 20s Typ. Parameters Description Test Conditions Min. (Note 1} Max. tac Resd Cycle Time 500 | ta Access Time __ ! tco CE LOW to Output - : tom | UiRter we arn - ton2 Previous Read Oats Valid with Respect to Chip Select two Write Cycie Time taw Address Set-Up Time twe Write Pulse Width twA Write Recovery Time tow Data Set-Up Time 1DH Data Hold Time tow Chip Enable Hold Time Am2102-2 SWITCHING CHARACTERISTICS AND OPERATING REQUIREMENTS (Ta = 0C to 70C, Vcc = 5V25%) Load 1 TTL Gate and 100 pF, Vj, + 0.65V, Vin = 2.2V, te * te > 208 Typ. Parameters Description Test Conditions Min woe n Max Units tac Read Cycle Time tA Access Time tco CE LOW to Output tout Previous Reed Data Valid with Respect to Address wove | Sonne twe Write Cycle Time taw Address Set-Up Time twe Write Pulse Width WR Write Recovery Time - tow Data Set-Up Time - ton Data Hold Time ~ tow Chip Enable Hold Time ~ 550 SWITCHING WAVEFORMS READ CYCLE al eo ADORESS Y 15v | one : ENABLE K'* ' Se ee -_ ah ee meee ton? OUTPUT chase vev f {age ee wr WRITE Sy ENABLE ' tow rere lon on iw para stan xX 5-196-2 DEFINITIC TERMS FUNCTIONAL TERMS CE Active LOW chip enabie, Data can be read from or written into the memory only if CE is LOW. WE Active LOW write enable. Data is written into the memory if WE is LOW and read from the memory if WE is HIGH. Static RAM) =A random access memory in which data is stored in bistable latch circuits, A static memory will store data as long as power is supptied to the chip without requiring any special Clocking or refreshing operations. N-Channel An insulated gate field effect transistor technology in which the transistor source and drains are made of N-type material, and electrons serve as the carriers between the two regions. N-Channet transistors exhibit lower thresholds and faster switching speeds than P-Channel transistors. SWITCHING TERMS tac Read Cycle Time. The minimum time required between successive address changes while reading. ta Access Time. The time delay between application of an address and stable data on the output when the chip is enabled. tog Access Time from Chip Enabie. The minimum time during which the chip enable must be LOW prior to reading data on the output. tOH1 Minimum Access Time. Minimum time which will elapse between change of address and any change on the data output. tou2 Minimum time which will elapse between a change on the chip enable and any change on the data output. two Write Cycle Time. The minimum time required between successive address changes while writing. taw Address Set-Up Time. The minimum time prior to the falling edge of the write enable during which the address inputs must be correct and stable, twp The minimum duration of a LOW tevel on the write enable guaranteed to write data. twa Address Hold Time. The minimum time after the rising edge of the write enable during which the address must remain steady. tow Data Set-Up Time. The minimum time that the data input must be steady prior to the rising edge of the write enabie. ton Oata Hold Time. The minimum time that the data input must remain steady after the rising edge of the write enable. teow Chip Enable Time During Write, The minimum duration of a LOW level on the Chip Select while the write enable is LOW to quarantes writing. PHYSICAL DIMENSIONS Duel-in-Line 16-Pin Side Brazed 16-Pin Molded oy) TY Ths . 2 # . ji +k 8 + 2 (SS a _ I, 4+ = pr at + s a MVitl Te Pe aed} thw +g +B re ae tt Om ve Yee 0 oe OE SIZE 0.126" x 0.164 ADVANCED MICRO DEVICES INC. 901 Thompson Place Sunnyvale California 94006 (408) 732-2400 TWX: 910-339-9200 TELEX: 34-8306 Achenced Micro Devices can not sesume reaponsibitity for use of sey corcurtry described other then cacuitry entirely embodied in an Advenced Mecro Denice product. eMPreliminary Information AMD<ad\ 21850E/0November 1998 AMD-K6-2 Processor Data Sheet Stop Clock Stop Grant State STPCLK# Sampled Negated Normal (Re-entered after PLL stabilization) CLK AVAVAVAUAVAUAUAUA\\GAUAUAUAVAVAVAUB WAUAUAVAY AI313] BE[7:0|# S f ADS# S$ TL M/\O# % v_/ D/C# S S W/R# 5 s\ CACHE# $5 mr STPCLK+# SS $ D[63:0] 5 KEN# 5) BRDV# Figure 75. Stop Grant and Stop Clock Modes, Part 2 Chapter 5 Bus Cycles 169AMD@ Preliminary Information AMD-K6-2 Processor Data Sheet 21850E/0November 1998 INIT-Initiated Transition from Protected Mode to Real Mode INIT is typically asserted in response to a BIOS interrupt that writes to an I/O port. This interrupt is often in response to a Ctrl-Alt-Del keyboard input. The BIOS writes to a port (similar to port 64h in the keyboard controller) that asserts INIT. INIT is also used to support 80286 software that must return to Real mode after accessing extended memory in Protected mode. The assertion of INIT causes the processor to empty its pipelines, initialize most of its internal state, and branch to address FFFF_FFFOhthe same instruction execution starting point used after RESET. Unlike RESET, the processor preserves the contents of its caches, the floating-point state, the MMxX state, Model-Specific Registers (MSRs), the CD and NW bits of the CRO register, the time stamp counter, and other specific internal resources. Figure 76 shows an example in which the operating system writes to an I/O port, causing the system logic to assert INIT. The sampling of INIT asserted starts an extended microcode sequence that terminates with a code fetch from FFFF_FFF0h, the reset location. INIT is sampled on every clock edge but is not recognized until the next instruction boundary. During an I/O write cycle, it must be sampled asserted a minimum of three clock edges before BRDY# is sampled asserted if it is to be recognized on the boundary between the I/O write instruction and the following instruction. If INIT is asserted synchronously, it can be asserted for a minimum of one clock. If it is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks. 170 Bus Cycles Chapter 5Preliminary Information AMD<ad\ 21850E/0November 1998 AMD-K6-2 Processor Data Sheet INIT Sampled Asserted Code Fetch CLK ADP DPD PPD PPS MN A133] CX % X BE[7:0]4 X S X ADSH LS SL MO# \ DICH __ \ wRe / 5 D[63:0] }+{ s (XXX }- KEN# V/ BRDY# / \ a INIT / \ Figure 76. INIT-Initiated Transition from Protected Mode to Real Mode Chapter 5 Bus Cycles 171AMDd@ Preliminary Information AMD-K6-2 Processor Data Sheet 21850E/0November 1998 172 Bus Cycles Chapter 5Preliminary Information AMDZI 21850E/0November 1998 AMD-K6-2 Processor Data Sheet Power-on Configuration and Initialization On power-on the system logic must reset the AMD-K6-2 processor by asserting the RESET signal. When the processor samples RESET asserted, it immediately flushes and initializes all internal resources and its internal state, including its pipelines and caches, the floating-point state, the MMX and 3DNow! states, and all registers. Then the processor jumps to address FFFF_FFFOh to start instruction execution. Signals Sampled During the Falling Transition of RESET FLUSH# BF[2:0] BRDYC# FLUSH# is sampled on the falling transition of RESET to determine if the processor begins normal instruction execution or enters Tri-State Test mode. If FLUSH# is High during the falling transition of RESET, the processor unconditionally runs its Built-In Self Test (BIST), performs the normal reset functions, then jumps to address FFFF_FFFOh to start instruction execution. (See Built-In Self-Test (BIST) on page 217 for more details.) If FLUSH# is Low during the falling transition of RESET, the processor enters Tri-State Test mode. (See Tri-State Test Mode on page 218 and FLUSH# (Cache Flush) on page 103 for more details.) The internal operating frequency of the processor is determined by the state of the bus frequency signals BF[2:0] when they are sampled during the falling transition of RESET. The frequency of the CLK input signal is multiplied internally by a ratio defined by BF[2:0]. (See BF[2:0] (Bus Frequency) on page 92 for the processor-clock to bus-clock ratios.) BRDYC# is sampled on the falling transition of RESET to configure the drive strength of A[20:3], ADS#, HITM#, and W/R#. If BRDYC# is Low during the fall of RESET, these outputs are configured using higher drive strengths than the standard strength. If BRDYC# is High during the fall of RESET, the standard strength is selected. (See BRDYC# (Burst Ready Copy) on page 95 for more details.) Chapter 6 Power-on Configuration and Initialization 173AMD@ Preliminary Information AMD-K6-2 Processor Data Sheet 21850E/0November 1998 6.2 RESET Requirements During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and Vcc reach specification. (See CLK Switching Characteristics on page 255 for clock specifications. See Electrical Data on page 247 for Vcc specifications.) During a warm reset while CLK and Vcc are within specification, RESET must remain asserted for a minimum of 15 clocks prior to its negation. 6.3 State of Processor After RESET Output Signals Table 31 shows the state of all processor outputs and bidirectional signals immediately after RESET is sampled asserted. Table 31. Output Signal State After RESET Signal State Signal State A[31:3], AP Floating || LOCK# High ADS#, ADSC# High M/lO# Low APCHK# High PCD Low BE[7:0]# Floating || PCHK# High BREQ Low PWT Low CACHE# High SCYC Low D/C# Low SMIACT# High D[63:0], DP[7:0] Floating TDO Floating FERR# High VCC2DET Low HIT# High VCC2H/L# Low HITM# High W/R# Low HLDA Low - - Registers Table 32 on page 175 shows the state of all architecture registers and Model-Specific Registers (MSRs) after the processor has completed its initialization due to the recognition of the assertion of RESET. 174 Power-on Configuration and Initialization Chapter 6