MJE13009 - ON Semiconductor

February, 2006 − Rev. 7 1Publication Order Number:

MJE13009/D

MJE13009

Preferred Device

SWITCHMODEt Series

NPN Silicon Power

Transistors

The MJE13009 is designed for high−voltage, high−speed power

switching inductive circuits where fall time is critical. They are

particularly suited for 115 and 220 V SWITCHMODE applications

such as Switching Regulators, Inverters, Motor Controls,

Solenoid/Relay drivers and Deflection circuits.

Features

•VCEO(sus) 400 V and 300 V

•Reverse Bias SOA with Inductive Loads @ TC = 100_C

•Inductive Switching Matrix 3 to 12 Amp, 25 and 100_C tc @ 8 A,

100_C is 120 ns (Typ)

•700 V Blocking Capability

•SOA and Switching Applications Information

•Pb−Free Package is Available*

MAXIMUM RATINGS

Rating Symbol Value Unit

Collector−Emitter Voltage VCEO(sus) 400 Vdc

Collector−Emitter Voltage VCEV 700 Vdc

Emitter−Base Voltage VEBO 9 Vdc

Collector Current − Continuous

− Peak (Note 1) IC

ICM 12

24 Adc

Base Current − Continuous

− Peak (Note 1) IB

IBM 6

12 Adc

Emitter Current − Continuous

− Peak (Note 1) IE

IEM 18

36 Adc

Total Device Dissipation @ TC = 25_C

Derate above 25°CPD2

16 W

W/_C

Total Device Dissipation @ TC = 25_C

Derate above 25°CPD100

800 W

W/_C

Operating and Storage Junction

Temperature Range TJ, Tstg −65 to

+150

_C

THERMAL CHARACTERISTICS

Characteristics Symbol Max Unit

Thermal Resistance, Junction−to−Ambient RqJA 62.5 _C/W

Thermal Resistance, Junction−to−Case RqJC 1.25 _C/W

Maximum Lead Temperature for Soldering

Purposes 1/8″ from Case for 5 Seconds TL275 _C

Maximum ratings are those values beyond which device damage can occur.

Maximum ratings applied to the device are individual stress limit values (not

normal operating conditions) and are not valid simultaneously. If these limits are

exceeded, device functional operation is not implied, damage may occur and

reliability may be affected.

1. Pulse Test: Pulse Width = 5 ms, Duty Cycle ≤ 10%.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

12 AMPERE

NPN SILICON

POWER TRANSISTOR

400 VOLTS − 100 WATTS

TO−220AB

CASE 221A−09

STYLE 11

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MARKING DIAGRAM

23

MJE13009G

AY WW

A = Assembly Location

Y = Year

WW = Work Week

G = Pb−Free Package

Device Package Shipping

ORDERING INFORMATION

MJE13009 TO−220 50 Units / Rail

MJE13009G TO−220

(Pb−Free) 50 Units / Rail

Preferred devices are recommended choices for future use

and best overall value.

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2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (TC = 25_C unless otherwise noted)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎÎ

Min

ÎÎÎ

Typ

ÎÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

OFF CHARACTERISTICS (Note 2)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Collector−Emitter Sustaining Voltage

(IC = 10 mA, IB = 0)

ÎÎÎÎ

VCEO(sus)

ÎÎÎÎ

400

ÎÎÎ

−

ÎÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Collector Cutoff Current

(VCEV = Rated Value, VBE(off) = 1.5 Vdc)

(VCEV = Rated Value, VBE(off) = 1.5 Vdc, TC = 100_C)

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

ICEV

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

−

ÎÎÎ

Î

ÎÎÎ

−

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

1

5

ÎÎÎ

Î

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Emitter Cutoff Current

(VEB = 9 Vdc, IC = 0)

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

IEBO

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

−

ÎÎÎ

Î

ÎÎÎ

−

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

1

ÎÎÎ

Î

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SECOND BREAKDOWN

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Second Breakdown Collector Current with base forward biased

Clamped Inductive SOA with Base Reverse Biased

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

IS/b

−

ÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎ

See Figure 1

See Figure 2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ON CHARACTERISTICS (Note 2)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Current Gain

(IC = 5 Adc, VCE = 5 Vdc)

(IC = 8 Adc, VCE = 5 Vdc)

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

hFE

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

8

6

ÎÎÎ

Î

ÎÎÎ

−

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

40

30

ÎÎÎ

Î

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Collector−Emitter Saturation Voltage

(IC = 5 Adc, IB = 1 Adc)

(IC = 8 Adc, IB = 1.6 Adc)

(IC = 12 Adc, IB = 3 Adc)

(IC = 8 Adc, IB = 1.6 Adc, TC = 100_C)

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

VCE(sat)

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

−

ÎÎÎ

Î

ÎÎÎ

−

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

1

1.5

3

2

ÎÎÎ

Î

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Base−Emitter Saturation Voltage

(IC = 5 Adc, IB = 1 Adc)

(IC = 8 Adc, IB = 1.6 Adc)

(IC = 8 Adc, IB = 1.6 Adc, TC = 100_C)

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

VBE(sat)

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

−

ÎÎÎ

Î

ÎÎÎ

−

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

1.2

1.6

1.5

ÎÎÎ

Î

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DYNAMIC CHARACTERISTICS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Current−Gain − Bandwidth Product

(IC = 500 mAdc, VCE = 10 Vdc, f = 1 MHz)

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

fT

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

4

ÎÎÎ

Î

ÎÎÎ

−

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

−

ÎÎÎ

Î

ÎÎÎ

MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Capacitance

(VCB = 10 Vdc, IE = 0, f = 0.1 MHz)

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

Cob

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

−

ÎÎÎ

Î

ÎÎÎ

180

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

−

ÎÎÎ

Î

ÎÎÎ

pF

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Resistive Load (Table 1)

ÎÎÎÎÎÎÎÎ

Delay Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

(VCC = 125 Vdc, IC = 8 A,

IB1 = IB2 = 1.6 A, tp = 25 ms,

Duty Cycle v 1%)

ÎÎÎÎ

td

ÎÎÎÎ

−

ÎÎÎ

0.06

ÎÎÎÎ

0.1

ÎÎÎ

ms

ÎÎÎÎÎÎÎÎ

Rise Time

ÎÎÎÎ

tr

ÎÎÎÎ

−

ÎÎÎ

0.45

ÎÎÎÎ

1

ÎÎÎ

ms

ÎÎÎÎÎÎÎÎ

Storage Time

ÎÎÎÎ

ts

ÎÎÎÎ

−

ÎÎÎ

1.3

ÎÎÎÎ

3

ÎÎÎ

ms

ÎÎÎÎÎÎÎÎ

Fall Time

ÎÎÎÎ

tf

ÎÎÎÎ

−

ÎÎÎ

0.2

ÎÎÎÎ

0.7

ÎÎÎ

ms

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Inductive Load, Clamped (Table 1, Figure 13)

ÎÎÎÎÎÎÎÎ

Voltage Storage Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

(IC = 8 A, Vclamp = 300 Vdc,

IB1 = 1.6 A, VBE(off) = 5 Vdc, TC = 100_C)

ÎÎÎÎ

tsv

ÎÎÎÎ

−

ÎÎÎ

0.92

ÎÎÎÎ

2.3

ÎÎÎ

ms

ÎÎÎÎÎÎÎÎ

Crossover Time

ÎÎÎÎ

tc

ÎÎÎÎ

−

ÎÎÎ

0.12

ÎÎÎÎ

0.7

ÎÎÎ

ms

2. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.

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IC, COLLECTOR CURRENT (AMP)

10m

σ

100m

σ

1m

s

dc

100

7

VCE, COLLECTOR−EMITTER VOLTAGE (VOLTS)

0.02

10

20

10

50

0.5

0.1

0.05

30 50 70 100

Figure 1. Forward Bias Safe Operating Area Figure 2. Reverse Bias Switching Safe

Operating Area

0.2

0.01

300 500520

14

0

800

2

100 300

TC ≤ 100°C

IB1 = 2.5 A

500 700

VBE(off) = 9 V

0

6

VCEV, COLLECTOR−EMITTER CLAMP VOLTAGE (VOLTS)

10

200 400 600

5 V

2

1

5

TC = 25°C

12

8

4

3 V

1.5

V

IC, COLLECTOR (AMP)

200

THERMAL LIMIT

BONDING WIRE LIMIT

SECOND BREAKDOWN LIM-

IT

CURVES APPLY BELOW RATED

VCEO

The Safe Operating Area figures shown in Figures 1 and 2 are specified ratings for these devices under the test conditions shown.

Figure 3. Forward Bias Power Derating

TC, CASE TEMPERATURE (°C)

040 120 160

0.6

POWER DERATING FACTOR

SECOND BREAK-

DOWN DERATING

1

0.8

0.4

0.2

60 100 14080

THERMAL

DERATING

20

There are two limitations on the power handling ability of

a transistor: average junction temperature and second

breakdown. Safe operating area curves indicate IC − V CE

limits of the transistor that must be observed for reliable

operation; i.e., the transistor must not be subjected to greater

dissipation than the curves indicate.

The data of Figure 1 is based on TC = 25_C; TJ(pk) is

variable depending on power level. Second breakdown

pulse limits are valid for duty cycles to 10% but must be

derated when TC ≥ 25_C. Second breakdown limitations do

not derate the same as thermal limitations. Allowable

current at the voltages shown on Figure 1 may be found at

any case temperature by using the appropriate curve on

Figure 3.

TJ(pk) may be calculated from the data in Figure 4. At high

case temperatures, thermal limitations will reduce the power

that can be handled to values less than the limitations

imposed by second breakdown. Use of reverse biased safe

operating area data (Figure 2) is discussed in the applications

information section.

t, TIME (ms)

1

0.01

0.7

0.2

0.1

0.05

0.02

r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)

0.05 1 2 5 10 20 50 100 200 500

ZqJC(t) = r(t) RqJC

RqJC = 1.25°C/W MAX

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

READ TIME AT t1

TJ(pk) − TC = P(pk) ZqJC(t)

P(pk)

t1

t2

DUTY CYCLE, D = t1/t2

D = 0.5

0.02

SINGLE PULSE

0.1

0.1 0.50.2 1.0 k

0.5

0.3

0.07

0.03

0.02

Figure 4. Typical Thermal Response [ZqJC(t)]

0.01

0.05

0.2

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VCE, COLLECTOR−EMITTER VOLTAGE (VOLTS)

IC, COLLECTOR CURRENT (AMP)IC, COLLECTOR CURRENT (AMP)

1.2

1.4

0.8

0.4

Figure 5. DC Current Gain

IC, COLLECTOR CURRENT (AMP)

0.5 1 5 7

10

Figure 6. Collector Saturation Region

0.05

IB, BASE CURRENT (AMP)

0.30.07

1.2

0.4

0

50

hFE, DC CURRENT GAIN

0.1 0.2 0.5 5

Figure 7. Base−Emitter Saturation Voltage Figure 8. Collector−Emitter Saturation

Voltage

Figure 9. Collector Cutoff Region

2

0.8

0.1

VBE, BASE−EMITTER VOLTAGE (VOLTS)

0

TJ = 25°C

0.7 3

Figure 10. Capacitance

4K

VR, REVERSE VOLTAGE (VOLTS)

C, CAPACITANCE (pF)

Cib

Cob

0.1

, COLLECTOR CURRENT (A)μIC

−0.4 −0.2

100

80

500

1.6

0.6

IC = 1 A

5

0.2 2

0.3 1 70.7 100.2 0.5 325

30

20

7

600

400

200

40

60

200100510.5

V, VOLTAGE (VOLTS)

+0.6

3 A

0.7 1 2

1

0.5

0.7

0.4

0

0.2

0.6

0.3

VCE = 5 V

TJ = 150°C

25°C

−

55°C

20

0.3

+0.4+0.2

1

10

100

1K

10K

800

1K

2K

10 50

REVERSE FORWARD

VCE = 250 V

10 20

5 A 8 A 12 A

3

TJ = −55°C

IC/IB = 3

25°C150°C

0.3 1 70.7 100.2 0.5 325 20

0.1

IC/IB = 3

TJ = 150°C

− 55°C

25°C

TJ = 150°C

125°C

100°C

75°C

50°C

25°C

0.2 2 20

TJ = 25°C

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t1

REVERSE BIAS SAFE OPERATING AREA AND INDUCTIVE SWITCHING RESISTIVE

SWITCHING

OUTPUT WAVEFORMS

TEST CIRCUITS

CIRCUIT

VALUES

TEST WAVEFORMS

NOTE

PW and VCC Adjusted for Desired IC

RB Adjusted for Desired IB1

5 V

PW

DUTY CYCLE ≤ 10%

tr, tf ≤ 10 ns 68

1

k

0.001 mF

0.02 mF

1N4933

270

+5 V

1 k

2N2905

47

1/2 W

100

−VBE(off)

MJE200

D.U.T.

IB

RB

1N4933

1N4933 33

33

2N2222

1

k

MJE210

VCC

+5 V

L

IC

MR826*

Vclamp

*SELECTED FOR ≥ 1 kV

VCE

5.1 k

51

+125 V

RC

SCOPE

−4.0

V

D1

RB

TUT

t1 ADJUSTED TO

OBTAIN IC

t1 ≈Lcoil (ICM)

VCC

t2 ≈Lcoil (ICM)

Vclamp

+10 V 25 ms

0

−8 V

Coil Data:

Ferroxcube Core #6656

Full Bobbin (~16 Turns) #16

GAP for 200 mH/20 A

Lcoil = 200 mHVCC = 20 V

Vclamp = 300 Vdc

VCC = 125 V

RC = 15 W

D1 = 1N5820 or Equiv.

RB = W

Test Equipment

Scope−Tektronics

475 or Equivalent

tr, tf < 10 ns

Duty Cycle = 1.0%

RB and RC adjusted

for desired IB and IC

IC

VCE

TIME

ICM

VCEM

t2

t

tf

tf CLAMPED

tf UNCLAMPED ≈ t2

Vclamp

Table 1. Test Conditions for Dynamic Performance

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APPLICATIONS INFORMATION FOR SWITCHMODE SPECIFICATIONS

INTRODUCTION

The primary considerations when selecting a power

transistor for SWITCHMODE applications are voltage and

current ratings, switching speed, and energy handling

capability. In this section, these specifications will be

discussed and related to the circuit examples illustrated in

Table 2. (Note 3)

VOLTAGE REQUIREMENTS

Both blocking voltage and sustaining voltage are

important in SWITCHMODE applications.

Circuits B and C in Table 2 illustrate applications that

require high blocking voltage capability. In both circuits the

switching transistor is subjected to voltages substantially

higher than VCC after the device is completely off (see load

line diagrams at IC = Ileakage ≈ 0 in Table 2). The blocking

capability at this point depends on the base to emitter

conditions and the device junction temperature. Since the

highest device capability occurs when the base to emitter

junction is reverse biased (VCEV), this is the recommended

and specified use condition. Maximum ICEV at rated VCEV

is specified at a relatively low reverse bias (1.5 V) both at

25°C and 100_C. Increasing the reverse bias will give some

improvement in device blocking capability.

The sustaining or active region voltage requirements in

switching applications occur during turn−on and turn−of f. If

the load contains a significant capacitive component, high

current and voltage can exist simultaneously during turn−on

and the pulsed forward bias SOA curves (Figure 1) are the

proper design limits.

For inductive loads, high voltage and current must be

sustained simultaneously during turn−off, in most cases,

with the base to emitter junction reverse biased. Under these

conditions the collector voltage must be held to a safe level

at or below a specific value of collector current. This can be

accomplished by several means such as active clamping, RC

snubbing, load line shaping, etc. The safe level for these

devices is specified as a Reverse Bias Safe Operating Area

(Figure 2) which represents voltage−current conditions that

can be sustained during reverse biased turn−off. This rating

is verified under clamped conditions so that the device is

never subjected to an avalanche mode.

In the four application examples (Table 2) load lines are

shown in relation to the pulsed forward and reverse biased

SOA curves.

In circuits A and D, inductive reactance is clamped by the

diodes shown. In circuits B and C the voltage is clamped by

the output rectifiers, however, the voltage induced in the

primary leakage inductance is not clamped by these diodes

and could be large enough to destroy the device. A snubber

network or an additional clamp may be required to keep the

turn−off load line within the Reverse Bias SOA curve.

Load lines that fall within the pulsed forward biased SOA

curve during turn−on and within the reverse bias SOA curve

during turn−off are considered safe, with the following

assumptions:

1. The device thermal limitations are not exceeded.

2. The turn−on time does not exceed 10 ms (see standard

pulsed forward SOA curves in Figure 1).

3. The base drive conditions are within the specified

limits shown on the Reverse Bias SOA curve

(Figure 2 ) .

CURRENT REQUIREMENTS

An efficient switching transistor must operate at the

required current level with good fall time, high energy

handling capability and low saturation voltage. On this data

sheet, these parameters have been specified at 8 amperes

which re p r e s ents typical design conditions for these devices.

The current drive requirements are usually dictated by the

VCE(sat) specification because the maximum saturation

voltage is specified at a forced gain condition which must be

duplicated or exceeded in the application to control the

saturation voltage.

SWITCHING REQUIREMENTS

In many switching applications, a major portion of the

transistor power dissipation occurs during the fall time (tfi).

For this reason considerable effort is usually devoted to

reducing the fall time. The recommended way to accomplish

this is to reverse bias the base−emitter junction during

turn−off. The reverse biased switching characteristics for

inductive loads are discussed in Figure 11 and Table 3 and

resistive loads in Figures 13 and 14. Usually the inductive

load component will be the dominant factor in

SWITCHMODE applications and the inductive switching

data will more closely represent the device performance in

actual application. The inductive switching characteristics

are derived from the same circuit used to specify the reverse

biased SOA curves, (See Table 1) providing correlation

between test procedures and actual use conditions.

3. For detailed information on specific switching applications, see

ON Semiconductor Application Notes AN−719, AN−767.

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Figure 11. Turn−On Time

IC, COLLECTOR CURRENT (AMP)

tr

td @ VBE(off) = 5 V

100

50

1K

700

500

IC, COLLECTOR CURRENT (AMP)

0.7 3120.2

VCC = 125 V

IC/IB = 5

TJ = 25°C

0.5

200

300

t, TIME (ns)

0.3

Figure 12. Turn−Off Time

200

100

2K

1K

700 VCC = 125 V

IC/IB = 5

TJ = 25°C

300

500

t, TIME (ns)

70

75 10 20 0.7 1 20.2 0.50.3 751020

ts

tf

Figure 13. Inductive Switching

Measurements

TIME

Figure 14. Typical Inductive Switching Waveforms

(at 300 V and 12 A with IB1 = 2.4 A and VBE(off) = 5 V)

TIME 20 ns/DIV

IC

VCE

IC

VCE

CURRENT 2 A/DIV

VOLTAGE 50 V/DIV

IC

Vclamp

IB90% IB1

10%

VCEM 10%

ICM 2%

IC

Vclamp

90% VCEM 90% IC

tsv trv tfi tti

tc

RESISTIVE SWITCHING PERFORMANCE

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CIRCUIT LOAD LINE DIAGRAMS TIME DIAGRAMS

SERIES SWITCHING

REGULATOR

RINGING CHOKE

INVERTER

PUSH−PULL

INVERTER/CONVERTER

SOLENOID DRIVER

VCC VO

N

VCC

VO

VCC

SOLENOID

Collector CurrentCollector CurrentCollector CurrentCollector Current

24 A

12 A

TC = 100°C

TURN−

ON TURN−

OFF

VCC 400 V 700 V

COLLECTOR VOLTAGE

350 V

TURN−ON (FORWARD BIAS) SOA

ton ≤ 10 ms

DUTY CYCLE ≤ 10%

PD = 4000 W

TURN−OFF (REVERSE BIAS)

SOA

1.5 V ≤ VBE(off) ≤ 9.0 V

DUTY CYCLE ≤ 10%

1

2

1

IC

VCE

VCC

TIME

t

24 A

TC = 100°C

12 A

TURN−OFF

TURN−ON

VCC 400 V 1

VCC + N(Vo)

350 V

PD = 4000 W 2

TURN−ON (FORWARD BIAS) SOA

TURN−ON ton ≤ 10 ms

TURN−ON DUTY CYCLE ≤ 10%

TURN−OFF (REVERSE BIAS) SOA

TURN−OFF 1.5 V ≤ VBE(off) ≤ 9.0 V

TURN−OFF DUTY CYCLE ≤ 10%

700 V 1

COLLECTOR VOLTAGE

24 A

12 A

TC = 100°C

TURN−OFF

TURN−ON

VCC 400 V 1700 V 1

2 VCC

350 V

PD = 4000 W 2

TURN−ON (FORWARD BIAS) SOA

TURN−ON ton ≤ 10 ms

TURN−ON DUTY CYCLE ≤ 10%

TURN−OFF (REVERSE BIAS) SOA

TURN−OFF 1.5 V ≤ VBE(off) ≤ 9.0 V

TURN−OFF DUTY CYCLE ≤ 10%

24 A

12 A

TC = 100°C

TURN−OFF

TURN−ON

VCC 400 V 1700 V 1

COLLECTOR VOLTAGE

TURN−OFF (REVERSE BIAS) SOA

TURN−OFF 1.5 V ≤ VBE(off) ≤ 9.0 V

TURN−OFF DUTY CYCLE ≤ 10%

350 V

PD = 4000 W 2

TURN−ON (FORWARD BIAS) SOA

TURN−ON ton ≤ 10 ms

TURN−ON DUTY CYCLE ≤ 10%

IC

VCE

VCC

t

VCC+

N(Vo)

LEAKAGE

SPIKE

TIME

toff

ton

IC

VCE

ton

toff

t

VCC

2 VCC

IC

VCE

ton toff

t

VCC

A

B

C

D

Table 2. Applications Examples of Switching Circuits

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9

Table 3. Typical Inductive Switching Performance

ÎÎÎ

Î

ÎÎ

ÎÎÎ

IC

AMP

ÎÎÎ

ÎÎ

Î

ÎÎÎ

TC

_C

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

tsv

ns

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

trv

ns

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

tfi

ns

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

tti

ns

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

tc

ns

ÎÎÎ

3

ÎÎÎ

25

100

ÎÎÎÎ

770

1000

ÎÎÎÎ

100

230

ÎÎÎÎ

150

160

ÎÎÎÎ

200

ÎÎÎÎ

240

320

ÎÎÎ

Î

ÎÎ

ÎÎÎ

5

ÎÎÎ

ÎÎ

Î

ÎÎÎ

25

100

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

630

820

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

72

100

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

26

55

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

10

30

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

100

180

ÎÎÎ

Î

ÎÎ

ÎÎÎ

8

ÎÎÎ

ÎÎ

Î

ÎÎÎ

25

100

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

720

920

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

55

70

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

27

50

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

2

8

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

77

120

ÎÎÎ

12

ÎÎÎ

25

100

ÎÎÎÎ

640

800

ÎÎÎÎ

20

32

ÎÎÎÎ

17

24

ÎÎÎÎ

2

4

ÎÎÎÎ

41

54

NOTE: All Data recorded In the Inductive Switching Circuit In Table 1.

SWITCHING TIME NOTES

In resistive switching circuits, rise, fall, and storage times

have been defined and apply to both current and voltage

waveforms since they are in phase. However , for inductive

loads which are common to SWITCHMODE power

supplies and hammer drivers, current and voltage

waveforms are not in phase. Therefore, separate

measurements must be made on each waveform to

determine the total switching time. For this reason, the

following new terms have been defined.

tsv = Voltage Storage Time, 90% IB1 to 10% VCEM

trv = Voltage Rise Time, 10−90% VCEM

tfi = Current Fall Time, 90−10% ICM

tti = Current Tail, 10−2% ICM

tc = Crossover Time, 10% VCEM to 10% ICM

An enlarged portion of the turn−off waveforms is shown

in Figure 13 to aid in the visual identity of these terms.

For the designer, there is minimal switching loss during

storage time and the predominant switching power losses

occur during the crossover interval and can be obtained

using the standard equation from AN222/D:

PSWT = 1/2 VCCIC(tc) f

Typical inductive switching waveforms are shown in

Figure 14. In general, trv + tfi ] tc. However, at lower test

currents this relationship may not be valid.

As is common with most switching transistors, resistive

switching is specified at 25_C and has become a benchmark

for designers. However, for designers of high frequency

converter circuits, the user oriented specifications which

make this a “SWITCHMODE” transistor are the inductive

switching speeds (tc and tsv) which are guaranteed at 100_C.

MJE13009

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10

PACKAGE DIMENSIONS

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL

BODY AND LEAD IRREGULARITIES ARE

ALLOWED.

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.570 0.620 14.48 15.75

B0.380 0.405 9.66 10.28

C0.160 0.190 4.07 4.82

D0.025 0.035 0.64 0.88

F0.142 0.147 3.61 3.73

G0.095 0.105 2.42 2.66

H0.110 0.155 2.80 3.93

J0.018 0.025 0.46 0.64

K0.500 0.562 12.70 14.27

L0.045 0.060 1.15 1.52

N0.190 0.210 4.83 5.33

Q0.100 0.120 2.54 3.04

R0.080 0.110 2.04 2.79

S0.045 0.055 1.15 1.39

T0.235 0.255 5.97 6.47

U0.000 0.050 0.00 1.27

V0.045 −−− 1.15 −−−

Z−−− 0.080 −−− 2.04

B

Q

H

Z

L

V

G

N

A

K

F

123

4

D

SEATING

PLANE

−T−

C

S

T

U

R

J

TO−220AB

CASE 221A−09

ISSUE AA

STYLE 1:

PIN 1. BASE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

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