Advanced Power Electronics Corp. AP1260MP Peak 2.5A Sink/Source Bus Termination Regulator Features Description The AP1260MP is a simple, cost-effective and Ideal for DDR-I, DDR-II and DDR-III VTT Applications high-speed linear regulator designed to generate Sink and Source peak 2.5A for DDRI, DDRII and termination voltage in double data rate (DDR) DDRIII. memory system to comply with the JEDEC SSTL_2 Integrated Power MOSFETs and SSTL_18 or other specific interfaces such as Generates Termination Voltage for SSTL_2, SSTL HSTL, SCSI-2 and SCSI-3 etc. devices requirements. _18, HSTL, SCSI-2 and SCSI-3 Interfaces. The regulator is capable of actively sinking or sourcing High Accuracy Output Voltage at Full-Load up to 2.5A transient peak current while regulating an Output Adjustment by Two External Resistors output voltage to within 40mV. The output termination Low External Component Count voltage can be tightly regulated to track 1/2VDDQ by Shutdown for Suspend to RAM (STR) Functionality two external voltage divider resistors or the desired with High-Impedance Output output voltage can be programmed by externally Current Limiting Protection forcing the REFEN pin voltage. On-Chip Thermal Protection The AP1260MP also incorporates a high-speed Available in ESOP-8 (Exposed Pad) Packages differential amplifier to provide ultra-fast response in VIN and VCNTL No Power Sequence Issue line/load transient. Other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. The AP1260MP are available in the ESOP-8 (Exposed Pad) surface mount packages. Pin Configuration 100% Lead (Pb)-Free Application Desktop PCs, Notebooks, and Workstations Graphics Card Memory Termination Set Top Boxes, Digital TVs, Printers Embedded Systems Active Termination Buses DDR-I, DDR-II & DDRIII Memory Systems Block Diagram ESOP-8 (MP) (Top View) VIN GND REFEN VOUT 1 8 NC 2 7 GND 3 6 4 5 NC VCNTL NC Pin Description Pin Name Pin function VIN Power Input GND Ground VCNTL Gate Drive Voltage REFEN Reference Voltage input and Chip Enable VOUT Output Voltage 1 200811123 Advanced Power Electronics Corp. AP1260MP Peak 2.5A Sink/Source Bus Termination Regulator Absolute Maximum Rating (1) Parameter Symbol Value Unit Input Voltage VIN 6 V Control Voltage VCNTL 6 V Power Dissipation PD Internally Limited -- ESD Rating -- 2 KV Storage Temperature Range TS -65 to 150 C Lead Temperature (Soldering, 5 sec.) TLEAD 260 C Package Thermal Resistance JC 28 C/W Operating Rating(2) Parameter Symbol Value Units Input Voltage VIN 2.5V to 1.5V 3% V Control Voltage VCNTL 5.0 or 3.3 5% V Ambient Temperature TA -40 to +85 Junction Temperature TJ -40 to +125 Electrical Characteristics VIN=1.8V, VCNTL=3.3V, VREFEN=0.9V, COUT=10F (Ceramic)), TA=25C, unless otherwise specified Parameter Symbol Test Conditions Min Typ Max Units VCNTL Operation Current ICNTL IOUT=0A -- 1 3 mA Standby Current ISTBY VREFEN < 0.2V (Shutdown),RLOAD = 180 -- 50 90 A Output Offset Voltage(3) VOS VLOAD IOUT= 0A -20 -- +20 mV IOUT= +2A -20 -- +20 2.5 -- -- Input Output Load Regulation (4) IOUT= -2A Protection Current limit ILIM Thermal Shutdown Temperature TSD TSD 3.3V VCNTL 5V -- 170 -- 3.3V VCNTL 5V -- 35 -- VIH Enable 0.6 -- -- VIL Shutdown -- -- 0.2 Thermal Shutdown Hysteresis A REFEN Shutdown Shutdown Threshold V Note 1: Exceeding the absolute maximum rating may damage the device. Note 2: VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN Note 3: VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN. Note 4: Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load regulation in the load range from 0A to 2A. 2 Advanced Power Electronics Corp. AP1260MP Peak 2.5A Sink/Source Bus Termination Regulator Typical Operating Characteristics 3 Advanced Power Electronics Corp. AP1260MP Peak 2.5A Sink/Source Bus Termination Regulator Application Information Thermal Consideration Input Capacitor and Layout Consideration AP1260MP regulators have internal thermal limiting Place the input bypass capacitor as close as possible to the AP1260MP. A low ESR capacitor larger than 470uF is recommended for the input capacitor. Use short and wide traces to minimize parasitic resistance and inductance. circuitry designed to protect the device during overload conditions.For continued operation, do not exceed maximum operation junction temperature 125. The power dissipation definition in device is: PD = (VIN - VOUT) x IOUT + VIN x IQ Inappropriate layout may result in large parasitic inductance and cause undesired oscillation between AP1260MP and the preceding powe converter. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature Consideration while designs the resistance of difference between junction to ambient. The voltage divider maximum power dissipation can be calculated by Make sure the sinking current capability of following formula: pull-down NMOS if the lower resistance was PD(MAX) = ( TJ(MAX) -TA ) /JA chosen so that the voltage on VREFEN is below 0.2V. In addition, the capacitor and voltage divider form Where TJ(MAX) is the maximum operation junction the lowpass filter. There are two reasons doing this temperature 125, TA is the ambient temperature design; one is for output voltage soft-start while and the JA is the junction to ambient thermal another is for noise immunity. resistance. The junction to ambient thermal resistance (JA is layout dependent) for ESOP-8 package (Exposed Pad) is 75/W on standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The maximum power dissipation at TA = 25 can be calculated by following formula: PD(MAX) = (125 - 25) / 75/W = 1.33W The thermal resistance JA of ESOP-8 (Exposed Pad) is determined by the package design and the PCB design. However, the package design has been decided. If possible, it's useful to increase thermal performance by the PCB design. The thermal resistance can be decreased by adding copper under the expose pad of ESOP-8 package. We have to consider the copper couldn't stretch infinitely and avoid the tin overflow. 4 Advanced Power Electronics Corp. AP1260MP Peak 2.5A Sink/Source Bus Termination Regulator Application Diagram R1 = R2 = 100K, RTT = 50/33/25 COUT, min = 10F (Ceramic) + 1000F under the worst case testing condition RDUMMY = 1k as for VOUT discharge when VIN is not present but VCNTL is present CSS = 1F, CIN = 470F(Low ESR), CCNTL = 47F 5 ADVANCED POWER ELECTRONICS CORP. Package Outline : ESOP-8 P Millimeters Q B A2 SYMBOLS MIN NOM MAX A 5.80 6.00 6.20 B 4.80 4.90 5.00 C 3.80 3.90 4.00 D 0 4 8 E 0.40 0.65 0.90 F 0.19 0.22 0.25 M 0.00 0.08 0.15 H 0.35 0.42 0.49 L 1.35 1.55 1.75 J 0.375 REF. K 45 G 1.27 TYP. P 2.15 2.25 2.35 Q 2.15 2.25 2.35 L I J 1.All Dimension Are In Millimeters. 2.Dimension Does Not Include Mold Protrusions. Part Marking Information & Packing : ESOP-8 Part Number Package Code 1260MP YWWSSS Date Code (YWWSSS) YLast Digit Of The Year WWWeek SSSSequence 6