CS42406 24-Bit, 192 kHz 2-In 6-Out Audio CODEC D/A Features A/D Features 24-Bit Conversion 102 dB Dynamic Range at 5 V -91 dB THD+N Digital Volume Control with Soft Ramp 24-Bit Conversion 105 dB Dynamic Range at 5 V -98 dB THD+N Advanced Multi-Bit Delta-Sigma Architecture High Pass Filter to Remove DC Offsets Auto-Mode Selection - 119 dB Attenuation - 1 dB Step Size - Zero Crossing Click-Free Transitions ATAPI Mixing Low Clock Jitter Sensitivity Popguard Technology(R) for Control of Clicks and Pops Serial Audio Input/Output Internal Voltage Reference Volume Controls Mixers Level Translator VA = 3.3 V to 5 V Register / Hardware Configuration PCM Serial Interface VLS 1.8 V to 5 V Level Translator PDN/Reset Direct interface with 5 V to 1.8 V logic levels Supports Multiple Sample Rate Operation Operation as Clock Master or Slave Supports all Audio Sample Rates Including 192 kHz Single-Ended Inputs/Outputs Analog/Digital Core Supplies From 3.3 V to 5V VD = 3.3 V to 5 V VLC = 1.8 V to 5 V Hardware or I2C/SPI Control Data System Features Interpolation Filters External Mute Control Modulators Switched Capacitor DACs and Filters Mute Controls Analog Outputs High Pass Filter Anti-Alias Filter Multibit Oversampling ADC Left Input High Pass Filter Anti-Alias Filter Multibit Oversampling ADC Right Input Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. http://www.cirrus.com Copyright (c) Cirrus Logic, Inc. 2004 (All Rights Reserved) MAR `04 DS614PP2 1 CS42406 Stand Alone Mode Feature Set System features - ADC serial audio port master or slave operation - Independent ADC and DAC reset/power-down - 256x or 384x MCLK/LRCK ratio selectable D/A features - Auto-mute on static samples - 44.1 kHz 50/15 s de-emphasis available - Selectable serial audio interface formats Left justified up to 24-bit data IS up to 24-bit data Right justified, 16-bit data Right justified, 24-bit data A/D features - Serial audio port master or slave operation - Auto-mode select in slave mode - High-pass filter - Selectable serial audio interface formats Left justified up to 24-bit IS up to 24-bit data Control Port Mode Feature Set D/A features - Selectable auto-mute - Selectable 32, 44.1, and 48 kHz de-emphasis filters - Configurable ATAPI mixing functions - Configurable volume and muting controls - Selectable serial audio interface formats Left justified up to 24-bit IS up to 24-bit Right justified 16, 18, 20, and 24-bit 2 General Description The CS42406 is a low cost, integrated audio CODEC. The CS42406 performs stereo analog-todigital (A/D) conversion and six channels of digitalto-analog (D/A) conversion of up to 24-bit serial values at sample rates up to 200 kHz. The D/A offers a volume control that operates with a 1 dB step size. It incorporates selectable soft ramp and zero crossing transition functions to eliminate clicks and pops. The D/A's integrated digital mixing functions allow a variety of output configurations ranging from a channel swap to a stereo-to-mono down-mix. Standard 50/15 s de-emphasis is available for sampling rates of 32, 44.1, and 48 kHz for compatibility with digital audio programs mastered using the 50/15 s pre-emphasis technique. Integrated level translators allow easy interfacing between the CS42406 and other devices operating over a wide range of logic levels. High-pass filters are available for the right and left channel of the A/D. This allows the A/D to remove unwanted DC offsets. The CS42406's wide dynamic range, negligible distortion, and low noise make it ideal for applications such as A/V receivers, DVD receivers, settop box systems, and automotive audio systems. ORDERING INFORMATION CS42406-CQ -10 to 70 C CS42406-DQ -40 to 85 C CDB42406 48-pin LQFP 48-pin LQFP Evaluation Board DS614PP2 CS42406 TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................... 6 2 CHARACTERISTICS AND SPECIFICATIONS ......................................................................... 8 SPECIFIED OPERATING CONDITIONS ................................................................................. 8 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 8 DAC ANALOG CHARACTERISTICS (CS42406-CQ) .............................................................. 9 DAC ANALOG CHARACTERISTICS (CS42406-DQ) ............................................................ 11 DAC FILTER RESPONSE...................................................................................................... 13 ADC ANALOG CHARACTERISTICS (CS42406-CQ) ............................................................ 16 ADC ANALOG CHARACTERISTICS (CS42406-DQ) ............................................................ 18 ADC DIGITAL FILTER RESPONSE....................................................................................... 20 DC ELECTRICAL CHARACTERISTICS ................................................................................ 23 DIGITAL CHARACTERISTICS............................................................................................... 24 SWITCHING CHARACTERISTICS - DAC SERIAL AUDIO PORT ........................................ 25 SWITCHING CHARACTERISTICS - ADC SERIAL AUDIO PORT ........................................ 27 SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE ....................................... 30 3. TYPICAL CONNECTION DIAGRAM .................................................................................... 32 4. APPLICATIONS ..................................................................................................................... 33 4.1 Single, Double, and Quad-Speed Modes ........................................................................ 33 4.1.1 ADC Serial Port ................................................................................................... 33 4.1.2 DAC Serial Port ................................................................................................... 33 4.1.2a Stand Alone Mode ............................................................................... 33 4.1.2b Control Port Mode ................................................................................ 34 4.2 ADC Serial Port Operation as Either a Clock Master or Slave ........................................ 34 4.2.1 Operation as a Clock Master .............................................................................. 34 4.2.2 Operation as a Clock Slave ................................................................................ 35 4.3 Digital Interface Format ................................................................................................... 35 4.3.1 DAC Serial Port ................................................................................................... 35 4.3.1a Stand Alone Mode ............................................................................... 36 4.3.1b Control Port Mode ............................................................................... 36 4.3.2 ADC Serial Port ................................................................................................... 36 4.4 De-Emphasis Control ...................................................................................................... 36 4.4.1 Stand Alone Mode .............................................................................................. 36 4.4.2 Control Port Mode ............................................................................................... 36 4.5 Analog Connections ........................................................................................................ 37 4.5.1 Capacitor Size on the Reference Pin (FILT+) ..................................................... 37 4.6 Recommended Power-up Sequence ............................................................................... 38 4.6.1 Stand Alone Mode .............................................................................................. 38 4.6.2 Control Port Mode ............................................................................................... 38 4.7 Popguard(R) Transient Control .......................................................................................... 38 4.7.1 Power-up ............................................................................................................. 38 4.7.2 Power-down ........................................................................................................ 38 4.7.3 Discharge Time ................................................................................................... 38 4.8 Mute Control .................................................................................................................... 39 4.9 Grounding and Power Supply Arrangements .................................................................. 39 4.9.1 Capacitor Placement ........................................................................................... 39 4.10 Control Port Interface .................................................................................................... 39 4.10.1 Memory Address Pointer (MAP) ....................................................................... 39 4.10.1a INCR (Auto Map Increment) .............................................................. 40 4.10.1b MAP0-3 (Memory Address Pointer) ................................................... 40 4.10.2 IC Mode ........................................................................................................... 40 4.10.2a IC Write ............................................................................................. 40 3 CS42406 4.10.2b IC Read ............................................................................................. 40 4.10.3 SPI Mode .......................................................................................................... 41 4.10.3a SPI Write ............................................................................................ 41 5. REGISTER QUICK REFERENCE ......................................................................................... 43 6. REGISTER DESCRIPTIONS .................................................................................................. 44 6.1 Mode Control 1 (address 01h) ......................................................................................... 44 6.2 Invert Signal (address 02h).............................................................................................. 45 6.3 Mixing Control Pair 1 (Channels A1 & B1) (address 03h) Mixing Control Pair 2 (Channels A2 & B2) (address 04h) Mixing Control Pair 3 (Channels A3 & B3) (address 05h) ............................................. 45 6.4 Volume Control (addresses 06h - 0Bh) ............................................................................ 47 6.5 Mode Control 2 (address 0Ch).......................................................................................... 47 7 PARAMETER DEFINITIONS ................................................................................................... 50 8. PACKAGE DIMENSIONS ....................................................................................................... 51 9. REVISION HISTORY .............................................................................................................. 52 LIST OF FIGURES Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. 4 Output Test Load ......................................................................................................... 10 Maximum Loading ........................................................................................................ 10 Single-Speed Stopband Rejection ............................................................................... 14 Single-Speed Transition Band ..................................................................................... 14 Single-Speed Transition Band (Detail) ......................................................................... 14 Single-Speed Passband Ripple ................................................................................... 14 Double-Speed Stopband Rejection .............................................................................. 14 Double-Speed Transition Band .................................................................................... 14 Double-Speed Transition Band (Detail) ....................................................................... 15 Double-Speed Passband Ripple .................................................................................. 15 Single-Speed Mode Stopband Rejection ..................................................................... 21 Single-Speed Mode Stopband Rejection ..................................................................... 21 Single-Speed Mode Transition Band (Detail) ............................................................... 21 Single-Speed Mode Passband Ripple ......................................................................... 21 Double-Speed Mode Stopband Rejection .................................................................... 21 Double-Speed Mode Stopband Rejection .................................................................... 21 Double-Speed Mode Transition Band (Detail) ............................................................. 22 Double-Speed Mode Passband Ripple ........................................................................ 22 Quad-Speed Mode Stopband Rejection ...................................................................... 22 Quad-Speed Mode Stopband Rejection ...................................................................... 22 Quad-Speed Mode Transition Band (Detail) ................................................................ 22 Quad-Speed Mode Passband Ripple ........................................................................... 22 DAC Serial Audio Port .................................................................................................. 26 Master Mode, Left Justified SAI ................................................................................... 28 Slave Mode, Left Justified SAI ..................................................................................... 28 Master Mode, IS SAI ................................................................................................... 28 Slave Mode, IS SAI ..................................................................................................... 28 Left Justified up to 24-Bit Data ..................................................................................... 29 IS, up to 24-Bit Data .................................................................................................... 29 Right Justified Data ...................................................................................................... 29 Control Port Timing - IC Mode .................................................................................... 30 Control Port Timing - SPI Mode ................................................................................... 31 DS614PP2 CS42406 Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Typical Connection Diagram ........................................................................................ 32 ADC Serial Port, Master Mode Clocking ...................................................................... 35 De-Emphasis Curve ..................................................................................................... 36 CS42406 Recommended Analog Input Buffer ............................................................. 37 CS42406 ADC: THD+N versus Frequency .................................................................. 37 IC Write ....................................................................................................................... 40 IC Read ....................................................................................................................... 41 SPI Write ...................................................................................................................... 42 ATAPI Block Diagram .................................................................................................. 46 LIST OF TABLES Table 1. ADC Speed Modes and the Associated Output Sample Rates (Fs) for 256x Mode .......... 33 Table 2. ADC Speed Modes and the Associated Output Sample Rates (Fs) for 384x Mode .......... 33 Table 3. CS42406 Stand Alone DAC Operational Modes ................................................................ 34 Table 4. CS42406 Control Port DAC Operational Modes ................................................................ 34 Table 5. CS42406 ADC Serial Port Mode Control ........................................................................... 34 Table 6. DAC Digital Interface Format - Stand Alone Mode............................................................. 36 Table 7. Digital Interface Formats - Control Port Mode.................................................................... 44 Table 8. ATAPI Decode.................................................................................................................... 46 Table 9. Example Digital Volume Settings ....................................................................................... 47 Table 10. Revision History ............................................................................................................... 52 5 CS42406 AOUTA2 AOUTA1 AOUTB1 MUTEC2 TST MUTEC1 VLS ADC_M0 ADC_M1 PIN DESCRIPTION SDIN3 SDIN2 SDIN1 1. 48 47 46 45 44 43 42 41 40 39 38 37 DAC_SCLK DAC_LRCK 1 36 AOUTB2 2 MCLK 3 35 34 ADC_FILT+ VLS 4 33 GND SDOUT ADC_384x/256x VD 5 32 VA 31 GND 30 AOUTA3 6 GND 7 8 VD 9 CS42406 29 AOUTB3 28 MUTEC3 TST 26 25 13 14 15 16 17 18 19 20 21 22 23 24 AINR ADC_VQ AINL 27 11 12 DAC_FILT+ DAC_VQ TST 10 VLC DAC_M1 ADC_PDN TST TST DAC_RST ADC_SCLK ADC_LRCK DIF1/SCL/CCLK DIF0/SDA/CDIN DAC_M0/AD0/CS TST Pin Name # Pin Description DAC_SCLK 1 DAC Serial Clock (Input) - Serial clock for the DAC serial audio interface. DAC_LRCK 2 DAC Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the DAC serial audio data line. MCLK 3 Master Clock (Input) - Clock source for the delta-sigma modulators and digital filters. VLS 4 45 Serial Audio Interface Power (Input) - Positive power for the serial audio interface. SDOUT 5 Serial Audio Data Output (Output) - Output for two's complement serial audio data. ADC_384x/256x 6 ADC MCLK/LRCK Ratio Select (Input) - Selects the base MCLK/LRCK ratio for the ADC serial port. VD 7 9 Digital Power (Input) - Positive power supply for the digital section. GND 8 31 33 Ground (Input) RST_DAC 10 DAC Reset (Input) - Powers down the DAC and resets all internal resisters to their default settings. ADC_SCLK 11 ADC Serial Clock (Input/Output) - Serial clock for the ADC serial audio interface. ADC_LRCK 12 ADC Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the ADC serial audio data line. VLC 16 Control Port Interface Power (Input) - Positive power for the control port interface. ADC_PDN 18 ADC Power-Down (Input) - The ADC enters a low power mode when low. TST 6 19,20 Test Pin (Input) - Connect to GND. 23,27 35,42 DS614PP2 CS42406 DAC_FILT+ 21 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. DAC_VQ 22 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. AINL AINR 24 26 Analog Inputs (Input) - The full scale analog input level is specified in the "ADC Analog Characteristics (CS42406-CQ)" on page 16. ADC_VQ 25 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. AOUTB3 AOUTA3 AOUTB2 AOUTA2 AOUTB1 AOUTA1 29 30 36 37 39 40 Analog Outputs (Output) - The full scale analog line output level is specified in the "DAC ANALOG CHARACTERISTICS (CS42406-CQ)" on page 9. MUTEC3 MUTEC2 MUTEC1 28 38 41 Mute Control (Output) - Control signals for optional mute circuit. VA 32 Analog Power (Input) - Positive power supply for the analog section. ADC_FILT+ 34 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. ADC_M1 ADC_M0 43 44 ADC Mode Selection (Input) - Determines the operational speed mode of the ADC. SDIN1 SDIN2 SDIN3 46 47 48 Serial Audio Data Input (Input) - Input for two's complement serial audio data. SCL/CCLK 13 Serial Control Port Clock (Input) - Serial clock for the control port interface. SDA/CDIN 14 Serial Control Data I/O (Input/Output) - Input/Output for IC data. Input for SPI data. AD0/CS 15 Address Bit / Chip Select (Input) - Chip address bit in IC Mode. Control signal used to select the chip in SPI mode. DIF1 DIF0 13 14 Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial Clock and Serial Audio Data for the DAC. DAC_M0 DAC_M1 15 17 Mode Selection (Input) - Determines the operational speed mode of the DAC. DAC Control Port Definitions DAC Stand Alone Definitions 7 CS42406 2 CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at typical supply voltages and TA = 25C.) SPECIFIED OPERATING CONDITIONS (GND = 0 V, all voltages with respect to 0 V.) Parameter Power Supplies Analog Digital (Note 2) Logic/Serial Interface Control Port Interface Ambient Temperature Commercial Automotive -CQ -DQ Symbol Min Typ Max Unit VA VD VLS VLC 3.1 3.1 1.7 1.7 (Note 1) 3.3 3.3 3.3 5.25 5.25 5.25 5.25 V V V V TA -10 -40 - +70 +85 C C Notes: 1. This part is specified at typical analog voltages of 3.3 V and 5.0 V. See DAC ANALOG CHARACTERISTICS (CS42406-CQ)/(CS42406-DQ) and ADC Analog Characteristics (CS42406CQ)/(CS42406-DQ) Applications, for details. 2. Nominal VD supply must be less than or equal to the nominal VA supply. ABSOLUTE MAXIMUM RATINGS (GND = 0 V, All voltages with respect to ground.) (Note 5) Parameter DC Power Supplies: Analog Digital Serial Audio Interface (SAI) Control Port Interface Symbol Min Max Units VA VD VLS VLC -0.3 -0.3 -0.3 -0.3 +6.0 +6.0 +6.0 +6.0 V V V V Input Current (Note 3) Iin - 10 mA Analog Input Voltage (Note 4) VIN GND-0.7 VA+0.7 V -0.3 -0.3 VLS+0.4 VLC+0.4 V V Digital Input Voltage(Note 4) Serial Audio Data Interface VIND_S Control Port Interface VIND_S Ambient Operating Temperature (Power Applied) TA -50 +95 C Storage Temperature Tstg -65 +150 C Notes: 3. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SRC latch-up. 4. The maximum over/under voltage is limited by the input current. 5. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 8 DS614PP2 CS42406 DAC ANALOG CHARACTERISTICS (CS42406-CQ) Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load RL = 10 k, CL = 10 pF (see Figure 1). VA = 5.0 V Parameter Single-Speed Mode Dynamic Range Dynamic Range 40 kHz Bandwidth Total Harmonic Distortion + Noise Dynamic Range 40 kHz Bandwidth Total Harmonic Distortion + Noise Max Min Typ Max Unit 93 96 99 102 - 88 91 94 97 - dB dB - -91 -79 -39 -85 - - -91 -74 -34 -85 - dB dB dB 93 96 - 99 102 100 - 88 91 - 94 97 97 - dB dB dB - -91 -79 -39 -85 - - -91 -74 -34 -85 - dB dB dB 93 96 - 99 102 100 - 88 91 - 94 97 97 - dB dB dB - -91 -79 -39 -85 - - -91 -74 -34 -85 - dB dB dB (Note 6) Fs = 96 kHz (Note 6) unweighted A-Weighted A-Weighted (Note 6) 0 dB -20 dB -60 dB Quad-Speed Mode Typ (Note 6) 0 dB -20 dB -60 dB Double-Speed Mode Min Fs = 48 kHz unweighted A-Weighted Total Harmonic Distortion + Noise VA = 3.3 V Fs = 192 kHz (Note 6) unweighted A-Weighted A-Weighted (Note 6) 0 dB -20 dB -60 dB Notes: 6. One-half LSB of triangular PDF dither is added to data. 9 CS42406 DAC ANALOG CHARACTERISTICS (CS42406-CQ) (Continued) Parameters Symbol Min Typ Max Units - 102 - dB - 0.1 - dB - 100 - ppm/C Dynamic Performance for All Modes Interchannel Isolation (1 kHz) DC Accuracy Interchannel Gain Mismatch ICGM Gain Drift Analog Output Characteristics and Specifications Full Scale Output Voltage 0.60*VA 0.66*VA 0.72*VA Output Impedance Vpp Zout - 100 - Minimum AC-Load Resistance (Note 7) RL - 3 - k Maximum Load Capacitance (Note 7) CL - 100 - pF 7. See Figure 1-2. R L and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively move the dominant pole of the two-pole amp in the output stage. Increasing this value beyond the recommended 100 pF can cause the internal op-amp to become unstable. . 3.3 F AOUTx + V out R L AGND C L Capacitive Load -- C L (pF) 125 100 75 25 2.5 3 Figure 1. Output Test Load 10 Safe Operating Region 50 5 10 15 20 Resistive Load -- RL (k ) Figure 2. Maximum Loading DS614PP2 CS42406 DAC ANALOG CHARACTERISTICS (CS42406-DQ) Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load RL = 10 k, CL = 10 pF (see Figure 1). VA = 5.0 V Parameter Single-Speed Mode Dynamic Range Dynamic Range 40 kHz Bandwidth Total Harmonic Distortion + Noise Dynamic Range 40 kHz Bandwidth Total Harmonic Distortion + Noise Max Min Typ Max Unit 92 95 99 102 - 87 90 94 97 - dB dB - -91 -79 -39 -84 - - -91 -74 -34 -84 - dB dB dB 92 95 - 99 102 100 - 87 90 - 94 97 97 - dB dB dB - -91 -79 -39 -84 - - -91 -74 -34 -84 - dB dB dB 92 95 - 99 102 100 - 87 90 - 94 97 97 - dB dB dB - -91 -79 -39 -84 - - -91 -74 -34 -84 - dB dB dB (Note 6) Fs = 96 kHz (Note 6) unweighted A-Weighted A-Weighted (Note 6) 0 dB -20 dB -60 dB Quad-Speed Mode Typ (Note 6) 0 dB -20 dB -60 dB Double-Speed Mode Min Fs = 48 kHz unweighted A-Weighted Total Harmonic Distortion + Noise VA = 3.3 V Fs = 192 kHz (Note 6) unweighted A-Weighted A-Weighted (Note 6) 0 dB -20 dB -60 dB 11 CS42406 DAC ANALOG CHARACTERISTICS (CS42406-DQ) (Continued) Parameters Symbol Min Typ Max Units - 102 - dB - 0.1 - dB - 100 - ppm/C Dynamic Performance for All Modes Interchannel Isolation (1 kHz) DC Accuracy Interchannel Gain Mismatch ICGM Gain Drift Analog Output Characteristics and Specifications Full Scale Output Voltage 0.60*VA 0.66*VA 0.72*VA Output Impedance 12 Vpp Zout - 100 - Minimum AC-Load Resistance (Note 7) RL - 3 - k Maximum Load Capacitance (Note 7) CL - 100 - pF DS614PP2 CS42406 DAC FILTER RESPONSE The filter characteristics and the X-axis of the response plots have been normalized to the input sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. Parameter Min Typ Max Unit 0 0 - 0.4535 0.4998 Fs Fs -0.02 - +0.035 dB Single-Speed Mode - (4 kHz to 50 kHz sample rates) Passband to -0.05 dB corner to -3 dB corner Passband Ripple StopBand 0.5465 - - Fs 50 - - dB - 9/Fs - s Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz - - +0.2/-0.1 +0.05/-0.14 +0/-0.22 dB dB dB Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz - - +1.5/-0 +0.05/-0.14 +0.2/-0.4 dB dB dB 0 0 - 0.4621 0.4982 Fs Fs -0.1 - 0 dB 0.577 - - Fs 55 - - dB - 4/Fs - s 0 - 0.25 Fs -0.7 - 0 dB - 1.5/Fs - s StopBand Attenuation (Note 8) Group Delay De-emphasis Error (Relative to 1 kHz) Control Port Mode Stand-Alone Mode (Note 9) Double-Speed Mode - (50 kHz to 100 kHz sample rates) Passband to -0.1 dB corner to -3 dB corner Passband Ripple StopBand StopBand Attenuation (Note 8) Group Delay Quad-Speed Mode - (100 kHz to 200 kHz sample rates) Passband to -3 dB corner Passband Ripple Group Delay Notes: 8. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs. 9. De-emphasis is only available in Single-Speed Mode. 13 CS42406 Figure 3. Single-Speed Stopband Rejection Figure 4. Single-Speed Transition Band Figure 5. Single-Speed Transition Band (Detail) Figure 6. Single-Speed Passband Ripple Figure 7. Double-Speed Stopband Rejection 14 Figure 8. Double-Speed Transition Band DS614PP2 CS42406 Figure 9. Double-Speed Transition Band (Detail) Figure 10. Double-Speed Passband Ripple 15 CS42406 ADC ANALOG CHARACTERISTICS (CS42406-CQ) Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. VA = 5.0 V Parameter Single-Speed Mode Dynamic Range Total Harmonic Distortion + Noise Dynamic Range 40 kHz Bandwidth Total Harmonic Distortion + Noise unweighted A-Weighted Dynamic Range 40 kHz Bandwidth Total Harmonic Distortion + Noise Typ Max Min Typ Max Unit 96 99 102 105 - 93 96 99 102 - dB dB - -98 -82 -42 -92 - - -95 -79 -39 -89 - dB dB dB 96 99 - 102 105 99 - 93 96 - 99 102 96 - dB dB dB - -98 -82 -42 -92 - - -95 -79 -39 -89 - dB dB dB 96 99 - 102 105 99 - 93 96 - 99 102 96 - dB dB dB - -98 -82 -42 -92 - - -95 -79 -39 -89 - dB dB dB (Note 10) Fs = 96 kHz unweighted A-Weighted unweighted (Note 10) -1 dB -20 dB -60 dB Quad-Speed Mode Min Fs = 48 kHz -1 dB -20 dB -60 dB Double-Speed Mode VA = 3.3 V Fs = 192 kHz unweighted A-Weighted unweighted (Note 10) -1 dB -20 dB -60 dB Note: 10. Referred to the typical full-scale input voltage 16 DS614PP2 CS42406 ADC ANALOG CHARACTERISTICS (CS42406-CQ) (Continued) Parameters Min Typ Max Units - 90 - dB Interchannel Gain Mismatch - 0.1 - dB Gain Error - - 10 % Gain Drift - 100 - ppm/C Dynamic Performance for All Modes Interchannel Isolation DC Accuracy Analog Input Characteristics Full Scale Input Voltage Input Impedance 0.53*VA 0.56*VA 0.59*VA 18 - - Vpp k 17 CS42406 ADC ANALOG CHARACTERISTICS (CS42406-DQ) Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. VA = 5.0 V Parameter Single-Speed Mode Dynamic Range Total Harmonic Distortion + Noise Dynamic Range 40 kHz Bandwidth Total Harmonic Distortion + Noise unweighted A-Weighted Dynamic Range 40 kHz Bandwidth Total Harmonic Distortion + Noise Typ Max Min Typ Max Unit 94 97 102 105 - 91 94 99 102 - dB dB - -98 -82 -42 -90 - - -95 -79 -39 -87 - dB dB dB 94 97 - 102 105 99 - 91 94 - 99 102 96 - dB dB dB - -98 -82 -42 -90 - - -95 -79 -39 -87 - dB dB dB 94 97 - 102 105 99 - 91 94 - 99 102 96 - dB dB dB - -98 -82 -42 -90 - - -95 -79 -39 -87 - dB dB dB (Note 11) Fs = 96 kHz unweighted A-Weighted unweighted (Note 11) -1 dB -20 dB -60 dB Quad-Speed Mode Min Fs = 48 kHz -1 dB -20 dB -60 dB Double-Speed Mode VA = 3.3 V Fs = 192 kHz unweighted A-Weighted unweighted (Note 11) -1 dB -20 dB -60 dB 11. Referred to the typical full-scale input voltage 18 DS614PP2 CS42406 ADC ANALOG CHARACTERISTICS (CS42406-DQ) (Continued) Parameters Min Typ Max Units - 90 - dB Interchannel Gain Mismatch - 0.1 - dB Gain Error - - 10 % Gain Drift - 100 - ppm/C Dynamic Performance for All Modes Interchannel Isolation DC Accuracy Analog Input Characteristics Full Scale Input Voltage Input Impedance 0.50*VA 0.56*VA 0.62*VA 18 - - Vpp k 19 CS42406 ADC DIGITAL FILTER RESPONSE The filter characteristics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. Parameter Min Typ Max Unit 0 - 0.49 Fs - - 0.035 dB 0.57 - - Fs 70 - - dB - 12/Fs - s 0 - 0.49 Fs Single-Speed Mode (4 kHz to 50 kHz sample rates) Passband to -0.1 dB corner Passband Ripple Stopband Stopband Attenuation Total Group Delay Double-Speed Mode (50 kHz to 100 kHz sample rates) Passband to -0.1 dB corner Passband Ripple Stopband Stopband Attenuation Total Group Delay - - 0.025 dB 0.56 - - Fs 69 - - dB - 9/Fs - s 0 - 0.26 Fs - - 0.025 dB 0.50 - - Fs 60 - - dB - 5/Fs - s - 1 20 - Hz Hz - 10 - Deg - - 0 dB Quad-Speed Mode (100 kHz to 200 kHz sample rates) Passband to -0.1 dB corner Passband Ripple Stopband Stopband Attenuation Total Group Delay High Pass Filter Characteristics Frequency Response -3.0 dB -0.13 dB (Note 12) Phase Deviation (Note 12) @ 20 Hz Passband Ripple Note: 12. Response shown is for Fs equal to 48 kHz. 20 DS614PP2 0 0 -10 -20 -30 -10 -20 -30 -40 -50 -60 -70 -40 -50 -60 -70 Amplitude (dB) Amplitude (dB) CS42406 -80 -90 -100 -110 -80 -90 -100 -110 -120 -130 -120 -130 -140 0.40 0.42 0.44 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.54 0.56 0.58 0.60 Figure 12. Single-Speed Mode Stopband Rejection 0 0.10 -1 0.08 -2 0.06 Amplitude (dB) Amplitude (dB) Figure 11. Single-Speed Mode Stopband Rejection -3 -4 -5 -6 -7 0.04 0.02 0.00 -0.02 -0.04 -8 -0.06 -9 -0.08 -0.10 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0 0.55 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (norm alized to Fs) Frequency (norm alized to Fs) Figure 13. Single-Speed Mode Transition Band (Detail) Figure 14. Single-Speed Mode Passband Ripple 0 0 -10 -20 -30 -10 -20 -30 -40 -50 -60 -70 -40 -50 -60 -70 Amplitude (dB) Amplitude (dB) 0.52 Frequency (norm alized to Fs) Frequency (norm alized to Fs) -10 0.45 0.46 0.48 0.50 -80 -90 -100 -110 -120 -130 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (norm alized to Fs) Figure 15. Double-Speed Mode Stopband Rejection -140 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 Frequency (norm alized to Fs) Figure 16. Double-Speed Mode Stopband Rejection 21 0 0.10 -1 0.08 -2 0.06 Amplitude (dB) Amplitude (dB) CS42406 -3 -4 -5 -6 -7 0.04 0.02 0.00 -0.02 -0.04 -8 -0.06 -9 -0.08 -10 0.46 0.47 0.48 0.49 0.50 0.51 -0.10 0.00 0.05 0.52 Frequency (norm alized to Fs) 0 0 -10 -20 -30 -10 -20 -30 -40 -50 -60 -70 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0.20 0.25 0.30 0.35 0.40 0.45 0.50 -80 -90 -100 -110 -120 -130 -140 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 Frequency (norm alized to Fs) Frequency (norm alized to Fs) Figure 19. Quad-Speed Mode Stopband Rejection Figure 20. Quad-Speed Mode Stopband Rejection 0 0.10 -1 0.08 -2 0.06 Amplitude (dB) Amplitude (dB) 0.15 Figure 18. Double-Speed Mode Passband Ripple Amplitude (dB) Amplitude (dB) Figure 17. Double-Speed Mode Transition Band (Detail) -3 -4 -5 -6 0.04 0.02 0.00 -0.02 -7 -0.04 -8 -0.06 -9 -0.08 -10 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (norm alized to Fs) Figure 21. Quad-Speed Mode Transition Band (Detail) 22 0.10 Frequency (norm alized to Fs) -0.10 0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28 Frequency (normalized to Fs) Figure 22. Quad-Speed Mode Passband Ripple DS614PP2 CS42406 DC ELECTRICAL CHARACTERISTICS GND = 0 V; all voltages with respect to GND. Parameters Symbol Min Typ Max Units VA = 5.0 V VD, VLS, VLC = 5.0 V IA IDT - 43 40 48 45 mA mA VA = 3.3 V VD, VLS, VLC = 3.3 V IA IDT - 40 25 44 26 mA mA All Supplies = 5.0 V All Supplies = 3.3 V - 415 215 465 231 mW mW Power Supply Current All Supplies = 5.0 V All Supplies = 3.3 V - 2 1 - mA mA Power Dissipation All Supplies = 5.0 V All Supplies = 3.3 V - 10 3.3 - mW mW - 60 - dB 0.5*VA 250 25 0.01 - k k Maximum allowable DC current source/sink - mA Filt+ Nominal Voltage - VA - V MUTEC Low-Level Output Voltage - 0 - V MUTEC High-Level Output Voltage - VA - V Maximum MUTEC Drive Current - 3 - mA Normal Operation (Note 13) Power Supply Current (Note 14) Power Dissipation Power-down Mode (Note 15) All Modes of Operation Power Supply Rejection Ratio (Note 16) VQ Nominal Voltage Output Impedance 1 kHz DAC_VQ ADC_VQ PSRR V Notes: 13. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS digital input sampled at the highest Fs for each speed mode, and open outputs, unless otherwise specified. Analog inputs are driven with a 1 kHz, -1 dBFS sine wave and sampled at the highest Fs for each speed mode. 14. IDT measured with no external loading on pin 14 (SDA). 15. Power Down Mode is defined as DAC_RST = LO, PDN_ADC = LO, with all clocks and data lines held static. 16. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 33. 23 CS42406 DIGITAL CHARACTERISTICS GND = 0 V; all voltages with respect to GND. Parameters Input Leakage Current Symbol Min Typ Max Units Iin - - 10 A Input Capacitance - 8 - pF High-Level Input Voltage (% of VLS/VLC) VIH 70% - - V Low-Level Input Voltage (% of VLS/VLC) VIL - - 13% V High-Level Output Voltage at Io = 100 A (% of VLS/VLC) VOH 70% - - V Low-Level Output Voltage at Io =100 A (% of VLS/VLC) VOL - - 15% V 24 DS614PP2 CS42406 SWITCHING CHARACTERISTICS - DAC SERIAL AUDIO PORT (Logic "0" = GND = 0 V, Logic "1" = VLS) Parameter Symbol MCLK Specifications MCLK Frequency Min Typ Max Unit 1.024 - 12.8 MHz 22 - 25.6 MHz MCLK Duty Cycle 45 - 55 % Single-Speed* DAC_LRCK Duty Cycle 45 - 55 % - - 128xFs Hz DAC_SCLK Pulse Width Low tsclkl 20 - - ns DAC_SCLK Pulse Width High tsclkh 20 - - ns DAC_SCLK rising to DAC_LRCK edge delay tslrd 20 ns DAC_SCLK rising to DAC_LRCK edge setup time tslrs 20 ns SDINx valid to DAC_SCLK rising setup time tsdlrs 20 ns DAC_SCLK rising to SDINx hold time tsdh 20 ns DAC_SCLK Frequency Double-Speed* DAC_LRCK Duty Cycle 45 - 55 % DAC_SCLK Frequency - - 64xFs Hz DAC_SCLK Pulse Width Low tsclkl 20 - - ns DAC_SCLK Pulse Width High tsclkh 20 - - ns DAC_SCLK rising to DAC_LRCK edge delay tslrd 20 ns DAC_SCLK rising to DAC_LRCK edge setup time tslrs 20 ns SDINx valid to DAC_SCLK rising setup time tsdlrs 20 ns DAC_SCLK rising to SDINx hold time tsdh 20 ns Quad-Speed* DAC_LRCK Duty Cycle 45 - 55 % DAC_SCLK Frequency - - MCLK/2 Hz DAC_SCLK Pulse Width Low tsclkl 20 - - ns DAC_SCLK Pulse Width High tsclkh 20 - - ns DAC_SCLK rising to DAC_LRCK edge delay tslrd 20 ns DAC_SCLK rising to DAC_LRCK edge setup time tslrs 20 ns SDINx valid to DAC_SCLK rising setup time tsdlrs 20 ns DAC_SCLK rising to SDINx hold time tsdh 20 ns * For a description of Speed Modes, please refer to Section 4.1.2 on page 33. 25 CS42406 DAC_LRCK t t slrd t slrs sclkh t sclkl DAC_SCLK t sdlrs t sdh SDINx Figure 23. DAC Serial Audio Port 26 DS614PP2 CS42406 SWITCHING CHARACTERISTICS - ADC SERIAL AUDIO PORT Logic "0" = GND = 0 V; Logic "1" = VLS, CL = 20 pF Parameter Symbol Min Typ Max Unit 1.024 - 12.8 MHz 22 - 25.6 MHz 45 - 55 % MCLK Specifications MCLK Frequency MCLK Duty Cycle Master Mode ADC_SCLK falling to ADC_LRCK tmslr -20 - 20 ns ADC_SCLK falling to SDOUT valid tsdo 0 - 32 ns - 50 - % 40 50 60 % ADC_SCLK Duty Cycle Slave Mode Single-Speed* ADC_LRCK Duty Cycle ADC_SCLK Period tsclkw 156 - - ns ADC_SCLK Low tsclkl 55 - - ns ADC_SCLK High tsclkh 55 - - ns ADC_SCLK falling to SDOUT valid tdss - - 32 ns ADC_SCLK falling to ADC_LRCK edge tslrd -20 - 20 ns 40 50 60 % tsclkw 156 - - ns Double-Speed* ADC_LRCK Duty Cycle ADC_SCLK Period ADC_SCLK Low tsclkl 55 - - ns ADC_SCLK High tsclkh 55 - - ns ADC_SCLK falling to SDOUT valid tdss - - 32 ns ADC_SCLK falling to ADC_LRCK edge tslrd -20 - 20 ns 40 50 60 % Quad-Speed* ADC_LRCK Duty Cycle ADC_SCLK Period tsclkw 78 - - ns ADC_SCLK Low tsclkl 40 - - ns ADC_SCLK High tsclkh 40 - - ns ADC_SCLK falling to SDOUT valid tdss - - 32 ns ADC_SCLK falling to ADC_LRCK edge tslrd -8 - 8 ns * For a description of Speed Modes, please refer to Table 1 on page 33. 27 CS42406 t sclkh t sclkl ADC_SCLK output ADC_S CLK input t mslr ADC_LRCK input t sdo SDOUT t sclkw t sl rd ADC_LRCK output MSB t lrdss MSB-1 SDOUT Figure 24. Master Mode, Left Justified SAI MSB t dss MSB-1 MSB-2 Figure 25. Slave Mode, Left Justified SAI t sclkh t sclkl ADC_SCLK output ADC_SCLK input t mslr t sclkw ADC_LRCK output t sdo SDOUT ADC_LRCK input t dss MSB SDOUT Figure 26. Master Mode, IS SAI 28 MSB MSB-1 Figure 27. Slave Mode, IS SAI DS614PP2 CS42406 Left Channel LRCK Right Channel SCLK SDIN/SDOUT MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 28. Left Justified up to 24-Bit Data Left Channel LRCK Right Channel SCLK SDIN/SDOUT MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 29. IS, up to 24-Bit Data LRCK Righ t Cha n n el Le ft Ch a nne l SCLK S DIN L SB MSB -1 -2 -3 -4 -5 +7 +6 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 -5 +7 +6 +5 +4 +3 +2 +1 LSB Figure 30. Right Justified Data 29 CS42406 SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE Inputs: Logic 0 = GND, Logic 1 = VLC Parameter Symbol Min Max Unit SCL Clock Frequency fscl - 100 kHz DAC_RST Rising Edge to Start tirs 500 - ns Bus Free Time Between Transmissions tbuf 4.7 - s Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - s Clock Low time tlow 4.7 - s Clock High Time thigh 4.0 - s Setup Time for Repeated Start Condition tsust 4.7 - s thdd 0 - s tsud 250 - ns Rise Time of SCL and SDA trc, trc - 1 s Fall Time SCL and SDA tfc, tfc - 300 ns Setup Time for Stop Condition tsusp 4.7 - s tack - (Note 19) ns IC Mode SDA Hold Time from SCL Falling (Note 17) SDA Setup time to SCL Rising Acknowledge Delay from SCL Falling (Note 18) Notes: 17. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. 18. The acknowledge delay is based on MCLK and can limit the maximum transaction speed. 19. DAC_RST 5 5 5 --------------------- for Single-Speed Mode, --------------------- for Double-Speed Mode, ------------------ for Quad-Speed Mode. 64 x Fs 256 x Fs 128 x Fs t irs Stop Repeated Start Start t rd t fd Stop SDA t buf t t hdst t high t fc hdst t susp SCL t low t hdd t sud t ack t sust t rc Figure 31. Control Port Timing - IC Mode 30 DS614PP2 CS42406 SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE Parameter (Continued) Symbol Min Max Unit CCLK Clock Frequency fsclk - 6 MHz DAC_RST Rising Edge to CS Falling tsrs 500 - ns tspi 500 - ns CS High Time Between Transmissions tcsh 1.0 - s CS Falling to CCLK Edge tcss 20 - ns CCLK Low Time tscl 1 ----------------MCLK - ns CCLK High Time tsch 1 ----------------MCLK - ns CDIN to CCLK Rising Setup Time tdsu 40 - ns SPI Mode CCLK Edge to CS Falling (Note 20) CCLK Rising to DATA Hold Time (Note 21) tdh 15 - ns Rise Time of CCLK and CDIN (Note 22) tr2 - 100 ns Fall Time of CCLK and CDIN (Note 22) tf2 - 100 ns Notes: 20. tspi only needed before first falling edge of CS after DAC_RST rising edge. tspi = 0 at all other times. 21. Data must be held for sufficient time to bridge the transition time of CCLK. 22. For fsclk < 1 MHz. DAC_RST t srs CS t spi t css t scl t sch t csh CCLK t r2 t f2 CDIN t dsu t dh Figure 32. Control Port Timing - SPI Mode 31 CS42406 3. TYPICAL CONNECTION DIAGRAM * +3. 3 V to +5 V V A 3 D ig ita l A ud io 11 5 A O U TB 1 SDIN1 + 3 .3 F SDIN3 MU TEC 1 A O U TA 1 10 k 6 18 +1 .8 V t o +5 V 4, 45 SD OU T A O U TA 2 A D C _ M0 A O U TB 2 10 k A O U TA 2 + 3 .3 F 15 17 AD C _PD N MU TE C 2 V LS 36 + 3 .3 F 16 O P TI O N A L 10 k A O U TB 2 MUTE CIRCUIT C RL 38 560 29 + 3 .3 F D IF 1 /S C L/ C C LK D IF 0 /S D A /C D IN D A C _M0 /A D 0/ C S MU TE C 3 D A C _F IL T+ D A C _ M1 A O U TA 3 10 k C R 560 28 + 3 .3 F D A C _R S T D A C _V Q +1 .8 V t o +5 V C A D C _ 3 84 x / 25 6 x A O U TB 3 14 10 k RL 560 C S4 2 4 0 6 13 RL 56 0 37 0 .0 1 F C/ Mo d e C o nf ig urat io n A O U TB 1 CIRCUIT C 41 A D C _ M1 A O U TA 3 10 O PTIO N A L MUTE + 3 .3 F VLS or G N D ** 43 RL A D C _ S C LK 10 k 44 C 560 39 SDIN2 AD C _LR C K 5 60 40 MC LK D AC _LR C K 12 7 ,9 A O U TA 1 D AC _ S C LK 48 1 F VD 2 47 0. 01 F 32 1 46 +3. 3 V to +5 V 5. 1 0 .0 1 F 1 F O P TI O N A L MUTE 10 k A O U TB 3 CIRCUIT C LO A D R LO A D 30 21 + 22 0 .0 1 F + 3. 3 F VLC 0. 01 F R LOAD + 5 60 3 .3 F C= 4 F s (RLOAD 5 6 0) 0. 01 F A D C _F IL T+ 26 An a log I np ut B u f f er 24 AINR A D C _V Q 34 25 1 F A IN L 0 .0 1 F 0 .0 1 F GND 8 GND GND 31 33 2 2 F * Res is tor may only be us ed if V D is der iv ed f rom V A . If us ed, do not driv e any other logic f r om V D ** Pull- up to V LS f or I 2S Pull- dow n to GND f or LJ Figure 33. Typical Connection Diagram 32 DS614PP2 CS42406 4. APPLICATIONS 4.1 4.1.1 Single, Double, and Quad-Speed Modes ADC Serial Port The ADC's internal to the CS42406 can support output sample rates from 2 kHz to 200 kHz, and a base MCLK/ADC_LRCK ratio of either 256x or 384x. The proper speed mode can be determined by the desired output sample rate and the external MCLK/ADC_LRCK ratio, as shown in Table 1 and Table 2. Please see section 4.2 for a discussion on how to select the desired speed mode. Speed Mode Single-Speed Mode Double-Speed Mode Quad-Speed Mode MCLK/ADC_LRCK Ratio Output Sample Rate Range (kHz) 512x 43 - 50 256x 2 - 50 256x 86 - 100 128x 50 - 100 128x 172 - 200 64x* 100 - 200 * Quad-Speed Mode, 64x only available in Master Mode. Table 1. ADC Speed Modes and the Associated Output Sample Rates (Fs) for 256x Mode Speed Mode Single-Speed Mode Double-Speed Mode Quad-Speed Mode MCLK/LRCK Ratio Output Sample Rate Range (kHz) 768x 43 - 50 384x 2 - 50 384x 86 - 100 192x 50 - 100 192x 172 - 200 96x* 100 - 200 * Quad Speed Mode, 96x only available in Master Mode. Table 2. ADC Speed Modes and the Associated Output Sample Rates (Fs) for 384x Mode 4.1.2 4.1.2a DAC Serial Port Stand Alone Mode The DAC's internal to the CS42406 operate in one of four operational modes determined by the DAC_Mx pins when in Stand Alone Mode. Sample rates outside the specified range for each mode are not supported. Refer to Table 3. 33 CS42406 DAC_M1 DAC_M0 Input Sample Rate (Fs) 0 0 4 kHz - 50 kHz 0 1 32 kHz - 48 kHz 1 0 50 kHz - 100 kHz 1 1 100 kHz - 200 kHz MODE Single-Speed Mode (without De-emphasis) Single-Speed Mode (with De-emphasis) Double-Speed Mode Quad-Speed Mode Table 3. CS42406 Stand Alone DAC Operational Modes 4.1.2b Control Port Mode The DAC's operate in one of three operational modes determined by the FM bits (see section 6.1.4) in Control Port mode. Sample rates outside the specified range for each mode are not supported. FM1 0 0 1 1 FM0 0 1 0 1 Input Sample Rate (Fs) 4 kHz - 50 kHz 50 kHz - 100 kHz 100 kHz - 200 kHz Reserved MODE Single-Speed Mode Double-Speed Mode Quad-Speed Mode Reserved Table 4. CS42406 Control Port DAC Operational Modes 4.2 ADC Serial Port Operation as Either a Clock Master or Slave The CS42406 ADC serial port supports operation as either a clock master or slave. As a clock master, the ADC_LRCK and ADC_SCLK pins are outputs with the left/right and serial clocks synchronously generated on-chip. As a clock slave, the ADC_LRCK and ADC_SCLK pins are inputs and require the left/right and serial clocks to be externally generated. The selection of clock master or slave is made via the ADC_Mx pins as shown in Table 5. ADC_M1 0 0 1 1 ADC_M0 0 1 0 1 MODE Clock Master, Single-Speed Mode Clock Master, Double-Speed Mode Clock Master, Quad-Speed Mode Clock Slave, All Speed Modes Table 5. CS42406 ADC Serial Port Mode Control 4.2.1 Operation as a Clock Master As a clock master, ADC_LRCK and ADC_SCLK operate as outputs. The left/right and serial clocks are internally derived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in Figure 34. 34 DS614PP2 CS42406 /1 0 / 256 Single Speed 00 / 128 Double Speed 01 / 64 Quad Speed 10 1 /2 Auto-Select ADC_LRCK Output (Equal to Fsout) 0 MCLK ADC_M1 ADC_M0 1 / 1.5 /4 Single Speed 00 /2 Double Speed 01 /1 Quad Speed 10 0 1 /3 ADC_SCLK Output ADC_384x/256x Auto-Select Figure 34. ADC Serial Port, Master Mode Clocking 4.2.2 Operation as a Clock Slave ADC_LRCK and ADC_SCLK operate as inputs in clock slave mode. It is recommended that the left/right clock be synchronously derived from the master clock and must be equal to Fs. It is also recommended that the serial clock be synchronously derived from the master clock and be equal to 64x Fs to maximize system performance. A unique feature of the CS42406 ADC serial port is the automatic selection of either Single, Double or Quad-Speed Mode when operating as a clock slave. The auto-mode selection feature supports all standard audio sample rates from 2 to 200 kHz. However, there are ranges of non-standard audio sample rates that are not supported when operating with a fast MCLK (512x/768x, 256x/384x, 128x/192x for Single, Double, and Quad-Speed Modes, respectively). Please refer to Table 1 and Table 2 for supported sample rate ranges. 4.3 4.3.1 Digital Interface Format DAC Serial Port The CS42406 DAC serial port will accept audio samples in 1 of 4 digital interface formats in Stand Alone Mode, as illustrated in Table 6, and 1 of 6 formats in Control Port mode, as illustrated in Table 7 on page 44. 35 CS42406 4.3.1a Stand Alone Mode The desired format for the DAC serial port is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship between the DAC_LRCK, DAC_SCLK and SDINx, see Figures 28-30. DIF1 0 0 1 1 DIF0 0 1 0 1 DESCRIPTION FORMAT 0 1 2 3 Left Justified, up to 24-bit Data IS, up to 24-bit Data Right Justified, 16-bit Data Right Justified, 24-bit Data FIGURE 29 28 30 30 Table 6. DAC Digital Interface Format - Stand Alone Mode 4.3.1b Control Port Mode The desired format for the DAC serial port is selected via the DIF2, DIF1 and DIF0 bits in the Mode Control 2 register (see section 6.1.2). For an illustration of the required relationship between DAC_LRCK, DAC_SCLK and SDINx, see Figures 28-30. 4.3.2 ADC Serial Port The CS42406 ADC serial port supports both IS and Left Justified serial audio formats. Upon start-up, the CS42406 will detect the logic level on SDOUT. A 10 k pull-up resistor to VLS is needed to select IS format, and a 10 k pull-down resistor to GND is needed to select Left Justified format. Please see Figures 28 and 29 for an illustration of the required relationship between ADC_LRCK, ADC_SCLK, and SDOUT. 4.4 De-Emphasis Control The CS42406 includes on-chip digital de-emphasis. Figure 35 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Gain dB T1=50 s 0dB T2 = 15 s -10dB F1 3.183 kHz F2 Frequency 10.61 kHz Figure 35. De-Emphasis Curve Notes: De-emphasis is only available in Single-Speed Mode. 4.4.1 Stand Alone Mode The operational mode pins, DAC_M1 and DAC_M0, selects the 44.1 kHz de-emphasis filter. Please see section 4.1.2a for the desired de-emphasis control. 4.4.2 Control Port Mode The Mode Control bits selects either the 32, 44.1, or 48 kHz de-emphasis filter. Please see section 6.1.3 for the desired de-emphasis control. 36 DS614PP2 CS42406 4.5 Analog Connections The analog modulator samples the input at 6.144 MHz. The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are multiples of the input sampling frequency (n * 6.144 MHz), where n=0,1,2,... Refer to Figure 36 which shows the suggested filter that will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. 634 4.7 F 100 k CS42406 470 pF C0G VA 91 - AINL + Input1 2700 pF C0G 100 k * 634 470 pF C0G VA 4.7 F 100 k Input2 - 91 AINR + 2700 pF C0G 100 k * *Place as close to the CS42406 as possible. Figure 36. CS42406 Recommended Analog Input Buffer 4.5.1 Capacitor Size on the Reference Pin (FILT+) The CS42406 requires an external capacitance on the internal reference voltage pin, ADC_FILT+. The size of this decoupling capacitor will affect the low frequency distortion performance as shown in Figure 37, with larger capacitor values used to optimize low frequency distortion performance. 1 uF 2.2 uF 3.3 uF 4.7 uF 5.6 uF 6.8 uF 10 uF 22 uF 47 uF 100 uF Figure 37. CS42406 ADC: THD+N versus Frequency 37 CS42406 4.6 4.6.1 Recommended Power-up Sequence Stand Alone Mode 1) Hold DAC_RST and ADC_PDN low until the power supplies and configuration pins are stable, and the master and left/right clocks are locked to the appropriate frequencies. In this state, the control port is reset to its default settings. 2) Bring DAC_RST and ADC_PDN high. The CS42406 DAC will remain in a low power state with DAC_VQ low and will initiate the Stand Alone power-up sequence after approximately 512 DAC_LRCK cycles in Single-Speed Mode (1024 DAC_LRCK cycles in Double-Speed Mode, and 2048 DAC_LRCK cycles in Quad-Speed Mode). The CS42406 ADC will begin the power-up sequence immediately following ADC_PDN going high. 4.6.2 Control Port Mode 1) Hold DAC_RST and ADC_PDN low until the power supplies are stable, and the master and left/right clocks are locked to the appropriate frequencies. In this state, the control port is reset to its default settings. 2) Bring DAC_RST and ADC_PDN high. The CS42406 DAC will remain in a low power state with DAC_VQ low. 3) Load the desired register settings while keeping the PDN bit set to 1. 4) Set the PDN bit to 0. This will initiate the power-up sequence for the DAC, which lasts approximately 50 s when the POPG bit is set to 0. If the POPG bit is set to 1, see Section 4.7 for a complete description of power-up timing. 4.7 Popguard(R) Transient Control The CS42406 uses a technique to minimize the effects of output transients during power-up and powerdown. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated inside the CS42406 when the DAC_RST pin or PDN bit is enabled/disabled and requires no other external control, aside from choosing the appropriate DC-blocking capacitors. 4.7.1 Power-up When the device is initially powered-up, the audio outputs, AOUTAx and AOUTBx, are clamped to GND. Following a delay of approximately 1000 DAC_LRCK cycles, each output begins to ramp toward the quiescent voltage. Approximately 10,000 DAC_LRCK cycles later, the outputs reach DAC_VQ and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, minimizing the power-up transient. 4.7.2 Power-down To prevent transients at power-down, the CS42406 must first enter its power-down state. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTAx and AOUTBx. In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on. 4.7.3 Discharge Time To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before turning on the power or exiting the power-down state. If full discharge does not occur, a transient will occur when the audio outputs are initially clamped to GND. The time that the device must remain in the 38 DS614PP2 CS42406 power-down state is related to the value of the DC-blocking capacitance and the output load. For example, with a 3.3 F capacitor, the minimum power-down time will be approximately 0.4 seconds. 4.8 Mute Control The Mute Control pins go high during power-up initialization, reset, muting (see section 6.1.1 and 6.4.1), or if the MCLK to DAC_LRCK ratio is incorrect. These pins are intended to be used as control for external mute circuits to prevent the clicks and pops that can occur in any single-ended single supply system. Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. Please see the CDB42406 data sheet for a suggested mute circuit. 4.9 Grounding and Power Supply Arrangements As with any high resolution converter, the CS42406 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 33 shows the recommended power arrangements, with VA, VD, VLS and VLC connected to clean supplies. If the ground planes are split between digital ground and analog ground, the GND pins of the CS42406 should be connected to the analog ground plane. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The CDB42406 evaluation board demonstrates the optimum layout and power supply arrangements. 4.9.1 Capacitor Placement Decoupling capacitors should be placed as close to the CS42406 as possible, with the low value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same layer as the converter. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin and referenced to analog ground. Due to the proximity of the two VD pins (pins 7 and 9), one set of decoupling capacitors will be sufficient for the digital supply. Please refer to Figure 33. 4.10 Control Port Interface The control port is used to load all the internal register settings (see section 6). The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port operates in one of two modes: IC or SPI. Notes: MCLK must be applied during all IC communication. 4.10.1 Memory Address Pointer (MAP) The MAP byte precedes the control port register byte during a write operation and is not available again until after a start condition is initiated. During a read operation the byte transmitted after the ACK will contain the data of the register pointed to by the MAP (see sections 4.10.2a and 4.10.2b for write/read details). 7 INCR 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 MAP3 0 2 MAP2 0 1 MAP1 0 0 MAP0 0 39 CS42406 4.10.1a INCR (Auto Map Increment) The CS42406 has MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive IC writes or reads and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes of successive registers. Default = `0' 0 - Disabled 1 - Enabled 4.10.1b MAP0-3 (Memory Address Pointer) Default = `0000' 4.10.2 IC Mode In the IC mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial control port clock, SCL. There is no CS pin. Pin AD0 enables the user to alter the chip address (001000[AD0][R/W]) and should be tied to VLC or GND as required, before powering up the device. If the device ever detects a high to low transition on the AD0/CS pin after power-up, SPI mode will be selected. 4.10.2a IC Write To write to the device, follow the procedure below while adhering to the control port timing as described in "SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE" on page 30. 1) Initiate a START condition to the IC bus followed by the address byte. The upper 6 bits must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth bit of the address byte is the R/W bit. 2) Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This byte points to the register to be written. 3) Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to by the MAP. 4) If the INCR bit (see section 4.10.1a) is set to 1, repeat the previous step until all the desired registers are written, then initiate a STOP condition to the bus. 5) If the INCR bit is set to 0 and further IC writes to other registers are desired, it is necessary to repeat the procedure detailed from step 1. If no further writes to other registers are desired, initiate a STOP condition to the bus. SD A 001000 AD0 W ACK M AP 1-8 ACK DATA 1-8 ACK SC L S top S tart Figure 38. IC Write 4.10.2b IC Read To read from the device, follow the procedure below while adhering to the control port Switching Specifications. During this operation it is first necessary to write to the device, specifying the appropriate register through the MAP. 40 DS614PP2 CS42406 1) After writing to the MAP (see section 4.10.1), initiate a repeated START condition to the IC bus followed by the address byte. The upper 6 bits must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte is the R/W bit. 2) Signal the end of the address byte by not issuing an acknowledge. The device will then transmit the contents of the register pointed to by the MAP. The MAP will contain the address of the last register written to the MAP. 3) If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Continue providing a clock but do not issue an ACK on the bytes clocked out of the device. After all the desired registers are read, initiate a STOP condition to the bus. 4) If the INCR bit is set to 0 and further IC reads from other registers are desired, it is necessary to repeat the procedure detailed from step 1. If no further reads from other registers are desired, initiate a STOP condition to the bus. SDA 0 01 00 0 AD 0 W ACK M AP 1-8 ACK 0 01 00 0 AD0 R AC K D ata 1 -8 (po in te d to b y MA P) ACK D ata 1-8 (p oin te d to b y MA P) SC L R ep e a te d S T A R T or Ab o rte d W R IT E S ta rt S to p Figure 39. IC Read 4.10.3 SPI Mode In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK (see Figure 40 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and is used to control SPI writes to the control port. When the device detects a high to low transition on the AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the rising edge of CCLK. 4.10.3a SPI Write To write to the device, follow the procedure below while adhering to the control port Switching Specifications. 1) Bring CS low. 2) The address byte on the CDIN pin must then be 00100000. 3) Write to the memory address pointer, MAP. This byte points to the register to be written. 4) Write the desired data to the register pointed to by the MAP. 5) If the INCR bit (see section 4.10.1a) is set to 1, repeat the previous step until all the desired registers are written, then bring CS high. 6) If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring CS high, and repeat the procedure detailed from step 1. If no further writes to other registers are desired, bring CS high. 41 CS42406 CS CCLK CHIP ADDRESS CDIN 0010000 MAP R/W DATA MSB byte 1 LSB byte n MAP = Memory Address Pointer Figure 40. SPI Write 42 DS614PP2 CS42406 5. REGISTER QUICK REFERENCE Addr 1h Function Mode Control 1 default 2h Invert Signal default 3h Mixing Control P1 default 4h Mixing Control P2 5h Mixing Control P3 default default 6h Volume Control A1 default 7h Volume Control B1 default 8h Volume Control A2 9h Volume Control B2 default default 0Ah Volume Control A3 default 0Bh Volume Control B3 default 0Ch Mode Control 2 default 7 6 5 4 3 2 1 0 AMUTE DIF2 DIF1 DIF0 DEM1 DEM0 FM1 FM0 1 0 0 0 0 0 0 0 Reserved Reserved INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1 0 0 0 0 0 0 0 0 Reserved Reserved Reserved 0 0 0 Reserved Reserved Reserved 0 0 0 Reserved Reserved Reserved 0 0 0 A1_MUTE A1_VOL6 0 0 B1_MUTE B1_VOL6 0 0 A2_MUTE A2_VOL6 0 0 B2_MUTE B2_VOL6 0 0 A3_MUTE A3_VOL6 0 0 B3_MUTE B3_VOL6 Reserved P1ATAPI3 P1ATAPI2 P1ATAPI1 P1ATAPI0 0 0 0 0 0 A2_VOL5 A2_VOL4 0 0 B2_VOL5 B2_VOL4 0 0 A3_VOL5 A3_VOL4 0 0 1 1 0 0 1 Reserved P3ATAPI3 P3ATAPI2 P3ATAPI1 P3ATAPI0 B1_VOL5 B1_VOL4 0 0 Reserved P2ATAPI3 P2ATAPI2 P2ATAPI1 P2ATAPI0 A1_VOL5 A1_VOL4 0 1 0 B3_VOL5 B3_VOL4 1 A1_VOL3 0 B1_VOL3 0 A2_VOL3 0 B2_VOL3 0 A3_VOL3 0 B3_VOL3 0 0 A1_VOL2 A1_VOL1 0 0 B1_VOL2 B1_VOL1 0 0 A2_VOL2 A2_VOL1 0 0 B2_VOL2 B2_VOL1 0 0 A3_VOL2 A3_VOL1 0 0 B3_VOL2 B3_VOL1 0 0 0 0 0 0 SZC1 SZC0 CPEN PDN POPG FREEZE 1 0 0 1 1 0 0 1 A1_VOL0 0 B1_VOL0 0 A2_VOL0 0 B2_VOL0 0 A3_VOL0 0 B3_VOL0 0 Reserved SNGLVOL 0 0 43 CS42406 6. REGISTER DESCRIPTIONS Note: All registers are read/write in IC mode and write only in SPI, unless otherwise stated. 6.1 MODE CONTROL 1 (ADDRESS 01H) 7 AMUTE 1 6.1.1 6 DIF2 0 5 DIF1 0 AUTO-MUTE (AMUTE) 4 DIF0 0 3 DEM1 0 2 DEM0 0 1 FM1 0 0 FM0 0 BIT 7 Default = 1 0 - Disabled 1 - Enabled Function: The CS42406 DAC output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits in the Power and Muting Control register. 6.1.2 DIGITAL INTERFACE FORMAT (DIF) BIT 6-4 Default = 000 - Format 0 (Left Justified, up to 24-bit data) Function: The required relationship between the DAC_LRCK, DAC_SCLK, and SDINx is defined by the Digital Interface Format and the options are detailed in Figures 28-30. DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIF0 0 1 0 1 0 1 0 1 DESCRIPTION Left Justified, up to 24-bit data IS, up to 24-bit data Right Justified, 16-bit data Right Justified, 24-bit data Right Justified, 20-bit data Right Justified, 18-bit data Reserved Reserved Format 0 1 2 3 4 5 - FIGURE 28 29 30 30 30 30 - Table 7. Digital Interface Formats - Control Port Mode 44 DS614PP2 CS42406 6.1.3 DE-EMPHASIS CONTROL (DEM) BIT 3-2 Default = 00 00 - Disabled 01 - 44.1 kHz 10 - 48 kHz 11 - 32 kHz Function: Selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (See Figure 35.) Note: 6.1.4 De-emphasis is only available in Single-Speed Mode. FUNCTIONAL MODE (FM) BIT 1-0 Default = 00 00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 200 kHz sample rates) 11 - Reserved Function: Selects the required range of input sample rates. 6.2 INVERT SIGNAL (ADDRESS 02H) 7 Reserved 0 6.2.1 6 Reserved 0 5 INV_B3 0 4 INV_A3 0 INVERT SIGNAL POLARITY (INV_XX) 3 INV_B2 0 2 INV_A2 0 1 INV_B1 0 0 INV_A1 0 BIT 5-0 Default = 0 0 - Disabled 1 - Enabled Function: When enabled, these bits invert the signal polarity for each of their respective channels. 6.3 MIXING CONTROL PAIR 1 (CHANNELS A1 & B1) (ADDRESS 03H) MIXING CONTROL PAIR 2 (CHANNELS A2 & B2) (ADDRESS 04H) MIXING CONTROL PAIR 3 (CHANNELS A3 & B3) (ADDRESS 05H) 7 Reserved 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 PxATAPI3 1 2 PxATAPI2 0 1 PxATAPI1 0 0 PxATAPI0 1 45 CS42406 6.3.1 ATAPI CHANNEL MIXING AND MUTING (ATAPI) BIT 3-0 Default = 1001 - AOUTAx = L, AOUTBx = R (Stereo) Function: The CS42406 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Table 8 and Figure 41 for additional information. Note: All mixing functions occur prior to the digital volume control. Mixing only occurs in channel pairs. ATAPI3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ATAPI2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ATAPI1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ATAPI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 AOUTAx MUTE MUTE MUTE MUTE R R R R L L L L [(L+R)/2] [(L+R)/2] [(L+R)/2] [(L+R)/2] AOUTBx MUTE R L [(L+R)/2] MUTE R L [(L+R)/2] MUTE R L [(L+R)/2] MUTE R L [(L+R)/2] Table 8. ATAPI Decode A Channel Volume Control & Mute Left Channel Audio Data AoutA Right Channel Audio Data B Channel Volume Control & Mute AoutB Figure 41. ATAPI Block Diagram 46 DS614PP2 CS42406 6.4 VOLUME CONTROL (ADDRESSES 06H - 0BH) 7 xx_MUTE 0 6.4.1 6 xx_VOL6 0 5 xx_VOL5 0 MUTE (MUTE) 4 xx_VOL4 0 3 xx_VOL3 0 2 xx_VOL2 0 1 xx_VOL1 0 0 xx_VOL0 0 BIT 7 Default = 0 0 - Disabled 1 - Enabled Function: The CS42406 DAC output converter output will mute when enabled. The quiescent voltage on the output will be retained. The muting function is affected, similar to attenuation changes, by the Soft and Zero Cross bits. The MUTECx pins will go active during the mute period if the Mute function is enabled for both channels in the pair. 6.4.2 DAC VOLUME CONTROL (XX_VOL) BIT 6-0 Default = 0 Function: The Digital Volume Control registers allow independent control of the signal levels in 1 dB increments from 0 to -119 dB. Volume settings are decoded as shown in Table 9. The volume changes are implemented as dictated by the Soft Ramp and Zero Cross bits. All volume settings less than -119 dB are equivalent to enabling the MUTE bit. Binary Code 0001010 0010100 0101000 0111100 1011010 Decimal Value 10 20 40 60 90 Volume Setting -10 dB -20 dB -40 dB -60 dB -90 dB Table 9. Example Digital Volume Settings 6.5 MODE CONTROL 2 (ADDRESS 0CH) 7 SZC1 1 6.5.1 6 SZC0 0 5 CPEN 0 4 PDN 1 3 POPG 1 2 FREEZE 0 1 RESERVED 0 0 SNGLVOL 0 SOFT RAMP AND ZERO CROSS CONTROL (SZC) BIT 7-6 Default = 10 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp and Zero Cross Function: Immediate Change When Immediate Change is selected all level changes will be implemented immediately in one step. 47 CS42406 Zero Cross Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz input sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 DAC_LRCK periods. Soft Ramp and Zero Cross Soft Ramp and Zero Cross dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and will be implemented on successive signal zero crossings. The 1/8 dB level changes will occur after timeout periods between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz input sample rate) if the signal does not encounter zero crossings. The zero cross function is independently monitored and implemented for each channel. 6.5.2 CONTROL PORT ENABLE (CPEN) BIT 5 Default = 0 0 - Disabled 1 - Enabled Function: The Control Port will become active and reset to the default settings when this function is enabled. 6.5.3 POWER DOWN (PDN) BIT 4 Default = 1 0 - Disabled 1 - Enabled Function: The DAC will enter a low-power state when this function is enabled, but the contents of the control registers will be retained in this mode. The power-down bit defaults to `enabled' on power-up and must be disabled before normal operation in Control Port mode can occur. 6.5.4 POPGUARD(R) TRANSIENT CONTROL (POPG) BIT 3 Default = 1 0 - Disabled 1 - Enabled Function: The PopGuard(R) Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to the quiescent voltage during power-on or power-off when this function is enabled. Please see section 4.7 for implementation details. 48 DS614PP2 CS42406 6.5.5 FREEZE CONTROLS (FREEZE) BIT 2 Default = 0 0 - Disabled 1 - Enabled Function: This function allows modifications to be made to the registers without the changes taking effect until the FREEZE is disabled. To have multiple changes in the control port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit. 6.5.6 SINGLE VOLUME CONTROL (SNGLVOL) BIT 0 Default = 0 0 - Disabled 1 - Enabled Function: The individual channel volume levels are independently controlled by their respective Volume Control Bytes when this function is disabled. When enabled, the volume on all channels is determined by the A1 Channel Volume Control Byte, and the other Volume Control Bytes are ignored. 49 CS42406 7 PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog input for a full-scale digital output. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. 50 DS614PP2 CS42406 8. PACKAGE DIMENSIONS 48L LQFP PACKAGE DRAWING E E1 D D1 1 e B A A1 L DIM A A1 B D D1 E E1 e* L MIN --0.002 0.007 0.343 0.272 0.343 0.272 0.016 0.018 0.000 * Nominal pin pitch is 0.50 mm INCHES NOM 0.055 0.004 0.009 0.354 0.28 0.354 0.28 0.020 0.24 4 MAX 0.063 0.006 0.011 0.366 0.280 0.366 0.280 0.024 0.030 7.000 MIN --0.05 0.17 8.70 6.90 8.70 6.90 0.40 0.45 0.00 MILLIMETERS NOM 1.40 0.10 0.22 9.0 BSC 7.0 BSC 9.0 BSC 7.0 BSC 0.50 BSC 0.60 4 MAX 1.60 0.15 0.27 9.30 7.10 9.30 7.10 0.60 0.75 7.00 Controlling dimension is mm. JEDEC Designation: MS026 51 CS42406 9. REVISION HISTORY Revision Date Changes 1 August 2003 Initial Release 2 March 2004 Added Revision History Table. Gain error changed from 5% to 10% in the ADC Analog Characteristics. Removed "Inter Channel" and "Intra Channel Phase Deviation" specification on page 13 and page 20. Removed ADC & DAC FILT+ "Output Impedance" and "Current Source Sink" specification on page 23. Maximum VOL changed from 13% to 15% on page 24. MCLK min/max duty cycle changed from 40/60% to 45/55% on page 27. Added Figure 37 on page 37. Table 10. Revision History Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com/ IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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