74LCXH162373 - Fairchild Semiconductor

Februa ry 200 1

Revised March 2002

74LCXH162373 Low Voltage 16-Bit Transparent Latch with Bushold and 26

Ω

Series Resistor Outputs

74LCXH162373

Low Voltage 16-Bit Transparent Latch

with Bushold and 26ΩSeries Resistor Outputs

General Description

The LCXH162373 contains sixteen non-inverting latches

with 3-STATE outputs and is intended for bus oriented

applications. The device is byte controlled. The flip-flops

appear transparent to the data when the Latch Enable (LE)

is HIGH. When LE is LOW, the data that meets the setup

time is l atched. Da ta appea rs on the bus whe n the Outp ut

Enable (O E ) is LOW. When OE is HIGH, the outp uts are in

a high impedance state.

The LCXH162373 is designed for low voltage (2.5V or

3.3V) VCC applications with capability of interfacing to a 5V

signal environment. The 26Ω series resistor helps reduce

output overshoot and undershoot.

The LCXH162373 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing CMOS low power dissipation.

The LCXH162373 data inputs include active bushold cir-

cuitry, eliminating the need for external pull-up resistors to

hold unused or floating data inputs at a valid logic level.

Features

■5V tolerant control inputs and outputs

■2.3V–3.6V VCC specifications provided

■Equivalent 26Ω series resistors on outputs

■Bushold on inputs eliminates the need for external

pull-up/pull-down resistors

■6.2 ns tPD max (VCC = 3.3V), 20 µA ICC max

■Power down high impedance inputs and outputs

■±12 mA output drive (VCC = 3.0V)

■Implements patented noise/EMI reduction circuitry

■Latch-up per for man c e exce eds 500 mA

■ESD performa nce :

Human body model > 2000V

Machine model > 200V

■Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA) (Preli minary)

Ordering Code:

Note 1: BGA package available in Tape and Reel only.

Logic Symbol

Order Number Package

Number Package Description

74LCXH162373GX

(Note 1) BGA54A

(Preliminary) 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

74LCXH162373MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

[RAIL]

74LCXH162373MEX MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

[TAPE and REEL]

74LCXH162373MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

[RAIL]

74LCXH162373MTX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

[TAPE and REEL]

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74LCXH162373

Connection Diagrams

Pin Assignment for SSOP and TSSOP

Pin Assignment for FBG A

(Top Thr u View)

Pin Descriptions

FBGA Pin Assignments

Truth Tables

H = HIGH Voltage Lev el

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

O0 = Previous O0 before HIGH -t o-LOW tr ans it ion of Lat ch Enable

Pin Names Description

OEnOutput Enable Input (Active LOW)

LEnLatch Enable Input

I0–I15 Inputs (Bushold)

O0–O15 Outputs (Bushold)

NC No Connect

123456

AO0NC OE1LE1NC I0

BO2O1NC NC I1I2

CO4O3VCC VCC I3I4

DO6O5GND GND I5I6

EO8O7GND GND I7I8

FO10 O9GND GND I9I10

GO12 O11 VCC VCC I11 I12

HO14 O13 NC NC I13 I14

JO15 NC OE2LE2NC I15

Inputs Outputs

LE1OE1I0–I7O0–O7

XH X Z

HL L L

HL H H

LL X O

Inputs Outputs

LE2OE2I8–I15 O8–O15

XH X Z

HL L L

HL H H

LL X O

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74LCXH162373

Functional Description

The LCXH162373 contains sixteen D-type latches with

3-STATE standard outputs. The device is byte controlled

with each byte functioning identically, but independent of

the ot h er. Co nt r ol pins can be s h or t ed t o ge t he r to o b t ain f u l l

16-bit operation. The following description applies to each

byte. When the Latch Enable (LEn) input is HIGH, data on

the In enters the latches. In this condition the latches are

transparent, i.e. a latch ou tput will chang e state each tim e

its I input changes. When LEn is LOW, the latches store

information that was present on the I inputs a setup time

preceding the HIGH-to-LOW transition of LEn. The

3-STATE standard outputs are controlled by the Output

Enable (OEn) input. When OEn is LOW, the standard out-

puts are in the 2-state mode. When OEn is HIGH, the stan-

dard outputs are in the high impedance mode but this does

not interfere with entering new data into the latches.

Logic Diagrams

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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74LCXH162373

Absolute Maximum Ratings(Note 2)

Recommended Operating Conditions (Note 4)

Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated

at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-

mend ed Operating Co nditions ” ta ble will defi ne t he cond it ions for act ual device operation.

Note 3: IO Absolute Maximum Rating must be observed.

Note 4: Floating or unused control inputs must be HIGH or LOW.

DC Electrical Characteristi cs

Symbol Parameter Value Conditions Units

VCC Supply Voltage −0.5 to +7.0 V

VIDC Input Voltage I0 - I15 −0.5 to VCC + 0.5 V

OEn, LEn−0.5V to 7.0V

VODC Output Voltag e −0.5 to +7.0 Output in 3-STATE V

−0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 3)

IIK DC Input Diode Current −50 VI < GND mA

IOK DC Output Diode Current −50 VO < GND mA

+50 VO > VCC

IODC Output Source/Sink Current ±50 mA

ICC DC Supply Current per Supply Pin ±100 mA

IGND DC Ground Current per Ground Pin ±100 mA

TSTG Storage Temperature −65 to +150 °C

Symbol Parameter Min Max Units

VCC Supply Voltage Operati ng 2.0 3.6 V

Data Retention 1.5 3.6

VIInput Voltage 0 VCC V

VOOutput Voltage HIGH or LOW State 0 VCC V

3-STATE 0 5.5

IOH/IOL Output Current VCC = 3.0V − 3.6V ±12

VCC = 2.7V − 3.0V ±8mA

VCC = 2.3V − 2.7V ±4

TAFree-Air Operating Temperature −40 85 °C

∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V 0 10 ns/V

Symbol Parameter Conditions VCC TA = −40°C to +85°CUnits

(V) Min Max

VIH HIGH Level Input Voltage 2.3 − 2.7 1.7 V

2.7 − 3.6 2.0

VIL LOW Level Input Voltage 2.3 − 2.7 0.7 V

2.7 − 3.6 0.8

VOH HIGH Level Output Voltage IOH = −100 µA2.3 − 3.6 VCC − 0.2

IOH = −4 mA 2.3 1.8

IOH = −4 mA 2.7 2.2

IOH = −6 mA 3.0 2.4

IOH = −8 mA 2.7 2.0

IOH = −12 mA 3.0 2.0

VOL LOW Level Output Voltage IOL = 100 µA2.3 − 3.6 0.2

IOL = 4 mA 2.3 0.6

IOL = 4 mA 2.7 0.4

IOL = 6 mA 3.0 0.5 5

IOL = 8 mA 2.7 0.6

IOL = 12 mA 3.0 0.8

IIInput Leakage Current VI = VCC or GND 2.3 − 3.6 ±5.0 µA

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74LCXH162373

DC Electrical Characteristics (Continued)

Note 5: Outputs disabled or 3-STATE only.

Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.

Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.

AC Electrical Characteristics

Note 8: Skew is def ined as t he absolute va lue of the differenc e betwee n the ac tu al propa gation d elay for any two s eparate outpu ts of the same d evi ce. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (t OSLH). Param eter guara nteed by design.

Symbol Parameter Conditions VCC TA = −40°C to +85°CUnits

(V) Min Max

II(HOLD) Bushold Input Minimum VIN = 0.7V 2.3 45

µA

Drive Hold Current VIN = 1.7V −45

VIN = 0.8V 3.0 75

VIN = 2.0V −75

II(OD) Bushold Input Over-Drive (Note 6) 2.7 300

µA

Current to Change State (Note 7) −300

(Note 6) 3.6 450

(Note 7) −450

IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 5.5V 2.3 − 3.6 ±5.0 µA

VI = VIH or VIL

IOFF Power-Off Leakage Current VO = VCC 010µA

ICC Quiescent Supply Current VI = VCC or GND 2.3 − 3.6 20 µA

3.6V ≤ VO ≤ 5.5V (Note 5) 2.3 − 3.6 ±20

∆ICC Increase in ICC per Input VIH = VCC −0.6V 2.3 − 3.6 500 µA

Symbol Parameter

TA = −40°C t o +85°C, RL = 500Ω

Units

VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V

CL = 50 pF CL = 50 pF CL = 30 pF

Min Max Min Max Min Max

tPHL Propagation Delay 1.5 6.2 1.5 6.7 1.5 7.4 ns

tPLH In to On1.5 6.2 1.5 6.7 1.5 7.4

tPHL Propagation Delay 1.5 6.3 1.5 7.2 1.5 7.6 ns

tPLH LE to On1.5 6.3 1.5 7.2 1.5 7.6

tPZL Output Enable Time 1.5 6.9 1.5 7.3 1.5 9.0 ns

tPZH 1.5 6.9 1.5 7.3 1.5 9.0

tPLZ Output Disable Time 1.5 6.0 1.5 6.3 1.5 7.2 ns

tPHZ 1.5 6.0 1.5 6.3 1.5 7.2

tSSetup Time, In to LE 2.5 2.5 3.0 ns

tHHold Time, In to LE 1.5 1.5 2.0 ns

tWLE Pulse Width 3.0 3.0 3.5 ns

tOSHL Output to Output Skew (Note 8) 1.0 ns

tOSLH 1.0

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74LCXH162373

Dynamic Switching Characteristics

Capacitance

Symbol Parameter Conditions VCC

(V)

TA = 25°CUnits

Typical

VOLP Quiet Output Dynamic Peak VOL CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.35 V

CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 0.25

VOLV Quiet Output Dynamic Valley VOL CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 −0.35 V

CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 −0.25

Symbol Parameter Conditions Typical Units

CIN Input Capacitance VCC = Open, VI = 0V or VCC 7pF

COUT Output Capacitance VCC = 3.3V, VI = 0V or VCC 8pF

CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 20 pF

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74LCXH162373

AC LOADING and WAVEFORMS Generic for LCX Family

FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)

Waveform for Inverting and Non-Inverting Functions

Propagation Delay. Pulse Width and trec Waveforms

3-STATE Output Low Enable and

Disable Times for Logic

3-STATE Output High Enable and

Disable Times for Logic

Setup Time, Hold Time and Re covery Time for Logic

trise and tfall

FIGURE 2. Waveforms

(Input Characteristics; f = 1 MHz, tr = tf = 3 ns)

Test Switch

tPLH, tPHL Open

tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V, and 2.7V

VCC x 2 at VCC = 2.5 ± 0.2V

tPZH, tPHZ GND

Symbol VCC

3.3V ± 0.3V 2.7V 2.5V ± 0.2V

Vmi 1.5V 1.5V VCC/2

Vmo 1.5V 1.5V VCC/2

VxVOL + 0.3V VOL + 0.3V VOL + 0.15V

VyVOH − 0.3V VOH − 0.3V VOH − 0.15V

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74LCXH162373

Schematic D ia gr a m Generic for LCX Family

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74LCXH162373

Physical Dimensions inches (millimeters) unless otherwise noted

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Package Number BGA54A

Preliminary

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74LCXH162373

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

Packag e Num b er MS48A

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74LCXH162373 Low Voltage 16-Bit Transparent Latch with Bushold and 26

Ω

Series Resistor Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lea d Th in S hri n k Small Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 6.1mm Wide

Package Number MTD48

Fairchild does not assume an y responsibility for u se of any circuitry d escribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

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1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

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to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A crit ical componen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife s upport

device or system, or to affect its safety or effectiveness.