Order Number: 250210, Revi sion: 009
07-Oct-2005
Intel® IXF1110 10-Port 1000 Mbps
Ethernet Media Access Controller
Datasheet
The I nte l® IXF1110 MAC is a 10-port Ethernet Me dia Acce ss Controller (MAC) that sup ports
IEE E 802.3 1000 Mbps applications. The device supports a System Packet Interface Level 4
Ph a se 2 (S P I 4-2 ) s yst e m interf a c e to th e netw or k pro cess o r or AS I C.
The I X F1110 MA C imp lem e nt s an in te r n al Se r ia li ze r /D e s er i al i zer ( Ser D e s ) to all ow dire ct
connection to optical modules. The integration of the SerDes functionality reduces PCB real-
es tate and syst em-cost requirements.
Applications
In general, the Intel® IXF11101000 Mbps Ethernet Media Access Controller (calle d hereafter
the IXF1110 MAC) is appropriate for high-end switching applications where MAC and SerDes
functions ar e not integrat ed into the system ASIC.
Product Featu res
■High-End Optical Ethernet Switches
■Multi-Service Optical Ethernet Switches ■High-End Ether net LAN/WAN Routers
■Ser D es inter fac e w ith op ti cal m o du l e
connect ions for Ethernet physical connec tivity
■Integrated termination
■I2C Rea d /Wri te cap a bi li ty
■System Packet Interface Level 4 Phase 2 (SPI4-
2)
■Capable of da ta transfers from 10.24 Gbp s up to
12.8 Gbps
■Su pport s dynamic phase alignm ent
■Integrated termination
■Ten indepen dent 100 0 Mbps full-duplex
Et herne t M AC po rts
■32- bi t CPU in te rfac e
■Ope rating Te m p erature Ra ng e:
—Mi n: 0 °C Max: +70 °C
■RMO N statistics
■JTAG boundary scan
■Complian t with IEEE 802.3x Standard for flow
control
■Jum bo frame support for 9.6 KB pa ckets
■.18 μ CMOS process technology
■Supports IEEE 802.3 fiber auto-negotiation,
including forced m ode
■SFP MSA compati ble
■In terna l 17.0 KB receive FIFO and 4.5 KB
transmit FIFO per port
■Independent enable/disable of any port
■Detection of overly large packets
■Counters for dropped and errored packet s
■CRC calcu lation and error det ection
■Programmabl e options:
—Filter packets with errors
—F ilte r, broa d ca s t, m u ltica s t , an d unicas t
address packets
—Automatic ally pad transm itted packets less
th an the minimum frame s ize
■552-Cerami c BGA
■552-Cerami c BGA
(RoHS-compliant)
■1.8 V and 2.5 V oper ation
■Powe r consumption: 490 mW per-port typical
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
2 Order N umber: 250210, Revisi on: 009
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in nuclear facility applications.
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presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by
estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
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Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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Copyright © 2005, Intel Corporation. All Rights Reserved.
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Co ntroller
Order Number : 250210, Revision: 009 3
Contents
1.0 Introduction..................................................................................................................................14
1.1 What You Will Find in This Document ................................................................................14
1.2 Related Documents. ...........................................................................................................15
2.0 General Description ....................................................................................................................16
3.0 Ball Assignments and Ball List Tables......................................................................................18
4.0 Ball Assignm ents and Sign al Descrip tions ..............................................................................19
4.1 Naming Conventions ..........................................................................................................19
4.1.1 Signal Name Conventions ....... ....... ............ ....... ....... ............ ............ ....... ............ ..19
4.1.2 Reg ister Add r es s Conven tions ..... .......... .... .......... .... ................. ..... ................ ..... ..19
4.2 Interface Signal Groups..... ............ ............ ............ ......... ....... ............ ............ ............ .........20
4.3 Ball List Tables ...................................................................................................................32
4.3.1 Balls Listed in Alphanumeric Order by Signal Name............ ....... ....... ............ .......32
4.3.2 Balls Listed in Alphanumeric Order by Ball Location................... ....... ............ .......38
5.0 Functional Descriptions..............................................................................................................44
5.1 Media Access Controller.....................................................................................................44
5.1.1 Ge n eral Descript ion... ..... ......... ..... ................. .... ................. ..... ......... ..... ................44
5.1.2 MAC Functions ......................................................................................................44
5.1.2.1 Paddi ng of Undersized Frames on Trans m it ......... ................................44
5.1.2.2 Automa tic CRC Generation .......... ................... ......................................45
5.1.2.3 Fi lteri n g of Receive Packet s .......... ......... ..... ......... ..... ......... ................. ..45
5.1.3 Flow Control... ..... ..... ......... ..... ......... ..... .......... .... .......... ..... ......... ..... ................ ..... ..47
5.1.3.1 802.3x Flow Con trol (Full-Duplex Operation).........................................47
5.1.4 Fiber Operation .... ................... ..... ........................ .... ........................ ..... ................51
5.1.5 Auto-Negotiation ...................................................................................................52
5.1.5.1 Determ ining If Link Is Established in Auto-Negotiation Mode. ...............52
5.1.6 Forced Mode Operat ion ...................................... .............................. ....................53
5.1.6.1 Determ ining If Link Is Established in Forced Mode........................... .....53
5.1.7 Jumbo Packet Support ................... ................... ................... .............. ............ .......53
5.1.8 RMON Statistics Support........... ................... .............. ................... ................... .....54
5.1.8.1 RMON Statistics.....................................................................................54
5.1.8.2 Conventions...........................................................................................56
5.1.8.3 Additional Statistics................................................................................56
5.2 System Packet Inte rface Level 4 Phase 2..........................................................................58
5.2.1 Data Pa th.............. ..... ........................ ..... ................ ..... ....................... ..... ..............59
5.2.1.1 Control Words........................................................................................60
5.2.1.2 EOP Abort..............................................................................................62
5.2.1.3 DIP4.......................................................................................................63
5.2.2 St a rt- U p Pa ra me te rs.... ..... ..... ......... ..... ........................ ..... ....................... ..... .........64
5.2.2.1 CALENDAR_LEN ..................................................................................64
5.2.2.2 CALENDAR_M ......................................................................................65
5.2.2.3 DIP2_Thr................................................................................................65
5.2.2.4 Loss_Of_Sync........................................................................................65
5.2.2.5 DATA_MAX_T .......................................................................................65
5.2.2.6 REP_T ...................................................................................................65
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
4 Order N umber: 250210, Revisi on: 009
5.2.2.7 DIP4_UnLock.........................................................................................65
5.2.2.8 DIP4_Lock .............................................................................................65
5.2.2.9 MaxBurst1..............................................................................................66
5.2.2.10 MaxBurst2..............................................................................................66
5.2.3 Dynamic Phase Alignment Training Sequence (Data Path De-skew)...................66
5.2.3.1 Training at Start-up................................................................................66
5.2.3.2 Periodic Training....................................................................................66
5.2.3.3 Training in a Practical Imple mentation...................................................67
5.2.4 FIFO S tatus Channel....................................... ........................................ ..............67
5.2.5 DC Paramete rs.... .... ..... ................. .... .......... ..... ................ ..... ................ ..... ...........71
5.3 SerDes Interface ................................................................................................................71
5.3.1 Introduction............................................................................................................71
5.3.2 Features.................................................................................................................71
5.3.3 Functional Description................................... ....... ....... ............ ............ ....... ...........72
5.3.3.1 Transmitter Ope rational Overview.........................................................72
5.3.3.2 Transmitter Programmab le Driver-Power Levels...................................72
5.3.3.3 Receiver Operational Overview.............................................................73
5.3.3 .4 Sele c ti ve Po we r - Do wn................... ..... ......... ..... .......... .... ................. ..... .73
5.3.4 Timing and E lectrical Characteristics......................................... ................... .........73
5.4 Optical Mod ule Interface ....................................................................................................73
5.4.1 Introduction............................................................................................................73
5.4.2 IXF1110 Suppo r ted Optical Module In te r face Sig n als....................... .... ..... .......... .73
5.4.3 Functional Descriptions ..................... ............ ....... ............ ............ ......... ............ ....74
5.4.3 .1 Hig h - Sp e ed Se rial Inter face....................... ..... ..... ......... ..... ....................74
5.4.3. 2 Low-Speed S tatus Signaling Interface. ............................. ................... ..74
5.4.4 I2C Module Configuration Interface . .. .......... .. ....... ..... .. .......... .. ..... ....... .. ..... ....... ....76
5.4.4 .1 Gen eral Description.... ................. ..... ................ ..... ................ ..... ...........77
5.4.4.2 I2C Protoco l Speci fics. ........................ ..... ......... ..... ................ ..... ...........79
5.4.4.3 Port Pro tocol Operation .........................................................................79
5.4.4.4 Clock and Data Transitions....................................................................79
5.4.4 .5 AC Timin g Chara cte ristics ........... ..... ......... ..... ......... ..... ......... ..... .......... .83
5.5 LED Interface......................................................................................................................83
5.5.1 Introduction............................................................................................................83
5.5.2 Modes of Operation...............................................................................................83
5.5.2.1 Mode 0...................................................................................................84
5.5.2.2 Mode 1...................................................................................................84
5.5.3 LED Interface Signal Desc ription. . ................... ................... ..................... ..............84
5.5.4 Mode 0: Det a il e d Operation.................. ..... ....................... ..... ........................ .... ....84
5.5.5 Mode 1: Det a il e d Operation.................. ..... ....................... ..... ........................ .... ....85
5.5.6 Powe r-On, Reset, and Initialization ..... ................... ...............................................86
5.5.6.1 Enabling the LED Interface................... ....... .......... ....... ....... .. ............ ....86
5.5.7 LED Data Decodes................ ................... ............................................... ..............87
5.5.7.1 LED Signaling Behavior................. .............. ................... ................... ....87
5.6 CPU Interface.....................................................................................................................88
5.6.1 General Description........................... .......... ....... ....... ....... ....... ....... ....... .......... ......88
5.6.2 Functional Description................................... ....... ....... ............ ............ ....... ...........89
5.6.2. 1 Read A ccess................. ............................................. ............................90
5.6.2.2 Write Access..........................................................................................91
5.6.2 .3 Ti ming parame te rs...... ..... .......... .... .......... .... ........................ ..... .............92
5.6.3 Endian....................................................................................................................92
5.7 JTAG (Bou ndar y Sca n )................ ..... ................. ..... ................ ..... ................ ..... .......... .... ....92
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Co ntroller
Order Number : 250210, Revision: 009 5
5.7.1 TAP In te r face (JTAG ) ..... ................... ..... ....................... ..... ........................ .... .......92
5.7.2 TAP Sta te Machin e.............. .... ........................ ..... ....................... ..... .....................93
5.7.3 Instruction Register and Supported Instructions....... ................... ............ ..............93
5.7.4 ID Register.............................................................................................................93
5.7.5 Boundary Scan Register............ .......................... .......................... ........................94
5.7.6 Byp ass Register.....................................................................................................94
5.8 Clocks.................................................................................................................................94
5.8.1 System Interface Reference Clocks.......................................................................94
5.8.1.1 CLK125..................................................................................................94
5.8.1.2 CLK50....................................................................................................94
5.8.2 SPI4-2 Receive and Transmit Data Path Clocks. ................... .............. .................95
5.8.3 JTAG Clock............................................................................................................95
5.8.4 I2C Clock........... ................ ..... ......... ..... .......... .... .......... ..... ................ ..... ......... ..... ..95
5.8.5 LED Clock.... ..... ......... ..... ......... ..... ................. .... ................. ..... ................ ..... .........95
6.0 Applications.................................................................................................................................96
6.1 Power Su p ply Se q uen cing...... .......... .... ................. ..... ....................... ..... ........................ ....96
6.1.1 Power-Up Sequence....................... .......... .. ....... ....... .......... .. ....... ....... .......... .. .......96
6.1.2 Power-Down Sequence............. ............................................................................96
6.2 Analog Power Filtering........................................................................................................97
6.3 TX FI FO and RX FIFO Ope ration.............................. .......................... ................... ............97
6.3.1 TX FIFO.................................................................................................................98
6.3.1.1 MAC Transfer Thre sh old.... ..... ......... ..... ......... ..... ................ ..... ..............98
6.3.1.2 TX FIFO Relation to the SPI4-2 Transmit FIFO Status (TSTAT ). ..........99
6.3.1.3 TX FIFO Drain (IXF1110 Ver sion) ........ ......... ..... ................ ..... ..............99
6.3.2 RX FI FO....... ..... ......... ..... ........................ .... ........................ ..... ....................... .....100
6.4 Rese t a n d Ini tializati on............ ........................ ..... ....................... ..... ........................ .... ... ..101
6.4.1 SPI4-2 Initialization..............................................................................................1 01
6.4.1.1 RX SPI4-2............................................................................................101
6.4.1.2 TX SPI4-2 ............................................................................................102
6.4.1.3 SerDes.................................................................................................102
6.4.1.4 CPU .....................................................................................................102
6.5 SerDes Po we r -D o wn Cap abi liti es..... .... .......... ................ ..... .......... .... .......... .... .......... .......102
6.5.1 Placing th e SerDes Port in Power-Down Mod e...................................................102
6.5.2 Bringing the SerDes Port Out of Power-Down Mode...........................................1 03
6.6 IXF 1110 MAC Unused P orts ...... ...................................... ...................................... ..........1 03
6.7 Optical Module Connections to the IXF1110 MAC ............................ ....... ................. .......103
6.7.1 SFP-to-IXF1110 Co nnec tion........... .......... ..... ................ ..... ................ ..... .......... ..103
7.0 Electrical Specifications ...........................................................................................................106
7.1 DC Specifica ti o ns ..... ......... ..... .......... .... ................. ..... ................ ..... ................ ..... ............108
7.2 Undershoot/Overshoot Specifications .. ....... ............ ....... ....... ............ ....... ....... ............ .....109
7.3 CPU Timin g Specifica tion....... ..... ................ ..... ........................ ..... ....................... ..... .......110
7.4 JTAG Timing Specification ...............................................................................................1 12
7.5 Transmit Pause Control Timing Specifications.................................................................1 13
7.6 Optical Module Interrupt and I2C Timin g Speci ficat ion...... .... .......... ..... ......... ..... ......... .....114
7.7 Sy ste m Timi n g Specifications... ..... ..... ................. .... ........................ ..... ....................... .....117
7.8 LED Timi n g Speci fications. ..... .......... .... ........................ ..... ....................... ..... ...................118
7.9 SerDes Ti mi n g Specification.......... ..... ......... ..... .......... .... ................. ..... ......... ..... ......... .....119
7.10 SPI4-2 Timing Specifications............................................................................................121
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
6 Order N umber: 250210, Revisi on: 009
8.0 Register Definitions...................................................................................................................123
8.1 Introduction.......................................................................................................................123
8.2 Documen t Structure..........................................................................................................123
8.3 Graphical Representation. .... ....... .......... ....... ....... ....... ....... ....... .......... ....... ....... ....... ....... ..123
8.4 Per Port Registers............................................................................................................125
8.5 Memory Map.... ................. .... ........................ ..... ....................... ..... ........................ ..... ......125
8.5.1 MAC Control Registers........................................................................................133
8.5.2 M AC RX Statistics Reg ister Overview.................................................................141
8.5.3 MAC TX Statistics Register Overview .................................................................145
8.5.4 Globa l Status and Configura tion Register Overview ........................ ...................149
8.5.5 Glob al RX Block Re gi ster Overview..................... ..... .......... .... .......... .... .......... ....154
8.5.6 TX Blo ck Regi ste r Overview............ ..... ................ ..... ................. .... ................. ....163
8.5.7 SPI4-2 Block Regi ste r Overview.................... ..... ................. .... ................. ..... ......173
8.5.8 SerDes Register Overview .................................................................................175
8.5.9 O ptical Module Interface Block Register Overview .............................................177
9.0 Mech anical Speci fications........................................................................................................179
9.1 Features............................................................................................................................179
9.2 IXF1110 MAC Packa g e Spec ifics............ ..... ................. .... ................. ..... ................ ..... ....179
9.2.1 Markings..............................................................................................................180
10.0 Product Ordering Information..................................................................................................183
Figures
1 IXF1110 MAC Block Diagram. ............... ............................................................................ .........16
2 IXF1110 MAC System Block Diagram.................................. .............. ...................................... ..17
3 552-Ball CBGA Assignme nts (Top View) ............................. .............. ...................................... ..18
4 I nt e r fa ce Diag r a m...... ................. ..... ................ ..... ................. .... ................. ..... ................ ...........20
5 Packet Buffering FIFO................................................................................................................48
6 Ethernet Frame Format..............................................................................................................48
7 PAUSE Frame Format................................................................................................................49
8 Transmit Pause Control Interface...............................................................................................51
9 SPI4-2 Interfacing with the Network Processo r or Forwarding Engine.......................................58
10 Data Pa th Sta te............ ....................... ..... .......... .... ................. ..... ................ ..... .........................60
11 Per-Port Sta te Diagram with Tra n sitions at Cont ro l Words ....... ................. ..... ......... ..... ......... ....62
12 DIP-4 Calculation Boundaries ................................................................................................. ...63
13 DIP-4 Calculation Algorithm .......................................................................................................64
14 FIFO Status State Diagram........................................................................................................68
15 Exa mple of DIP-2 En coding ......................................................................................................69
16 Data Va lidity Timing........... ......... ..... ......... ..... ................. .... ................. ..... ................ ..... .............80
17 Sta r t a nd Stop Def in i tion Ti mi ng. ..... .... ................. ..... ....................... ..... ................. .... ............ ....80
18 A ckno wledge Timi ng ... ...................................... ............................................. ............................81
19 Random Read ............................................................................................................................82
20 Byte Write...................................................................................................................................83
21 Mode 0 Timing............................................................................................................................85
22 Mode 1 Timing............................................................................................................................86
23 CPU Interface Inpu ts/Outp u ts....... ..... .......... .... .......... ..... ................ ..... ......... ..... ......... ..... ...........89
24 Read Timing – Asynchronous Interface ...................... ....... ....... ....... .......... ....... .. ....... .......... ......91
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Co ntroller
Order Number : 250210, Revision: 009 7
25 Write Timing – Asynchronous Interface...... .. ....... .......... .. ....... ....... ..... ....... ..... ....... .. .......... ....... ..91
26 Power Sequencing................ .............. ................... .....................................................................96
27 Analog Power Supply Filter Network..................... ...................................... .............. .................97
28 Packet Buffering FIFO................................................................................................................98
29 SFP-to-IXF1 110 Connect ion . .............. ........................ ..................... ................... ......................104
30 CPU Port Read Timing.............................................................................................................110
31 CPU Port Write Timing .............................................................................................................110
32 JTAG Timing.... ........................ ..... ....................... ..... ........................ ..... ....................... ............112
33 Transmi t Pause Control Interface... .......... .... .......... ..... ................ ..... ......... ..... ......... ..... .......... ..113
34 Optical Module Interrupt Timing.................... ....... ............ ....... ....... ............ ....... ....... ............ .....114
35 I2C Bus Timing..........................................................................................................................115
36 I2C Write Cycle .........................................................................................................................115
37 Ha r d war e Rese t Ti mi n g......... ......... ..... ......... ..... .......... ................ ..... ......... ..... ......... ..... ............117
38 LED Timing...............................................................................................................................118
39 SerDes Timing..........................................................................................................................119
40 SPI4-2 Transmit FIFO Status Bus Timing ................................................................................1 21
41 SPI4-2 Receive FIF O Statu s Bu s Ti mi n g ..... ................. ..... ......... ..... ................ ..... ................. ..122
42 Memory Overvie w.....................................................................................................................124
43 Register Overview ....................................................................................................................125
44 Markings...................................................................................................................................180
45 552-Ceramic Ball Grid Array (CBGA) Packag e Specifications.................................................181
46 CBGA Pac ka ge Si de View Diagram.... ......... ..... .......... .... .......... .... ................. ..... ................ .....182
47 Ordering Information - Sample.................................................................................................183
Tables
1 SPI4-2 Interfac e Signal Descriptions.. ................... ................... ................... ................... ............21
2 SerDes In te r face Sign al Desc r iptions........... .......... ..... ......... ..... ......... ..... ......... ..... .......... .... .......23
3 CPU Interface Signal Descriptions .............................................................................................24
4 Pause Control Interfa ce Signal Descriptio ns..............................................................................25
5 Optical Module Interface Signal Descriptions........... ....... ....... ..... ....... ....... ....... ..... ....... ....... ..... ..26
6 LED Interface Signal Descriptions..............................................................................................27
7 JTAG Interface Signal Descriptions. .................................. .......................... .......................... .....28
8 Syste m In te rface Sig n al Descript ions.. ......... ..... ................. .... ................. ..... ......... ..... ................28
9 Power Supply Signal Descript ions. ............ ..... ......... ..... ................ ..... ................. .... ................. ..29
10 Unused Balls/Reserved.............................................................................................................31
11 Ball List in Alphanumeric Order by Signal Name........................... .......... ....... ......... .......... ....... ..32
12 Ball List in Alphanumeric Order by Ball Location........................... ............ ............ ............ .........38
13 Pa u s e Pack e ts Dr op Ena bl e Be havi o r............. .... ................. ..... ................ ..... ................. .... .......46
14 CRC Errored Packets Drop Enable Behavior............................................................ ............ .....47
15 Va lid Decodes for TXP AUSEADD[3:0]............ ................ ..... ......... ..... .......... .... .......... ................50
16 RMON Additional Statistics Registers ........................................................................................55
17 SPI4-2 Interface Signal Summary .................. .................................................... ................... .....58
18 Control Word Format..................................................................................................................61
19 Control Word Definitions.............................................................................................................61
20 FIFO Status Format....................................................................................................................70
21 SerDes Driver TX Power Levels.................................................................................................72
22 IXF1110 -to-SFP Connect ions......................... ................... .......................... .......................... .....74
23 LED Signal Descriptions..................... ................... ................... ................... .............. .................84
24 Mode 0 Clock Cycle to Data B it Relationship........ ...................................... .............. .................85
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
8 Order N umber: 250210, Revisi on: 009
25 Mode 1 Clock Cycle to Data Bit Relationship.............................................................................86
26 LED Data Decodes......... ..... .. ..... .. ..... ..... ....... .. ..... .. ..... ..... .. ..... ....... .. ..... ..... .. ..... .. ..... ....... ... ........87
27 LED Behavior.............................................................................................................................88
28 CPU Interface Signals ......... .. ..... .. ..... .. .......... .. ..... .. ..... ....... ..... .. ..... .. ..... ....... ..... .. ..... .. ..... ...........89
29 Recom me nded J TAG Termination. .................................................... ................... ................... ..92
30 Supported Boundary Scan Instructions........... ....... ............ ....... ....... ............ ....... ....... ............ ....93
31 Power Se q uen cing .... ..... ................. .... ................. ..... ................ ..... ................. .... .......................97
32 Analog Power Balls ....................................................................................................................97
33 SFP-to-IXF1110 Connec tion .... ......... ..... ................ ..... ........................ ..... ....................... ..... ....104
34 Absolute Maxi mu m Ratings............... ..... ................ ..... .......... .... .......... ..... ......... ..... ......... ..... ....106
35 Ope r at i n g Condi tions ............ .......... .... ................. ..... ................ ..... ................. .... .......... ...........107
36 2.5 V LVTT L an d CMOS I/O Electric al Chara cteristics .... ..... ......... ..... ......... ..... ......... ..... .........10 8
37 LVDS I/ O El e ctr i c a l Chara c te ristics.......... ..... ......... ..... .......... .... ................. ..... ................ ..... ....108
38 Undershoot/Overshoot Limits....... ....... .......... .. ....... .......... ....... ....... .. ............ ..... ....... ....... ....... ..109
39 CPU Timin g Parameters........ ..... ................. .... ................. ..... ................ ..... ................ ..... ...... ...110
40 JTAG Timin g Parameters.........................................................................................................112
41 Transmit Pause Control Interface Parameters.........................................................................113
42 Opt ical Module Interrupt Timing Paramet ers...................................... ................... ...................114
43 I2C AC Ti mi ng Chara cteri stics..................... .... .......... ................ ..... .......... .... .......... .... .......... ....11 5
44 Hardware Reset T iming Parame ters........................................................................................117
45 LED Timi n g Parameters. ................. .... ................. ..... ......... ..... ................. .... ................. ..... ......118
46 Transmitter Characteristics.......................................................................................................119
47 Receiver Characte ristics ...........................................................................................................120
48 SPI4-2 Transmit FIFO Status Bus Timing Parameters .............................................................121
49 SPI4-2 Receive FIFO Status Bus Timing Pa rameters..............................................................122
50 SPI4-2 LVDS Rise/Fall Times ..................................................................................................122
51 MAC Control Register Map.......................................................................................................125
52 MAC RX Statistics Register Map..............................................................................................126
53 MAC TX Statistics Register Map..............................................................................................127
54 Gl obal Sta tu s a nd Configuration Regi ste r Ma p.. .... ................. ..... ......... ..... ......... ..... ................128
55 RX Blo ck Regi ste r Map ....... ......... ..... .......... .... ................. ..... ................ ..... ................ ..... .........129
56 TX Block Register Map.............................................................................................................130
57 SPI4-2 Block Register Map ......................................................................................................131
58 SerDe s Block Registe r Map ............. ..... ......... ..... ................. .... ................. ..... ................ ..... ....131
59 Opt ical Module Interface Block Register Map . .............................................. ..........................132
60 S tation Address Low ($ Port_Index + 0x00)................................ .......................... ...................133
61 Sta tion Addre ss High ( $ Port_Index + 0x01 )............................. ..... ................. .... .......... ..... ......133
62 FDFC Type ( $ Port_ Index + 0x03 ) .... ..... ........................ .... ........................ ..... ....................... ..133
63 FC TX Timer Value ($ Port_Index + 0x07)...............................................................................133
64 FDFC Ad d re ss Low ($ Por t_ Index + 0x08 ).. ....................... ..... ................. .... ........................ ....13 4
65 FDF C Address High ($ Port_Index + 0x09)....... ................... .............. ................... ...................134
66 IPG Tr ansmit Time ($ Po rt_ Index + 0x0C )........... .......... .... ........................ ..... ....................... ..134
67 P ause Threshold ($ Port_Index + 0x0E ) ..................................... .............................. ...............135
68 Max Frame Size ($ Port_Ind ex + 0x0F)....................................................................................135
69 FC E nable ($ Port_Index + 0x12)................................................................... ..........................136
70 Discard Unknown Contro l Frame ($ Port_Index + 0x15)..........................................................136
71 RX Config Word ($ Port_Index + 0x16) ...................... ....... ....... ..... ....... ....... ..... ....... ....... ....... ..136
72 TX Config Word ($ Port_Ind ex + 0x17) ....................................................................................137
73 Diverse C onfig ($ Port_Index + 0x18) .....................................................................................138
74 RX Packet Filter Control ($ Port_Index + 0x19) ............... ....... ....... ....... ....... ....... ..... ....... ....... ..139
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Co ntroller
Order Number : 250210, Revision: 009 9
75 Port Multicast Address Low ($ Port_Index + 0x1A)......................... ................... ................... ...140
76 Port Multicast Address High ($ Port_Index + 0x1B) .................................................................140
77 MAC RX Statistics ($ Port_Index + 0x20 - Port_Index + 0x39)..... .......... ....... .. ....... .......... .. .....141
78 MAC TX Statistics ($ Port_Index + 0x40 - Port_Index + 0x58) . .......................... ......................1 45
79 Port Enable ($ 0x500). ........................ ................... .......................... ................... ......................149
80 Link LED Enable ($ 0x502).......................................................................................................150
81 Core Clock Soft Reset ($ 0x504)..............................................................................................150
82 MAC Soft Reset ($ 0x505)......... ..... .. .......... .. ....... ..... ..... ....... .. ..... ....... ..... .. ....... ..... .. .......... .. .....151
83 CPU Interface ($ 0x508)....... ..................................................................................... ...............151
84 L ED Contro l ($ 0x509).... .... ..... ......... ..... ................. ..... ................ ..... ................ ..... ...................152
85 LED Flash Rate ($ 0x50A)........................................................................................................152
86 LED Fault Disable ($ 0x50B)....................................................................................................152
87 JTAG ID Revision ($ 0x50 C) . ......... ..... ......... ..... .......... .... .......... .... .......... ..... ......... ..... ......... .....153
88 RX FIFO High Watermark Ports 0 to 9 ($ 0x5 80 - 0x589). .............. ...................................... ...154
89 RX FIFO Low Watermark Ports 0 to 9 ($ 0x58A - 0x593) ........................................................155
90 RX FIFO Number of Frames Remov ed Ports 0 to 9 ($ 0x594 - 0x59D). ................... ...............1 57
91 RX FIFO Port Reset ($ 0x59E).................................................................................................159
92 RX FIFO Errored Frame Drop Enable ($ 0x59F)...... ....... ....... ....... .......... .. ....... ....... .......... .......160
93 RX FIFO Overflow Event ($ 0x5A0 ) ..........................................................................................161
94 TX FIFO High Watermark Ports 0 to 9 ($ 0x600 - 0x609) .................................. ......................163
95 TX FIFO Low Watermark Ports 0 to 9 ($ 0x60A - 0x613)....... ....... ..... ....... ..... ....... .. .......... .. .....164
96 TX FIFO MAC Transfer Threshold Ports 0 to 9 ($ 0x614 - 0x61D) . .........................................166
97 TX FIF O Overflow Event ( $ 0x61 E).. ............ ..... ........................ .... ........................ ..... ..............168
98 TX FIF O Drain ($ 0x 620 ).......... ......... ..... ................. ..... ................ ..... ................ ..... .......... .... . ....169
99 TX FIFO Info Out-of-Sequence ($ 0x621) ................ ....... ....... ....... ............ ....... ....... .......... .......170
100 TX FIFO Numbe r of Frames Removed Ports 0-9 ($ 0x622 - 0 x62B) ................. ......................171
101 SPI4 - 2 RX Burst Si ze ($ 0x 700)............ ..... ......... ..... ........................ ..... ....................... ..... ...... .173
102 SPI4-2 RX Training ($ 0x701)........... ............ ..... ....... ....... ....... ....... ............ ..... ....... ....... ....... .....173
103 SPI4-2 RX Calenda r ($ 0x702)........... ...................................... ................... .............. ...............174
104 SPI4-2 TX Syn chronization ($ 0x703) ......................................................................................1 75
105 SerDes Tx Driver Power Level Ports 0 -6 ($ 0x784) ............................................ ................... ...175
106 SerDes Tx Driver Power Level Ports 7 -9 ($ 0x785) ............................................ ................... ...176
107 SerDes TX and RX Power-Down Ports 0-9 ($ 0x787).......... .. ..... .. .......... .. ..... ....... .. ..... ....... .....176
108 Optical Modul e Status Ports 0-9 ($ 0x799)............ .......................... ....................... ..................1 77
109 Optical Module Control Ports 0-9 ($ 0x79A).................... ..... ....... .. .......... .. ....... ..... ....... ....... .....177
110 I2C Control Ports 0-9 ($ 0x79B) ...............................................................................................177
111 I2C Data Ports 0-9 ($ 0x79C)....................................................................................................178
112 Product Ordering Information ................ ....... ....... ..... ....... ....... ..... ....... ....... ....... ..... ....... ....... .....183
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
10 Order N umber: 250210, Revision: 009
Revision History
Revision Number: 009
Revision Date: 07-Oct-2005
Page # Description
1Added “552-Ceramic BGA (RoHS-compliant)”
28 Table 7 “JT AG Interface Signal Descriptions” Cha ng ed Stan da rd to 3.3 V LVTTL f rom 2. 5 V CMOS
32/38 Modified Table 11 “Ball Lis t in Alphanumeric Or der by Signal Name” and Table 1 2 “Ball List i n
Alphanumeric Order by Ball Location”:
48 Fi gu re 6 “ Ether n et Fr a me For m at ” Changed Preamble byte count to 7 bytes
49 Figure 7 “PAUSE Frame Format” Changed Prea mble b y te count to 7 bytes
180 Fi gu re 44 “M ark in g s” New image (Added RoHS marking)
183 Modified Figure 47 “Ordering Information - Sample”
Revision Number: 008
Re vis i on Da te: Au gu st 10 , 200 4
Page # Description
All Globally replac ed the following: “AVDD ” to “AVD D1P8_1, AVDD1P8_2” and “AVDD2” to
“AVDD2P5_1, AVDD2P5_2”.
All Globally replaced the following: “AIDD” to “AIDD1P8_1, AIDD1P8_2” and “AIDD2” to “AIDD2P5_1,
AIDD2P5_2”.
45 Corrected ball number for RDAT15_P from K1 to K12 in Table 3 “SPI4-2 Interface Signal
Descriptions”.
125 Removed Short Runts Threshold Register ($ Port_Index 0x14) and changed to Reserved in
“Table 51 “MAC Control Register Map”.
Revision Number : 007 (Sheet 1 o f 2)
Revision Date: May 5, 2004
Page # Description
1 Changed produc t ordering number to reflect B2 [H FIXF1110CC.B2: 860817].
41 Modif ied Table 11 “Power Supply Signal Descr ipt ion s ” [changed AVDD to AVDD1P8_1/2 and
AVDD2 to AVDD2P5_1/2].
42 Added note under Section 5.1.2.1, “Padding of Undersized Frames on Transmit”.
42 Modified Section 5.1.2.3.1, “Filter on Unicast Packet Match” [added text to end of paragraph].
45 Ad de d Sec t i on 5.1.3, “Flo w Co nt r ol ”.
66 Modified t hird and fourth paragr aphs of Section 5.2.2.2, “CALEND AR_M”.
97 Ad de d Sec t i on 6.2, “ Anal og Po wer Fil tering ” (I XF111 0 on ly )
116 M odi fied Section 6.3.1, “TX FIFO” [added note].
99 Added Section 6.3.1.3, “TX FIFO Drain (IXF1110 Version)”.
110 Added Table 48 “SPI4-2 LVDS Rise/Fall Times”.
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Co ntroller
Order Number : 250210, Revision: 009 1 1
126 Modified Table 72 “RX Packet Fi lte r Control ($ Port _Index + 0x19)” ( removed tabl e note from the
bit 4 description].
170 Mod ifi ed Table 114 “SP I4-2 R X Calendar ($ 0 x 702)” [chan ged Regis ter bits 3:0 t o Reserved].
154 Mod ified Table 88 “JTAG ID Revision ($ 0x50C)” [adde d table no te 2].
163 Added Table 105 “TX FIFO Drain ($0x620)”.
176 Modif ied Table 116 “Intel® IXF1010 MAC Product Information” [changed part number and MM
num b er to reflec t B2] .
Revision Number: 006
Revision Date: Dece mber 30, 2003
Page # Description
NA Deleted old Tabl e 19: 1x 9-to-IXF1110 Connection
136 Mod ified text under Section 6.5, “SerDes Pow er-D own Ca pab ili ties (IXF1110 Only)”.
NA Changed Table 98: TX F IFO Por t Reset Register (Addr: 0x620) to R eserved.
Revision Number: 005 (Sheet 1 of 3)
Revision Date: November 24, 2003
Page # Description
1Added product ordering and ope rating tempe rature range information, and chan ged SFF-8053,
Revision 5.5 Compatible to SFP MSA c ompa tible.
17 Deleted old Figures 6, 7, and 8 (Revision 004) and replaced with Figure 6 “Intel® IXF1110 552-Ball
CBGA Assignments (Top View) ”
18 Adde d ne w S ec ti on 3.1 , “Int el ® IXF1110 Ball List Tables” including Table 1 “Intel® IXF1110 Ball List
in Alphanumeric Order by Signal Name” and Tabl e 2 “Intel® IXF1110 Ball Li st in Alph anum eric
Order by Ball Location”.
30 Modified Figu re 4 “Intel® IX F1110 I nterface Diagram” .
31 Broke up old Table 3 into Table 3 “Intel® IXF1110 SPI4-2 Interface Signal Descriptions” through
Tab le 1 2 “ Int el® IXF1110 System Interface Signal Descriptions”.
34 Modified Table 5 “Intel® IXF1110 CPU Interface Signal Descriptions”.
36 Modified Table 7 “Intel® IXF1110 Optical Module Interface Si gnal Descriptions” .
43 Added note under Section 5.1.2.3.5, “Filter PAUSE Packets ”.
43 Added note under Section 5.1.2.3.6, “F ilter CRC Errored Packets”.
44 Added third note to Section 5.1.3, “Fiber Operation”.
46 Modified text and ad ded note under Section 5.1 .4, “Fiber Auto-Negot iation”.
46 Modified Section 5.1.5, “Forced Mode Operation”
52 Modified Figure 6 “Intel® IXF1110 SPI4- 2 Interfacing with the Network Processor or Forwarding
Engine”.
52 Adde d Ta ble 1 7 “I nt el® IXF1110 SPI4-2 Interface Signal Summary”.
56 Added new Section 5.2.1.2, “EOP Abort”.
Revision Number: 007 (Sheet 2 of 2)
Revision Date: May 5, 2004
Page # Description
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
12 Order N umber: 250210, Revision: 009
65 Globally modified SFF-8053, Revision 5.5 Compatible to SFP MSA compatible under Section 5.3,
“SerDes Interface”.
66 Modified Section 5.3.3, “Functional Description”.
66 Added Section 5.5.4.1 “Transmitter Programmable Driver-Power Levels”.
67 Ad de d Table 21 “ In tel® IXF1110 SerDes Driver TX Power Levels”.
68 Changed Gigabit Interface Converter section to Section 5.6, “Optical Module Interface”. Globally
change d G BIC to Optical Module.
69 Mod if i ed Se c tio n 5.4 . 3 .2. 1, “M OD _D E F _9 :0” .
69 Mod if i ed Se c tio n 5.6 . 3 .2. 2, “TX _ FA U LT_ 9:0 ” .
70 Mod if i ed Se c tio n 5.6 . 3 .2. 3, “R X_ LO S_9:0”.
86 Ad de d no t e to “U P X_ R D Y” under Section 5. 8 .2, “Fu nc tional De sc r ip ti on” .
95 Added note under Section 6.2.1, “TX FIFO”.
95 Added note under Section 6.2.1.1, “MAC Transfer Threshold”.
104 M odi fie d/added Power Consumption Max to Tab le 49 “Intel® IXF1110 Operating Conditions”.
105 Modified Table 36 “Intel® IXF1110 2.5 V LVTTL and CMOS I/O Electrical Characteristics”.
105 Added Section 7. 2, “Undershoot/Overshoot Specifications”.
107 Modified Table 39 “Intel® IXF1110 CPU Timing Parameters”.
115 Modified Table 46 “Intel® IXF1110 Transmitter Characteristics”.
116 Modified Table 47 “Intel® IXF1110 Receiver Characteristics” (ad ded Common Mode Voltage Spec).
119 Added caution note under Section 8.0, “Regis ter D efin itions”.
124 Modified Table 53 “Intel® IXFIXF1110 Global Stat us and Configuration Register Map”.
130 M odi fied Tabl e 65 “IPG Transmit Time Register (Addr: P ort_Index + 0x0C)” .
131 Modified Table 66 “Pause Threshold Register (Addr: Port_Index + 0x0E)”.
132 M odi fie d Table 68 “FC Enable Register (Ad dr: Port _Ind ex + 0x12)”.
132 Modified Table 69 “Short Runts Threshold Register (Addr: Port_Index + 0x14)”.
132 M odi fie d Table 71 “RX Config Word R egister (Addr: Port_Index + 0x16)”.
133 M odi fie d Table 72 “TX Config Word Register ( Addr: Port_Index + 0x17)”.
134 Modified Table 73 “Diverse Config Register (Addr: Port_Index + 0x18)”.
135 Modified Tabl e 74 “RX Packet Filter Control Reg ister ( Addr: Port_Index + 0x19)” (removed note 2
from bit 4, modified bit 5 description).
137 Modified Table 77 “MAC RX Statistics Registers (Addr: Port_Index + 0x20 - Port_Index + 0x39)”.
146 Added Table 81 “Core Clock Soft Reset Register (Addr: 0x504)”.
147 Added Table 82 “MAC Soft Reset Register (Addr: 0x505)”.
155 Added Table 91 “RX FIFO Port Reset Register (Addr: 0x59E)”.
165 Added Section 98, “TX FIFO Port Reset Register (Addr: 0x620)”.
167 Modified Table 100 “TX FIFO Number of Frames Removed Ports 0-9 (Addr: 0x622 - 0x62B)”.
170 M odified Table 103 “SPI4 -2 RX Calendar R egister (Addr : 0x702)”.
171 Modified Table 104 “SPI4-2 TX Synchronization Register (Addr: 0x703) (B0 Silicon Revision)”.
Revision Number : 005 (Sheet 2 o f 3)
Revision Date: November 24, 2003
Page # Description
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Co ntroller
Order Number : 250210, Revision: 009 1 3
173 Added Table 106 “SerDes Tx Driver Po wer Level P orts 0-6 R egister (Addr: 0x784)”.
173 Added Table 107 “SerDes Tx Driver Po wer Level P orts 7-9 R egister (Addr: 0x785)”.
Revision Number: 005 (Sheet 3 of 3)
Revision Date: November 24, 2003
Page # Description
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
14 Order N umber: 250210, Revision: 009
1.0 Introduction
This document describes the functionality and operation of the Intel® IXF1110 10-Port Gigabit
Ethernet Media Access Controller.
1.1 What You Will Find in This Document
This document contains the following se ctions:
•Section 2.0, “General Description” on page 16
IX F1110 MAC block di agram system architecture.
•Section 3.0, “Ball Assignments and Bal l Li st Tables ” on page 18
I XF1110 MAC ball grid diagram with two ball lis t tables (by pin numb er and signal name)
•Section 4.0, “Ball Assignm ents and Signal Descriptions” on page 19
Si gnal naming met hodology and si gnal descriptions.
•Section 5.0, “Function al Descriptio ns” on page 44
Deta il ed inform ation abo ut the oper ation of the IXF1 110 MAC inc luding gen eral fea tures, a nd
interface types and descriptions.
•Section 6.0, “Applications” on page 96
Discusses the following:
—“Power S upply Sequencing”
—“TX FIFO and RX FIFO Operation”
—“Reset and Initialization”
—“Optical Module Connections to the IXF1110 MAC”
•Section 7.0, “Electri ca l Specifications” on page 106
I nform ation on the product-operating param eters, electrical spe cificat ions, and timi ng
parameters.
•Section 8.0, “Register Definitions” on page 123
Memo ry map/detailed descriptions and default val ues for the regis ter se t.
•Se ction 9.0, “Mechanical Specificati ons” on page 179
I XF1110 MAC pac kaging information.
•Section 10.0, “Product Ordering Information” on page 183
Provides a table with part-number information and diagram to order the
I XF1110 MAC.
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Co ntroller
Order Number : 250210, Revision: 009 1 5
1.2 Related Docum ents
§ §
Title Document
Number
Intel® IXF1110 MAC Specification Update 251436
Intel® IXF 1010 and IXF1110 10- Port Gigabit E thernet Media Access Control lers Design and
Layout Guide 250676
Intel® IXF1110 Demo Board Development Kit Manual 250807
Intel® SPI4 Phase 2 Performance in Gigabit Ethernet Media Access Controllers Application
Note 250643
Interfacing with the Intel® IXF1010 and Intel® IXF1110 10-Port Gigab it Ethernet Media A c cess
Controllers Application Note 250856
Intel® IXF1110 Thermal Design Considerations Application Note 250289
Flow Control in the Intel® IXF1010 and Intel® IXF1110 10-Port Gigabit Ethernet Media Access
Controllers Application Note 250236
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
16 Order N umber: 250210, Revision: 009
2.0 General Descripti on
The I nte l® IXF1110 MAC is a 10-port 1000 Mbps Ethernet Media Access Controller ( MAC). The
10 Gigab it inte rface to th e network process or is s upporte d throu gh a Syst em Pack et Inte rface Lev el
4 Pha se 2 (SPI 4-2), and the media interfac e is an integrat ed Serializer/Deserializer (SerDes).
Figure 1 illustrat es the IXF11 10 MAC block diagram.F igure 2 repr esents th e I X F1110 MA C
system block diagram.
Figure 1. IXF1110 MAC Block Diagram
SPI4-2
SPI4-2
Scheduler
CPU Interface
LED
Controller
RMON
Statistics
Optical
Module
Controller
IXF1110
SerDes 0
SerDes 1
SerDes 2
SerDes 3
SerDes 4
SerDes 5
SerDes 6
SerDes 7
SerDes 8
SerDes 9
MAC Core RX/TX FIFOs 0
MAC Core RX/TX FIFOs 1
MAC Core RX/TX FIFOs 2
MAC Core RX/TX FIFOs 3
MAC Core RX/TX FIFOs 4
MAC Core RX/TX FIFOs 5
MAC Core RX/TX FIFOs 6
MAC Core RX/TX FIFOs 7
MAC Core RX/TX FIFOs 8
MAC Core RX/TX FIFOs 9
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Co ntroller
Order Number : 250210, Revision: 009 1 7
§ §
Figure 2. IXF1 110 MAC System Block Diagram
IXF1110 CPU
LED
Serial-to-Parallel
C o nverte r u P IF
LE D Seria l
Interface
Por t 0 Optics Module
Por t 1 Optics Module
Por t 2 Optics Module
Por t 3 Optics Module
Por t 4 Optics Module
Por t 5 Optics Module
Por t 6 Optics Module
Por t 7 Optics Module
Por t 8 Optics Module
Por t 9 Optics Module
S er De s/O p tic al Mo du le Inter fa ce
Forwarding
Engine
Network
Processor
SPI4-2
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
18 Order N umber: 250210, Revision: 009
3.0 Ball Assignment s and Ball List Tables
Fi gure 3 i llu strates t he IXF1 110 MAC 552-Ball CBGA as signmen ts. Table 11 an d Table 12 provide
ball lis t tables in alphan umer ic order by signal na me and ball location under Section 4.3, “Ba ll List
Ta ble s” on page 3 2 .
§ §
Figure 3. 552-Ball CBGA Assignmen ts (Top View)
B2510-01
1
ABCDEFGHJKLMNPRTUVWYAA
AB
ACAD
ABCDEFGHJKLMNPRTUVWYAAABACAD
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A5
A4
A3
A2
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B5
B4
B3
B2
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C5
C4
C3
C2
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D5
D4
D3
D2
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E5
E4
E3
E2
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F5
F4
F3
F2
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G5
G4
G3
G2
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H5
H4
H3
H2
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J5
J4
J3
J2
A1B1C1D1E1F1G1H1J1K1L1M1N1
L1R1T1U1V1W1Y1AA1AB1AC1AD1
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K5
K4
K3
K2
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L5
L4
L3
L2
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M5
M4
M3
M2
N6
N7
N8
N9
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N5
N4
N3
N2
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P5
P4
P3
P2
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R5
R4
R3
R2
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T5
T4
T3
T2
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U5
U4
U3
U2
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V5
V4
V3
V2
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W5
W4
W3
W2
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y5
Y4
Y3
Y2
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA5
AA4
AA3
AA2
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB5
AB4
AB3
AB2
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD5
AD4
AD3
AD2
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC5
AC4
AC3
AC2
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Co ntroller
Order Number : 250210, Revision: 009 1 9
4.0 Ball Assignments and Signal Descriptions
4.1 Naming Conventions
4.1.1 Signal Name Conventions
Sig nal names begin with a Signal Mnemonic , and can also contain one or more of the following
des ignations : a differential pair de signation, a serial des ignation, and an active Low designation.
Sig nal naming conventions are as follows:
Differential Pair + Port Designation. The p o sitive and negative components of differ ential pairs
tied to a specific port are designated by the Signal Mnemonic, immediately followe d by an
underscore and either P (positive component) or N (negative component), and a n underscore
followed by the port designation. For example , SerDes interface signals for port 0 are identified as
TX_P_0 and T X_ N_0.
Serial Designation. A set of signa ls that ar e not tied to any spec ific port are de signated by the
Signal Mnemonic, followed by a bracketed serial designation. For example, the set of 11 CPU
Addres s Bus signals is identified as UPX_ADD[1 0:0].
Port Designation. Individu al signals th at apply to a particular port are designated by the Signa l
Mnemonic, immedi ate ly followed by an undersco re and the Port Designation. For exa mple,
Optical module I2C S erial Data signals would be identified as I2C_DATA_0, I2C _D ATA_ 1 , et c.
Active Low Designation. A control input or indicat or output that is act ive Low is designated by a
final suf fix consi stin g of an un dersc ore foll owe d by an up per ca se “L” . For exa mple , the CPU cycle
complete identifier is shown as UPX_R DY_ L.
4.1.2 Register Address Conventions
Regis ters loc ated in on-chi p memory are a ccessed using a register address, which is prov ided in
Hex notation. A Register Address is indicated by the dollar sign ($), followed by the memory
location in Hex.
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IIXF1110 1 0-Port 1000 Mbp s Ether net Medi a Access C ontroller
20 Order N umber: 250210, Revision: 009
4.2 Interface Signal Groups
Thi s section describes the IXF1 110 MAC signal s in groups accor ding to the assoc iated inte rface or
function. Figur e 4 and Table 1, “SPI4-2 Interface Signal Descriptions” through Table 10, “Unused
Balls/Reserved” descri be the s ignals used by the IXF1110 MAC.
Figure 4. Interface Diagram
Intel®
IXF1110
TDAT[15:0]_P/N
TDO
RSCLK
RCTL_P/N
RDCLK_P/N
RSTAT[1:0]
RDAT[15:0]_P/N
TSCLK
TCTL_P/N
TDCLK_P/N
TSTAT[1:0]
UPX_ADD[10:0]
UPX_DATA[31:0]
TXPAUSEFR
TXPAUSEADD[3:0]
TCLK
TDI
TMS
UPX_WR_L
UPX_RD_L
UPX_CS_L
UPX_RDY_L
SerDes
Interface
JTAG
Interface
CPU
Interface
RX_P/N_0:9
SPI4-2
Interface
TX_P/N_0:9
P
ause Control
Interface
Optica
l
Modul
e
Interfac
e
MOD_DEF_0:9
TX_DISABLE_0:9
TX_FAULT_0:9
RX_LOS_0:9
TX_FAULT_INT
RX_LOS_INT
MOD_DEF_INT
I2C_CLK
I2C_DATA_0:9
LED
Interface
LED_CLK
LED_LATCH
LED_DATA
CLK125 System
Interface
CLK50
SYS_RES_L
B2585-02
TRST_L
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 21
Table 1. SPI4-2 Interface Signal Descri ption s (Sheet 1 of 2)
S ign al Nam e Ba ll Des ign ato r Typ e Standa rd Signa l Des cr ip tion
TDAT15_P, TDAT15_N
TDAT14_P, TDAT14_N
TDAT13_P, TDAT13_N
TDAT12_P, TDAT12_N
TDAT11_P, TDAT11_N
TDAT10_P, TDAT10_N
TDAT9_P, TDAT9 _N
TDAT8_P, TDAT8 _N
TDAT7_P, TDAT7 _N
TDAT6_P, TDAT6 _N
TDAT5_P, TDAT5 _N
TDAT4_P, TDAT4 _N
TDAT3_P, TDAT3 _N
TDAT2_P, TDAT2 _N
TDAT1_P, TDAT1 _N
TDAT0_P, TDAT0 _N
G11
C9
J9
H7
E8
E9
B7
L5
C7
L8
G5
F7
G9
B5
H3
J6
H11
D9
K10
J8
E7
F9
C8
M5
C6
L7
H5
G6
H9
C5
J3
J5
Input LVDS
Transmit Data Bus: Carries
payload data and in-band control
words to the IXF1110 link-layer
device.
Inte rna lly termi na ted diffe rentia ll y
wi t h 10 0 Ω.
TDCLK_P
TDCLK_N D3
E4 Input LVDS
Transmit Data Clock: Clock
as sociated with TDAT[15:0] and
TCTL. Data and contr ol lines a re
driven off the risin g and falling
edges of the clock.
Inte rna lly termi na ted diffe rentia ll y
wi t h 10 0 Ω.
NOTE: If TDCLK is applied to the
IXF 1110 af ter t he dev ice has co me
out of reset, the system designer
must ensure the TDCLK is stable
whe n a ppli e d. F ailu re t o due so ca n
result in the IX F1110 tr aining on a
non-stab le clo ck, causing DIP4
err ors and data corrup tion.
TCTL_P
TCTL_N M10
N10 Input LVDS
Transmit Control: TCTL is High
when a c ontrol word is p resent on
TD AT [15:0 ]. Ot he rwise , TCTL is
Low.
Inte rna lly termi na ted diffe rentia ll y
wi t h 10 0 Ω.
TSCLK C11 Output 2.5 V
LVTTL
Transmit Status Clock: Clock
associated with TSTAT [1:0].
Frequency is equal to one-quarter
TDCLK.
TSTAT1
TSTAT0 E6
E5 Output 2.5 V
LVTTL
Transmit FIFO Status: Carries
round-robi n FIFO status
information, along with a ssociated
err or detection and fr am ing.
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IIXF1110 1 0-Port 1000 Mbp s Ethernet M edia Access Cont roller
22 Order N umber: 25 0210, Revi sion: 009
RDAT1 5_P, RDAT15 _N
RDAT1 4_P, RDAT14 _N
RDAT1 3_P, RDAT13 _N
RDAT1 2_P, RDAT12 _N
RDAT11 _P, RDAT11_N
RDAT1 0_P, RDAT10 _N
RDAT9_P, RDAT9_N
RDAT8_P, RDAT8_N
RDAT7_P, RDAT7_N
RDAT6_P, RDAT6_N
RDAT5_P, RDAT5_N
RDAT4_P, RDAT4_N
RDAT3_P, RDAT3_N
RDAT2_P, RDAT2_N-
RDAT1_P, RDAT1_N
RDAT0_P, RDAT0_N
K12
F16
E13
A13
J16
G17
D18
C16
M15
E16
L17
J18
G21
F18
B20
E19
K13
G16
E14
A14
K15
G18
E18
D16
N15
E17
L18
J19
H20
G19
C20
E20
Output LVDS
Receive Data: Carries payload
data and in-band control from the
IXF1 110 link-layer device.
Internally terminated differentially
with 100 Ω.
RDCLK_P
RDCLK_N C18
C19 Output LVDS
Receive Data Clock: Clock
associated w ith RDAT[15:0] and
RC TL. D ata and con trol lines are
driv en off the rising and falling
edges of the clock.
The frequency range is
320-400 Mhz. F requency is always
a mu lt iplied- by-8 version of t he
CLK50 refer ence clock.
Internally terminated differentially
with 100 Ω.
RCTL_P
RCTL_N H16
H18 Output LVDS
Receive Co ntrol: RCTL is High
whe n a co ntrol word is pr e se nt on
RD AT[15:0]. Otherwise, RCTL is
Low.
Internally terminated differentially
with 100 Ω.
RSCLK J17 Input 2.5 V
LVTTL Receive Stat us Clock: The clo c k
associated with RS TAT[1: 0].
RSTAT1
RSTAT0 J20
L20 Input 2.5 V
LVTTL
Receive FIFO Status: Carries
round-robin FIFO status
information, along with associa ted
error detection and fr aming.
Table 1. SPI4-2 Interface Signal Descriptions (S heet 2 of 2)
Signal Name Ball Designator Type Standard Signal Description
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 23
Table 2. SerDes Interface Signal Descriptions
Signal Name Ball Designator Type Standard Signal Description
TX_P_0, TX_ N _0
TX_P_1, TX_ N _1
TX_P_2, TX_ N _2
TX_P_3, TX_ N _3
TX_P_4, TX_ N _4
TX_P_5, TX_ N _5
TX_P_6, TX_ N _6
TX_P_7, TX_ N _7
TX_P_8, TX_ N _8
TX_P_9, TX_ N _9
V20
Y19
V22
Y23
AB12
AD12
AB9
AD9
T3
T5
V21
Y20
W22
Y22
AB11
AD11
AC9
AD10
U3
U5
Output SerDes Transmit Differential Output:
Carries the 1.25 GHz data to the
optics module.
RX_P_0, RX_N_0
RX_P_1, RX_N_1
RX_P_2, RX_N_2
RX_P_3, RX_N_3
RX_P_4, RX_N_4
RX_P_5, RX_N_5
RX_P_6, RX_N_6
RX_P_7, RX_N_7
RX_P_8, RX_N_8
RX_P_9, RX_N_9
T22
T20
U24
W24
AB13
AD13
AB16
AD16
V5
Y6
U22
U20
T24
V24
AB14
AD14
AC16
AD15
V4
Y5
Input SerDes
Receive Differential Input:
Carries the 1.25 GHz data from
th e op t ic s mod ule.
Inte rna lly termi na ted diffe rentia ll y
wi t h 10 0 Ω.
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IIXF1110 1 0-Port 1000 Mbp s Ethernet M edia Access Cont roller
24 Order N umber: 25 0210, Revi sion: 009
Table 3. CPU Interface Signal Descriptions (Sheet 1 of 2)
Sign a l Name Ball Designator Type S tandard Sign a l Des c ription
UPX_ADD10
UPX_ADD9
UPX_ADD8
UPX_ADD7
UPX_ADD6
UPX_ADD5
UPX_ADD4
UPX_ADD3
UPX_ADD2
UPX_ADD1
UPX_ADD0
C2
F1
F5
C3
G1
E2
E3
H1
F3
G4
J1
Input 2.5 V
CMOS Address bus: 11-bit address bus
UPX_CS_L F20 Input 2.5 V
CMOS Chip Select Signal: Act ive Low chip
select
UPX_DATA31
UPX_DATA30
UPX_DATA29
UPX_DATA28
UPX_DATA27
UPX_DATA26
UPX_DATA25
UPX_DATA24
UPX_DATA23
UPX_DATA22
UPX_DATA21
UPX_DATA20
UPX_DATA19
UPX_DATA18
UPX_DATA17
UPX_DATA16
UPX_DATA15
UPX_DATA14
UPX_DATA13
UPX_DATA12
UPX_DATA11
UPX_DATA10
UPX_DATA9
UPX_DATA8
UPX_DATA7
UPX_DATA6
UPX_DATA5
UPX_DATA4
UPX_DATA3
UPX_DATA2
UPX_DATA1
UPX_DATA0
C23
B22
A21
B18
A17
C17
A16
G14
E15
B16
G13
A15
A12
F14
C14
D14
D7
F11
E10
G12
A11
E12
A9
A10
A8
C13
E11
C12
A7
B9
A4
B3
Input/
Output 2.5 V
CMOS Bi-di r ect ion al da ta bus: 32-bit bi-
dir ec tiona l data bus
1. This I/ O meets the 2.5 V CMOS spe c ification on ly during bounda ry scan m ode .
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 25
UPX_WR_L A18 Input 2.5 V
CMOS Write Strobe: Active Low Wr ite str obe
UPX_RD_L H14 Input 2.5 V
CMOS Read Stro be: Active Low Read strobe
UPX_RDY_L C22 Open
Drain
Output* 2. 5 V
CMOS1
Cycle complete indicator: Indicates
that Read or Write is complete.
NOTE: An external pull-up resistor is
requir e d for prop er operation.
NOTE: *Dual-mode I/O.
Normal oper ation: Op en drain
output
Boundary Scan Mode: S tandard
CMOS output
Table 4. Pause Control Interface Signal Descri ption s
Signal Name Ball Designator Type Standard Signal Description
TXPAUSEFR J7 Input 2.5 V
CMOS Pause Strobe: Indicat es when a
Pause frame is to be sent
TXPAUSEADD3
TXPAUSEADD2
TXPAUSEADD1
TXPAUSEADD0
K1
J2
G2
G3 Input 2.5 V
CMOS Pause Address Bus: Selects t he port
for th e Paus e frames
Table 3. CPU Interface Signal Descriptions (Sheet 2 of 2)
S ign al Nam e B all Desig nat or Ty pe Standar d Signal Des cription
1. This I/O meets the 2.5 V CMOS specification only during boundary scan mode.
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IIXF1110 1 0-Port 1000 Mbp s Ethernet M edia Access Cont roller
26 Order N umber: 25 0210, Revi sion: 009
Table 5. Optical Module Interface S ignal Descripti ons (Sheet 1 of 2)
Signal Name Ball Designator Type Standard Signal Description
TX_FAULT_0
TX_FAULT_1
TX_FAULT_2
TX_FAULT_3
TX_FAULT_4
TX_FAULT_5
TX_FAULT_6
TX_FAULT_7
TX_FAULT_8
TX_FAULT_9
M24
V23
Y17
R15
W14
W11
W9
AC5
P8
L2
Input 2.5 V
CMOS
Transmitter Fault: Input used to
de te rm ine w h en th ere i s a opt ica l
module transmitter fault.
RX_LOS_0
RX_LOS_1
RX_LOS_2
RX_LOS_3
RX_LOS_4
RX_LOS_5
RX_LOS_6
RX_LOS_7
RX_LOS_8
RX_LOS_9
L22
V17
AD18
R12
AB15
V12
Y9
AC3
T2
P2
Input 2.5 V
CMOS
Receiver L oss of Signal: Input
used to determine when the
o pti c al modu le rec eiver loses
synchronization.
MOD_DEF_0
MOD_DEF_1
MOD_DEF_2
MOD_DEF_3
MOD_DEF_4
MOD_DEF_5
MOD_DEF_6
MOD_DEF_7
MOD_DEF_8
MOD_DEF_9
N24
Y21
AA16
M20
AC14
U11
T4
AB2
R7
L1
Input 2.5 V
CMOS
Module Definition: Input used to
de te rm ine w h en a o pt ica l m odu l e
m o dule is presen t.
TX_DISABLE_0
TX_DISABLE_1
TX_DISABLE_2
TX_DISABLE_3
TX_DISABLE_4
TX_DISABLE_5
TX_DISABLE_6
TX_DISABLE_7
TX_DISABLE_8
TX_DISABLE_9
K22
M22
AC22
U18
U14
AA18
U9
AA9
V7
L4
Open
Drain
Output*
2.5 V
CMOS1
Transmitter Disable: Output
used to disable a optical module
transmitter.
External pull-up resistor usually
resident in a op tical m odu le is
required for proper operation.
NOTE: *Dual-mod e I/O.
Normal oper ation: Op en
drain output
Boundary Scan M ode:
Standar d CMOS output
TX_FAULT_INT B11 Open
Drain
Output* 2.5 V
CMOS1
Transmitter Fault interrupt:
Open dr ain output inter rupt t o
signal a TX_FAUL T condition.
NOTE: *Dual-mod e I/O.
Normal oper ation: Op en
drain output
Boundary Scan M ode:
Standar d CMOS output
1. This I/ O meets the 2.5 V CMOS spe c ification on ly during bounda ry scan m ode .
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 27
RX_LOS_INT B14 Open
Drain
Output* 2. 5 V
CMOS1
Receiver Loss of Signal
Interrupt: Open drain output
interrupt to signal an RX_LOS
condition.
NOTE: *Dual-mode I/O.
No r mal op er a tion: Ope n
drain output
Boundary Scan Mode:
Standard C M O S output
MOD_DEF_INT G15 Open
Drain
Output* 2. 5 V
CMOS1
Module Definition Interrupt:
Open dr ain ou tput interrupt to
signal a M O D_DEF co ndition.
NOTE: *Dual-mode I/O.
No r mal op er a tion: Ope n
drain output
Boundary Scan Mode:
Standard C M O S output
I2C_CLK L19 Output 2.5 V
CMOS I2C Reference Clock: Clock
used for I2C bus inter face.
I2C_DATA_0
I2C_DATA_1
I2C_DATA_2
I2C_DATA_3
I2C_DATA_4
I2C_DATA_5
I2C_DATA_6
I2C_DATA_7
I2C_DATA_8
I2C_DATA_9
G22
G23
J24
F22
E23
H24
G20
E22
G24
F24
Input/
Output* 2. 5 V
CMOS1
I2C Data Bus: Data I/O for the
I2C bus in terface.
NOTE: *Dual-mode I/O.
No r ma l op er a tion: Inpu t /
output
Boundary Scan Mode:
Standard C M O S output
Table 6. LED Interface Signal Descripti ons
Signal Name Ball Designator Type Standard Signal Description
LED_CLK A19 Output 2.5 V
CMOS LED Clock: Clock output for the
LED block.
LED_DATA A20 Output 2. 5 V
CMOS LED Dat a: Data output for the
LED block.
LED_LATCH K18 Output 2. 5 V
CMOS LED Latch : Latc h enable for the
LED block.
Table 5. Optica l Module Interface Signal Descrip tions (Sheet 2 of 2)
S ign al Nam e Ball Desig nator Type Standa rd S ign al Des crip t ion
1. This I/O meets the 2.5 V CMOS specification only during boundary scan mode.
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IIXF1110 1 0-Port 1000 Mbp s Ethernet M edia Access Cont roller
28 Order N umber: 25 0210, Revi sion: 009
Table 7. JTAG Interface Signal Descriptions
Signal Name Ball Designator Type Standard Signal Description
TCK AA24 Input 3.3 V
LVTTL JTAG Test Clock: Reference
clock for JTAG.
TMS T16 Input 3.3 V
LVTTL JTAG Test Mode Selec t: Selects
test mode for JTAG.
TDI AC18 Input 3.3 V
LVTTL
JTAG Test Data Input: Test data
sampled with respect to the rising
edge of TC K.
TRST_L N18 Input 3.3 V
LVTTL JTAG Test Reset: Reset input for
JTAG t est .
TDO Y24 Output 3.3 V
LVTTL
JTAG Test Data Output: Test
data driven with respe ct to the
falling edge of TCK.
Table 8. System Interface Signal Descriptions
Signal Name Ball Designator Type Standard Signal Description
CLK125 AA5 Input 2.5 V
CMOS 12 5 MHz R efe ren ce Clock: I nput
clock to PL L.
CLK50 C21 Input 2.5 V
CMOS
SPI4-2 Reference Clock: Input
clock to SPI4-2 RX PLL.
Input range is 40 MHz to 50 MHz.
This clock multiplied by eight must
eq ual the requi red RX SP I4-2
data clock frequency.
SYS_RES_L Y4 Input 2.5 V
CMOS System Re set: System hard
reset (active Low).
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 29
Tabl e 9. Power Supply Sign al Desc riptions (S heet 1 of 2)
Signa l Name Ba ll Des ign ato r Ty pe Standa rd S igna l Des crip tion
AVDD1P8_1 D1 E24 – – 1.8 V Analog Power
Supply: 1.8 V supply for
analog circuits.
AVDD1P8_2 P7
V14 P18
V18 V6 V11 ––
1.8 V Analog Power
Supply: 1.8 V supply for
analog circuits.
AVDD2P5_1 Y1 – – 2.5 V Analog Power
Supply: 2.5 V supply for
analog circuits.
AVDD2P5_2 N3
V10 N22
V15 P3 P22 ––
2.5 V Analog Power
Supply: 2.5 V supply for
analog circuits.
VDD
D6
D19
F21
J11
K5
L9
P9
R4
T11
W4
AA15
D10
D20
H10
J14
K8
L11
P11
R8
T14
W21
AA19
D11
E21
H15
K3
K17
L14
P14
R17
U10
AA6
AB4
D15
F4
J4
K4
K21
L16
P16
R21
U15
AA10
––
1.8 V Digital Power
Supply: 1.8 V co re
supply.
VDD2
B4
B17
F8
H2
J12
M9
M19
N9
N19
U2
W8
AA2
AC12
B8
B21
F12
H6
J13
M12
M23
N12
N23
U6
W12
AA23
AC13
B12
D2
F13
H19
M2
M13
N2
N13
T12
U19
W13
AC4
AC17
B13
D23
F17
H23
M6
M16
N6
N16
T13
U23
W17
AC8
AC21
––
2.5 V Digital Power
Supply: 2.5 V I /O supp ly.
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IIXF1110 1 0-Port 1000 Mbp s Ethernet M edia Access Cont roller
30 Order N umber: 25 0210, Revi sion: 009
GND
B6
C4
D12,
D22
F6
F23
H12
J10
K2
K14
K23
L10
L24
M11
M21
N14
P10
P21
R2
R10
R19
T8
T17
T23
U12,
U21
V16
W6
W19
Y3
Y15
AA3
AA12
AA21
AB17
AC7
AC19
B10
D4
D13
D24
F10
G10
H13
J15
K6
K16
K24
L12
M3
M14
N4
N17
P12
P23
R3
R11
R23
T9
T18
U4
U13
V2
W2
W7
W20
Y8
Y16
AA4
AA13
AB6
AB21
AC10
AC20
B15
D5
D17
E1
F15
H4
H17
J21
K9
K19
L3
L13
M4
M17
N8
N21
P13
P24
R6
R14
R24
T10
T19
U7
U16
V3
W3
W10
W23
Y12
Y18
AA7
AA14
AB7
AB23
AC11
AD21
B19
D8
D21
F2
F19
H8
H21
J23
K11
K20
L6
L15
M8
M18
N11
P1
P15
R1
R9
R16
T7
T15
T21
U8
U17
V13
W5
W15
Y2
Y13
AA1
AA8
AA17
AB10
AC6
AC15
––
Ground: Gr ound return
for all signals.
Table 9. Power Supply Signal Description s (Sheet 2 of 2)
Signal Name Ball Designator Type Standard Signal Description
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 31
§ §
Table 10. Unused Balls/Reserved
Signal Name Ball Designator Type Standard Signal Description
NC
A5
G7
K7
M7
N20
P17
R13
T1
V8
W16
Y11
AA22
AB18
AD4
AD8
A6
G8
L21
N1
P4
P19
R18
T6
V9
W18
Y14
AB3
AB19
AD5
AD17
C10
H22
L23
N5
P5
P20
R20
U1
V19
Y7
AA11
AB5
AB20
AD6
AD19
C15
J22
M1
N7
P6
R5
R22
V1
W1
Y10
AA20
AB8
AB22
AD7
AD20
– – No co nnec t ion.
No Ball
A2
A24
B24
AB24
AC24
AD22
A3
B1
C1
AC1
AD1
AD23
A22
B2
C24
AC2
AD2
AD24
A23
B23
AB1
AC23
AD3 ––
Balls removed from
substrate.
No Pad A1 – – Pad removed from
substra te. Us e this ball
locatio n as a ke y for de vice
placement onto the PCB.
Intel® II XF1110 10-Port 1000 Mbps Ethern et Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
32 Order N umber: 25 0210, Revi sion : 009
4.3 Ball List Tables
Ball list tables are provided in alphanumeric order by signal name (Table 11) and by ball loca tion
order (Table 12).
Note: Intel recommends that all unconnected balls be tied to their inactive states through external
pull-ups or pull-downs.
4.3.1 Balls Listed in Alphanumeric Order by Signal Name
Table 11 shows the ball l ocations and si gnal nam es arranged in al phanumeric order by s ignal name.
Tab le 11. B all Li st in Alp hanum eric Order by Si gnal Na me
Signal Ball
AVDD1P8_1 D1
AVDD1P8_1 E24
AVDD1P8_2 P7
AVDD1P8_2 P18
AVDD1P8_2 V6
AVDD1P8_2 V11
AVDD1P8_2 V14
AVDD1P8_2 V18
AVDD2P5_1 Y1
AVDD2P5_2 N3
AVDD2P5_2 N22
AVDD2P5_2 P3
AVDD2P5_2 P22
AVDD2P5_2 V10
AVDD2P5_2 V15
CLK125 AA5
CLK50 C21
GND B6
GND B10
GND B15
GND B19
GND C4
GND D4
GND D5
GND D8
GND D12
GND D13
GND D17
GND D21
GND D22
GND D24
GND E1
GND F2
GND F6
GND F10
GND F15
GND F19
GND F23
GND G10
GND H4
GND H8
GND H12
GND H13
GND H17
GND H21
GND J10
GND J15
GND J21
GND J23
GND K2
GND K6
GND K9
GND K11
GND K14
GND K16
GND K19
Signal Ball
GND K20
GND K23
GND K24
GND L3
GND L6
GND L10
GND L12
GND L13
GND L15
GND L24
GND M3
GND M4
GND M8
GND M11
GND M14
GND M17
GND M18
GND M21
GND N4
GND N8
GND N11
GND N14
GND N17
GND N21
GND P1
GND P10
GND P12
GND P13
Signal Ball
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 33
GND P15
GND P21
GND P23
GND P24
GND R1
GND R2
GND R3
GND R6
GND R9
GND R10
GND R11
GND R14
GND R16
GND R19
GND R23
GND R24
GND T7
GND T8
GND T9
GND T10
GND T15
GND T17
GND T18
GND T19
GND T21
GND T23
GND U4
GND U7
GND U8
GND U12
GND U13
GND U16
GND U17
GND U21
GND V2
GND V3
GND V13
GND V16
GND W2
Signal Ball
GND W3
GND W5
GND W6
GND W7
GND W10
GND W15
GND W19
GND W20
GND W23
GND Y2
GND Y3
GND Y8
GND Y12
GND Y13
GND Y15
GND Y16
GND Y18
GND AA1
GND AA3
GND AA4
GND AA7
GND AA8
GND AA12
GND AA13
GND AA14
GND AA17
GND AA21
GND AB6
GND AB7
GND AB10
GND AB17
GND AB21
GND AB23
GND AC6
GND AC7
GND AC10
GND AC11
GND AC15
GND AC19
Signal Ball
GND AC20
GND AD21
I2C_CLK L19
I2C_DATA_0 G22
I2C_DATA_1 G23
I2C_DATA_2 J24
I2C_DATA_3 F22
I2C_DATA_4 E23
I2C_DATA_5 H24
I2C_DATA_6 G20
I2C_DATA_7 E22
I2C_DATA_8 G24
I2C_DATA_9 F24
LED_CLK A19
LED_DATA A20
LED_LATCH K18
MOD_DEF_0 N24
MOD_DEF_1 Y21
MOD_DEF_2 AA16
MOD_DEF_3 M20
MOD_DEF_4 AC14
MOD_DEF_5 U11
MOD_DEF_6 T4
MOD_DEF_7 AB2
MOD_DEF_8 R7
MOD_DEF_9 L1
MOD_DEF_INT G15
NC A5
NC A6
NC C10
NC C15
NC G7
NC G8
NC H22
NC J22
NC K7
NC L21
NC L23
NC M1
Signal Ball
Intel® II XF1110 10-Port 1000 Mbps Ethern et Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
34 Order N umber: 25 0210, Revi sion : 009
NC M7
NC N1
NC N5
NC N7
NC N20
NC P4
NC P5
NC P6
NC P17
NC P19
NC P20
NC R5
NC R13
NC R18
NC R20
NC R22
NC T1
NC T6
NC U1
NC V1
NC V8
NC V9
NC V19
NC W1
NC W16
NC W18
NC Y7
NC Y10
NC Y11
NC Y14
NC AA11
NC AA20
NC AA22
NC AB3
NC AB5
NC AB8
NC AB18
NC AB19
NC AB20
Signal Ball
NC AB22
NC AD4
NC AD5
NC AD6
NC AD7
NC AD8
NC AD17
NC AD19
NC AD20
No Ball A2
No Ball A3
No Ball A22
No Ball A23
No Ball A24
No Ball B1
No Ball B2
No Ball B23
No Ball B24
No Ball C1
No Ball C24
No Ball AB1
No Ball AB24
No Ball AC1
No Ball AC2
No Ball AC23
No Ball AC24
No Ball AD1
No Ball AD2
No Ball AD3
No Ball AD22
No Ball AD23
No Ball AD24
No Pad A1
RCTL_N H18
RCTL_P H16
RDAT0_N E20
RDAT0_P E19
RDAT1_N C20
RDAT1_P B20
Signal Ball
RDAT2_N G19
RDAT2_P F18
RDAT3_N H20
RDAT3_P G21
RDAT4_N J19
RDAT4_P J18
RDAT5_N L18
RDAT5_P L17
RDAT6_N E17
RDAT6_P E16
RDAT7_N N15
RDAT7_P M15
RDAT8_N D16
RDAT8_P C16
RDAT9_N E18
RDAT9_P D18
RDAT10_N G18
RDAT10_P G17
RDAT11_N K15
RDAT11_P J16
RDAT12_N A14
RDAT12_P A13
RDAT13_N E14
RDAT13_P E13
RDAT14_N G16
RDAT14_P F16
RDAT15_N K13
RDAT15_P K12
RDCLK_N C19
RDCLK_P C18
RSCLK J17
RSTAT0 L20
RSTAT1 J20
RX_LOS_0 L22
RX_LOS_1 V17
RX_LOS_2 AD18
RX_LOS_3 R12
RX_LOS_4 AB15
RX_LOS_5 V12
Signal Ball
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 35
RX_LOS_6 Y9
RX_LOS_7 AC3
RX_LOS_8 T2
RX_LOS_9 P2
RX_LOS_INT B14
RX_N_0 U22
RX_N_1 U20
RX_N_2 T24
RX_N_3 V24
RX_N_4 AB14
RX_N_5 AD14
RX_N_6 AC16
RX_N_7 AD15
RX_N_8 V4
RX_N_9 Y5
RX_P_0 T22
RX_P_1 T20
RX_P_2 U24
RX_P_3 W24
RX_P_4 AB13
RX_P_5 AD13
RX_P_6 AB16
RX_P_7 AD16
RX_P_8 V5
RX_P_9 Y6
SYS_RES_L Y4
TCK AA24
TCTL_N N10
TCTL_P M10
TDAT0_N J5
TDAT0_P J6
TDAT1_N J3
TDAT1_P H3
TDAT2_P B5
TDAT3_N H9
TDAT3_P G9
TDAT4_N G6
TDAT4_P F7
TDAT5_N H5
Signal Ball
TDAT5_P G5
TDAT6_N L7
TDAT6_P L8
TDAT7_N C6
TDAT7_P C7
TDAT8_N M5
TDAT8_P L5
TDAT9_N C8
TDAT9_P B7
TDAT10_N F9
TDAT10_P E9
TDAT11_N E7
TDAT11_P E8
TDAT12_N J8
TDAT12_P H7
TDAT13_N K10
TDAT13_P J9
TDAT14_N D9
TDAT14_P C9
TDAT15_N H11
TDAT15_P G11
TDAT2_N C5
TDCLK- E4
TDCLK_P D3
TDI AC18
TDO Y24
TMS T16
TRST_L N18
TSCLK C11
TSTAT0 E5
TSTAT1 E6
TX_DISABLE_0 K22
TX_DISABLE_1 M22
TX_DISABLE_2 AC22
TX_DISABLE_3 U18
TX_DISABLE_4 U14
TX_DISABLE_5 AA18
TX_DISABLE_6 U9
TX_DISABLE_7 AA9
Signal Ball
TX_DISABLE_8 V7
TX_DISABLE_9 L4
TX_FAULT_0 M24
TX_FAULT_1 V23
TX_FAULT_2 Y17
TX_FAULT_3 R15
TX_FAULT_4 W14
TX_FAULT_5 W11
TX_FAULT_6 W9
TX_FAULT_7 AC5
TX_FAULT_8 P8
TX_FAULT_9 L2
TX_FAULT_INT B11
TX_N_0 V21
TX_N_1 Y20
TX_N_2 W22
TX_N_3 Y22
TX_N_4 AB11
TX_N_5 AD11
TX_N_6 AC9
TX_N_7 AD10
TX_N_8 U3
TX_N_9 U5
TX_P_0 V20
TX_P_1 Y19
TX_P_2 V22
TX_P_3 Y23
TX_P_4 AB12
TX_P_5 AD12
TX_P_6 AB9
TX_P_7 AD9
TX_P_8 T3
TX_P_9 T5
TXPAUSEADD0 G3
TXPAUSEADD1 G2
TXPAUSEADD2 J2
TXPAUSEADD3 K1
TXPAUSEFR J7
UPX_ADD0 J1
Signal Ball
Intel® II XF1110 10-Port 1000 Mbps Ethern et Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
36 Order N umber: 25 0210, Revi sion : 009
UPX_ADD2 F3
UPX_ADD3 H1
UPX_ADD4 E3
UPX_ADD5 E2
UPX_ADD6 G1
UPX_ADD7 C3
UPX_ADD8 F5
UPX_ADD9 F1
UPX_ADD1 G4
UPX_ADD10 C2
UPX_CS_L F20
UPX_DATA0 B3
UPX_DATA1 A4
UPX_DATA2 B9
UPX_DATA3 A7
UPX_DATA4 C12
UPX_DATA5 E11
UPX_DATA6 C13
UPX_DATA7 A8
UPX_DATA8 A10
UPX_DATA9 A9
UPX_DATA10 E12
UPX_DATA11 A11
UPX_DATA12 G12
UPX_DATA13 E10
UPX_DATA14 F11
UPX_DATA15 D7
UPX_DATA16 D14
UPX_DATA17 C14
UPX_DATA18 F14
UPX_DATA19 A12
UPX_DATA20 A15
UPX_DATA21 G13
UPX_DATA22 B16
UPX_DATA23 E15
UPX_DATA24 G14
UPX_DATA25 A16
UPX_DATA26 C17
UPX_DATA27 A17
Signal Ball
UPX_DATA28 B18
UPX_DATA29 A21
UPX_DATA30 B22
UPX_DATA31 C23
UPX_RD_L H14
UPX_RDY_L C22
UPX_WR_L A18
VDD D6
VDD D10
VDD D11
VDD D15
VDD D19
VDD D20
VDD E21
VDD F4
VDD F21
VDD H10
VDD H15
VDD J4
VDD J11
VDD J14
VDD K3
VDD K4
VDD K5
VDD K8
VDD K17
VDD K21
VDD L9
VDD L11
VDD L14
VDD L16
VDD P9
VDD P11
VDD P14
VDD P16
VDD R4
VDD R8
VDD R17
VDD R21
Signal Ball
VDD T11
VDD T14
VDD U10
VDD U15
VDD W4
VDD W21
VDD AA6
VDD AA10
VDD AA15
VDD AA19
VDD AB4
VDD2 B4
VDD2 B8
VDD2 B12
VDD2 B13
VDD2 B17
VDD2 B21
VDD2 D2
VDD2 D23
VDD2 F8
VDD2 F12
VDD2 F13
VDD2 F17
VDD2 H2
VDD2 H6
VDD2 H19
VDD2 H23
VDD2 J12
VDD2 J13
VDD2 M2
VDD2 M6
VDD2 M9
VDD2 M12
VDD2 M13
VDD2 M16
VDD2 M19
VDD2 M23
VDD2 N2
VDD2 N6
Signal Ball
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 37
VDD2 N9
VDD2 N12
VDD2 N13
VDD2 N16
VDD2 N19
VDD2 N23
VDD2 T12
VDD2 T13
VDD2 U2
VDD2 U6
VDD2 U19
VDD2 U23
VDD2 W8
VDD2 W12
VDD2 W13
VDD2 W17
VDD2 AA2
VDD2 AA23
VDD2 AC4
VDD2 AC8
VDD2 AC12
VDD2 AC13
VDD2 AC17
VDD2 AC21
Signal Ball
Intel® II XF1110 10-Port 1000 Mbps Ethern et Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
38 Order N umber: 25 0210, Revi sion : 009
4.3.2 Balls Listed in Alphanumeric Order by Ball Location
Table 12 shows the ball locations and signal names arranged in alphanumeric order by ball
location.
Note: Intel recommends that all unconnected balls be tied to their inactive states through external pull-
ups or pull-downs.
Table 12. Ball List in Alphanumeric Order by Ball Location
Ball Signal
A1 No Pad
A2 No Ball
A3 No Ball
A4 UPX_DATA1
A5 NC
A6 NC
A7 UPX_DATA3
A8 UPX_DATA7
A9 UPX_DATA9
A10 UPX_DATA8
A11 UPX_DATA11
A12 UPX_DATA19
A13 RDAT12_P
A14 RDAT12_N
A15 UPX_DATA20
A16 UPX_DATA25
A17 UPX_DATA27
A18 UPX_WR_L
A19 LED_CLK
A20 LED_DATA
A21 UPX_DATA29
A22 No Ball
A23 No Ball
A24 No Ball
B1 No Ball
B2 No Ball
B3 UPX_DATA0
B4 VDD2
B5 TDAT2_P
B6 GND
B7 TDAT9_P
B8 VDD2
B9 UPX_DATA2
B10 GND
B11 TX_FAULT_INT
B12 VDD2
B13 VDD2
B14 RX_LOS_INT
B15 GND
B16 UPX_DATA22
B17 VDD2
B18 UPX_DATA28
B19 GND
B20 RDAT1_P
B21 VDD2
B22 UPX_DATA30
B23 No Ball
B24 No Ball
C1 No Ball
C2 UPX_ADD10
C3 UPX_ADD7
C4 GND
C5 TDAT2_N
C6 TDAT7_N
C7 TDAT7_P
C8 TDAT9_N
C9 TDAT14_P
C10 NC
C11 TSCLK
C12 UPX_DATA4
C13 UPX_DATA6
C14 UPX_DATA17
C15 NC
C16 RDAT8_P
Ball Signal
C17 UPX_DATA26
C18 RDCLK_P
C19 RDCLK_N
C20 RDAT1_N
C21 CLK50
C22 UPX_RDY_L
C23 UPX_DATA31
C24 No Ball
D1 AVDD1P8_1
D2 VDD2
D3 TDCLK_P
D4 GND
D5 GND
D6 VDD
D7 UPX_DATA15
D8 GND
D9 TDAT14_N
D10 VDD
D11 VDD
D12 GND
D13 GND
D14 UPX_DATA16
D15 VDD
D16 RDAT8_N
D17 GND
D18 RDAT9_P
D19 VDD
D20 VDD
D21 GND
D22 GND
D23 VDD2
D24 GND
Ball Signal
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 39
E1 GND
E2 UPX_ADD5
E3 UPX_ADD4
E4 TDCLK-
E5 TSTAT0
E6 TSTAT1
E7 TDAT11_N
E8 TDAT11_P
E9 TDAT10_P
E10 UPX_DATA13
E11 UPX_DATA5
E12 UPX_DATA10
E13 RDAT13_P
E14 RDAT13_N
E15 UPX_DATA23
E16 RDAT6_P
E17 RDAT6_N
E18 RDAT9_N
E19 RDAT0_P
E20 RDAT0_N
E21 VDD
E22 I2C_DATA_7
E23 I2C_DATA_4
E24 AVDD1P8_1
F1 UPX_ADD9
F2 GND
F3 UPX_ADD2
F4 VDD
F5 UPX_ADD8
F6 GND
F7 TDAT4_P
F8 VDD2
F9 TDAT10_N
F10 GND
F11 UPX_DATA14
F12 VDD2
F13 VDD2
F14 UPX_DATA18
F15 GND
Ball Signal
F16 RDAT14_P
F17 VDD2
F18 RDAT2_P
F19 GND
F20 UPX_CS_L
F21 VDD
F22 I2C_DATA_3
F23 GND
F24 I2C_DATA_9
G1 UPX_ADD6
G2 TXPAUSEADD1
G3 TXPAUSEADD0
G4 UPX_ADD1
G5 TDAT5_P
G6 TDAT4_N
G7 NC
G8 NC
G9 TDAT3_P
G10 GND
G11 TDAT15_P
G12 UPX_DATA12
G13 UPX_DATA21
G14 UPX_DATA24
G15 MOD_DEF_INT
G16 RDAT14_N
G17 RDAT10_P
G18 RDAT10_N
G19 RDAT2_N
G20 I2C_DATA_6
G21 RDAT3_P
G22 I2C_DATA_0
G23 I2C_DATA_1
G24 I2C_DATA_8
H1 UPX_ADD3
H2 VDD2
H3 TDAT1_P
H4 GND
H5 TDAT5_N
H6 VDD2
Ball Signal
H7 TDAT12_P
H8 GND
H9 TDAT3_N
H10 VDD
H11 TDAT15_N
H12 GND
H13 GND
H14 UPX_RD_L
H15 VDD
H16 RCTL_P
H17 GND
H18 RCTL_N
H19 VDD2
H20 RDAT3_N
H21 GND
H22 NC
H23 VDD2
H24 I2C_DATA_5
J1 UPX_ADD0
J2 TXPAUSEADD2
J3 TDAT1_N
J4 VDD
J5 TDAT0_N
J6 TDAT0_P
J7 TXPAUSEFR
J8 TDAT12_N
J9 TDAT13_P
J10 GND
J11 VDD
J12 VDD2
J13 VDD2
J14 VDD
J15 GND
J16 RDAT11_P
J17 RSCLK
J18 RDAT4_P
J19 RDAT4_N
J20 RSTAT1
J21 GND
Ball Signal
Intel® II XF1110 10-Port 1000 Mbps Ethern et Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
40 Order N umber: 25 0210, Revi sion : 009
J22 NC
J23 GND
J24 I2C_DATA_2
K1 TXPAUSEADD3
K2 GND
K3 VDD
K4 VDD
K5 VDD
K6 GND
K7 NC
K8 VDD
K9 GND
K10 TDAT13_N
K11 GND
K12 RDAT15_P
K13 RDAT15_N
K14 GND
K15 RDAT11_N
K16 GND
K17 VDD
K18 LED_LATCH
K19 GND
K20 GND
K21 VDD
K22 TX_DISABLE_0
K23 GND
K24 GND
L1 MOD_DEF_9
L2 TX_FAULT_9
L3 GND
L4 TX_DISABLE_9
L5 TDAT8_P
L6 GND
L7 TDAT6_N
L8 TDAT6_P
L9 VDD
L10 GND
L11 VDD
L12 GND
Ball Signal
L13 GND
L14 VDD
L15 GND
L16 VDD
L17 RDAT5_P
L18 RDAT5_N
L19 I2C_CLK
L20 RSTAT0
L21 NC
L22 RX_LOS_0
L23 NC
L24 GND
M1 NC
M2 VDD2
M3 GND
M4 GND
M5 TDAT8_N
M6 VDD2
M7 NC
M8 GND
M9 VDD2
M10 TCTL_P
M11 GND
M12 VDD2
M13 VDD2
M14 GND
M15 RDAT7_P
M16 VDD2
M17 GND
M18 GND
M19 VDD2
M20 MOD_DEF_3
M21 GND
M22 TX_DISABLE_1
M23 VDD2
M24 TX_FAULT_0
N1 NC
N2 VDD2
N3 AVDD2P5_2
Ball Signal
N4 GND
N5 NC
N6 VDD2
N7 NC
N8 GND
N9 VDD2
N10 TCTL_N
N11 GND
N12 VDD2
N13 VDD2
N14 GND
N15 RDAT7_N
N16 VDD2
N17 GND
N18 TRST_L
N19 VDD2
N20 NC
N21 GND
N22 AVDD2P5_2
N23 VDD2
N24 MOD_DEF_0
P1 GND
P2 RX_LOS_9
P3 AVDD2P5_2
P4 NC
P5 NC
P6 NC
P7 AVDD1P8_2
P8 TX_FAULT_8
P9 VDD
P10 GND
P11 VDD
P12 GND
P13 GND
P14 VDD
P15 GND
P16 VDD
P17 NC
P18 AVDD1P8_2
Ball Signal
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 41
P19 NC
P20 NC
P21 GND
P22 AVDD2P5_2
P23 GND
P24 GND
R1 GND
R2 GND
R3 GND
R4 VDD
R5 NC
R6 GND
R7 MOD_DEF_8
R8 VDD
R9 GND
R10 GND
R11 GND
R12 RX_LOS_3
R13 NC
R14 GND
R15 TX_FAULT_3
R16 GND
R17 VDD
R18 NC
R19 GND
R20 NC
R21 VDD
R22 NC
R23 GND
R24 GND
T1 NC
T2 RX_LOS_8
T3 TX_P_8
T4 MOD_DEF_6
T5 TX_P_9
T6 NC
T7 GND
T8 GND
T9 GND
Ball Signal
T10 GND
T11 VDD
T12 VDD2
T13 VDD2
T14 VDD
T15 GND
T16 TMS
T17 GND
T18 GND
T19 GND
T20 RX_P_1
T21 GND
T22 RX_P_0
T23 GND
T24 RX_N_2
U1 NC
U2 VDD2
U3 TX_N_8
U4 GND
U5 TX_N_9
U6 VDD2
U7 GND
U8 GND
U9 TX_DISABLE_6
U10 VDD
U11 MOD_DEF_5
U12 GND
U13 GND
U14 TX_DISABLE_4
U15 VDD
U16 GND
U17 GND
U18 TX_DISABLE_3
U19 VDD2
U20 RX_N_1
U21 GND
U22 RX_N_0
U23 VDD2
U24 RX_P_2
Ball Signal
V1 NC
V2 GND
V3 GND
V4 RX_N_8
V5 RX_P_8
V6 AVDD1P8_2
V7 TX_DISABLE_8
V8 NC
V9 NC
V10 AVDD2P5_2
V11 AVDD1P8_2
V12 RX_LOS_5
V13 GND
V14 AVDD1P8_2
V15 AVDD2P5_2
V16 GND
V17 RX_LOS_1
V18 AVDD1P8_2
V19 NC
V20 TX_P_0
V21 TX_N_0
V22 TX_P_2
V23 TX_FAULT_1
V24 RX_N_3
W1 NC
W2 GND
W3 GND
W4 VDD
W5 GND
W6 GND
W7 GND
W8 VDD2
W9 TX_FAULT_6
W10 GND
W11 TX_FAULT_5
W12 VDD2
W13 VDD2
W14 TX_FAULT_4
W15 GND
Ball Signal
Intel® II XF1110 10-Port 1000 Mbps Ethern et Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
42 Order N umber: 25 0210, Revi sion : 009
W16 NC
W17 VDD2
W18 NC
W19 GND
W20 GND
W21 VDD
W22 TX_N_2
W23 GND
W24 RX_P_3
Y1 AVDD2P5_1
Y2 GND
Y3 GND
Y4 SYS_RES_L
Y5 RX_N_9
Y6 RX_P_9
Y7 NC
Y8 GND
Y9 RX_LOS_6
Y10 NC
Y11 NC
Y12 GND
Y13 GND
Y14 NC
Y15 GND
Y16 GND
Y17 TX_FAULT_2
Y18 GND
Y19 TX_P_1
Y20 TX_N_1
Y21 MOD_DEF_1
Y22 TX_N_3
Y23 TX_P_3
Y24 TDO
AA1 GND
AA2 VDD2
AA3 GND
AA4 GND
AA5 CLK125
AA6 VDD
Ball Signal
AA7 GND
AA8 GND
AA9 TX_DISABLE_7
AA10 VDD
AA11 NC
AA12 GND
AA13 GND
AA14 GND
AA15 VDD
AA16 MOD_DEF_2
AA17 GND
AA18 TX_DISABLE_5
AA19 VDD
AA20 NC
AA21 GND
AA22 NC
AA23 VDD2
AA24 TCK
AB1 No Ball
AB2 MOD_DEF_7
AB3 NC
AB4 VDD
AB5 NC
AB6 GND
AB7 GND
AB8 NC
AB9 TX_P_6
AB10 GND
AB11 TX_N_4
AB12 TX_P_4
AB13 RX_P_4
AB14 RX_N_4
AB15 RX_LOS_4
AB16 RX_P_6
AB17 GND
AB18 NC
AB19 NC
AB20 NC
AB21 GND
Ball Signal
AB22 NC
AB23 GND
AB24 No Ball
AC1 No Ball
AC2 No Ball
AC3 RX_LOS_7
AC4 VDD2
AC5 TX_FAULT_7
AC6 GND
AC7 GND
AC8 VDD2
AC9 TX_N_6
AC10 GND
AC11 GND
AC12 VDD2
AC13 VDD2
AC14 MOD_DEF_4
AC15 GND
AC16 RX_N_6
AC17 VDD2
AC18 TDI
AC19 GND
AC20 GND
AC21 VDD2
AC22 TX_DISABLE_2
AC23 No Ball
AC24 No Ball
AD1 No Ball
AD2 No Ball
AD3 No Ball
AD4 NC
AD5 NC
AD6 NC
AD7 NC
AD8 NC
AD9 TX_P_7
AD10 TX_N_7
AD11 TX_N_5
AD12 TX_P_5
Ball Signal
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 43
AD13 RX_P_5
AD14 RX_N_5
AD15 RX_N_7
AD16 RX_P_7
AD17 NC
AD18 RX_LOS_2
AD19 NC
AD20 NC
AD21 GND
AD22 No Ball
AD23 No Ball
AD24 No Ball
Ball Signal
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
44 Order N umber: 25 0210, Revi sion : 009
5.0 Functional Descriptions
5.1 Media Access Controller
5.1.1 General Description
The IXF11 10 MAC main functional block consis ts of a 1000 Mbps Ethernet Media Access
Controller (MAC), supporting the following features:
•1000 Mbps full-duplex operation
•Independent enable/disable of any port
•Detection of length erroror overly large packets
•RMON stati st ics and error counters
•Cyclic Redundancy Check (CRC) calculation and error detection
•Programmable opt ions:
— Filter packe ts with errors
— Filter, broadcas t, multicast, and unic as t address packets
— Aut o maticall y p ad transmitted pa ckets less t h an the min imum frame si ze
•Comp liance with IEEE 802.3x S tandard for Flow Control (symmetric pause capability)
The MAC is fully integr ate d, design ed for us e with Ethernet 802.3 F ram e types, and is compliant
with all of the requi red IEEE 802. 3 MAC requirements.
The MAC adds preamble and Start-of-Frame Delimiter (SFD) to all frames sent to it (transm it
path) and remove s prea mbl e an d SFD on al l frames received by it (receive path) . A CRC check is
als o appli ed to al l trans mit a nd rece ive pac kets . Packet s with a bad CRC are marked, c ounted i n the
statistics block, and may be optionally dropped or se nt to the SPI4-2 interfac e.
5.1.2 MAC Functions
Section 5.1.2.1, “Padding of Undersized Frames on Tr ansmit” on page 44 through Section 5.1.2.3,
“Filtering of Receive Packets” on page 45 cover the MAC functions.
5.1.2 .1 Padding of Undersized Frames on Transmit
The padding featur e al lows Ethernet frames smal ler than 64 bytes to be transf erred across the
SPI4-2 interface and automaticall y padded up to 64 bytes by the MAC. Thi s feature is enabled by
se tting bi t 7 of the “Di verse Config ($ Port_Index + 0x18)” on page 138.
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 45
Note: If fra mes under 64 byt es are sent to the MAC, the padding feature must be enabled for proper
operation. A 9-byte packet is the minimum size pac ket that can be padd ed up to 64 bytes. Packe ts
under 9 bytes are not padde d and are automat ically dropped.
5.1. 2.2 Automatic CRC Generation
The Au tomatic CRC Generati on is use d in conjunction with the pa dding feature to generate and
append a correct CRC to any incoming frame from th e SP I4-2 interface. Thi s feature is enable d by
set ting bit 6 of the “Diverse Config ($ Port_Index + 0x18)” on page 138
Note: When padding of undersiz ed frames on transmit is ena bled, the automatic CRC generation must be
enabled for proper operation of the IXF1110 MAC.
5.1 .2 .3 Fi lt er i n g of Rece iv e Packets
This feature allows the MAC to filter receive packe ts under various conditions and drop the
packets via an interaction with the Receive FIFO control.
Note: Jumbo frames (1519 - 9600 bytes) matching the f ilter conditions, which would ca use the frame to
be dropped by the RX FIFO, are not dropped. Instead, jumbo frame s that are expected to be
dropped by the RX FIFO, based on the filter settings in Ta ble 74, “RX Packet Filter Control ($
Port _Index + 0x19)” on page 139 , are sent across the SPI4-2 interface as an EOP abort frame.
Jumbo frames matching the filter conditions are not counted in the RX FIFO Numb er of Fr am es
Remo ved Regist er beca use the y are not remove d by the RX FIFO. Only standard pac ket si zes (64 -
1518 bytes) meeting the filter conditions set in the Table 74, “RX Packet Filter Control ($
Port _Index + 0x19)” on page 139 are actually dropped by the RX FIF O and counted in the RX
FIFO Number of Frames Removed.
5. 1.2.3. 1 Filter on U n i cas t Packet Match
This feature is ena bled when bit 0 of the RX Pack et Filter Contr ol Register = 1. Any frame
rece ived in this mode containing a Unica st Destination Addre ss that does not match the Station
Addres s is marked by the MAC to be dropped. The frame is dr opped if the appropriate bit in th e
RX FIFO Err o r ed Frame Dr o p En able Regi ster = 1. O t h erwise, all unica st frames are sent to the
SPI 4- 2 interface, but wit h an EOP Ab ort code to the switch or Network Pro cessor.
Note: The VLAN f i lter ov er rides the unica st filter. Thus , a VLAN frame can not be fi ltered b ased on t h e
unica st addres s.
5. 1.2.3. 2 Filter on M u l ticast Pack et Matc h
This feature is ena bled when bit 1 of the RX Pack et Filter Contr ol Register = 1. Any frame
received in this mode containing a Multicast Destination Address which does not match the Port
Multicast Addr ess is marked by the MAC to be dropped. The frame is dropped if the appr opriate
bit in the RX FIFO Errored Frame Drop Enable register = 1. Otherwise, all multicast frames are
sen t to the SPI4-2 interface, but with an EOP Abort code to the switch or Network Proc essor.
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
46 Order N umber: 25 0210, Revi sion : 009
5.1.2.3.3 Filter Broadcast Packets
This feature is enabled when bit 2 of the “RX Packet Filter Control ($ Port_Index + 0x19)” = 1.
Any br oadc as t frame received in this mo de is ma rked by the MAC to be dropped. The frame is
dr opped if the appropri at e bit in the RX FIFO Er rored Fra me Drop Enable Re giste r = 1. Other wise,
all broadcast frames are se n t to the SPI4- 2 in terface, but with a n EOP Abor t code to the switch or
Network Processor.
5.1.2.3.4 Filter VLAN Packets
This feature is enabled when bit 3 of the “RX Packet Filter Control ($ Port_Index + 0x19)” = 1.
VLAN frames received in this mode are m arked by the MAC to be dropped. The frame is dropped
if th e ap p ro pr i at e b it in the RX F IF O Er ror e d F r am e D r op En able Reg iste r = 1. O ther w i s e , al l
VLAN fr ames are sent to the S PI4-2 int er f ace, but with an EOP Abort code to the switch or
Network Processor.
5.1.2.3.5 Filter PAUSE Packets
This feature is enabled when bit 4 of the “RX Packet Filter Control ($ Port_Index + 0x19)” = 0.
PAUSE frames rece ived in thi s mode are marked by the MAC to be drop ped. The frame is droppe d
if the approp riate bit in the “RX FIFO Errored Frame Drop Enabl e ($ 0x59F)” = 1. Otherwis e, all
PAUSE frames are sent to the SPI4-2 interface.
5.1 .2 .3. 6 Filter CRC Errored Packet s
This feature is enabled when bit 5 of the “RX Packet Filter Control ($ Port_Index + 0x19)” = 0.
Fra mes received with a n errored CRC are marked as ba d frames and may op tionally be dropped in
the RX FIFO. Othe rwise, the f ram es are sent to the SPI4-2 interface and may be dropped by the
switc h or system contr oller (see Table 14, “CRC Errored Packets Drop Enabl e Be havior” on
page 47).
Note: Whe n the CRC Err o r Pass Filter bit = 0 (“RX Pac ket Filter Control ($ Port_Index + 0x19)”), it
takes precedence over the other filter bits. Any packet ( Paus e, Unicast, Multicast or Broadcast
p acket ) with a CRC err or will be marked as a bad frame when the CRC Err o r Pass Filter bit = 0.
Table 13. Pause Packets Drop Enable Behavio r
Pause Frame Pass Frame Drop En Actions
10
Packets are passed to the SPI4-2 interface. They are not marked
as bad a nd are sent to the swi tch or Ne tw ork P rocessor.
00
Packets are marked as bad but not dropped in the RX FIFO. These
packe ts are sent to th e SPI4 -2 interface, but with an EOP Abort
c ode to the sw itch or Network Processor.
11
Packets are not marked as bad and sent to the switch or Network
Pr ocessor, regardless of the Fr ame Drop En s ettin g.
01
PAUSE Packets are ma rked as bad , are dropped in the RX FIFO ,
and nev er appear at the SPI4-2 interface.
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 47
5.1.3 Flow Control
Flow Control is an IEEE 802.3x-defined mechanism for one network node to request that its link
partner take a temporary “Pause” in packet tr ans mission. This allows the requesti ng network node
to pr event FIFO overru ns and droppe d packets, by mana ging incoming traff ic to fit its available
memory. The tem porary pause all ows th e device to process pac kets already received or in transit,
thus free ing up the FIFO space allocated to thos e packets.
The IXF1 110 MAC impl ements the I EEE 802.3x s tanda rd RX F IFO t hresho ld-bas ed Flow Cont rol.
When approp riate ly programme d, the MAC can both gen erate and respon d to IEEE standa rd pause
frames . Th e IXF1110 MAC also supports externally triggered flow cont rol through the T r ansmit
Pause Control interface.
5.1.3 .1 802.3x Flow Control (Full-Duplex Operation)
The IEEE 802.3x st anda rd identifies four opti ons related to system flow contr ol:
•No Pause
•Symmetri c Pause (both directi ons )
•Asymmetric Pause (Rec eive direction only)
•Asymmetric Pause (T ransmit directi on only)
The IXF1110 MAC supports all four options on a per-port basis. Bits 1:0 of the “F C Enable ($
Port _Index + 0x12)” on page 136 provide programm able control for ena bling or disabling flow
control in each direc tion independentl y.
The IEEE 802.3x f low control m echanism i s accompli s hed within the MAC subl ayer, and is based
on RX FIFO thresholds called wate rmarks. The RX FIFO level rises and falls as pac kets are
received and p r ocessed. When the RX FIFO reaches a wat ermark (either ex ceeding a High or
dropping below a Low after exceeding a High), the IXF1110 MAC control sublayer signals an
internal state machine to trans mit a PAUSE frame. The FIFOs automatically generate PAUSE
frames (also called control frames) to initiate the following:
•Halt the link partner whe n the High watermark is reached.
•Restart the link partner when the data stored in th e F I FO falls below the Low watermark.
Figure 5 illustrates the IEEE 802.3 FIFO flow control functions.
Table 14. CRC E rrored Packets Drop En able Behavior
CRC Errored PASS Frame Drop En Actions
10
Packets are pas s ed to the SP I4-2 interfac e. They are not
marked as bad and are sent to the swi tch or Ne tw ork
Processor.
00
Packets are marked as b ad but not dropped in the RX FIFO.
These packets are sent to the SPI4-2 interface, but with an
EOP A bort co de to th e swit ch or Network Proces sor.
11
Packets are not mar k ed as bad an d ar e sent to the swi tch or
Net work Processor reg ardless of t he Frame D rop En sett ing.
01
CR C error ed pack ets are ma rked as bad , dropped in the RX
FIFO, a nd nev er appear at the S PI4- 2 interface.
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
48 Order N umber: 25 0210, Revi sion : 009
5.1.3. 1.1 Pau se F r ame For mat
PAUSE frames are MAC control frames that are padded to the minimum size (64 bytes). Figure 6
and Figur e 6 illu str ate th e f r ame for m a t and co n tents .
Figure 5. Packet Buffering FIFO
MDI
High Water Mark Data Flow
MAC Transf er
Thresh old *
Low Water Mark
High Water Mark Data Flow
Low Water Mark
RX FIF O High
TxPauseFr (External 802.3x Pause Frame Generation
strobe)
TX FIFO TX Side
MAC
RX FIFO
802.3 Flow
control
RX Side
MAC
SPI4-2 Interface
Figure 6. Eth erne t Fram e Fo rmat
Number of bytes
Note:
!""# $ % !&"#
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 49
An IEEE 802.3 MAC PAUSE frame is identifie d by detectin g all of the following:
•OpCode of 00-01
•Lengt h/Type field of 88-08
•DA matching the unique multicas t address (01-80 -C2-00-00-01 )
XOFF. A PAUSE frame inform s the link partn er to halt tra nsmis sion for a specifi ed lengt h of time.
The PauseLength octets specify the duration of the no-transmit period. If this time is greater than
zero, the link partner must stop sending any further packets until this time has elapsed. This is
referr ed to as XOFF.
XON. The MAC continues to transmit PAUSE frames with the specified Pause Length as long as
the FI F O leve l exceeds the threshold. If the FIF O leve l falls below the threshold before the Pause
Lengt h time expir es, the MAC sends another PAUSE frame with the Pause Length time spe cified
as zero. Thi s is referred to as XON and infor ms the link partner to resume normal transmission of
packets.
5.1.3.1.2 Pause Settings
The MAC must send PAUSE frames repe atedly to maintain the link pa rtner in a Pause state . The
following two inter-related variable s co ntrol thi s proces s:
•Pau se Length is th e amount of tim e, meas ured in multiple s of 512 bit times, that the MAC
requests the link part ner to hal t transmissi on for.
•Pause Threshold is the amount of time, measured in multiples of 512 bit times, prior to the
expiration of the Paus e Length that the MAC trans m its anothe r Pause frame to maint ain the
link partner in the pause state.
The transmitted Pause Length in the IXF1110 MAC is set by the “FC TX Timer Value ( $
Port _Index + 0x07)".
The IXF1110 MAC PAUSE frame transmission interval is set by the “Pause Threshold ($
Port _Index + 0x0E)” on page 135.
Figure 7. PAUSE Fram e Form at
B3426-02
DA* or
01-80-
C2-00-
00-01 SA 88-08 FCS
S
F
D
Preamble
71 4662
Pause
Opcode
(00-01)
Pause
Length
22
46
Pad
(with 0s)
42
64 Bytes
Number of bytes
Note: In the Intel® IXF1110 architecture, the TX block of the MAC sets this as the pause multicast address.
The RX interface of the MAC will process this as the pause multicast or the MAC address.
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
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5.1.3. 1.3 R esp o ns e to R ecei ved PA U SE C o mman d Frames
When Flow Control is ena bled in the rec eive direction ( bit 0 in the “FC Enabl e ($ Port_Index +
0x12)” on page 136), the IXF1110 MAC responds to PAUSE Command frames received from the
link partner as follows:
1. T he IXF1110 MAC checks the entire frame to verify tha t it is a valid PAUSE control frame
addressed to the Multic ast Address 01- 80-C2-00-00-01 (as specified in IEEE 802.3, Annex
31B) or has a Des tinations Addre s s matching the address programmed in the “St ation Addre ss
Low ($ Port_Index + 0x00)" thro ugh “Station Addres s High ($ P ort_Index + 0x01)".
2. If the PAUSE f ram e is valid, the transmit si de of the IXF1 110 MAC paus es for the required
number of PAUSE Quanta , as specif ied in IEE E 802. 3, Clause 31.
3. PAUSE does not begin until completion of the frame currently being transmitted.
The I XF11 10 MAC response to valid received PAUSE frames is independent of the PAUSE frame
f ilter settings. Ref er to Se ction 5.1. 2.3.5, “Filter PAUSE Packets” on page 46 for additional details .
5.1.3. 1.4 Transmi t Pau se C o n tr o l In terf ace
The Transmit Pause Control interface allows an external device to trigger the generation of pause
f r ames . The Transmit Pause Control interface is comple tely asynchronous. It consists of four
addre ss signals (TXPAUSEADD[3:0]) and a strobe si gnal (TXPAUSEFR). The required address
f or this interfac e ope ration is place d on the TXPAUSEADD[3:0] sig nals and the TXPAUSEFR is
pulsed High and returned Low. Refer to Figure 8, “T ransmit Pause Contr ol Interface” on pa ge 51
and Table 41, “T ransmit Pause Control Interface Para meters” on page 113. Table 15 shows the
valid decodes for the TXPAUSEADD[3:0] signa ls. Figure 8 illustrates the transmit pause control
interface.
Note: Fl ow control must be en abled in the “FC Enable ($ Port_Index + 0x12)” for Tra nsmit Pause
Control interfac e operation.
Note: The re are two additi ona l decodes provi ded that allow the user to gene rate eithe r an XOFF frame or
XON frame from all ports simultaneou sl y.
The defa ult pau se qua nta for ea ch port i s held b y the “FC TX T i mer Value ($ P ort_Inde x + 0x07)" ).
The default value of this register is 0x05E after reset is applied.
Tab le 15. Valid De codes for TXPAUSEADD[3:0]
TXPAUSEADD[3:0] TX Pause Control Interface Operation
0x0 T ransmits a PAUSE fr ame on every port wi th a pause _time = ZERO (XO N)
(C ancels all pr evious pause comm ands ).
0x1 T ransm its a PAUS E fr ame on port 0 with pause_ time equal to the value programm ed
in the port 0 “F C TX Timer Value ($ Port_I ndex + 0x 07)" (XOFF).
0x2 T ransm its a PAUS E fr ame on port 1 with pause_ time equal to the value programm ed
in the port 1 “F C TX Timer Value ($ Port_I ndex + 0x 07)" (XOFF).
0x3 T ransm its a PAUS E fr ame on port 2 with pause_ time equal to the value programm ed
in the port 2 “F C TX Timer Value ($ Port_I ndex + 0x 07)" (XOFF).
0x4 T ransm its a PAUS E fr ame on port 3 with pause_ time equal to the value programm ed
in the port 3 “F C TX Timer Value ($ Port_I ndex + 0x 07)" (XOFF).
0x5 T ransm its a PAUS E fr ame on port 4 with pause_ time equal to the value programm ed
in the port 4 “F C TX Timer Value ($ Port_I ndex + 0x 07)" (XOFF).
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5.1.4 Fiber Operation
The data pat h in the MAC is an internal 10-bit interface, as described in the IE EE 802.3z St anda rd.
It is connected directly to an internal SerDes block for Serialization/Deserialization and
transmission/reception on the fiber medium to/from the link partner.
Note: T he MAC cont ains all the PCS (8B/10B encoding and 10B/8B de coding) required to encod e and
decode the data. The MAC also supports auto-negotiation per the IEE E 802.3z S tandard via a ccess
0x6 Transmits a PAUSE frame on port 5 with pause_time equal to the value programmed
in the port 5 “FC TX Timer Value ($ Port_Index + 0x07)" (XOFF).
0x7 Transmits a PAUSE frame on port 6 with pause_time equal to the value programmed
in the port 6 “FC TX Timer Value ($ Port_Index + 0x07)" (XOFF).
0x8 Transmits a PAUSE frame on port 7 with pause_time equal to the value programmed
in the port 7 “FC TX Timer Value ($ Port_Index + 0x07)" (XOFF).
0x9 Transmits a PAUSE frame on port 8 with pause_time equal to the value programmed
in the port 8 “FC TX Timer Value ($ Port_Index + 0x07)" (XOFF).
0xA Transmits a PAUSE frame on port 9 with pause_time equal to the value programmed
in the port 9 “FC TX Timer Value ($ Port_Index + 0x07)" (XOFF).
0xB - 0XE Reserved
0xF Transmits a PAUSE frame on every port with pause_time equal to the value
programmed in the “ FC TX Timer Value ($ P ort_I ndex + 0x07)" for each port (XOFF).
Figure 8. Transmit Pause Control Interface
Table 15. Valid Decodes for TXPAUSEADD[3:0]
TXPAUSEADD[3:0] TX Pause Control Interface Operation
B3366-01
TXPAUSEFR
TXPAUSEADD0
TXPAUSEADD1
TXPAUSEADD2
This example shows the following conditions:
Strobe 1:
Port 0: Transmit Pause Packet (XOFF)
Strobe 2:
All Ports: Transmit Pause Packet with pause_time = 0 (XON)
Strobe 3:
Port 3: Transmit Pause Packet (XOFF)
TXPAUSEADD3
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to the “TX Conf ig Word ($ Port_I ndex + 0x17)” on page 137, “RX Config Word ($ Port_Inde x +
0x16)” on pa ge 136, and Div erse Config Re giste rs (s ee “Diverse Confi g ($ Por t_Index + 0x18)” on
page 138.
By defa ult, IXF1110 auto-negotiation is disable d by Regi ster bit 5 (AN_enable) of the “Diverse
Config ($ Port_Index + 0x18)”. When auto-negotiat ion is disable d, the IXF11 10 can operate in
f orced mode, which is 1000 Mbps ful l duplex only. This is equivalent to entering the state
AN_DISABLE_LINK_OK as de scribed in Figure 37-6 of IEEE 802. 3. The IXF1110 can pass
packets when auto-negotiation is disabled only when the internal Synchronization State Machine
indicate s that the sync_status is OK as described in F igure 36-9 of IEEE 802.3.
Note: Packe t IP G must c ontain a minimum of three co nsecutive /I1/ or /I2/ ordered sets per IEEE 802.3
for correct operation.
Note: The IXF11 10 treats the K28.1 code word as an unknown control word; therefore, it should not be
used.
5.1.5 Auto-Negotiation
Auto-negotiation is carried out by an internal state machine within the MAC in the IXF1110. The
IX F1110 is fully IEEE 802.3z standard compliant.
The following thre e registers a re involved in this auto-negotiation process: RX Config Word
TX Config Word, and Diverse Config:
•The “RX Confi g Word ($ Port _Index + 0x16)” performs t he operat ion of a uto- negotia ti on base
page ability.
•The “TX Config Word ($ Port_I ndex + 0x17)” perform s the operation of auto-negotiation
advertisement.
•The “Dive rse Config ($ Port_Index + 0x18)” enables auto-negotiation.
The “TX Config Word ($ Port_I ndex + 0x17)” must be written to program the modes advertised.
The “Dive rse Config ($ Port_Index + 0x18)” bit 5 (AN_enable) must be written to enable auto-
negotiation. The “RX Config Word ($ Port_Index + 0x16)” bit 21 (AN_complete) must be polled
to determine when auto- negotiation is com plete. The foll owing MAC registers must be
programmed to match the results upon completion:
•Link LE D : Table 80, “Link LED Enable ($ 0x502)” on page 150
•Fl ow Control: If the link partner does not support flow control , the “FC Enable ($ Port_Index
+ 0x12)” on page 136 must be updated to reflect this change.
Note: I n auto-negoti ation mode, the TX SPI4-2 status bus (TSTAT[1:0]) is hel d in the SATISFIED st ate
until auto-negotiation completes and a valid link is established. This prevents the TX FIFO from
being f illed prior to tra nsmission of packets.
5.1.5 .1 Determining If Link Is Established in Auto-Negotiation Mode
A valid link is established when the ( AN_com plete) bit is set and the RX_Sync bit reports
syn chroniz ation has occurred. Bot h regist er bits ar e loc ated in the “RX Config Word ($ Port_Index
+ 0x16)”.
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If the link goes down aft er a uto-negotiation is completed, RX_Syn c indicates that a loss of
sync hronizati on occurred. The IXF1110 restarts auto-negotiat ion and attempt s to re-establish a
link. Once a link has been re-establis hed, the AN_compl ete bit is set and the RX_sync bit shows
that sync hronizati on has occurred.
To manually restart auto-negotiation, bit 5 of the “Diverse Config ($ P ort_Index + 0x18)”
(AN_enable) must be de-asse rted, then re-asserted.
5.1. 6 Forced Mod e Oper atio n
The fib er operation of the MAC can be forced to operated at 1000 Mbps, full duplex without
completion of the auto negotiation function. In this m ode, the receive path of the MAC must
achi eve syn chroniz ation wit h the link par tne r . Once this has been achieve d, the tra nsmit pa th of the
MAC will be en abled to allow data tr ansmission, which is known as “forced mode” operation.
Forced m ode is limite d to operation with a link partner that operates with a full-duplex link at a
spe ed of 1000 Mbps.
Forced m ode is enabled by Register bit 5 (AN_enab le) in the “Diverse Config ($ Po rt_Index +
0x18)”. By default, the IXF11 10 is set to forced mode operation.
Note: In forc ed mode, the TX SPI4-2 status bus (TSTAT[1:0]) is held in the SATISFIED state until
sync _status is OK. Thi s prevents the TX FIFO from being filled prior to tra ns mi ssion of packe ts .
5.1.6 .1 Determining If Link Is Established in Forced Mode
When the IXF1110 is in forced mode operation, the “RX Config Wo rd ($ Port_Index + 0x16)” bit
20 RX Sync indicates when synchronization has occ urred and valid link is es tablis hed.
Note: T he Rx Sync bit indicates a loss of synchronizati on when the link is down.
5.1.7 Jumbo Packet Support
The IXF1110 MAC suppor tss the co ncept of jumbo frames . The jumbo frame leng th is dependent
on the application, and the IXF1110 MAC design ha s been optimized for 9.6 KB jumbo fr ame
length. Lengths larger than thi s can be program med, but will limit system perf ormance.
The value pr ogrammed into the Max Fr ame Size Registe r (Addr: Port_Index + 0x0F) determines
the maxim um length frame size the MAC can receive or trans mi t without activating any error
counters, and without truncation.
The Max Fra me Size Register (Addr : Po rt_Index + 0x0F) bits 13:0 set the frame length. Th e
default value programmed into this register is 0x05EE (1518). The value is internally adjusted by
+4 if the frame has a VLAN tag. The ove rall programmable maximum is 0x3FFF or 16383 bytes.
The register should be programmed to 0x2667 for the 9.6 KB length jumbo frame for which the
IXF1110 MAC is optim ized.
The RMON counters are also af fected for jumbo frame support as follows:
RX S t atistics:
•RXOctetsTotalOK (Addr: Port_Index + 0x20)
•RXPkt s1519toMaxOctets (Addr: Port_Index + 0x2B)
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•RXFCSErrors (Addr: Po rt_Index + 0x2C)
•RXData Error (Addr: Port_Index + 0x02E)
•RXAlignE rrors (Addr: Port_Index + 0x2F)
•RXLongErrors (Addr: Port_Inde x + 0x30)
•RXJabberErrors (Addr: Port_Index + 0x31)
•RXVeryLongE rrors (Addr: P ort_Index + 0x34)
TX Stat ist ics :
•TXOctetsTotalOK (Addr: Po rt_Index + 0x40)
•TxPkts1519toMaxOctets (Addr: P ort_Index + 0x4B)
•TxExce ssiveLengthDrop (Addr: Port _Index + 0x53)
•TXCRCError (Addr: Port_Index + 0x56)
The IXF1110 MAC checkss the CRC for all legal length jumbo frames (frames between 1519 and
the Max Frame Size). On transmission, the MAC can be programmed to a ppend the CRC to the
f r ame or che ck the CRC and increment the appropriate counter. On reception, the MAC transmits
the se frames across the SPI4-2 interf ace (jumbo frame s with a bad CRC cannot be dropp ed and are
sent across the SPI4-2 interface). If the receive frame has a bad CRC, the appropriate counter is
in cremented and the EOP Abor t code is set in the SPI4 - 2 control word .
Jumbo frames also impact flow control. The maximum frame size needs to be taken into account
when det ermining the FIF O wate rmar ks. The current transmissi on must be comple ted before a
Pause fram e can be transmitted (needed when the receiver FIFO high watermark has be en
exceeded). If the curre nt transmis sion is a jumbo frame, the de lay may be si gnificant and inc rease
d ata loss du e to insuf ficien t avail able FIF O space.
5.1.8 RMON Statistics Support
5.1.8.1 RMON Statis ti cs
The IXF1110 MAC supplies RMON statistics via the CPU interface. These statistics are available
in the form of counter values tha t ca n be ac ce ssed at specif ic addresses in the IXF11 10 MAC
me mory map. Once read, these counters auto matically reset and begin counti ng from zero. A
separate set of RMON st atistics is available for each MAC device in the IXF1110 MAC.
Im plementation of the RMON Statistics block is similar to the functionality provided by existing
I ntel switc h and router products. This imp lementation allows the IXF1110 MAC to provid e al l of
the RMON St atisti cs group as defined by RF C2819.
The IXF1 110 MAC supportss the R MON RF C2819 Group 1 st atisti cs counters . Table 16 notes the
differences and additional statistics registers supported by the IXF1110 MAC that are outside the
sc ope of the RMON RFC2819 document.
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Table 16. RM ON Add itional Statistics Registers (Sheet 1 of 2)
RMON Ethernet Stati stics
Gr o up 1 Sta t is t ics Type IXF1110 MAC Equi valent
Statistics Type
Defi niti on of
RMON Versus
IXF1110
Documentation
etherStatsIndex Integer32 N/A N/A N/A
etherStatsDataSource Object
Identifier N/A N/A N/A
etherStatsDropEvents Counter32 RX/TX FIFO Number of
Frames Removed Counter32 See Table note 1.
etherStatsOctets Counter32
RXOctetsTotalOK
RXOctetsBad
TXOctetsTotalOK
TXOctetsBad Counter32
Note: The
IX F1110 MAC has
two counters for
RX and T X that
use different
naming
co nv en t i ons f or
total Octets and
Octets bad. These
count e r s ne ed to
be combined to
meet the RMON
spec.
etherStatsPkts Counter32 RX/TXUCPkts
RX/TXBCPkts
RX/TXMCPkts Counter32
Note: The
IX F1110 MAC has
three counters fo r
etherStatsPkts
that need to be
combined to give
the total packets
as defined by the
RMON spec.
etherStatsBroadcastPkts Counter32 RX/TXBCPkts Counter32 OK
ethe rStatsM ultica s tPkts Counter 32 RX/TXMC Pkts Counte r32 See table note 2.
etherStatsCRCAlignErrors Counter32 RXAlignErrors
RXFCSErrors
TXCRCError Counter32
Note: The
IX F1110 MAC has
two counters for
a lignm ent and
CRC errors for the
RX side only.
The IXF1 110 MAC
has CRCError for
the TX side.
etherStatsOversizePkts Counter32 RXLongErrors
TXExcessiveLengthDrop Counter32 OK
etherStatsJabbers Counter32 RXJabber Errors Counter32 OK
1. The RMON spec requires that this is, "The total number of events where packets were dropped by the
pr ob e due t o a la ck of r es our ces . No te th at th is num ber is not ne ce ssar ily the numb er of p ackets drop ped; it
is the number of times this condition has been detected." The RX/TX FIFO Number of Frames Removed
Register in the IXF1110 MAC supports this and will increment when either an RX or TX FIFO has over
flowed. If any IXF1110 MAC programmable packet filtering is enabled, the RX/TX Number of Frames
Removed Register increments with every frame removed in addition to the existing frames counted due to
FIFO overflow.
2. The IXF1110 MAC has an extra counter RX/TXUCPkts that can be used.
3. The IXF1 110 MAC has an extra counter RX/TXPktstoMaxOctets that can be used in addition to the RMON
s tats. Th is is requir ed to accommodate the Jum bo p acket frames req uirement.
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5.1.8.2 Conventions
The following conventions are us ed throughout th e RMON MIB and it s co mpanion documents.
•Good Packets: Error-free packets that have a valid fra me length. For example, on Etherne t,
good packet s are error-free pac kets th at are between 64 octets l ong and 1518 o cte ts long. The y
follow the form defined in IEEE 802.3, Section 3.2.
•Bad Packets: Packets that have proper framing and are therefore re cognized as packets , but
contain errors within the packet or have an invalid le ngth. For example, on Eth ernet, bad
packets have a valid preamble and SFD, bu t have a bad CRC, or are either shorter than 64
octets or longer than 1518 oc tets.
5.1.8.3 Add it ion al Statisti cs
The follow ing additional IXF1110 MAC registers support features not documented in RMON:
•MAC (flow) control frames
etherStatsCollisions Counter32 TXSingleCollisions
TXMultipleCollisions
TXLateCollisions
TXTotalCollisions
Counter32
OK
Note: Registers
exis t on the TX
side but should
not increment
since the IXF1110
MAC only
supports full-
duplex.
etherStatsPkts64Octets Counter32 RX/TXPkts64Octets Counter32 OK
etherStatsPkts65to127Octets Counter32 RX/TXPkts65to127Octets Counter32 OK
etherStatsPkts128to255Octets Counter32 RX/TXPkts128to255Octets Counter32 OK
etherS ta tsPkts256to511Octets Counter32 RX/TXPkts256to511Octets Counter32 OK
etherStatsPkts512to1023Octets Counter32 RX/TXPkts512to1023Octets Counter32 OK
etherStatsPkts1024to1518Octet
sCounter32 RX/
TXPkts1024to1518Octets Counter32 See table note 3.
etherStatsOwner Owner
String N/A N/A N/A
etherStatsStatus Entry
Status N/A N/A N/A
Tab le 16. RMON Additional Statistics Registers (Sheet 2 of 2)
RMON Ethernet Statistics
Group 1 Statistics Type IXF1110 MA C Equivalent
Statistics Type
Definit ion of
RMON Versus
IXF1110
Documentation
1. The RMON spec requires that this is, "Th e total num ber of events where packets were droppe d by the
probe due to a lack of resources. Note that this number is not necessarily the number of packets dropped; it
is the num ber of times this condition h as been detected." Th e RX/T X FIFO Number of Frames Remo ved
Register in the IXF1110 MAC supports this and will increment when either an RX or TX FIFO has over
flowed. If any IXF1110 MA C programmab le p acket filtering is enabled, the RX /TX N um ber of Fra m es
Removed Register increments with every frame removed in addition to the existing frames counted due to
FIFO overflow.
2. The IXF1110 MAC has an extra counter RX/TXUCPkts that can be used.
3. Th e IXF1110 MAC has an extra counter RX/ TXPktstoMaxO ctets that can be u s ed in addition to the R MON
stats. This is required to accommodate the Jumbo packet frames requirement.
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•VLAN tagged frames
•Sequence errors
•Symbol errors
•CRC errors
These additional counters allow for additiona l differentiation over and ab ove standard RMON
probes.
Note: A packet transfer with an inva lid 10-bit symbol will not always update the statistics registers
correctly.
•Behavior : The IXF1110 8B10B decoder substitutes a valid code word octet in its place. The
packe t transfer is aborted and marked as bad. T he new internal le ngth of the packet is equal to
the byte position where the invalid symbol was. No pac ket f ragm ents are seen at the ne xt
pa ck et transf er.
•Issue: If the i nvalid 10-bit code is inserted in a byte position of 64 or great er, expecte d RX
sta tistics are reported. However, if the inva lid code is inse rted in a byte position of less than
64, expe cted RX statis tics a re not stored.
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5.2 System Packet Interface Level 4 Phase 2
The System Packet Interface Level 4 Phase 2 (SPI4-2) provides a high-speed connection to a
net work proc essor or an ASIC. T he inte rface i mplemente d on t he IXF1 110 opera tes at da ta rat es up
to 12.8 Gbps and supports up to ten 1 Gbps MAC ports . The data path is 16 lan es wide in each
direction, with each lane operating from 640 Mbps up to 800 Mbps. Port addre ssing, start/end
packet control, and error control codes are al l transferred “in-band” on the da ta bus. In-band
addressing supports up to 10 ports. Separate transmit and receive FIFO status lines are used for
f low control. By keeping the FIFO stat us inform ation out-of-band, the transmit and re ceive
interfaces may be de-coupled to operate independe ntly. Figure 9 and Table 17 provide a n overview
of th e IXF 1110 S P I 4 - 2 inte r f a c e .
Figure 9. SPI4-2 Interfacin g with the Network P roces sor or Forw ard ing Engi ne
Table 17. SPI4-2 Interface Si gn al S ummary (Sh eet 1 of 2)
Signal Name Signal Description
Transmit
TDAT[15:0]_P/N Transmit Data Bus: Differential LVDS lines used to carry payload data and in-band
control words.
Internally terminated differentially with 100 Ω.
TDCLK_P/N
Transmit Data Clock: Differential LVDS clock associated with TDAT[15:0] and TCTL.
Data and control lines are driven off the rising and falling edges of the clock.
Internally terminated differentially with 100 Ω.
NOTE: If TDCLK is applied to the IXF1110 MAC after the device has come out of
reset, the system designer must ensure t he T D CLK is stable when appl ied. Failure to
due so can result in the IXF1110 MAC training on a non-stable clock, causin g D IP4
errors and data cor rupti on.
TCTL_P/N Transmit Control: Differential LVDS lines used to indicate when a control word is
being tran sm itted. A High level indicates a control word presen t on TD AT[15:0].
Internally terminated differentially with 100 Ω.
Intel®
IXF1110
MAC
Network Processor
or Forwarding Engine
with SPI4-2 I nterface
TSCLK TSCLK
TDAT[15:0]_P/N
SPI-4.2
Signals
TSTAT[1:0] TSTAT[1:0]
TDAT[15:0]_P/N
TDCLK_P/N TDCLK_P/N
TCTL_P/N TCTL_P/N
RSCLK RSCLK
RSTAT[1:0] RSTAT[1:0]
RDCLK_P/N RDCLK_P/N
RDAT[15:0]_P/N RDAT[15:0]_P/N
RCTL_P/N RCTL_P/N
Transmit
FIFO Status/
Flow Control
Receive
FIFO Status/
Flow Control
Transmit
Data
Control
Receive
Data
Control
B3432-01
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5.2.1 Data Path
Trans fer of complete packets or shorte r bursts is controlled by the progra mmed MaxBurst1 or
MaxBurs t2 in conjunction with the FI FO status bus. The maximum configured payload data
tr ans fer size must be a multiple of 16 bytes. Control words are inse rted betwee n burs t transfe r s
only. Once a transfer begins, data words are sent uninterrupted until an end-of-packet, or until a
multiple of 16 bytes is reached as programmed in MaxBurst1 and MaxBurst2. The interval
betwe en the end of a given tra nsfe r and the next payload con trol word (mar king the sta rt of another
tr ansf er) consist s of zero or more idle control words and/or traini ng patterns.
Note: T he system designer shou ld be aware that the MAC Transfer Threshol d Register must be set to a
value which exceeds the MaxBurst1 setting of the network proces sor or ASIC. Otherwise, a TX
FIFO under-run may result.
The minimum and maximum support ed packet lengths a r e determined by the app lication. Because
the IXF1110 MAC is tar ge ted at the Etherne t envir onment , th e minimum frame size is 64 byte s and
the maxi mum fr ame size is 1522 b ytes for VLAN packet s (1518 b ytes for non-VLAN packe ts). For
larger frames, adjust the value of the “Max Frame Size ($ Port_Index + 0x0F)” on page 135. For
ease of implementation, succ es sive start-of-pack ets must occur not le s s than e ight cycl es apart,
where a cycle is one control or data word. The gap between sho r ter packets is fil led with idle
control words.
Note: Da ta packets with fram e lengths les s than 64 bytes should not be transfer red to the IXF1110 MAC
unless pack et padding is ena bled. If this rule is disr ega r ded, unwanted fragments m ay be gen erated
on the net w ork at the SerDes interface.
Fig ure 10 on pa ge 60 shows cycl e-by-cyc le be havior of t he dat a path fo r valid s tate tr ansit ion s. The
states correspond to the type of words transferred on the data path. Transitions from the “Data
Burs t” state (to “Payload Control” or “Idle Control”) are possible only on the integer multiples of
TSCLK Transmit Status Cl ock: LVTTL cloc k associated wi th TSTAT [1:0] .
Frequenc y is equ al to one-quart er TD CLK.
TSTAT1, TST AT0 Tr a nsm i t FIFO Stat u s: LVTTL lines used to carry round-robin FIFO status
inf orm at io n, along w ith ass oc iat e d er ror det ection and f ram ing.
Receive
RDAT[15:0]_P/N Receive Data: Carr ies p ayload data an d in-band contr ol fro m the IXF1110 MA C link-
layer device.
Internally terminated differentially with 100 Ω
RDCLK_P/N Receive Data Clock: Dif fer ent ia l LVDS clock asso ciat ed wi th R DAT[1 5: 0] and RCT L.
Data and control lines are driven off the rising and falling edges of the clock.
Internally terminated differentially with 100 Ω
RCTL_P/N Receive Control: RCTL is High when a control word is present on RDAT[15:0].
Otherwise, RCTL is Low.
Internally terminated differentially with 100 Ω
RSCLK Rec eiv e Statu s Cl o c k: L VTTL clock associated with RSTAT[1:0].
RSTA T 1 , RSTAT0 Receive FIFO Status: L VTTL lines used to carry round-robin FIFO status information,
along with a ssociated error detection and f raming.
Table 17. SPI4-2 Interface Signal Sum mary (S heet 2 of 2)
S ign al Nam e Signa l Des cr ip tion
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eight cycles (corresponding to multiples of 16-byte segmentations) or upon end-of-packet. A data
burst must immediately follow a payload control word on the next cycle. Arcs not annot ate d
correspond to single cycles.
In the IXF111 0 MAC, the RX FIFO Status channel operates in a “pessimistic mode.” It is termed as
pes simisti c becau se it has the longest late ncy and largest i mpact on usable bandwidth. However, as
a DIP-2 c hec k error is a rare event, there will be no ‘real world’ effec t on bandwidth utilization and
no possibility of data loss. For example, if there is a DIP-2 check error found, all previously
gr anted credits ar e cancelle d and the internal s tatus for each p ort is set to SATISFIED. Any current
data burst in trans mission is compl eted. No new credits are grante d until a complete FIFO status
cycle has been received and validated by a correct DIP-2 check. This is the only method of
operation that can eliminate the poss ibility of an ove rrun in the link partner device.
5.2.1.1 Con tr o l Wor d s
A co mmon control wor d fo r ma t is used in both the transmit and receive in terfa ces. Table 18
des cribes t he fields in the control word. When inserted in the dat a path, the control word is alig ned
such that its MSB is se nt on the MSB of th e tr ansmit or r eceive d ata lines . A payload contr o l wor d
that separat es two adjacent burs t transfer s co ntains status information pertaining t o the pre vious
t ransfer and t h e f o llowi n g tr ansfer. Table 19 provides a list of control-word definitions.
Figure 10. Data Path State
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 61
Ta ble 1 8. Cont rol Word Fo rm at
Bit Position Label Description
15 Type
Control Word Type.
Set to either of the following values:
0 = Idle or training control word
1 = Payload control word (payload transfer will immediately follow the control word)
14:13 EOPS
End-of-Packet (EOP) Sta tus.
Set to the following values according to the status of the immediately preceding
payload transfer:
00 =Not an EOP.
01 =EOP Abort (application-specific error condition
10 =EOP Normal termination, 2 bytes valid
11 = EOP Normal termination, 1 byte valid
EOPS is valid in the first control word following a burst transfer . It is ignored and set to
“00” ot herwise.
12 SOP
Start-of-Packet.
Set to 1 if the payload tran sfer i mm ediately follo wing t he control word co r responds to
the start of a packet. Set to 0 otherwise.
Set to 0 in all idle and training control words
11:4 ADR
Port Address.
8-bit por t ad dr ess of the payloa d data transfer immediatel y following the control word.
None of th e addresses are re served (all are avail able for p ayload transfer).
Set to all zeroes in all idle control words
Set to all ones in all tr aining contr ol wor ds
3:0 DIP-4 4-bit Diagonal Interleaved Parity.
4-bit odd parity computed over the current control word and the immediately preceding
data words (if any) following the last control w ord
Table 19. Control Word Definitions (Sheet 1 of 2)
Bit
[15:12] Next Word
Status Prior Word Status Meaning
0 0000 Idle Conti nued Idl e, not E OP, tr aining co ntrol word
1 0001 Reserved Reserved Reserved
2 0010 Idle EO P w/abort I dle, Abort last pac ket
3 0011 Reserved Reserved Reserved
4 0100 Idle EO P w / 2 bytes Idle, E O P w ith 2 bytes valid
5 0101 Reserved Reserved Reserved
6 0110 Idle EO P w / 1 byte Idle, E O P w ith 1byte valid
7 0111 Reserved Reserved Reserved
8 1000 Vali d None Valid, no SOP, no EOP
9 1001 Valid/SOP None Valid, SOP, no EOP
A 1 010 Vali d EO P w /abor t Vali d, no SOP, abor t
B 1011 Valid/SOP EOP w/abort Valid, SOP, abort
C 1100 Valid EOP w/ 2 bytes V a lid, no SOP, EOP with 2 bytes valid
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
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Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
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The SPI4-2 spe cificat ion details all avail able Payload Control Words and should be used to
r efe rence the s pecific meaning of eac h. The IXF1110 MAC supports all required functions per this
specificat ion. However, th er e ar e various specific s in the way cert ain Control Words affe ct the
balance of the IXF1110 MAC opera tion, suc h as how the device deals with EOP Aborts.
The SPI4-2 specif ication al lows the EOP Abort Payload Control word, which signals that the dat a
as s ociated with a particular frame is errored and should be dropped, or errored and dropped by the
f ar-end link partner. In the IX F11 10 MAC, all TX SPI4-2 transfers that end with an EOP Abort
code have the TX SerDes CRC corrupted. This is true regardless of the MAC configuration.
Figure 11 shows per-port state transitions a t control-word boundaries. At any given time, a port
ma y be active (sending data), pau se d (not sending data but pending the completion of an
outstanding packet), or inactive (not sending data, no outstanding packet).
5.2.1.2 EOP A b o r t
EOP Abor ts is an End- of - Packe t ( EOP) termination that is sent out of the IXF 11 10
MAC SPI4- 2 to te ll the upstre am SPI 4-2 devic e that a packet i s bad. EOP Abort pac kets are sent by
the IXF1110 MAC under the following conditions:
D 1101 Val id EO P w/ 2 bytes Valid, SOP, EOP wi th 2 by tes valid
E 1110 Valid EOP w/ 1 byte Valid, no SOP, EOP with 1byte valid
F 1111 Valid EOP w/ 1 byte Valid, SOP , EOP with 1byte valid
Tab le 19. Control Word D efinitions (Sheet 2 of 2)
Bit
[15:12] Next Word
Status Prior Word Status Meaning
Figure 11 . Per-Port State Diagram with Tr ansitions at Con trol Words
PORT [n]
INACTIVE PORT [n]
ACTIVE PORT [n]
PAUSED
PC[n] & -SOP
(IC I PC[-n]) & -EOP
PC[n] & EOP & SOP
PC[n] & SOP
(IC I PC[-n]) & EOP
PC[n] & -EOP & -SOP
Key:
IC: Idle Control Word
PC[n]: Payload Control Word for port n
PC[-n): Payload Control Word for a port other than port n
SOP: Start-of-Packet in Payload Control Word
-SOP: No Start-of-Packet in Payload Control Word
EOP: End-of-:acket in Control Word
-EOP: No End-of-Packet in Control Word
&: AND
I: OR
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 63
•S tandar d siz e (64-1518 byt e) pac kets tha t are fil tered (“RX Pack et Filt er Cont rol ($ P ort_Inde x
+ 0x19)”) but not dropped due to the se tting in the “R X FI FO Erro red Frame Drop Enable ($
0x59F)” (see Section 5.1. 2.3, “Filtering of Rece ive Packets” on page 45).
•S tandar d siz e (64- 1518 byte ) pa ckets t hat are gre ater in si ze tha n t he se tting i n th e “Max Frame
Size ($ Port_Index + 0x0F)” and are not dropped due to the set ting in the “RX FIFO Errored
Fram e Drop Enable ($ 0x59F)”.
•Jum bo fra mes tha t mee t t he f ilter cond iti ons set in the “RX Packet Fi lter Control ($ Port_Inde x
+ 0x19)” on page 139 or are above the “Max Frame Size ($ Po rt_Index + 0x0F)” on page 135.
•RX FIFO overfl ows.
•Packets received with /V/ error codes on the SerDes interface that are not dropped due to
se tt in gs in th e “RX FIFO Errored Frame Drop Enable ($ 0x59F)” on page 160.
•Runt P acke ts (under 64 b yte s) rec eived that a re not dro pped due to th e set ting in the “RX FIFO
Errored Frame Drop Enable ($ 0x59F)” on page 160.
Note: EO P Abort pac kets sent out on th e RX SPI4-2 may have the pac ket size modified. When an EOP
abort packet is received on the TX SPI4-2, the IXF1110 MAC sends the packet out to the SerDes
interface with an invalid CRC and is recorded in the TX statistics as a CRC error.
5.2.1.3 DIP4
Figure 12 shows the range over which the Diagonal Interleaved Parity (DIP-4) parity bits are
comp uted. A funct ional description of calculating the DIP-4 code is given as f ollows. Ass ume that
the s tream of 16-bit data words are a rranged as shown in Figure 13 (MSB at th e left most column,
tim e mov ing downward). (The f irs t word received is at the top of the f igure; the last word is at the
bottom of the figure.) The parity bits are gene rated by summing diagonally (in the control word,
the s pace occupied by the DIP-4 code (bits a, b, c, d) is set to all 1s during enc oding). The first 16-
bit result is spli t into two bytes, which are added to each othe r m odulo-2 t o produce an 8-bit result.
The 8-bi t res ult is the n divided into two 4-bit nibbles, which are adde d to ea ch other modulo-2 to
produce th e final DIP-4 code. The pr ocedure describ ed a pplies t o ei ther pa rit y generati on on the Rx
path or to check parity on the Tx path.
Figure 12. DIP-4 Calculation Boundaries
A9039-01
Payload Payload
DIP-4 Codewords
Control Control Control Control
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
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5.2.2 Start-Up Parameters
5.2.2.1 CALENDAR_LEN
CA LE NDAR_ LE N speci f ies the length of each calendar sequence. As the IXF1110IXF1110 MAC
is a 10-port device, CALENDAR_LEN is fixed at 10 for both TX and RX data paths.
Figu re 13. D I P-4 Calc ul at i on Algorithm
A9040-01
1st SPI-4 Phase II data
word of incoming burst
10101 0110001011 1
10101010
11101010
01000000
16-bit parity sum
(DIP16[15:0])
0100
0000
0100
DIP4 parity bits
(DIP4[3:0])
8-bit parity sum
DIP4[3] = DIP16[15] DIP16[11] DIP16[7] DIP16[3]
DIP4[2] = DIP16[14] DIP16[10] DIP16[6] DIP16[2]
DIP4[1] = DIP16[13] DIP16[9] DIP16[5] DIP16[1]
DIP4[0] = DIP16[12] DIP16[8] DIP16[4] DIP16[0]
a, b, c and d are all set
to 1 during encoding.
0321
control word: not included in
parity calculations below
2nd SPI-4 Phase II data
word of incoming burst
3rd SPI-4 Phase II data
word of incoming burst
4th SPI-4 Phase II data
word of incoming burst
5th SPI-4 Phase II data
word of incoming burst
6th SPI-4 Phase II data
word of incoming burst
7th SPI-4 Phase II data
word of incoming burst
8th SPI-4 Phase II data
word of incoming burst
10110 1011100010 0
00001 1010010011 0
00110 0000100000 0
11010 1111110000 0
00000 0000100010 0
00010 1011100000 0
11010 1010001011 0
10110 00000
00000 0
11110 0a0bc00010 d
03214765811 10 91215 14 13
to 2
to 3
to 4
to 5
to 6
to 7
to 8
to 9
2
3
4
5
6
7
8
9
00100 1w1xy00010 z
Each bit of this 16-bit parity sum is the
result of a XOR operation along the
corresponding dashed line.
control word: included in parity
calculations (contains the results of
parity for the 8 SPI-4 Phase II data
words above and this control word)
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 65
5.2.2.2 CALENDAR_M
CALENDAR_M specifies th e number of times the cale ndar port status sequence is repe ated
between the framing and DIP2 cyc le of the calendar sequence.
In the IXF1110 MAC, the TX path CALENDAR _M is fixed at 1; thus, the port status for ports 0 -
9 will be tra nsmitted only once betwee n the framing and DIP2 cycle of the calendar s equence.
In the IXF1110 MAC, the RX path CALENDAR_M is also fixed at 1. Thus, the status for port 0-9
must only be sent once between fra mi ng and DIP2.
Theref ore, the value of both Tx and RX CALENDAR_M parameters is always fix ed a 1.
5.2.2.3 DIP2_Thr
DIP2_Thr is a parameter specifying the num ber of co nsecutive correct DIP2s required by the RX
SPI4-2 to validat e a calendar seque nce and therefore terminate sending training sequences . In
Table 103, “SPI4-2 RX Cale ndar ($ 0x702)” on page 174, bits 19 to 16 spe cify this parameter. The
default value for DIP2_Thr is 1.
5.2.2.4 Loss_Of_Sync
Loss_of_Sync is a parameter specifying the number of consecutive framing calendar cycles
required to indicate a loss of synchroniz ation and the r efore restart training sequences. Table 103,
“SPI4-2 RX Calendar ($ 0x702)” on page 174, bi ts 11 to 8 specify this parameter. The d efault
value for Loss_Of_Sync is three.
5.2.2.5 DATA_MAX_T
DATA_MAX_T is an RX SPI4-2 paramete r specifying the inte rval between trans mi ssion of
periodic training sequences. In Table 102, “SP I 4-2 RX Training ($ 0x701)” on page 173, bits 15 to
0 specify this pa rameter. The defa ult value for DATA_MAX_T is 0x0000, which dis ables periodic
tr aining seq uence trans mission.
5.2.2.6 REP_T
REP_T is an RX SPI4-2 parameter spec ifying the numbe r of repetitions of t he training sequence t o
be scheduled every DATA_MAX_T interval. In Table 102, “SP I4-2 RX Training ($ 0x701)” on
page 173, bits 23 to 16 specify this pa ram eter. The default val ue for REP_T is 0x00.
5.2.2.7 DIP4_UnLock
DIP4_UnLock is a TX SPI4-2 parameter specifying the num ber of consecutive incorrect DIP4
fields to be detecte d in order to declare loss of synchronizat ion and drive TSTAT[1:0] bus with
framing. In Table 104, “SPI 4-2 TX Synchronizati on ($ 0x703)” on page 175, bits 15 to 8 specify
this param eter. The default value for DIP4_UnLock is 0x4.
5.2.2.8 DIP4_Lock
DIP4_Lock is a TX SPI4-2 parameter specifying the number of consecutive correct DIP4 fields to
be detected in order to declare synchronization achieved and enable the calendar sequence. In
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
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Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
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Table 104, “SPI4-2 TX Synchr oniza tio n ($ 0x703)” on page 175, bits 7 to 0 speci f y this parameter.
The default value for DIP4 _Lock is 0x20.
5.2.2.9 MaxBurst1
MaxBurst1 is an RX SPI4-2 parameter specifying the maximum number of 16 byte blocks that
may be transmitted when the associated FIFO status indicates “starving”. Bits 24 to 16 of the
SPI4-2 RX Burst Size Register specify this parameter. The default value for MaxBurst1 is 0x006,
indicating a MaxBurst1 of 96 bytes [see Table 101, “SPI4-2 RX Burst Size ($ 0x700)” on
page 173].
5.2.2.10 MaxBurst2
MaxBurst2 is an RX SPI4-2 parameter specifying the maximum number of 16 byte blocks that
may be transmitted when the associated FIFO status indicates “hungry”. Bits 8 to 0 of the SPI4-2
RX Burst Si ze Register specify this param eter. The default value for Ma xBurs t2 is 0x002, i ndicat-
ing a Max Burs t2 of 32 bytes (see Table 101, “SPI 4-2 RX Burst Size ($ 0x700 )” on pag e 173).
5.2.3 Dynamic Phase Alignment Training Sequence (Data Path De-skew)
5.2.3.1 Training at Start-up
The SPI4-2 Specificat ion states that on power-u p or after a reset, the training sequence (as defined
in th e SP I4-2 Spe cific ation ) is sent indefi nit ely by th e sourc e sid e until it recei ves va lid F IFO stat us
o n th e FIFO bus. The specification als o states that it is poss ible for th e bus de- skew to be
com pleted after one tr aining sequence takes place. It is unlike ly that the bus can be de -skewed in a
single tra ining sequence because of the prese nce of both random and de terministic jitt er. The only
wa y to account for th e random el ement is to det er min e an average over repeated training
sequences. Since the required number of repeats is dependent on several characteristics of the
system in which the IXF1110 MAC is being used, power on training (or training following loss of
synchroniz ation) will continue until synchronizati on is achieved and the calendar is provi sioned.
The length of power on training will not be a fixe d num ber of repeats.
The numbe r of training sequence repeats could be fai r ly large (16, 32, or 64). If thi s is nec es sary
every tim e training is required, a significant use of interface bandwidth is needed jus t to train and
de-s kew the data path. This is onl y done at p ower -up or reset for a n optim al start ing point int erfac e.
After this, periodic training provides a better adjustment and a substantially lower bandwidth
overhead.
5.2.3 .2 Periodic Training
A scheduled training sequence is sent at le as t once every pre- configured bounded interval
(DATA_MAX_T) on both the transmit and receive paths. These training sequences are used by the
r eceiving end of eac h interface for de-skewing bit arrival times on the data and cont rol lines. The
se quence al lows th e rece iving e nd to corre ct for re la tive ske w dif fer ence of up t o +/ - 1 bit ti me. The
trai nin g sequence consist s of one (1) id le contr ol word fol lowed by one or more repe tition s of a 20-
word training pat tern cons is ting of 10 (repeated) traini ng-control words followed by 10 (repeate d)
tra in i ng - d at a w o r ds .
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
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The ini tial idle cont rol word removes depe ndencie s of the DIP-4 in the tr ainin g control words from
prece ding data words. As suming a maximum of +/- bi t tim e alignment jitter on each line, and a
maxi mu m of +/- bit time rel ative skew betwe en lines, there are at least eight bit times when a
rece iver can de tect a training c ontrol word prior to de-ske w. T he training data word is chosen to be
orthogonal to the tr aining control word. In the absence of bit errors in the training pattern, a
rece iver sh ould be able success full y to de-sk ew the data and c ontrol lin es with one tra ining pat tern.
The sending side of the data path on both the transmit and receive interfaces m ust schedule the
tr aining seq uenc e at least onc e eve r y DATA_MAX_T cyc les.
Note: DATA_MAX_T ma y be set to zero, disabling periodic training on the interface (refer to Ta ble 102,
“SPI4-2 RX Tr aining ($ 0x701) ” on pag e 173). Thi s is done when a sys tem shows very little drift
dur ing norm al operation, and no fin e-grain correction on an on-going basis is needed . This all ows
the maxim um possible bandwidth for data transfer. The tra nsmit and receive interface training
seq uences are scheduled independen tly.
5.2.3.3 Training in a Practical Implementation
The OIF Standard states that it shou ld be pos sible to train and de-skew the data input in a single
traini n g cycle. Howev er, f rom the r esearch carr ied out and th e variances in jitter and skew due to
board layout and clock tolerance issue s, some sort of ave r aging over several repeated training
patterns is required to reliably determine the optimal point a t wh ich to ca pture the incoming data.
This is true for both static alignment and dynamic phase alignment. Therefore, several training
pat te r n s ar e re q ui red f or an av erag e. Th e m o re tr ain i n g pa t te r ns , th e mo r e ac cu r at e th e ave r ag e .
The de-skew circuit in the IXF1110 MAC uses dyna mi c phase alignment with a typic al ave r aging
requirement of 32 training patt erns required to deliver a reliable result. During power-on training,
an unli mite d number of t raining cycles is sent by the data s ourcing device . (The standa rd stat es that
tr aining mus t be sou rced unt il a calen dar has been provi sione d.) In the IXF1 1 10 MAC, the de-s kew
circuit waits until completion of its programmed average over the training patterns, ensuring that
the required number of good DIP-4s is se en. Only then is a calendar provisioned.
During periodic training, it is important to ensure that the training result is no less accurate than
that already used for the initial decision during power-on training. Thus, a similar number of
training cycles must be averaged over (32). This could make the overhead associated with periodic
tr aining large if it is requ ired to be carried out too ofte n. We therefore recomme nd that periodi c
training be scheduled infrequently (DATA_MAX_T = a large number) and that the number of
repet itions of training be = 32(α).
5.2.4 FIFO Status Channel
FIFO st atus information is sent periodically over the TSTAT link from the IXF1110 MAC to the
upper layer processor device, and over the RSTAT link from the upper layer processor to the
IXF1110 MAC. The status channels operate independently.
Figure 14 shows the opera tion of the FIFO status channel. The se nding side of the FI FO status
ch ann el is in itial ly in t he DIS ABLE stat e an d se nds the “ 1 1” pat te rn repe at edl y. When FIFO st at us
transm ission is enab led, there is a trans ition to t he SYNC state and the “1 1” framing pattern is
sent. FIFO status words are then s ent according to the calendar sequence, repeating the sequence
CALENDAR_M times, followed by the DIP-2 code.
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
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The FIFO st atus of each port is encoded in a 2-bit data stru cture, whic h is defined in Table 20,
“FIF O S tatus Format” on page 70. The most si gnificant bit of ea ch port st atus is sent over
TSTAT[1]/RSTAT[1] and the least significant bit is sent over TSTAT[0]/RSTAT[0]. The “1 1”
pattern is reserve d for In-band framing, which must be s ent once pr ior to the start of the FIFO
status se quen ce .
I mmedi ately befor e the “1 1” frami ng pattern, a DIP-2 odd parity checksum is sent at the end of
each com plete sequence. The DIP-2 code is computed diagon ally over TSTAT[1]/RSTAT[1] and
TSTAT[0]/RSTAT[0] for all preceding FIFO status indications sent after the last “1 1” framing
pattern, as shown in Figure 15, “Example of DIP-2 Encoding” on page 69. The first word is at the
top of the figure and the last word is at the bottom. The parity bits are computed by summ ing
diagonally. Bit s a and b in line 9 corre sp ond to the space oc cupied by the DIP-2 parity bits and are
se t to 1 during encoding. The “1 1” framing pat tern is not inc luded in the parity calculation. The
procedure described applies to either parity generation on the egress path or to check parity on the
ingress path.
Figure 14. FIFO Status State Diagra m
Port 4Port 3Por t 2Port 1Port 0
Port 9Port 8Por t 7Port 6Port 5
SYNC 11DIP-2
Enable
Disable
11
Disable
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
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Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 69
When the parit y bits mimic the “1 1” pat tern, the receivin g end sti ll frames successfu lly by syncing
onto the la st cycle in a repe ated “1 1” pat ter n, and by making u se of the con figu red se quence length
when searching for the framing pattern.
To permit more efficient FIFO utilization, the MaxBurst1 and MaxBurst2 credits are granted and
cons umed in inc rements of 16-byt e bloc ks. For any give n port , these credit s corre spond to the most
rece ntly received FI F O st atus. They are not cumulative and s upersede previously granted credit s
for the giv en port. A burst transfer short er than 16 bytes (for example, an end-of-pac ket fragment)
consum es an entire 16-byte credit.
A continuous stream of repeated “1 1” framing patterns indicates a disabled status link. For
example, it may be sent to indicate that the da ta path de-skew is not yet com pleted or con firmed.
When a repeated “1 1” pattern is detected, all outstanding credits are cancelled and set to zero.
Figure 15. Example of DIP-2 Encoding
DIP2 Parity Bits
Framing Pattern
(not in cl uded
parity in
calculations)
1st Status Wo r d
2nd Status Wor d
3rd Status Word
4th Status Word
5th Status Word
6th Status Word
7th Status Word
8th Status Word
DIP2 Parity Bits
(DIP2[1:0]) a an d b are set to 1
during enccoding
1 1
1 0
0 0
1 0
0 0
0 0
0 0
1 0
0 1
0 1
a b
2
3
4
5
6
7
8
9
to 2
to 3
to 4
to 5
to 6
to 7
to 8
to 9
10
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
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The indicated FIFO status is based on the latest available information. A STARVING indication
pr ovides additi ona l feedb ack infor mati on, so th at tran sf ers are s chedul ed acc ordingly. Appli cati ons
that do not distingui sh betwe en HUNGRY and STARVING may only examine the most significant
FIFO status bit.
Note: If a port is disabled on the IXF1110 MAC, FIFO status for the port is set to SATISFIED to avoid
the possibility of any data being sent to it by the controlling device. This applies to the IXF1110
MAC transmit path.
Upon res et, the FIFOs in t he data path rec eiver a re emptie d, and a ny outst anding c redits are cl eare d
in the data path transmitter. After reset, and before active traffic is generated, the data transmitter
se nds continuous training patterns. Transmiss ion of the training patterns continues unti l valid
information is rece ived on the FIFO Status channel. The receiver ignore s all incoming data until it
has observe d the training patte rn and acquired synchr onization with the data. Synchroniz ation may
be declared afte r a provisional num ber of consecutive correct DIP-4 cod e words is seen. Loss of
synchronization may be report ed after a provisional number of con secutive DIP- 4 code words is
detected. [For details, see Table 104, “S P I 4-2 TX Syn chronizat ion ($ 0x703)” on page 175.]
The DIP-4 thresholds are programmable. However, there is a potentia l issue with the possibility of
a given link sh owing DIP-4 e rrors that may never lose synchroni za tion and re-trai n to fix the is sue.
This would mean an on-going and potential ly signific ant loss of data on the li nk affecting all ports
transferring data at that time.
Th is is su e m ay b e s een in th e fo ll o w in g tw o in s t an ces :
•Dur ing training (m ost likel y periodic tra ining)
•During data transfers where each of the data transfers (Ma xBurst1 or MaxBurst2) are
se parated by mor e than one idle control word
Ta b le 20. FIFO Status Format
MSB LSB Description
1 1 Reserved for framing or to indicate a disabled status link.
10
SATISFIED: Indicates that the corresponding port's FIFO is almost full. When SATISFIED is
received, only transfers using the remaining previously granted 16-byte blocks (if any) may
be s ent to the correspo nding port unti l the next status upda te. N o additional transfers to that
port are permitted while SATISFIED is indicated.
01
HUNGRY: When HUNGRY is received, transfers for up to MaxBurst2 16-byte blocks, or the
remainder of what was previously granted (whatever is greater), may be sent to the
corresponding port until the next status update.
00
STARVING: Indicates that buffer underflow is imminent in the corresponding PHY port.
When STARVIN G is received, tr ansfer s for up to MaxBur st1 16- byte blocks ma y be sen t to
the correspon ding port un til th e next status update
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 71
The mechanism for both issues is the same be cause data will not chang e during a repeated period
of the same control word being trans m itted on the link. If there have been some cons ecutive DIP-4
errors , they wil l be increment ed towards the Loss- of-S ync threshold. Thi s is most likely to occur
from a path requiring de-skew. If either a stream of idle s or training con trol words foll ow the burst
and the DIP-4 associated with each of the words is check ed, only the f irs t one and the last one will
be seen a s invalid. Any other control words in the mi ddle will be seen as having a valid DIP-4 and
will reset the Loss- of-S ync threshold counter ba ck to zero.
In order to avoid this , the IXF1110 MAC has altered th e way in which the check is done for idle
contro l words a nd tr aining c ont rol words . We now onl y valida te the fi rst occurre nce of t he DIP-4 in
both training cont rol words a nd idle control words for correctness. We do still chec k ea ch of the
words but only us e the first occur rence to clear the DIP-4 error c ounter. Any DIP- 4 error in any of
th ese words is still counted towards th e Loss-of-Sync th r es h old counter. It is now impossible to
mask the DIP-4 error on our interfac e.
5.2.5 DC Parameters
For DC parameters on the SPI4-2 interface, please refer to Table 36, “2. 5 V LVTTL and CMOS I/
O Electrical Char acteristics” on page 108 and Table 37, “LVDS I/O Electrical Characteristics” on
page 108.
5.3 SerDes Interface
5.3.1 Introduction
The IXF111 0 MAC has ten integr ated Serialize r /Des er ializ er (SerDes ) devi ces th at all o w di r ect
connection to optical modules. Each S erDes interfac e is fully compl iant with the re levant IEEE
802.3 Specifications, including auto-negotiation (see “Fiber Operation” on page 51. Each port is
als o compliant with and supports the require me nts of the Small F orm Factor Pluggable (SFP)
Multi-S ource Agreement (MSA), see “Optical Module Interface” on page 73.
The fol lowing sections describ e the opera tions supported by each SerD es interface, the
configurable options, and regis ter bits that control these options. (A full list of the register
addresses and full bit defi nitions ar e found in the Register Map (Table 58, “SerDes Bl ock Register
Map” on pag e 131).
5.3.2 Features
The SerDes core s ar e designed to operate in point-to-point data transmiss ion applications. Whil e
the core can be used across various media types, such as PCB or backplane s, it is configured
spe cificall y for use in 1000BASE-X Ethe rnet fiber applications in the IXF1 110. The following
feat ures are supported.
•10- bit data path, which connects to the output/i nput of the 8B/10B encoder/decoder PCS that
resi des in the MAC controller
•Data frequency of 1.25 GHz
•Low power: <200 mW per SerDes port
•Async hronous clock dat a recovery
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
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5.3.3 Functional Description
The SerDes transmit interface sends serialized data at 1.25 GHz. The interface is differential with
two pins for transmit operation. The transmit interface is designed to operate in a 100 Ω differential
envi ronment and a ll the te rmina tions are i nclude d on t he dev ice. The ou tputs are hi gh spe ed SerDe s
and AC coupling is recommended for this interface to ensure that the correct input bias current is
supplied at the rece iver.
The Se rDes rec eiv e in ter fac e rec eiv es s eri al ized d ata at 1. 25 GHz . Th e int er fac e is di f fe ren tia l wit h
two pins for the receive operation. The equalizer recei ves a differential s ignal that is equalized for
the assum e d m e di a cha n nel. The SerDes transmit and receive interf aces are designed to operat e
within a 100 Ω differential environment and all terminations are included on the device.
5.3.3.1 Transmitter Operational Overview
The tr ansmit se ction of the I X F1110 has to ser ial ize the Ten Bit Interface (TBI) d ata from the
I XF1110 MAC section and outputs this data at 1.25 GHz differential signal level s. The 1.25 GHz
d i ffer en tial SerD es signals are compliant with t h e Small For m Factor Pl u g gable (SFP) Multi -
So urc e A g re em en t (M SA ) .
The transmitter section take s the contents of the data register within the MAC and synchronousl y
tr ansfers the data out, ten bits at a time – Least S ignificant Bit (LSB) first, followed by the ne xt
Most Signific ant Bit (MSB). When thes e ten bits have been serialized and transmitted, the next
word of 10-bit data from the MAC is ready to be serial ized for transmiss ion.
The data is transmitted by the high-speed current mode differential SerDes output stage using an
internal 1. 25 GHz clo ck gen erated from the 125 MHz cloc k input.
5.3.3.2 Tran smi tter Pr o g r ammab l e D r iv er -Po wer L evel s
The IXF11 10 SerDes core has programmable trans mi tter power levels to enhance usability in any
give n applic at ion.Th e SerDes Regist ers are progra mmable to all ow adjust ment of the tra nsmi t core
dr iver outp ut powe r . When dri ving a 100 Ω dif fe rent ial te rmina ted net work, the se outp ut power set-
tings effectively establish the differential voltage swing s at the driver output.
The (Regis ter) al lows th e selec tion of 4 di screte power se ttings . The se lect ed power set ting of t hese
input s is ap plied to each of the tr ansmit cores driv ers on a per-port basis. T able 17, “SPI4-2 Interface
Si gnal Summary” lists th e Normalized power setting of the transmit drivers as a function of the
Drive r Power Con trol inputs . The normalized curr ent sett ing is 10 mA which co rrespo nds to the nor-
ma lized power setting of 1.0. T his is the default setting of the IXF1110 SerDes interface. Other val-
u es li sted in the Normalized Drive r Power Setting co lumn ar e multiples of 10 mA. F o r ex ampl e,
with inputs at 1110, the driver powe r is .5 x 10 mA = 5 mA.
Ta b le 21. SerDes Driver TX Po wer Le vels
DRVPWRx[3] DRVPWRx[2] DRVPWRx[1] DRVPWRx[0] Normalized
Driver Power
Setting Driver Power
0 0 1 1 1.33 13.3 mA
1 0 1 1 2.0 20 m A
1 1 0 1 1.0 10 m A
1110 0.5 5 mA
NOTE: A ll ot h er values ar e reserved.
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 73
5.3.3.3 Receiver Operational Overview
The rece iver structure performs Cloc k and Dat a Re covery (CDR) on the incoming ser ial data
stream . The quality of this operation is a dominant factor for the Bit Error Rate (BER) system
performance. Feed forward and feedba ck controls are combined in one receiver architecture for
enhanced performance. The data is over-sampled and a digital circuit detects the edge position in
the dat a s tream. A signal is not generated if an e dge is not found. A feedback loop takes ca re of
low-frequency ji tter phenom enon of unlim ited amplitude, while a feed forwa r d section suppresses
high-frequency jitter havin g limited amplitude. The stat ic e dge pos ition is held a t a con st ant
position in the ov er-sa mpl ed by a constant adjus tm ent of the sampling phases with the early and
late signa ls.
5.3.3.4 Selective Power-Down
The IXF1110 offers the ability to selectively power-down any of the SerDes TX or RX ports that
are not being used. This is done via “SerDes TX and RX Power-Dow n Ports 0-9 ($ 0x787)” on
page 176.
5.3.4 Timing and Electrical Characteristics
For timing and electrical characteristics for the IXF111 0, see Figure 39, “SerDes Timing” on
page 119, “Transmitter Char acteristics” on page 119 and “Receiver Characteri stics” on page 120.
5.4 Optical Module Interface
5.4.1 Introduction
This section des cribes the connectio n of the IXF1110 ports to an opt ical module, and the
connections s upported for corre ct ope ration are deta iled. The registers used to write control and
read sta tus in format ion are docum ented i n Section 8.5. 9, “ Opti cal Modu le Inter fac e Block Re gist er
Overview” on page 177).
The opt ical module interface al lows the IXF1110 a seamless connection to the Small Form Fact or
Optical Modules (SFP) that form the system’s physical media connection, eliminating the need for
any FP GAs or CPUs to proces s data. All requi red i nformation of the optica l modul es is a vaila ble to
th e system CPU thr o u gh the I X F1110 CPU interfac e, lead ing to a more integra ted, reliable, an d
cost-effective system.
5.4.2 IXF1110 Supported Optical Module Interface Signals.
For opt ical module int erfa ce operation, three supported signal subg roups are required, allowing a
more explicit definition of eac h function and implementation. The thre e su bgroups are as foll ows:
•High-Speed Serial Inter fac e
•Low-Speed Status Signaling Inte rface
•I2C Module Configuration Interface
Table 22 provides descriptions for IXF1110-to-SFP optical module connection pins.
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
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5.4.3 Functional Descriptions
5.4.3.1 High-Speed Serial Interface
These signals are responsible for transfer of the actual data at 1.25 Gbps. The data is 8B/10B
encoded and trans mi tted diff erentially at SerDes levels per the required specifications.
The signals required to implement the high-speed serial interface are:
•TX_9:0_P
•TX_9:0_N
•RX_9:0_P
•RX_9:0_N
5.4.3 .2 Low-Speed Sta tus Signaling Interface
The fo llowing low- spe ed signals indicate th e state of the line via the optical modul e:
•MOD_DEF_9:0
•TX_FAULT_9:0
•RX_LOS_9:0
•TX_DISABLE_9:0
•MOD_DEF_Int
•TX_FAULT_Int
•RX_LOS_Int
Tab le 22. IXF1110-to-SFP Conne ctions
IXF1110
Pin Names SFP Modul e
Pin Name Description Notes
TX_9:0_P TD+ Transmit Data, Differential SerDes Output from the
IXF1110
TX_9:0_N TD-
RX_9:0_P RD+ Receive Data, Differential SerDes Input to the IXF1110
RX_9:0_N RD-
I2C_CLK MOD-DEF1 I2C_CLK Output from IXF1110 (SCL) Output from the
IXF1110
I2C_DATA_9:0 MOD-DEF2 I2C_DATA I/O (SDA) Input/Output
MOD_DEF_9:0 MOD-DEF0 MO D_DE F(0) shou ld b e TTL Low le vel during
normal operation. Input to the IXF1110
TX_DISABLE_9:0 TX DISABLE Transmitter Disable, Logic High, Open
colle ctor co m patibl e Output from the
IXF1110
TX_FAULT_9:0 TX FAULT Transmitter Fault, Logic High, Open collector
compatible Input to the IXF1110
RX_LOS_9:0 LOS Receiver Loss of S ign al, Logic High, Op en
colle ctor co m patibl e Input to the IXF1110
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 75
5.4.3.2.1 MOD_DEF_9:0
These sig nals are dir ect inputs to the IXF11 10 and are pulled to a logic Low level during normal
operation, indica ting that a module is prese nt for each p ort, res pectivel y. If a module is not prese nt,
a logic High is received , which is ach ieved by an externa l pull-up resi st or at the IXF1110 pad.
The status of eac h bit (one for ea ch port) is found in bits 9:0 of the Optical Module S tatus Register
(refer to Table 108, “Optic al Module Status P orts 0-9 ($ 0x799)” on pag e 177). Any change in the
state of these bits causes a logi c Lo w leve l on the MOD_DEF_Int output if this operation is
enabled.
5.4.3.2.2 TX_FAULT_9:0
These 10 pins are inputs to th e IXF1110. These signals are pulled to a logic Low le vel by the
optical module during normal operation, which indicates no fault condition exists. If a fault is
pres ent, a logic High is r ec eived via the use of an ext ernal pull-up resis tor at the IXF1110 pad.
The sta tus of each bit (one for eac h port) ca n be found in bits 19:10 of the Optical Module S tatus
Reg ist er (see Table 108 , “Optical Module S tatus P orts 0-9 ($ 0x799 )” on page 177 ). Any change in
the s tate of these bi ts cau se s a logi c Low level on the TX_FAULT_Int output if this operation is
enabled.
5.4.3.2.3 RX_LOS_9:0
These 10 pins are inputs to th e IXF1110. During norma l operation, these signa ls are pull ed to a
logic Low level by the optical modul e, which indicates tha t no Loss - of-Signal exists. If a Loss-of-
Sig nal occu rs, a logic High is rece ived on these inputs via the use of an external pull-up resist or at
the IXF1110 pad.
The sta tus of ea ch bit (one for each port) is found in “Optical Module Status Ports 0-9 ($ 0x799)”
bits 29:20. Any change in the sta te of thes e bits causes a logic Low level on the RX_LOS_Int
output if this ope ration is enabled.
5.4.3.2.4 TX_DISABLE_0:9
These 10 pins a re outputs from the IXF 1110. During normal operation, these signal s are pulled to a
lo gic Low level by the I X F11 10, ind icating that the optical mo dule tra nsmitte r is enabled. If the
optical module transmitter is disabled, these signal s are switched to a logic High level. On the
IXF1 1 1 0, thes e outputs are open- drain type s and pull ed up by the 4.7k to 10k pull-up resis tor at the
optical module. Each of these s ignals is controlled via “Optical Module Contr ol P orts 0-9 ($
0x79A)” bits 9:0, respectively.
5.4.3.2.5 MOD_DEF_INT
MOD_DEF_Int is a single out put, open-drain type signal, and is active Low. A change in state of
any of the MOD_DEF_9:0 inputs caus es this signal to swi tch Low and remain in this st ate until a
Read of the “Optical Modu le Status Ports 0-9 ($ 0x799)” takes plac e. The signal then retur ns to an
in acti ve state.
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
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Note: The MOD_DEF_9:0 inputs shown in Table 108, “Optical Module Status Ports 0-9 ($ 0x799)” on
page 177 are sy n c h ro ni zed wi th an in ter n al sys t em clo ck. T hi s r esu lts in a de lay fr o m th e ti m e th e
signal is active to the register bit and/or interrupt being set.
5.4.3.2.6 Tx_FAULT_INT
TX_FAULT_Int is a single output, open-drain type signal, and is active Low. A change in state of
any of the TX_FAULT_9:0 inputs causes this signa l to switch Low and remain in this state until a
Read of the “Opt ical Module S tatus Port s 0-9 ($ 0x799)” tak es p l ace. The si g nal then returns to an
inact iv e s t at e.
Note: The TX_FAULT_9:0 inputs shown in Table 108, “Optical Module Status Ports 0-9 ($ 0x799)” on
page 177 are sy n c h ro ni zed wi th an in ter n al sys t em clo ck. T hi s r esu lts in a de lay fr o m th e ti m e th e
signal is active to the register bit and/or interrupt being set.
5.4.3.2.7 RX_LOS_INT
RX_LOS_INT is a single output, open-drain type signal, and is active Low. A change in state of
any of the RX_LOS_0:9 inputs cau se s this s ignal to switch Low and remain in this state until a
Rea d of the Optical Module Status register has taken place. The s ignal then ret urns to an inactive
state.
Note: The RX_LOS_0:9 inputs shown in Table 108, “Optical Module Status P orts 0-9 ($ 0x799)” on
page 177 are sy n c h ro ni zed wi th an in ter n al sys t em clo ck. T hi s r esu lts in a de lay fr o m th e ti m e th e
signal is active to the register bit and/or interrupt being set.
Note: MOD_DEF_INT, TX_FAULT_INT, and RX_LOS_ I NT are open-drain type outputs. With the
three signals on the device , the system can decide which Optical module Sta tus Register bits to
look at to identify the interrupt cond ition source port. However, this is achi eved at the expen se of
two device pins.
I n systems that canno t support multiple interrupt sig nals (applications that do not have ex tra
hardware pins), these three outputs can be connected to a single pull-up resis tor and used as a
single interrupt pin.
5.4.4 I2C Module Configuration Interface
The I 2C int erfa ce is supported on SFP opti cal modules . Det ails of the operation are found in the
SFP multi-source agreement (MSA). This document details the contents of the registers and
addresses accessible on a given optical module supporting this interface.
The SFP MSA identifies up to 512 8-bit registers that are acces sible in each opt ical module. The
I2C interfac e is Read/Writ e capable and supports eith er sequent ial or random access to the 8-bit
parameters. Th e maximum cloc k rate of the int erfa ce is 100 kHz. All address select pins on the
internal E2PROM are tied Low to give a device address equal to zero (00h).
The s p ec if i c in t er f ac e in th e I X F 1110 su pp o r t s on ly a su bset of th e ful l I 2C interface, and only the
f eatures required to support the optical modules ar e implemented, leading to the foll owing support
features:
•Si ngle I2C_CLK pin connected to all m odules, and im plemented to save unnecess ary pin use.
•Te n per-port I2C_DATA pins optical (I2C_DATA_9:0) are required due to the optical module
r equirement that all module s must be addressed as 00h.
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
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•Due to the singl e inte rnal control ler , only one optic al modu le may be acce ssed at any on e time.
Optical module accesses contains a single regis ter Read. Si nce these regis ter accesses will
most likely be done during power -up or dis covery of a new module , these restrictions should
not affect normal operation.
•The I2C interface also supports byte write accesses to the full address ran ge.
5.4.4.1 General Description
In the IXF1110, the entire I2C interface is contro lled through separate I 2C Control and Data
Registers (see “I2C Control Ports 0-9 ($ 0x79B)” on page 177 and “I2C Data Ports 0-9 ($ 0x79C)”
on page 178. The gene ral operation is desc ribed below.
The I2C Control Register is divided into the following sections:
•Port Address Error
•Write Protect Error bit
•No Acknowledge Error bit
•I2C Enable bit
•I2C Start Ac cess bit
•Writ e A cce ss C omplete bi t
•Read DataValid bit
•4-bit Port Address Select
•Read /Wr it e ac ces s se l ec t
•4-b it Device ID
•11-bit Register Address
The I2C Data Register is divided into the following sections:
•8-b it Write Data
•8-bit Read Data
The 4-bi t Device ID field def aults to Ah, thi s value is compati ble with s tandard fiber module base d
on the Atm el Serial E2Pr om famil y. I2C accesses to non-Atmel compatible devices will require to
update this field with the appropriate value.
The 11-bit Regis ter Addres s is split into two sub-fi elds:
•Bits [10 :8] must b e se t to 0h t o be compati ble with s tandar d fib er opti cal m odule. Alt ernati vely
thes e bits can be set to 1h - 7h to permit access to se ven other I2C co m ponent on the s am e bu s .
•Bits [7:0] spe cify the particular loca tion to be acc essed within the device specified by the
Devic e ID fiel d and Re gister Addre s s[10:8].
Initiating an access where the 4-bit Port Address field to a value > 9h will not generate an I2C
access. Instead the Port Address Error will be set.
Initiating a write access where the Device ID field = Ah and the Register Address[10:8] = 0h will
generate an I2C acc es s. In ad dition the Wr ite Protect Error bit will be set to indicate a write has
been initiated to the write protecte d optical module.
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5.4.4.1.1 Read Access Operation Example
The following sequ ence provide s an example of readin g the da ta stored in the Opti cal Module
Register 0x000 for Port 5:
1. Program the “I2C Control Ports 0-9 ($ 0x79B)” on page 177 with the following inf or mation:
a. Enab l e I2C Block by setting bit 25 to ‘1’.
b. Set the port to be accessed by setting bits [19:16] to 0x5.
c. Select a READ access by setting bit 15 to ‘1 ’.
d. Set the Device ID, bits [14:11] to be 0xA (Atmel compatible).
e. Set the 11-bit Regis ter Addres s, bits [10:0] to 0x000.
f. Initiat e the I2C transfe r b y setting bit 24 to ‘1’.
All other bits in thi s register should be wr itten with the value ‘0’.
T h is d at a is w r it ten in to th e I2C Control Re g ister in a single cycle via the CPU interface.
2. When this register is written and the I2C Start bi t is at a Logic 1, the I2C access state machine
ex amin es the Port Address Select and enabl es the I2C_DATA_0:9 output for the selected port.
3. T he state machine use s the da ta in the Device ID and Register Addres s fields to build the data
f r am e to be sent to the optical module.
4. The I2C DATA_REA D _ FSM internal stat e machin e take s over the task o f transferring th e
actual data bet w een the IXF1110 and the selected op tical module (refer to the details in
Section 5.4.4.2, “I2C Pr otocol Spe cifics” o n page 79).
5. The I2C DATA_READ_FSM internal state machine places the received data into the
Rea d_Data field, bits [7:0] of t he I2C Data Registe r, and sets the Read Data Valid bit, bit 20 of
the I2C Control Reg ister to ‘1 ’ to signify that th e Read dat a is valid.
6. T he data is read through the CPU i nterface . The C P U mu st poll the Read Da ta Valid bit un til i t
is set to ‘1 . O n ly once th i s bi t is s et , it is sa f e to r ead the data in th e I2C D at a Reg iste r.
5.4.4. 1.2 Wri te A ccess O peration Examp l e
The following sequ ence provide s an example of writing data to the Optical Module Re gis ter 0xFF
fo r P ort 9 :
1. Program the “I2C Control Ports 0-9 ($ 0x79B)” with the foll owing inform atio n:
a. Enab l e I2C Block by setting bit 25 to ‘1’.
b. Set the port to be accessed by setting bits [19:16] to 0x9.
c. Sel ect a W R I TE acces s b y se t t in g bi t 15 to ‘0 ’ .
d. Set the Device ID, bits [14:11] to be 0xA (Atmel compatible).
e. Set the 11-bit Regis ter Addres s, bits [10:0] to 0xFF.
f. Initiat e the I2C transfe r b y setting bit 24 to ‘1’.
All other bits in thi s register should be wr itten with the value ‘0’.
T h is d at a is w r it ten in to th e I2C Control Re g ister in a single cycle via the CPU interface.
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
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2. Whe n th is re g is t er is w r it t en an d the I2C Star t bi t is at a Log i c 1, th e I 2C access state machine
examines the Port Address Select and enables the I2C_DATA_0:9 output for th e selected por t.
3. T he s tate machi ne us es the data in the Devic e ID and Regi ster Address fields to bui ld the data
frame to be sent to the o ptical module.
4. T he I2C DATA_WRITE_FSM internal state machine takes over the task of transferring the
actual data between the IXF1110 and the selected opt ical module (refer to the details in
Section 5.4.4.2, “I2C Prot ocol Specifics” on page 79).
5. T he I2C DATA_ WRITE _ FS M in t er n al s ta te m ach i n e us es th e dat a f r om th e Write _Data fi el d ,
bits [23 :16] of th e I2C Da ta Regis ter , and s ets the W r ite _Co mplet e bit, bi t 22 of the I2C Contro l
Reg ister to ‘1’ to sign ify th at the Write Ac cess is compl ete.
6. The data is written through the CPU int er face. The CPU must p oll the Wri te_Complete bit
until it is se t to ‘ 1. Only onc e this bit is se t, it is s afe to request a new acces s.
Note: Only one optical module I2C access sequence can be run at any given time. If a second Write is
carr ied o ut t o the I2C Control R egister before a resul t is retu rned for th e previo us W ri te, the da ta for
th e f ir st Write is lo st. To ensure no data is lost, ma ke sure Write com plete = 1 bef ore star ting the
next Write seque nce .
5.4.4.2 I2C Protocol Specifics
This section describes the I2C protoc ol behavior supported by the IXF11 10, which is controlled by
an inte rnal st ate machine. Specifi c proto col state s are def ined belo w , with an addit iona l descript io n
of the hard ware pins use d on the interface.
The Serial Clock Line (I2C_CLK) is an IXF1110 output. The serial data is synchronous with this
clock and is driven off the rising edge by th e IXF1110 and off the falling edge by the optical
module. The IXF1110 has only one I2C_CLK line that drives all of the optical modules. The
I2C_CLK runs continuousl y when enabled (I2C Enable = 01h0).
The Serial Data (I2C_DATA_0:9) pins (one per port) are bi-directional for serial data transfer, and
are ope n dr ain.
5.4.4.3 Port Protocol Operation
5. 4.4.4 Clo ck and D ata Tran sit i o n s
The I2C_DATA is normally pulled High with a n extra device. Data on the I2C_DATA pin changes
only during the I2C_CLK Low time periods (see Figure 16). Data changes during I2C_CLK High
periods indic ate a start or stop condition.
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5.4.4.4.1 Sta rt Condition
A High-to-Low transition of I2C_DATA, with I2C _ CLK High, is a start condition that must
precede any o ther co mmand (s ee Figure 17).
5.4 .4 .4. 2 Stop Condition
A Low-to-High transition of the I2C_D ATA with I2C_CLK High is a stop condition. After a Read
se quence, th e st op command places the E2PROM in the opt ical in a standby power mode (see
Figure 17).
5.4.4.4.3 Acknowledge
All a ddre sses and da ta words are seri ally tr ansm itted to and from the opti cal m odule i n 8-bit words .
The optical module E2PROM sends a zero to ac knowledge tha t it has received each word, which
happens durin g the ninth clock cycle (see Figure 18 ).
Figure 16. Data Validity Timing
DATA STABLE DATA STABLE
DATA
CHANGE
I2C_DATA
I2C_CLK
Figu re 17 . Start and Stop De fin iti on Tim in g
START STOP
I2C_DATA
I2C_CLK
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5.4.4.4.4 Memory Reset
After an interru ption in p rotocol, power loss, or system reset, any two-wire Optical Module can be
res et by following thre e steps:
1. Clock up to nine cycles
2. Wait for I2C _ D ATA Hi g h in ea ch cy cl e w h il e I2C_CLK is High
3. Initiate a start condition
The following defines de vice memory reset:
•Always add a stop condition f ollowing th e s tart as there is no clean finish to end the reset of
the memo ry with a start conditio n after completing steps one through three. Thi s e ns ures a
clean pr o to c ol te rm in ati o n if th e re is no m o r e da t a to tran s f e r at th e en d of th e re set cy cl e.
5. 4.4.4. 5 De vi ce Ad d r essi n g
All E2PROMs in Opti cal Module devices require an 8-bit devi ce addre ss word following a start
condition to enable the chip to read or write. The devic e address word consists of a mandatory one,
zero sequence for th e four most si gnificant bits. This is com mo n to all devices. The next 3 bits are
th e A2, A1 and A0 devi ce add res s b it s tha t ar e ti ed t o ze ro in a opt ic al modu le. T he e igh th b it o f t he
device address is the Read/Write operation select bit. A Read operation is initiated if this bit is
Hig h and a Write oper ati on is initiated if thi s bit is Low.
Upon comp arison of the device address, the optical module outputs a zero. If a comparison is not
made, the optica l m odule E2P ROM returns to a standby state.
When not accessing the optical module E2PROM, the device address or devi ce ID is compl etely
programm able for maxi mum flexibility.
5.4.4 .4.6 Random Read Operation
A random Read requires a “du mmy” Byte/W r i te sequence to l o ad the data word ad d r ess. The
following describes how to achieve the “dummy” Write:
Figure 18. Acknowledge Timing
START ACKNOWLEDGE
I2C_DATA
DATA IN
DAT A OUT
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•The IXF11 10 generates a sta r t condition.
•The IXF11 10 sends a de vice address word with the Read/Write bit cl eared to Low, s ignaling a
Write operat ion.
•The optical module acknowle dges receipt of the device addr es s word.
•The IXF1110 sends the data word addre ss, which is again acknowledged by the opti cal
module.
•The IXF11 10 generates an other start condition.
This completes the “dummy ” Write and sets the optical module E2PROM pointers to the desired
location.
The following describes how the IXF1110 initiates a current address Read:
•The IXF1110 sends a device address with the Rea d/Write bit set High
•The op tical module acknowledges the device addres s a nd se rially clocks out the dat a word.
•The IXF1110 does not respond with a zero but generates a stop condition (see Figure 19).
Timing diagrams and tables can be found in Section 7.0, “Electrical Specifications” on page 106 .
5.4.4. 4.7 B yte Writ e Ope r ati o n
The following describes how to achieve the byte wr ite operation:
•The IXF11 10 generates a sta r t condition.
•The IXF11 10 sends a de vice address word with the Read/Write bit cl eared to Low, s ignaling a
Write operat ion.
•The optical module acknowle dges receipt of the device addr es s word.
•The IXF1110 sends the data word address.
•The optical module acknowle dges receipt of the data word address.
•The IXF1110 sends the data byte to be written.
•The optical module acknowledges the data word.
•The IXF11 10 generates a stop condition (see Figure 20).
Figu re 19. R ando m Read
DEVICE
ADDRESS
DEVICE
ADDRESS
WORD
ADDRESS
SDA LINE
DU MMY WR I TE
(* = DON'T CARE bit for 1k)
START
S
T
A
R
T
R
E
A
D
S
T
A
R
T
W
R
I
T
E
S
T
O
P
M
S
B
M
S
B
M
S
B
L
S
B
R
/
W
L
S
B
DATAn
L
S
B
A
C
K
N
O
A
C
K
A
C
K
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5.4.4.5 AC Timing Characteristics
Table 43, “I2C AC Timing Characteri stics” on page 115, Table 35, “I2C Bus Timi ng” on page 115,
and Table 36, “I2C Wr ite Cycle” on page 115 provide the AC timing characteristics of the optical
modul e interface.
5.5 LED Interface
5.5.1 Introduction
The IXF1110 MAC uses s a serial interface consisting of three s ignals to prov ide LED data to a
serial-to-parallel logic external driver. The three signals are as follows:
•LED CLK: Th is cl ock is pr ovided by the IXF11 10 MAC to cloc k th e exter nal para llel -to- seria l
shift registers.
•LED DATA: T his s erial da ta is prov ided by t he I XF1 1 1 0 MAC to t he e xter nal pa ra llel- to-s e rial
shift registers.
•LED LATCH: This latch is pr ovided by the IXF1110 MAC to latch the data on the parallel-to-
ser ial shift regi sters.
The LE D_DATA str eam pr ovides da ta for 3 0 sep arate dir ect drive LEDs and allows t hree L EDs per
MAC port. Th e three LED pins outlined above a re detailed in Table 23, “LED Sig nal
Descriptions”.
There are two modes of operation, each with its own separate LED decode mapping. Modes of
operation and LEDs are de tailed in Section 5.5.2, “Modes of Operation”.
5.5.2 Modes of Operation
Mode selection is accomplis hed by using bit 0 of the “LED Control ($ 0x509)” on page 152. This
bit is globally selected and controls the mod e of operation of al l ports Section 5.5.2. 1 an d Section
5.5.2.2 provide the two modes of operation.
Figure 20. Byte Write
DEVICE
ADDRESS WORD
ADDRESS
I
2C_Data Line
(* = DON'T CA RE bit fo r 1k)
S
T
A
R
T
W
R
I
T
E
M
S
B
M
S
B
L
S
B
R
/
W
L
S
B
A
C
K
*
A
C
K
S
T
O
P
DATAn
A
C
K
A
C
K
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5.5.2.1 Mod e 0
This mode selects operations com patible with the SGS Tho mpson M5450 Led Display Driver
Device. This device converts the se rial data stre am, output by the IXF1110 MAC, into 30 direct-
dr ive LE D outputs. In this mo de, the latch signal is not required. This mode is sel ected by setting
b it 0 of the “LED Control ($ 0x509)” to 0 (default).
5.5.2.2 Mod e 1
This mode selects operati ons compatible with TTL (74LS595) or HCMOS (74HC595) octal shift
r egisters. This device converts the ser ial data stream, output by the IXF1110 MAC, into 30 direct-
dr ive LED outputs. In this mode the LED DATA, LED CLK and LED LATCH signals ar e used.
This mode is sel ected by setting bit 0 of the “LED Control ($ 0x509)” to 1.
5.5.3 LED Interface Signal Description
The IXF1110 MAC LED interface consi sts of three output signal pins that are 2. 5 V CMOS le vel
pads. Table 23, “LED Signal Des criptions ” provides LED signal names, pin numbers, and
descriptions.
5.5.4 Mode 0: Detailed Operation
Note: Pl ea se refe r to the SGS Tho mpson M5450 data sheet for device-operation informa tion.
The operation of the LED Interface in Mode 0 is based on a 36-bit counter loop. The data for each
LE D is pla ced in turn on the serial dat a line and clocked out by the LED_ CLK. Figure 21 on
page 85 shows the basic timing relationship and relative positioning in the data stream of each bit.
Figure 21 shows the 36 clocks that are output on the LED_CLK pin. The data changes on the
f alling edge of the cl ock and is valid for almost the e ntire clock cycl e. Thi s e nsures that the data is
valid during the ris ing edge of the LED_CLK, which is used to clock the data into the M5450
device.The actual data shown in Figure 21 cons ists of a chai n of 36 bi ts only, 30 of which are valid
LE D DATA. The 36-bit data chain is bui lt up as follows:
Table 23. LED Signal Descriptions
Sig n al N am e Ball
Designator Signal Description
LED_CLK A20
LED_CLK: This sig nal is an output that pr ovides a continu ous clock synchronous to
the ser ial data stream out put on the LED_DATA pin. This clock has a maxi mum speed
of 720 hz.
The behavior of this signal re mains con s tant in all m odes of operation.
LED_DATA A19
LED_DATA: This signal provi des the data, in various format s , as a s er ial bit st ream.
The dat a must be valid on the risi ng edge of the LED_CLK signal.
In Mode 0, the data presented on this pi n is TRUE (Lo gic 1 = High) .
In Mode 1, the data presented on this pi n is INVERTED (Logic 1 = Low).
LED_LATCH K18 LED_LATCH: This is an output pin and the signal is used only in Mode 1 as the
Latch enable for the shift register chain.
Thi s s ignal is no t used in Mod e 0, and should be left unconnected.
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
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When implemented on a board with the M5450 device, the LED DATA bit 1 appears on output bit
3 of the M5450 a nd the LE D DATA bit 2 appea rs on outpu t bit 4, etc. Thi s means that out put bi ts 1,
2, 3, 34, and 35 will never have valid data and should not be used.
5.5.5 Mode 1: Detailed Operation
Note: Ple as e refe r to manufacturers’ 74LS /HC595 datashe et for information on device operat ion.
The operation of the LED Interface in Mode 1 is again based on a 36-bit counter loop. The data for
each LED is placed in turn on the serial d ata line and clocked out by the LED_C LK.
Figure 22 on page 86 shows the b asic tim ing r elati onshi p and re lativ e p ositi oni ng in the da ta s tream
of each bi t. Figure 22 shows the 36 clocks that are output on the LED_CLK pin. The data changes
on the fal ling edge of the cloc k and is valid for almos t the entire clock cycle. This ensure s that the
data is valid during the rising edge of the LED_CLK, which is used to clock the data into the Shift
Reg i ster chain devices.
The LED_LATCH signal is required in Mode 1, and is use d to latch the data shifted into th e shift
regis ter chain into the output latches of the 74HC595 device. As see n in Figure 22, the
LED_LATCH signal is activ e High during the Low period on the 36th LED_CLK cycle. This
avoids any poss ibility of trying to latch data as it is shifting through the register.
Figure 21. Mode 0 Timing
Table 24. M ode 0 Clock Cycle to Data Bit Relationship
LED_CLK CYCLE LED_DATA NAME LED_DATA DESCRIPTION
1START BIT This bit is used to synchronize the M5450 device to expect 35 bits
of dat a to follo w.
2:3 PAD BITS These bits are used only as fillers in the data stream t o extend the
length from the actual 30 bit LED DATA to the required 36-bit
frame lengt h. These bits should alwa ys be a Logic 0.
4:33 LED DATA 1-30
These bits are the actual data transmitted to the M5450 device.
The decode for each individual bit in each mode is defined in
Table 23, “LED Signal Descr iptions” on page 84 .
The data is TRUE. Logic 1(LED ON) = High
34:36 PAD BI TS These bits are used as fillers in the data stream to extend the
length from the actual 30-bit LED DATA to the required 36-bit
frame lengt h. These bits should alwa ys be a Logic 0.
123 24 25 26 27 28 29 30
13526234
LED_CLK
LED_DATA
LED_LATCH
3427 333231302928 36
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When this operation mode is implemented on a board with a shift register chain containing three
74HC595 devices, the LED DATA bit 1 is output on Shift Register bit 1, and so on up the chain.
Only Shift Register bits 31 and 32 do not contain valid data. The actual data shown in Figure 22
cons ists of a 36-bit chain, of which 30 bits are valid LED DATA. The 36-bit data chain is built up
as follows:
Note: The LED_DATA signal is now inverted from the state in Mode 0.
5.5.6 Power-On, Reset, and Initialization
The LED interface is disabled at power-on or reset. The system software controller must enable the
LED interfac e. The internal state m achines and output pin s are held in r eset until the f ull IXF11 10
MAC configuration is com pleted.
5.5.6 .1 Enabling the LED Interface
“LED Control ($ 0x509)”: This register must be s et to globally enable LED int erface. Thi s i s done
by setting the LED_ENABLE bit to a logic 1. The power-on default for this bit is Logic 0.
“Port Enable ($ 0x500)”: This register ena bles and d is ables ports on a per port basis. A port must
be enabled for the LE Ds to operate for that port. If the port is not enabled, the LE Ds will be off for
that port. The power-on defa ult for this register is 0x3FF, which means all ports are enabl ed.
“Link LED Enable ($ 0 x502)”: This register must be set on a per port basis when link is de tected
by the syste m software. This enable s the per-port link LEDs for the IXF1110 MAC. Link LEDs do
not automatic ally update. For more details on which LEDs are affected by this register, refer to
section S ection 5. 5.7.1, “LED Sign aling Behavior” on page 87.
Figu re 22 . Mode 1 Timing
Tab le 25. Mode 1 Clock Cycle to Data Bit Relationsh ip
LED_CLK
CYCLE LED_DATA
NAME LED_DATA DESCRIPTION
1START BITThis bit has no meaning in Mode 1 operation and is shifted out of the 32-stage shift
regis ter chain before the LED_LATCH sig nal is asse rted.
2:3 PAD BITS Thes e bits have no meaning in Mode 1 oper ation an d are shifted out of the 32-stage
shif t reg ister chain before t he L ED_LATCH signal is asser ted.
4:33 LED DATA 1-30 T hes e bits are the actu a l data to be tran sm it te d to the 32-stag e shift re gister chain . Th e
dec ode f or each bit in each mode i s defined in Tab le 25 on page 86.
The dat a is INVERTED. Logi c 1 (LED ON) = Low.
34:36 PAD BITS These bi ts have no meani ng in Mode 1 oper ation an d are latched into po s it ions 31 and
32 in the shift register chain. These bits are not considered as valid data and should be
ignored. They should always be a Lo gic 0 = High.
123 24 25 26 27 28 29 30
135234
LED_CLK
LED_DATA
LED_LATCH
3332313029282726 34 36
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5.5.7 LED Data Decodes
Table 26 shows the data de code of the data for the IXF1110 MAC.
5.5.7 .1 LED Signaling Behavior
The operation in each mode for the decoded LED data in Table 26 is detailed in Table 27.
Table 26. LED Data Decodes
LED_DATA# MACPORT
#IXF1110 D e s ignat ion
1
0
Rx LED - Amber
2 Rx LED - Green
3 Tx LED - Green
4
1
Rx LED - Amber
5 Rx LED - Green
6 Tx LED - Green
7
2
Rx LED - Amber
8 Rx LED - Green
9 Tx LED - Green
10
3
Rx LED - Amber
11 Rx LED - Green
12 Tx LED - Green
13
4
Rx LED - Amber
14 Rx LED - Gree n
15 Tx LED - Green
16
5
Rx LED - Amber
17 Rx LED - Gree n
18 Tx LED - Green
19
6
Rx LED - Amber
20 Rx LED - Gree n
21 Tx LED - Green
22
7
Rx LED - Amber
23 Rx LED - Gree n
24 Tx LED - Green
25
8
Rx LED - Amber
26 Rx LED - Gree n
27 Tx LED - Green
28
9
Rx LED - Amber
29 Rx LED - Gree n
30 Tx LED - Green
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5.6 CPU Interface
5.6.1 General Description
The CPU Int erfa ce bloc k pr ovides access to registers and s tatistics in the IXF1110 MAC. The
inte rfa ce is a synchr onous e xterna lly and opera tes within t he 125 MHz clo ck domain i nt ernall y. The
in terfa ce provides acce ss to the foll owing registers:
•MAC Control
•MAC RX Statistics
•MA C T X St at istics
•Global St atus and Configuration
•RX B lock
•TX Blo ck
•SPI4-2 Block
•SerDes Block
•Optical Module Block
Figure 23 illu strates the I/O for the CPU interf ace on the IXF1110 MAC.
Table 27. LED Behavior
Type Status Description
RXLED
Off Synchronizat ion has o ccurr ed but no pac kets are being
rece ived an d “L ink L E D En abl e ($ 0x 502 )” has not been
set.
Amber On RX Synchronization has not occurred or no optical
signal ex is t s.
Amber Blinking Port has remote fault and “LED Fault Disable ($
0x50B)” is not set. Based on remote fault bit setting
received in R X_Confi g w ord.
Green On RX Synchroni z ation has occurr ed an d the “L ink LED
Enable ($ 0x502)” bit is se t.
Green B linki ng RX Synchroni z ation has occurr ed an d port is r eceiving
data.
TXLED
Off Port is not transmitting data or “Link LED Enable ($
0x502)” is not set.
Green B linki ng Port is transmitting data and “Link LED Ena ble ($
0x502)” bit is set
NOTE: The L ED beh avior t able assum es the port is enabled in the “Port Enable ($ 0x500)” and t he LED s ar e
enabled in the “LED Control ($ 0x509)”. If a port is not enabled, all the LEDs for that port will be off. If
the LED s ar e not enabled, all of the LEDs will be off.
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5.6.2 Functional Description
The CP U interface is designed for a generic 32-bit asyn chronous C PU bus. The bus is a 32-bit data
bus only and has an 11-bi t address bus.
The IXF1110 MAC external CPU in terface is asynchronous and has no cl ock. This all ows
flexibility for CPU selection.The interface to all IXF1110 MAC registers is synchronous to 125
MHz in ternally.
In some applications, synchronous-to-asynchronous glue logic is required between the IXF1110
MAC and the system CPU. This glue logic must be designed so that the IXF1110 MAC Read and
W rite access time s a re not violate d . It may be pos sible to interface without glue logic if the CPU
can meet the timing seen in Figure 24, “Read Timing – Asynchronous Interface” on page 91,
Figure 25, “Write Tim ing – Asyn chr onous Interfa ce” on page 91, and Table 39, “CPU Timing
Parameters” on page 110
UPX_ADD[10:0]
Internal IXF1110 MAC registers and counters are selected using the 11-bit address bus input
provided at the CPU interface. This address must be stable for the entire cycle.
Figure 23. CP U Interface Inp uts/O utp uts
UPX_WR_L
UPX_RD_L
UPX_CS_L
U
PX_RDY_L
UPX_DATA[31:0]
UPX_ADDR[10:0]
CPU Inter face
32
11
B3379-0
1
Table 28. CPU Interface Signals
Name Direction Standard Description
UP X_AD D[10:0] In put CMO S 2.5 V A ddress bu s
UP X_CS _L Inpu t C M OS 2. 5 V Chip Select Signal
UP X_DATA[31:0] Bi_Di r CMO S 2.5 V Bi-direction al data bus
UP X_WR_L Input CM OS 2. 5 V Write Strobe
UPX_RD_L Input CMOS 2.5 V Read Strobe
UPX_RDY_L Output CMOS 2.5 V Cycle complete indicator
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UPX_CS_L
The chip select input when acti ve Low selects IXF1110 MAC for the cur r ent cycle. No CPU cycle
is recogni ze d without this signal being active. At the end of the cycl e, the c hip sele ct can be driven
High to desel ect t he devi ce or it c an be le ft act ive if t he next acce ss is t o the sam e devic e (as long a s
b o th Read and Writ e control signals are inac tive betwee n cy cles).
The CPU usually suppo rts multiple chip sel ec ts, and glu e logic is required to drive separate chip
selects if more than one IXF1110 MAC is being controlled by one CPU.
UPX_DATA[31:0]
The se pins compris e the 32-bit data bus pins containing data to and from the CP U interface. Thi s
data is asynchronous on the IXF1110 MAC. The W rite data provided by the CPU must be st able
d u ring t he entire CP U cy cle to prevent erroneous Write o p erations to a regist er.
UPX_WR_L
This pin indicates there is data on the CPU dat a bus to be written to the IXF1110 MAC. A Low-to-
High transit ion latches the data and a High-t o-Low trans ition latches the address. This Wri te
o p er ati on is active Low.
UPX_RD_L
This pin indicates there is data on the CPU data bus to be read from th e IXF1110 MAC. A High-to-
Low transition latches the address. This Read oper ati on is active Low.
UPX_RDY_L
This pin indicates the Rea d or Write cycle is complete for the IXF1110 MAC. Thi s operation is
active Low.
Note: Ext ernal pull-up re s is tor required for proper operation.
5.6.2.1 Read Access
The IXF1110 MAC read access cycle operation is done in the following order:
1. C hip Selec t (UPX_CS_L) is asserte d at all time s for the duration of the ope ration. The addre ss
to be read s hould be on the IXF1110 MAC address bus (UPX_ADD[ 10:0]).
2. UPX_RD_L shoul d be ass erted by the CPU. The IXF1110 latches the address.
3. IXF1110 MAC dr ives valid data onto the process or bus (UPX_DATA[31:0]).
4. I XF1 110 MAC ass erts async hrono us-ready ( UPX_R DY_L). This indic ates t o t he CPU tha t t he
Re ad cy cl e is complete.
Figure 24 provides the timing of the asynchronous in terface for Read access.
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
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.
5. 6.2.2 W r i t e A cces s
The IXF1110 MAC Write access cycle operation is done in the following orde r:
1. Chip Select (UPX_CS_L) is asserted at a ll tim es for t he duration of the operation. The add res s
to be read should be on the IXF1110 MAC address bus (UPX_ADD[10:0]).
2. UPX_WR_L shou ld be asserte d by the CPU. The IXF1110 MAC latches the add r es s.
3. T he CPU drives valid data onto the processor bus (UPX_DATA[31:0]).
4. T he CPU de-asserts the asynchronous Write si gnal (UPX_WR_L) of th e IXF1110 MAC. The
IXF1110 MAC latcheses the data.
5. The IXF1110 MAC assertss asynchronous-ready (UP X_RDY_L). T he glue logic indicates to
the CPU that the Write cycle is complete.
Figure 25 provides the timing of the asynchronous int erface for W r ite access .
Figure 24. Read Timing – Asynchrono us Interface
Tcah
UPX_ADD[10:0]
UPX_CS_L
UPX_RD_L Tcrh
Tcas
Tcrr
Tcdrh
Tcdrs
U
PX_DATA[31:0]
UPX_RDY_L
Tcdrh B3381-0
1
Figure 25. Write Timing – Asynchron ou s Inte rface
TCAS TCAH
TCWL
TCDWS
TCDWD
TCYD
TCWH
UPX_ADD[10:0]
UPX_WR_L
UPX_CS_L
U
PX_DATA[31:0]
UPX_RDY_L
TCDWH
B3382-0
1
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5.6.2.3 Timin g par amete r s
Timing parameters for the CPU interface are seen in Table 39, “CPU Timing Parameters” on
page 110.
5.6.3 Endian
The Endian of the CPU interface may be changed to allow conne ction of various CP Us to the
I XF1 110 MAC. The End ian se lecti on is determ in ed by sett ing the Endia n bit in the “C PU Interface
($ 0x508)” on page 151).
5.7 JTAG (Boundary Scan)
The IXF1110 MAC includes an IEEE 1149.1 boundary scan test port for board level testing. All
inputs are accessible. The BSDL file for this device is availabl e by ac ce ssing the intel website
developer.intel.com.
5.7.1 TAP Interface (JTAG)
The IXF1110 MAC includess an IEEE 1149.1 compliant Test Access Port (TAP) interface used
during boundary scan tes ting. The interface cons ists of the following fiv e pins:
•TDI – Serial data input
•TMS – Test mode select
•TCLK – TA P cl o ck
•TRST _L – Active low asynchronous reset for the TAP
•TDO – Serial data output
TDI and TMS require external pull-up resistors to float the pins High per the IEEE 1149.1
spe cific ation . Pull-ups are re commended on TCK and TDO. For norm al ope ration, T RST_L can be
p u lled Low, permanent ly d isab ling the JTAG interface. If the JTAG interface is used, t h e TAP
controller must be reset as desc ribed in Secti on 5.7.2, “TAP S tate Machine” on page 93 and
returned to a logic High.
Note: The JTAG pins m ust be terminated correctly for proper device operation.
Table 29. Recomme nded JTAG Termi nation
Signal Description
TRST_L1Pull-down throug h 10 K Ω resistor
TDO Pull-up through 10 K Ω resistor
1. TRST_L must be pulled Low to ensure pr ope r IXF11 10 MAC operatio n. When TRST_L is Low, the JTAG
interface is disabled. If the boundary scan logic is used, TRST_L must be pulsed Low after power-up to
ensure reset of the TAP controller. For more information, refer to Sect ion 5.7.2, “TAP State Machin e” on
page 93 or the IEEE 1149.1 Boundary Scan Specification.
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5.7.2 TAP State Machine
The TAP pins dr ive a TAP contro ller, which imp lements the 16-state mac hine specified by the
IEEE 1149.1 specification. Following power up, the TAP controller must be reset by one of
following two mechanisms:
•Asynchronous reset – achieved by pulsing or holding TRST_L low
•Synchronous reset – achieved by clocking TCK with five clock pulses while TMS is held or
floats High.
This e nsures that the boundary scan cells do not block the pin to core connections in theIXF1110
MAC.
5.7.3 Instruction Register and Supported Instructions
The i nstruction register is a 4-bit register that enacts the bo undary scan instruc tions. After the st ate
mac hine resets, the default instruct ion is IDCODE. The decode logic in the TAP cont r oller selec ts
the appropriate data register and configures the boundary s can cells for the current in structio n. The
table below shows the supported boundary sc an ins tructions.
5.7.4 ID Register
The ID regis ter is a 32- bit regis ter. The IDCODE instruc tion connect s this register betwe en TDI
and TDO. Refer toTable 87, “JTAG ID Revisi on ($ 0x50C)” on page 153 for registe r bit
descriptions.
TDI Pul l-up thr o ugh 10 K Ω resi stor
TMS Pul l-up t hro ugh 10 K Ω resi stor
TCK Pull-u p thr o ug h 10 K Ω resi stor
Tabl e 29. Reco m mend ed JTAG Term i na tion
Signal Description
1. TRST_L must be pulled Low t o ensure pr oper IXF1110 MAC operati on. When TRST_L is Low, the JTAG
interface is disabled. If the boundary scan logic is used, TRST_L must be pulsed Low after power-up to
ensure reset of the TAP controller. For more information, refer to Section 5.7.2, “TAP State Machine” on
page 93 or the IEEE 1149.1 B ound ary Scan Sp ecification .
Table 30. Supported Boundary Scan Instructions
Instructi on C ode Descr ipti on Data Registe r
EXT EST 0000 External Test Boundary Scan
SAMPLE 0001 Sample Boundary Boundary Scan
HIGHZ 0101 Float Boundary Bypass
IDCODE 0110 ID Code Inspection ID
CLAMP 0111 Clamp Boundary Bypa ss
BYPASS 1111 1-bit Bypass Bypass
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Note: The four bit version field is stepping dependent. The seven bit Manufacturers ID is the
Intel® JE D E C ID le s s the par ity bit per th e I E E E 1149 . 1 s p ecif i c a ti on .
5.7.5 Boundary Scan Register
The boundary sca n regist er is a shi ft regis ter made up of a ll the boun dary scan c ells as sociat ed with
the device pins. The num ber, type, and order of the boundary scan cells are spe cified in the
I XF1110 BSDL file. The EXTEST and SAMPLE instructions connect this regist er between TDI
and TDO.
5.7.6 Bypass Register
The bypas s register is a one bit regis ter that is used so the IXF110 can be bypassed to reduc e the
length of the JTAG chain whe n trying to access other devic es on the chai n bes ides the IXF11 10
MAC. The BYPASS, HIGHZ, and CLAMP instructions connect thi s regis ter between TDI an d
TDO.
5.8 Clocks
The IXF 1110 hash as system interface reference clocks, SPI4-2 data path input and output clocks, a
JTAG input c lo ck, a I2C o utput cl ock, a nd an L ED output clock . Se ction 5 .8 d etail s the unique clock
source requirements.
5.8.1 System Interface Reference Clocks
There are two system inter face clo cks require d b y th e IXF1110 MAC :
5.8.1.1 CLK125
The sys tem interfa ce clock, wh ich suppli es the cloc k to the majority of the i nterna l circuitry, is the
125 MHz clock. The source of this c lock must meet the following specifications :
•2.5 V CMOS drive
•+/- 50 ppm
•Maxim um duty cycle distortion 40/60
5.8.1.2 CLK50
The other system interface clock supplies the clock source to the SPI4-2 receive circuitry. The
source of this clock must meet the following specifica tions:
•2.5 V CMOS drive
•1/8 frequency of the SPI4-2 data pat h clock (RDCLK_P/N)
•Maxim um duty cycle distortion 45/55
•Maxim um peak-to-pea k jitter (low and high frequency) of 125 pS
•Range = 40 Mhz to 50 MHz
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5.8.2 SPI4-2 Receive and Transmit Data Path Clocks
The SPI4-2 data path clocks are compliant with the OIF 2000.88.4 Spec ification.
The IXF1110 has the following requirements on the transmit dat a pat h:
•2.5 V LVDS dri ve
•Maximum duty cycle distortion 45/55
•Maximum peak-to-peak jitter (low and high frequency) of 125 pS
•S table (frequency and leve l) when reset is removed or when sourced, whichever ha ppens last
•TSCLK frequency is one-qua rter TDCLK frequency
The IXF1110 meets the following specifications on the receive data path:
•2.5 V LVDS dri ve
•Maximum duty cycle distortion 45/55
•Maximum peak-to-peak jitter (low and high frequency) of 125 pS
•Stabl e w h en s our c ed
5.8. 3 JTAG Clock
The IXF1110 MAC suppor ts JTAG. The source of this clock must m eet the following
specifications:
•2.5 V CMOS driv e
•Maximum clock frequency 11 MHz
•Maximum duty cycle distortion 40/60
5.8.4 I2C Clock
The IXF1110 device supports a si ngle output I2C clock to support all 10 optical module interfaces.
The IXF1110 meets the following specificati ons for this clock:
•2.5 V CMOS drive
•Maximum clock frequency of 100 kHz
5.8.5 LED Clock
The IXF1110 MAC supportss a serial LED data stream. This interface implements a 2.5 V CMOS
output clock with a maximum frequency of 720 Hz.
The IXF1110 MAC supportss a serial LED data stream. The IXF1110 MAC meetss the following
spe cificati ons for this clock:
•2.5 V CMOS drive
•Maximum frequency of 720 Hz
•Maximum duty cycle distortion: 50/50
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6.0 Applications
6.1 Power Supply Sequencing
Fol low the power-up and power-down sequence describ ed in this sect ion to ensure correct
IX F1110 operation. The sequence covers all IXF1110 MAC digital and analog supplies.
Caution: Fa ilure to follow the power-up and power-down sequences will damage the IXF11 10 MAC.
6.1.1 Power-Up Sequence
Ensure that the 1.8 V supplies (VDD/AVDD1P8_1/AVDD1P8_2) are applied and stable prior to
the application of the 2.5 V supplies (VDD2/AVDD2P5_1/AVDD2P5_2).
Caution: If the 2.5 V supplies (VDD2/AVDD2P5_1/AVDD2P5_2) exceed th e 1.8 V (VDD/AVDD1P8_1/
AVDD1P8_2) s upplies by more than 2.0 V during power -up, the ESD str uctures within the analog
I/Os can be damaged.
6.1.2 Power-Down Sequence
The power-down sequence is the revers e of the power-u p sequence. Remov e the 2.5 V supplies
pr ior to removing the 1.8 V supplies.
Figure 26 and Table 31 provide informati on on power s equencing .
Note: I f the 2. 5 V supplies (VDD2/AVDD2P5_1/AVDD2P5_2) exceed the 1.8 V (VDD/AVDD1P8_1/
AVDD1P8_2) s upplies by more than 2.0 V duri ng power-down, damage can occur to the ESD
structures within th e analog I /Os.
Figu re 26 . Power Sequenc i ng
Time
t=0 Apply VDD, AVDD1P8_1/
1.8 V Supplies Stable
Apply VDD2, AVDD2P5_1/
2.5 V Supplies S table
Apply SYS_RES_L
AVDD1P8_2 AVDD2P5_2
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6.2 Analog Power Fil tering
Figure 32 illustrates an analo g power s upply filter network and Table 32 li st s th e an al o g po w er
balls.
6 .3 TX FI F O an d R X FI FO Op erati o n
The IXF1110 MAC packet buffering is compr ised of indivi dual port FIFOs and s ystem-inte rfac e
FIFOs. Figur e 28 illustrates the interaction of these FIFOs.
Table 31. Power Sequencing
Power Supply Power-Up Order Time Delt a to Next
Supply1Description
VDD, AVDD1P8_1/
AVDD1P8_2 First 0 1.8 V supplies
VDD2, AVDD2P5_1/
AVDD2P5_2 Second 10 μs 2.5 V supplies
1. Th e valu e of 10 μs given is a nominal value only. The ex act time difference be tw een the applic ation of the
2.5 V analog supply will be determined by a number of factors dependent on the power management
m ethod used.
Figure 27. Anal og Pow er Supp ly Filter Networ k
Tab l e 32. An alog P owe r Bal ls
Signal Name Ball Designator Comments
AVDD1P8_1 D1 E24 Need to provide a filter (see Figure 27).
R: AVDD1P8_1 and AVDD2P5_1 = 5.6 Ω resist or.
AVDD2P5_1 Y1
AVDD1P8_2 P7
V14 P18
V18 V6 V11 Need to provide a filter (see Figure 27).
R: AVDD1P8_2 and AVDD2P5_2 = 1.0 Ω resist or.
AVDD2P5_2 N3
V10 N22
V15 P3 P22
0.1 μF
VDD
0.1 μF
Analog
Power Ba
ll
2.5 or 1.8 V R
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6.3.1 TX FIFO
The IXF1110 M AC TX FIFOs are implemented with 4.5 KB for each port. T his provides enough
space for at least one maximum size packet per-port storage and ensures that no under-run
conditions o cc ur, assuming that the sending device can supply data at the required data rate.
Note: The TX FIFO Hi gh and L ow Wate rmark mus t be pr ogra mmed corr ectly to ens ure th at the TX FI FO
does not overflow.
6.3.1.1 MAC Tran sfer T h r esh o ld
The “TX FIFO MAC Transfer Thre s hold Ports 0 to 9 ($ 0x61 4 - 0x61D)” paramet er, whic h is user
programmable, determines when data is transmitted out of the TX FIFO to the MAC. This
parameter is configurable for specific block sizes and the user must ensure that an under-run does
not occur. The threshold must be set to a value tha t exceeds the programmed MaxBurst1 parameter
f rom the Network Proces so r (NPU) or SPI 4-2 ASIC. This method of operation eliminates the
possibility of under-run, except when the controlling NPU device fails.
The MAC trans fer thresh old operates on a per pack et bas is . Once the number of bytes of a packet
r eceived in the TX FIFO exceeds the MAC tr ansf er threshold, it wi ll start to be transmitted to th e
MAC. If the MAC transfer is greater than the packet size, the packet is sent to the MAC once an
EOP is r ec ei v ed .
Figure 28. Packet Buffering FIFO
MDI
High Water Mark Data Flow
MAC Transfer
Threshold *
Low Water Mark
High Water Mark Data Flow
Low Water Mark
RX FIFO High
TxPauseFr (External 802.3x Pause Frame Generation
strobe)
TX FIFO TX Side
MAC
RX FI FO
802.3 Flow
control
RX Side
MAC
SPI4-2 Interface
NOTE: The MAC Transfer Threshold determines when the transmit data is transferred from the TX
FIFO to the TX side of the MAC. Once the data has been sent from the TX FIFO to the MAC, it
will be tr ansmitted to the PHY and cannot be flow controlled from the link p artner .
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The MAC t r ans fer threshold sh ould be set below the Table 94 , “TX FIFO High Wate rmark Ports 0
to 9 ($ 0x600 - 0x6 09)” on page 163. If the MAC transfer t hreshold i s set above the TX FIFO hi gh
watermark, the TX FIFO high watermark will act as th e MAC tra nsfer thres hold. Data is
tr ansmit ted out of the TX FIFO to the MAC when the TX FIFO high waterma r k is reached.
6.3.1 .2 TX FIFO Relation to the SPI4-2 Transmit FIFO Status (TSTAT)
The amount of data in the TX FIFO dictates the FIFO status sent to the NPU on the TSTAT bus.
The fol lowing list s how the FIFO status is determined from the TX FIFO High and Low
Watermarks.
SATISF IED: Th e status gi ven f or a port whe n the amount of da ta in th e per port TX FIFO is great er
than the programmed “TX FIFO High Watermark Port s 0 to 9 ($ 0x600 - 0x609)”.
HUNGRY: The stat us given for a port when the amount of data in the per port TX FIF O is between
the programmed “TX FIFO High Watermark Ports 0 to 9 ($ 0x600 - 0x609)” and the “TX FIFO
Low Watermark Ports 0 to 9 ($ 0x60A - 0x613)”.
STARVING: The status given for a port when the a m ount of data i n the per port TX FIF O is below
the programmed val ue in “TX FIFO Low Wate rmark P orts 0 to 9 ($ 0x60A - 0x613)”.
Note: The user mu st ensure the TX FIFO High and L ow Wate rm arks are programmed correctly to ensure
no underrrun or overflow occur. Failure to do this may result in packet loss.
6.3.1 .3 TX FIFO Drain (IXF1110 Version)
The IXF111 0 can allow the SPI4- 2 NPU or ASI C to dum p data to the IXF11 10 while the link is
down. This allows the NPU or ASIC to empty its FIFOs, if necessary.
The IXF1110 opera tes in the following manner under normal operat ing conditions:
If the IXF1110 detects that the link is down for a given port, the SPI4-2 interface FIFO
sta tus bus indicates SATISFIED. This tel ls the NPU or ASIC th at no da ta can be pas s ed
across the SPI4-2.
The IXF111 0 oper ate s in the fo llowin g th e mann er when th e TX FIFO d r ain is en abled:
The SPI4-2 F IF O status bus indicates STARVING for the give n port. This tells the NPU
or ASIC that it can pass data to the IXF1 110 for that port , regard less of the link statu s, and
all data sent to that port will be dis carded.
Note: The TX FIFO drain is enabled using the Section 98, “TX FIFO Drain ($0x620)”.
6.3.1 .3.1 Enabling the TX FIFO Drain
The TX FIFO drain is enabled using the “TX FIFO Drain ($0x620)”. The fol lowing occurs when
the TX FIFO drain is enabled for a given port:
•The TX FIFO is held in reset
•The FIFO status for that port indicates SATISFIED
•Al l data sent to that po r t is di s car d e d
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6.3.1.3.2 Putting the TX FIFO in Drain Mode
Use the TX FIFO drain when the link is down. The f ollowing is a step-by-step sequence to put a
port(s) into the TX FIFO drain mode:
1. T he system detect s that link is down for a gi ven port using bit s 21:20 of the RX Config Wor d
Register ($Port_Index + 0x16). The SPI4-2 TX FIFO port status is SATISFIED when the link
is d own.
2. Set the appro priate bit to 1 for the given port in the TX FIFO Drain Regi ster ($0x620) onc e
link is down. This incurs the foll owing:
a. Enables the drain mode
b. Causes the TX FIFO for the selected port to enter a reset state
c. Causes th e TX FIFO SPI4-2 FIF O status for that port to change to STARVING.
3. Set the MAC Soft Reset Register bit to 1 for the port(s) that has entered the TX FIFO drain
mode.
4. De-assert the MAC Soft Reset Register. Redo the MAC configurations. If applicable, re-
enable auto -negotiation for the selected port(s) by setting bit 5 of the Diverse Config Regist er
ba ck to 1.
5. T he conne cted SPI4-2 NPU or ASIC can now dump data to the port(s) that has entered the
dr ain mode. All data sent to the port( s) selecte d is disc arde d and not recorde d in an y r egister in
the IXF1110.
6. Monitor the RX Config Word Regis ter to reestablis h link with the link partner. Exit the TX
FIFO drain mode when the sys tem software detects link establis hm ent.
6.3.1.3.3 Exiting the TX FIFO Dra in Mode
To exit the TX FIFO drain mode.
1. Set the TX FIFO Drain Registe r bits back to 0. This exits the TX FI FO drain mode and the
TX FIFO status bus now indicates the actual TX FIFO status.
2. T he IXF1110 is read y to resum e normal data trans mi ssion.
6.3.2 RX FIFO
The IXF1110 M AC RX FIFOs are provisioned so that each port has its own 17.0 KB memory
spa ce . T his is enough memo ry to ensure agai nst an over -run on any port while transferring normal
Eth erne t fra me-s ize data.
The RX FIFOs are configured by defaul t to automatically generate Paus e control frames to i nitiate
the f o llo w in g :
•Halt the link partner when the RX FIFO High Wa termark is reached
•Restart the link partner when the data stored in the RXFIFO falls below the Low Watermark.
Pause control fr ame generation is enabled by default in the “FC Ena ble ( $ Port_Index + 0x12)”.
Section 8.5.5, “Global RX Block Register Overview” on pa ge 154 documents the registers needed
t o set the RX FIF O watermar ks.
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Note: Users s hould ensure that flow cont rol is enabled to preve nt RX F IF O overflows. If an RX FIFO
overfl ow occurs, da ta is s ent out on the SPI 4-2 inte rface regardl ess of t he “ RX FI FO E rr o r e d F r a m e
Drop Enable ($ 0x59F)” settings. The data is mark ed with an EOP abort code to inf o r m th e
upstream devic e that this data is corrupted.
6.4 Reset and Initialization
When pow ering up the IXF1110 MAC, the hardware reset signal (SYS_RES_L) should be held
act ive Low for a minimum of 100 ns after a ll of the power rails have fully sta bilized to their
nominal values and the input clocks have rea ched their nomina l frequency (TDCL K = 400 MHz,
CLK125 = 125 MHz, and CLK50 = 50 MHz).
Note: In systems where the SYS_RE S _L pin is driven from a sing le board-wide reset signal , the swi tch
or network processor only comes out of reset at the sa me tim e as the I XF1110 MAC, or possibl y
later. This means the TDCLK may not be applied to theIXF1110 MAC when the SYS_RES_L pin
is re lea sed. However, the system designer must ensure that the switch or network processor does
not output TDCLK unti l it is stable and has reached it s nomin al operating fr equency. Failure to
apply a stable TDCLK to the IXF1110 MAC can result in the IXF1110 MAC training on a non-
stable clock thu s c ausing DIP4 errors and data corruption. Th is will require a re-training once the
TDCLK is stable.
Wh e n th e TD CLK is ap p li ed af ter th e re set pin is re leased , a bu i lt - in fe atu r e in th e I X F1110 MAC
reacti vates the in ternal r eset once TDCLK is applied. The IXF1110 MAC extends th is hard ware
res et int ernall y to ensure s ynchroni zati on of all int ernal blocks within t he system. The in ter nal rese t
is extend e d f o r a mi n im um of 4. 11 ms aft er al l clo ck s are s t ab l e.
The device is corr ec tly initialized at thi s point and ready for use. Clocks start to appear at the
rele vant de vice por ts and the SPI4-2 int erf ace begin s to s ource a tra ini ng patte rn on the recei ve si de
while waitin g for a trai nin g patte rn o n the t ransmit s ide. The SPI4-2 i nt erface s ynchroni zes with the
connected switc h or network processor per the SPI4-2 Specificati on.
The CPU accesses can begin to configure the device for any existing user pre f erences desired.By
default, all ports on the IXF1110 MAC are enab led after power-up. The device is ready for use at
this time if the defau lt s ettings are t o be us ed. Otherwis e, access t he required registers via the CPU
interface and configure the contro l registers to the required settings.
6.4.1 SPI4-2 Initialization
6. 4.1.1 RX SP I 4- 2
After reset or Power-up the RX SPI4-2 interface will start to source training patterns on the dat a
bus to the upstream SPI4-2 device. The IXF1110 MAC will continue to send the tra ining patterns
until a valid calendar is sent on RSTAT[1:0] from the upstream device to the IXF1110 MAC. At
th is point, synchronizati on with the upstream device is comple te and the IXF1110 MAC will start
to send data once data is available and a credit has been granted from the RSTAT [1:0] bus.
When synchronization is comple ted, bit 13 of the “SPI4-2 RX Calendar ($ 0x702)” is “1”. Before
completion, bit 13 is “0”, indicating the IXF1110 MAC is sending out training patterns on the RX
SPI4-2 data bus.
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6.4.1.2 TX SP I 4-2
After rese t or power -up, the T X SPI4-2 i nte rface out puts a c onstant framin g pa ttern on TSTAT unti l
it rec eives the proper SPI4-2 training pattern f rom th e ups tream SPI4-2 device. For more
inform ation on the re quired training pattern, see “Dynamic Pha se Alignment Training S equence
(D ata Path De-skew)” on page 66.
Note: I f TDCL K is ap plied to the IXF1110 MAC after the devic e has come out of res et, the syst em
des igner must ensure the TDCLK is stable when applied. Failure to due so can resul t in the
I XF11 10 MAC training on a non-stable clo ck, causing DIP4 errors and data corr uption.
Once the val id training pattern is received and the IXF1 110 MAC outputs a 10-port calendar on
TSAT, bit 12 of the “SP I4-2 RX Calendar ($ 0x702)” on page 174 will be set. This indicates that
synchro nization on the TX SPI4- 2 is com plete.
Ports will show a SATISFIED status on the SPI4-2 TSTAT bus until a valid link is established for
that port. To determi ne if a valid link is e stablished, see “Fiber Operation” on page 51.
6.4.1.3 SerDes
After res et or powe r-up the SerDes interface will start to output idles on the TX_P/N for forc ed
mode operat ion. If Auto- Negot iati on mode is re quire d bit 5 of the “Diverse C onfig ($ Port_Index +
0x18)” on page 138 must be se t. A link is es tablished when the RX Se r D es has received the
appropriate code words from the link partner. Refer to “Fiber Operation” on page 51 for more
information.
6.4.1.4 CPU
The CPU int erface is ready for operation after power-up or reset. Through thi s inte rface, the user
can confi gure the de vice for any desired setting from the defa ults. (Refer to “ C PU I nter f a ce” on
page 88 for more information.)
6.5 SerDes Power-Down Capa bilities
The IXF1110 has the ability to power down the TX and RX SerDes individually on each port (s ee
Section 5.3, “ SerDes Interfac e” on page 71). Us e the foll owing seque nce to cor rectl y power up and
power down the SerDes ports.
Note: The se sequence s must be followed to ensure a port corre ctly ope rates when broug ht out of a power-
down mode:
6.5.1 Placing the SerDes Port in Power-Down Mode
1. Disable the port(s ) by de-asser ting the appropri ate bit(s) in the “Port Enable ($ 0x500)”
2. Power-down “S erDes TX and RX Power-Down Ports 0-9 ($ 0x787)”
3. T he SerDes port is now powered down and the TSAT S tatus for the port is S ATISFIED
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6.5.2 Bringing the Ser Des Port Out of Power-Down Mode
1. Power up TX and RX SerDes
2. E nable the port (s) by de-asserting the approp riate bit(s) in the “Port Enable ($ 0x500)”
3. Enable auto-negotiation (if applicable). The device defaults to forced mode if it is not enabled.
4. Onc e a valid l ink is est ablis hed, t he TSTAT status bu s for that p ort c hanges fro m SATISFED to
STARVING.
6.6 IXF1110 MAC Unused Ports
Intel reco mmen ds the fol lowing be used to dis able an unused port. The SPI4-2 TSTAT status bus
will al ways reflect sta tus for ten ports regardless of the number of IXF11 10 MAC unused ports.
Any port whic h is di sabl ed wil l have a cons tant stat us of SATISFIED. RSTAT must also be input to
reflect the status of all ten ports rega rdless of how many are disabled.
1. Disable ports by se tting the ap propriate bits in the “Port Enable ($ 0x500)”.
2. Power down SerDes for the unused port by settin g the appropriate bits in the “SerDes TX and
RX Power-Down Ports 0-9 ($ 0x787)”
3. TX SerDes pairs can be left unconnected.
4. RX SerDes pairs should be connected to ground
6.7 Optical Module Conne ctions to the IXF1110 MA C
6.7.1 SFP-to-IXF1110 Connection
The IXF1110 SerDes and Optical Modul e interfaces allow system designers to connect the
IXF111 0 to various optica l transceive rs. When using Small Form Factor Pluggable (SFP) optical
tr ans ceivers to co nnect to the IXF1110, all SerDes and Optical Module status pins are used. Us e
Figure 29, “SFP-to-IXF1110 Connection” and T a ble 33, “SFP-to-IXF1 110 Connection” to connect
an SFP to the IXF1110.
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Figure 29. SFP-to-IXF1110 Con nection
Tab le 33. SFP-to-IXF1110 Conne ction (Sheet 1 of 2)
SFP
Pin # SFP Pin
Name IXF1110 Pin # 0:9 IXF1110 Pi n Nam e Descri pt ion
1 V eeT NA NA Connect to ground.
2TxFault
M2 4, V2 3, Y17 , R15 ,
W14, W11, W9,
AC5, P8, L2 TX_FAULT_[0:9] Use an extern al 4.7 kΩ pull-up resistor to
3.3 V.
3 TxDisable K22, M2 2, AC22,
U18, U 14, AA 18,
U9, AA9, V7, L4 TX_DISABLE_[0:9] SFP module has internal pull-up.
4MOD_DEF
(2) G22, G 23, J24, F22,
E23 , H24, G20, E22,
G24, F24 I2C_DATA_[0:9] Use an extern al 4.7 k Ω pull-up resistor to
3.3 V.
5MOD_DEF
(1) L19 I2C_CLK Use an external 4.7 kΩ pull-up resistor to
3.3 V.
6MOD_DEF
(0)
N24, Y2 1, AA16,
M20, AC14, U1 1, T4,
AB2, R7, L1 MOD_DEF_[0:9] U se an external 4.7 kΩ pull-up resistor to
3.3 V.
7 Rate Select NA NA Leave floating.
8LOS
L22, V17, AD18,
R12, AB15, V12, Y9,
AC3, T2, P2 RX_LOS_[0:9] Us e an external 4.7 kΩ pull-up resistor to
3.3 V.
9 VeeR NA NA Connect to ground.
10 VeeR NA NA Connect to gr oun d.
11 V eeR NA NA Connect to ground.
TX_FAULT
TX_DISABLE
TX+
TX-
RX+
RX-
I2C_DATA
I2C_CLK
MOD_DEF
RX_LOS
TXFault
TXDisable
TD+
TD-
RD-
RD+
MOD_DEF(0)
LOS
MOD_DEF(2)
MOD_DEF(1)
Rate_Select
VeeR 14
VccR 15
VeeR 9
VeeR 11
VeeR 10
VccT 16
VeeT 1
VeeT 17
VeeT 20
4.7 kΩ
IXF1110 SFP
VDD 3.3 V
VDD 3.3 V
TX_FAULT_Int
RX_LOS_Int
MOD_DEF_Int
E xternal C PU
2
4
5
6
3
8
18
19
12
13
7
4.7 kΩ
VDD 3.3 V
4.7 kΩ4.7 kΩ4.7 kΩ4.7 kΩ
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§ §
12 RD- U22, U20, T24, V24,
AB14, AD14, AC16,
AD15, V4, Y5 RX_N_[0:9] The IXF1110 has a 100 Ω differential
termination on the chip that requir es it to
be AC-coupled. AC-coupling is done
insi de the SFP mod ule an d is not requi red
on the host board.
13 RD+ T22, T2 0, U2 4, W24,
AB13, AD13, AB16,
AD16, V5, Y6 RX_P_[0:9]
14 VeeR N A NA Connect to gr ound .
15 VccR NA NA Connect to filtered 3.3 V.
16 VccT NA NA Connect to filtered 3.3 V.
17 Ve eT NA NA Connect to ground.
18 TD+ V20, Y19, V22, Y23,
AB12, AD12, AB9,
AD9, T3, T5 TX_P_[0:9] These pins are the differential transmitter
inputs. They are AC-coupled differential
lines with 100 Ω differential termination
insid e the SFP module. The AC -coupl ing
is done inside the SFP module and is no t
required on the host board.
19 TD- V21, Y20, W22,
Y22, AB11, AD11,
AC9, AD10, U3, U5 TX_N_[0:9]
20 Ve eT NA NA Connect to ground.
N/A N/A B11 TX_FAULT_Int Connect to Interrupt Service Routine.
Use an ex ternal 4.7 kΩ pull-up resistor to
3.3 V.
N/A N/A B14 RX_LOS_Int Connect to Interrupt Service Routine.
Use an ex ternal 4.7 kΩ pull-up resistor to
3.3 V.
N/A N/A G15 MOD_DEF_Int Connect to Interrupt Service Routine.
Use an ex ternal 4.7 kΩ pull-up resistor to
3.3 V.
Table 33. S FP-to-IXF1110 Connection (Sheet 2 of 2)
SFP
Pin # SFP Pin
Name IXF1110 Pi n # 0:9 IX F11 10 Pin Name Descripti on
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7.0 Electrical Specifications
Table 34 th rough Table 49 on page 122 and Figure 30 on pa ge 110 through Figure 41 on page 122
r epr esent the target sp ecifi catio ns of th e f ollowing IXF1110 MAC inter f aces:
•“CPU Timing Specification”
•“JTAG Timing Specification”
•“Transmit Paus e Control T iming Specifications”
•“Optical Module Interrupt and I2C Timing Specificati on”
•“S ystem Timing Spe cifications”
•“LED Timing Specifications”
•“SerDes Timing Specification”
•“SPI4-2 Timing Specifications”
Note: These specifications are not guaranteed and a re subject to change without notice. Minimum and
maximum values listed in Table 36 through Table 49 on page 122 apply over the r ecommended
op erating conditions specifi ed in Table 34.
Tab le 34. Absolute Maximum Rating s
Parameter Symbol Min Max Units
Supply Voltage
VDD -0.3 2.4 Volts
AVDD1P8_1/
AVDD1P8_2 -0.3 2.4 Volts
VDD2 -0.3 3.0 Volts
AVDD2P5_1/
AVDD2P5_2 -0.3 3.0 Volts
Operat ing Temperature Ambient TOPA -15 +85 oC
Case TOPC – +130 oC
Storage Te m pe r atu r e TST -65 +125 oC
Caution: Exce eding these values may cause pe rma nent damage. Fun ctional ope ration
under these conditions is not im plied. Exposure to maxim um ra ting conditions
for extended perio ds may affect devi ce reliabili ty.
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Table 35. Operating Conditions
Parameter Symbol Min Typ1Max Units
Recommended Supply Voltage
VDD,
AVDD1P8_1,
AVDD1P8_2 1.71 1.80 1.89 Volts
VDD2,
AVDD2P5_1,
AVDD2P5_2 2.375 2.50 2.625 Volts
Operating Current 1000BASE-SX
IDD and
AIDD1P8_1,
AIDD1P8_2 –2.312.75Amps
I DD 2 an d
AIDD2P5_1,
AIDD2P5_2 – 0.310 0.42 Amps
Recommended
Operating Temperat ure2
Ambient TOPA 0 – 70 oC
Case with Heat Sink TOPC-HS 0 – 119 oC
Case with out Heat
Sink TOPC-NHS 0 – 118 oC
Recommended St orage Temperature TOST -65 – 40 oC
Power Consumption
1000BASE-SX full-
duplex all ports
enabled and passing
data
P – 4.9 6.3 Watts
1000BASE-SX full-
duplex six ports
enabled and passing
data
P – 4.5 5.2 Watts
1. Ty pi cal valu es ar e at 25 oC and are for design aid only; not guaranteed and not subject to production
testing.
2. Refer to the Intel® IXF1110 Thermal Design Guidelines (document number 250289).
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7.1 DC Specifications
Table 36. 2.5 V LVTTL and CMOS I/O Electrical Characteri stics
Parameter Symbol Min Typ1Ma x Units Test Co nditions
Input Low Voltage VIL – – 0.70 V VCC = MIN
Input High Voltage2VIH 1.7–3.6VVCC = MIN
Ou tput Lo w Volt a ge VOL – – 0.40 V VCC = MIN, IOL = 3.9 mA
Output High Voltage VOH 2.0 – – V VCC = MIN, IOH = -2.9 mA
Ou t p ut Leak age
Current IOZ ––10μA VCC = MAX
1. Typi cal values a re at 25 oC and are for design ai d only; not guaranteed and not subje ct to production
testing.
2. 3.3 V CM OS to lerant.
Table 37. LVDS I/O Electrical Characteristics
Parameter Symbol Min Typ1Max Units Test Conditions
Input Voltage Range VI -0.20 – VddMax+
0.20 V–
Differential Input
Voltage |V I D| 100 – – mV @ 400 MH z
Input Common-Mode
Current ICM – – – μA LVDS Input VOS = 1.2 V
Threshold Hysteresis TH 25 – – mV –
Differential Input
Impedance RIN 85 100 115 ΩTy pica l 100 Ω
Out put Low Voltage VOL 0.95 – – V –
Output High Voltage VOH ––1.51V –
Differential Output
Voltage |VOD| 330 – 446 mV –
De lta Diffe r en tia l
Out put Voltage
(Complementary
States)
Δ|VOD| – – 25 mV –
Offset (Comm on-
Mode) Voltage VOS 1.12 – 1.30 V –
Out put Leakage
Current IOZ – – 10 μA–
1. T ypical valu es are at 25 oC and are for d esign aid on ly; not guaranteed and n ot subject to production
testing.
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7.2 Undershoot/Overshoot Sp ec ifications
The overshoot figure s given in this sectio n represent the maximum voltage that can be applied
without affecting the r eliability of the device (see Table 38).
Caution: Exce eding thes e values will damage the device.
Table 38. Undershoot/Overshoot Limit s
Ball Type Undershoot Overshoot
2.5 V CMOS -0.60 V 3.9 V
2.5 V LVT TL -0.60 V 3.9 V
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7.3 CPU Timing Specification
Figu re 30. C P U Po rt R ead Tim i ng
Figu re 31. CPU Po rt Writ e Timin g
Table 39. CPU Timing Parameters (Sheet 1 of 2)
Parameter Symbol Min Typ1Max Units Test
Conditions
UPX_ADD[12:0 ], UPX_CS_L Setup
Time TCAS 10 – – ns –
UPX_ADD[12:0], UPX_CS_L Hold Ti me TCAH 10 – – ns –
UPX_RDY_L Assertion to UPX_RD_L
De-assertion TCRR 10 – – ns –
1. Typi cal values a re at 25 oC and are for design ai d only; not guaranteed and not subje ct to production
testing.
TCAS TCAH
TCRR
TCDRS
TCDRH
TCDRD
TCRH
uPx_Add[10:0]
uPx_Rd
uPx_Cs
uPx_Data[31:0]
uPx_Rdy
TCAS TCAH
TCWL
TCDWS
TCDWD
TCYD
TCWH
uPx_Add[10:0]
uPx_Wr
uPx_Cs
uPx_Data[31:0]
uPx_Rdy
TCDWH
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UPX_RD_L High Width TCRH 24
(3x cycle ) ––ns –
UPX_DA T A[31:0] to UPX_RDY_L Setup
Time TCDRS 10 – – ns –
UPX_DATA[31:0] to UPX_RD_L Hold
Time TCDRH 8 – 32 ns –
Read UPX_DATA[31:0] Dr iving Delay TCDRD 24 – 355 ns –
UPX_WR_L Width TCWL 40 – – ns –
UPX_RDY_L to UPX_WR_L Hold Time TCWH 16 – – ns –
UPX_DATA[31:0] to UPX_WR_L Setup
Time TCDWS 10 – – ns –
UPX_RDY_L to UPX_DATA[31:0] Hold
Time TCDWH 10 – – ns –
UP X_DATA[3 1:0] Latching Delay TCDWD 8 – 40 ns –
UPX_RDY_L Width in Write Cycle TCYD 24 – 40 ns –
Read UP X_RDY_L de-assertion to
UPX_WR_L Assertion TRTW 32 – – ns –
Writ e UPX _R DY_L de-a sserti on to
UPX_RD_L Assertion TWTR 32 – – ns –
Ta bl e 3 9. CPU Timin g P ara m et ers (She et 2 of 2)
Parameter Symbol Min Typ1Max Units Test
Conditions
1. Ty pi cal valu es ar e at 25 oC and are for design aid only; not guaranteed and not subject to production
testing.
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7.4 JTAG Timing Specification
Figu re 32 . JTAG Timi ng
Table 40. JTAG Timi ng Par ameters
Parameter Symbol Min Typ1Max Units Test Conditions
TC LK Cyc le Ti me TJC 90 – – ns –
TC LK Hig h Ti me TJH 0.4 x TJC – 0.6 x TJC ns –
TC LK Lo w Tim e TJL 0. 4 x TJC – 0.6 x TJC ns –
TCLK Falling Edge to
TD O Va li d TJVAL ––25ns –
TMS/ TDI Setup to
TCLK TJSU 20 – – ns –
TMS/ TD I Hol d from
TCLK TJSH 5––ns –
1. T ypical valu es are at 25 oC and are for d esign aid on ly; not guaranteed and n ot subject to production
testing.
TDO
TMS,
TDI
TCLK
Tjval
Tjl
Tjh
Tjc
Tjsu
Tjsh
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7.5 Trans mit Pause Con trol Timing Spec ificatio ns
Figure 33. Transmit Pause Control Interface
Table 41. Transmit Pause Control Interface Parameters
Parameter Symbol Min Typ1Max Units Test Conditions
TXP AUSEFR Width TPW 16 – – ns –
TXPAUSEADDR[3:0]
Setup to TXPAUSEFR TSU 16 – – ns –
TXPAUSEADDR[3:0]
Hold from
TXPAUSEFR THD 32 – – ns –
TXPAUSEFR Pulse to
Pulse TBTP 48 – – ns –
1. Typical values are at 25 oC a nd are for de sign aid on ly; not guaranteed and not subje ct to production
testing.
TxPauseFr
TxPauseAddr[3:0]
Tbtp
Tpw
Tsu Thd
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7.6 Optical Module Interrupt and I2C Timing Specification
Figu re 34. Op t ic a l M odu le Interrupt Timing
Ta b le 42. Optical Module Interrupt Timing Parameters
Parameter Symbol Min Typ1Max Units Test Conditions
Change of state on MOD_DEF_9:0
or TX_FAUL T_9:0 or RX_LOS_9:0
to assertion (active Low) on
MOD_DEF_Int or TX_FAULT_Int
or R X_LO S_Int
TDI 24 – – ns –
1. T ypical valu es are at 25 oC and are for d esign aid on ly; not guaranteed and n ot subject to production
testing.
MOD_DEF_9:0
TX_FAULT_9:0
RX_LOS_9:0
MOD_DEF_Int
TX_FAULT_Int
RX_LOS_Int
Tdi
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Figure 35. I2C Bu s Timing
Figure 36. I2C Write Cycle
Table 43. I2C AC Timing Chara cteristics (Sheet 1 of 2)
Parameter Symbol Min Typ1Max U ni ts Te st C ond i ti o ns
Clo ck Frequency, SCL fSCL ––100kHz –
Cl oc k Pu ls e Widt h Low tLOW 4.7 – μs–
Cl oc k Pu ls e Widt h H ig h t HIGH 4.0 – μs–
Noi s e Suppr ession tI––100ns –
Clock Low to Data Valid Out tAA 0.1 – 4.5 μs–
Time bus must be free before a
new t ransmiss ion starts tBUF 4.7 – – μs–
Start Hold Time tHD.STA 4.0 – – μs–
Start Setup Time tSU.STA 4.7 – – μs–
Data In Hol d Time tHD.DAT 0––μs–
Data In Set up time tSU.DAT 200 – – ns –
Inputs Rise T ime tR––1.0μs–
1. Typical values are at 25 oC a nd are for de sign aid on ly; not guaranteed and not subje ct to production
testing.
I2C_CLK
I2C_ DATA Ou t
tDH
tHD.STA
tAA tBUF
tSU.STA
tHIGH tR
tSU.STO
tSU.DAT
tHD.DAT
tLOW
tF
I2C_DATA In
tLOW
ACK
8th
BIT
WORD n
I2C_CLK
I2C_DATA
STOP
CONDITION START
CONDITION
tWR(1)
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Inpu ts Fa ll Time tF––300ns –
Stop Setup Time tSU.STO 4.7 – – μs–
Data Out Hold Time t DH 100 – – ns –
Write Cycle Time tWR ––10ms –
Table 43. I2C AC Timing Characteristics (Sheet 2 of 2)
Parameter Symbol Min Typ1Max Units Test Conditions
1. T ypical valu es are at 25 oC and are for d esign aid on ly; not guaranteed and n ot subject to production
testing.
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
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7.7 System Timing Specifications
Figure 37. Hardw are Reset Timing
Table 44. Hardware Reset Timing Parameters
Parameter Symbol Min Typ1Max Units Test Conditions
Re s et Puls e Wi dth TRW 100 – – ns –
Reset Recovery Time TRT 4.11 – – ms –
1. Typical values are at 25 oC a nd are for de sign aid on ly; not guaranteed and not subje ct to production
testing.
Trw
Trt
Sys_Res
_______
CPU
Access
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7.8 LED Timing Specifications
Figu re 38 . L ED Timi ng
Table 45. LED Timing P arameter s
Parameter Symbol Min Typ1Max Units Test Conditions2
LED_CLK Cycle T ime TCYC 1.36 – 1.40 ms –
LED_CLK High Time THI 680 – 700 μs 50% duty cycle
LED _CLK Low Time TLOW 680 – 700 μs 50% duty cycle
LED_CLK Falling
Edge to LED_DATA
Valid TDATD 2–5ns –
LED_CLK Rising
Edge to LED_LATCH
Falling Edge THATL 690 –700 μs–
LED_CLK Falling
Edge to LED_LATCH
Rising Edge TLATH 690 –700 μs–
1. T ypical valu es are at 25 oC and are for d esign aid on ly; not guaranteed and n ot subject to production
testing.
2. Fla sh Rate = 100 m s, LED M ode 1.
LED_CLK
LED_DATA
L
ED_LATCH
Tcyc
Tlow
Thi
Tdatd
Tha
tl
Tlath
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7.9 SerDes Timing Specification
Table 46 specifies the transmit electrical specifications based on a rec ommended 1.8 V
AVDD1P8_1 an d AVDD1P8_2 te rminati on vo ltage and th e requi red 50 Ω term inati on a nd Table 46
specifies the receiver electrical specifications based on a recommended 1.8 V AVDD1P8_1 and
AVDD1P8_2 termination voltage. Figure 39 illustra tes the timing requi r ements for the IXF1110
transm it and recei ve SerDes signals.
Note: It is essential that both posit ive and negative drive leve ls at the receiver input m aintain a minimum
voltage of 0.8 V relative to ground to hel p ensure proper circ uit operation.
Figure 39. SerDes Timing
Table 46. Transmitter Characteristics (Sheet 1 of 2)
Parameter Symbol
Normalized
Power
Driver
Setting
Min Typ1Max Units Test Condit ions
T ransmit differential
signal level TV
0.50 180 230 325
mVpp
diff
AVDD1 P8_1 and
AVDD1P8_2
terminated to
1.8 V;
RLOAD = 50 Ω;
1.00 350 440 700
1.33 425 580 900
2.00 600 770 1050
T ra nsmitter
Co mmon Mode
Volt ag e R an ge –
0.50 1300 1600 1940
mV –
1.00 1000 1400 1870
1.33 800 1300 1825
2.00 700 1100 1760
Transmit Eye Width TT1.00 800 – – pS –
1. Ty pi cal valu es ar e at 25 oC and are for design aid only; not guaranteed and not subject to production
testing.
NOTE: Ref er to Table 21, “SerDes Driver TX Power Levels” on page 72 for valid SerDes power levels.
Tt
Rt
Rv Tv
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Differenti al signal
rise/fall time –1.006096132pS
RLOAD = 50 Ω;
20% to 80% m ax
Differential Output
Impedance – 60 100 150 Ω diff DC
Tran sm i t t er short
circu it current –-100–100mA–
Transmitter
Frequency –1.2498
75 1.25 1.25012
5GHz Reference
Oscillator
125 MHz +/-
100 ppm
Total Transmitter
output jitter – 122 pS p-p T otal Jitter at BER
1E-12
Table 47. Receiver Characteristic s
Parameter Symbol Min Typ1Max Units Test Conditions
Receiver differential
voltage requirement at
center of receive-eye RV200 – – mVp-p diff –
Receiver common mode
voltage range 900 1275 1650 mV –
Receive Eye Width RT280 – – pS –
Receiver termination
impedance –40 –62.5
Ω–
Signal detect level – 125 – 400 mVp-p diff –
Total Receiver jitter
tolerance – – – 600 pS p-p Total Jitter at BER
1E-12
1. Typi cal values a re at 25 oC and are for design ai d only; not guaranteed and not subje ct to production
testing.
Table 46. Transm itter Characteristi cs (Sheet 2 of 2)
Parameter Symbol
Normalized
Power
Driver
Setting
Min Typ1Max Units T est Conditions
1. Typi cal values a re at 25 oC and are for design ai d only; not guaranteed and not subje ct to production
testing.
NOTE: Refer to Table 21, “Se rDes Driver TX Power Levels ” on page 72 for valid SerDes power levels.
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
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7.10 SPI4-2 Timing Specifications
Figure 40. S P I4-2 Tr ansmi t FIFO Status Bus Timing
Table 48. SPI4-2 Transm i t FIFO Statu s Bus Timing Parameter s
Parameter Symbol Min Typ1Max Units Test Conditions
TSCLK Falling Edge to
TSTAT[1:0] Valid
(Active edge flipped to falling) TD1– –280pS –
TSCLK Rising Edge to
TSTAT[1:0] Valid
(De fault op eration) TD2– –280pS –
1. Typical values are at 25 oC a nd are for de sign aid on ly; not guaranteed and not subje ct to production
testing.
TSCLK
TSTAT[1:0]
TSTAT[1:0]
Td2
Td1
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122 Order N umber: 25 0210 , Revision: 009
§ §
Figure 41. SPI4-2 Receive FIFO Status Bus Tim ing
Table 49. SPI4-2 Receive FIFO Status Bus Timing Parameters
Parameter Symbol Min Typ1Max Units Test Conditions
RSTAT[1:0] Setup to RSCLK
Rising Edge
(D efault operation) TSU12 – – ns –
RSTAT[1:0] Hold From RSCLK
Rising Edge
(D efault operation) TH10.5 – – ns –
RSTAT[1:0] Setup to RSCLK
Falling Edge
(When active edge flipped to
falling)
TSU22 – – ns –
RSTAT[1:0] Hold From RSCLK
Falling Edge
(When active edge flipped to
falling)
TH20.5 – – ns –
1. T ypical valu es are at 25 oC and are for d esign aid on ly; not guaranteed and n ot subject to production
testing.
Tab le 50. SPI4-2 LV DS Rise/Fall Times
Parameter Symbol Min Typ Max Units Test Conditions
Ris e/Fall at
source RTsrc – – 0.2 ns 400 Mh z operation – measured using
conditions set forth in ANSI/TIA/EIA-
644-A-2001
Ris e/Fall at
sink RTsnk – – 0.4 ns 400 Mhz op erati on – measur ed usi ng
conditions set forth in ANSI/TIA/EIA-
644-A-2001
RSCLK
RSTAT[1:0]
RSTAT[1:0]
Tsu1
Th1 Th2
Tsu2
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
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Intel® IXF1110 10-Port 1000 M bps Ether net Me dia Access Contr oller
Order Number: 250210, Revision: 009 123
8.0 Register Definitions
8.1 Introduction
This section provides information on the location and functionality of the IXF1110 MAC Control
and S tatus Re gisters .
8.2 Document Struc ture
This document is structured to give a general overview of the register map and an in-depth
description of each bit of a register in later sections.
8.3 Graphical Representation
Figure 42 repr esen ts an overvie w o f th e IXF1110 MAC Global Con t r ol Status Registers that ar e
used to configure or report on all ports.
Caution: Do not write to any reserved register unless specified. Writing to a reserved register address may
cause impro per de vice operation.
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Figure 42. Mem or y Overview
Global Configuration
-RX Block Configuration
-T X Bloc k Configuraiton
Port 9 MAC Control & Statistics
Port 8 MAC Control & Statistics
Port 7 MAC Control & Statistics
Port 6 MAC Control & Statistics
Port 5 MAC Control & Statistics
Port 0 MAC Control & Statistics
Port 1 MAC Control & Statistics
Port2 MAC Control & Statistics
Port 3 MAC Control & Statistics
Port 4 MAC Control & Statistics
0x7FF
0x000
0x180
0x100
0x080
0x200
0x280
0x300
0x380
0x400
0x480
0x500
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
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Intel® IXF1110 10-Port 1000 M bps Ether net Me dia Access Contr oller
Order Number: 250210, Revision: 009 125
8.4 Per Port Registers
The following section covers all of the registers that are replicated in each of the 10 ports in the
IXF11 10 MAC. These registers perform an identical function in each port.
The address vector for the IXF1110 MAC is 11 bits w ide. This allows for 7 bits of port-specific
acc ess and a 4-bit vector to address each port and all gl obal registers. The a ddress format is shown
in Figure 43.
8 .5 M em or y Ma p
Table 51 through Table 59 on page 132 provide theIXF1110 MAC memory maps . A numb er of
global control and stat us registers are us ed to co nfigure or report on al l ports, and some re gisters
are replicated on a per-port basis.
Note: All registers in the IXF1110MAC are 32 bits.
Figure 43. Regi ster Over view
Port Select & Global Registers Per-Port Registers
10 0
6
Table 51. M AC Control Reg ister Map (Sheet 1 of 2)
Register Bit Size Mode1Ref
Page Offset
MAC Control Registers (Port Index + Offset)
“Station Addr ess Low ($ Port_Index + 0x0 0)” 32 R/W 133 0x00
“S tation Address High ($ Port_Index + 0x01)” 32 R/W 133 0x01
Reserved 32 RO – 0x02
“FDF C Typ e ($ Por t_Index + 0x03 )” 32 R/W 133 0x03
Reserved 32 R – 0x04
Reserved 32 RO – 0x05
Reserved 32 RO – 0X06
“FC TX Timer Value ($ Port_Index + 0x07)” 32 R/W 133 0x07
“FDFC A ddress Low ($ Port_ Index + 0x 08)” 32 R/W 134 0x08
“FDFC Address High ($ Port_Index + 0x09)” 32 R/W 134 0x09
Reserved 32 R – 0x0A
Reserved 32 R – Ox0B
“IPG Transmit Ti me ($ Port_Index + 0x0C)” 32 R/W 134 0x0C
Reserved 32 R/W -- 0x0D
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
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“Pause Threshold ($ Port_Index + 0x0E)” 32 R/W 135 0x0E
“Max Frame Size ($ Por t_Index + 0x0F)” 32 R/W 135 0x0F
Reserved 32 RO – 0x10
Reserved 32 RO – 0x11
“FC Enable ($ Port_Index + 0x12)” 32 R/W 136 0x12
Reserved 32 RO – 0x13-
0x14
“Discard Unknown Control Frame ($ Port_Index + 0x15)” 32 R/W 136 0x15
“RX Config Word ($ Port_Index + 0x16)” 32 R/W 136 0x16
“TX Config Word ($ Port_Index + 0x17)” 32 R/W 137 0x17
“Div erse Config ($ Port_Index + 0x 18)” 32 R/W 138 0x18
“RX Packet Filter Control ($ Port_Index + 0x19)” 32 R/W 139 0x19
“Port Multicast Address Low ($ Port_Index + 0x1A)” 32 R/W 140 0x1A
“ Por t Mu ltic as t Add r es s Hig h ($ P ort_I n de x + 0x1B)” 32 R/W 140 0x1B
Table 52. MAC RX St atisti cs Register Map (Sheet 1 of 2)
Register Bit Size Mode1Ref
Page Offset
MAC RX St a tistics Registers (Port Index + Offset)
RXOctetsTotalOK 32 CoR 141 0x20
RXOctetsBAD 32 CoR 141 0x21
RXUCPckts 32 CoR 141 0x22
RXMCPkts 32 CoR 141 0x23
RXBCPkts 32 CoR 141 0x24
RXPkts64Octets 32 CoR 141 0x25
RXPkts65to127Octets 32 CoR 141 0x26
RXPkts128to255Octets 32 CoR 141 0x27
RXPkts256to511Octets 32 CoR 141 0x28
RXPkts512to1023Octets 32 CoR 141 0x29
RXPkts1024to1518Octets 32 CoR 141 0x2A
RXPkts1519toMaxOctets 32 CoR 141 0x2B
RXFCSErrors 32 CoR 141 0x2C
RXTagged 32 CoR 141 0x2D
RXDataError 32 CoR 141 0x2E
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
Tab le 51. MAC Control Register Map (Sheet 2 of 2)
Register Bit Size Mode1Ref
Page Offset
MAC Control Registers (Port Index + Offset)
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
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RXAlignErrors 32 CoR 141 0x2F
RXLongErrors 32 CoR 141 0x30
RXJabberErrors 32 CoR 141 0x31
RXPauseMacControlCounter 32 CoR 141 0x32
RXUnknownMacControlFrameCounter 32 CoR 141 0x33
RXVeryLongErrors 32 CoR 141 0x34
RXRuntErrors 32 CoR 141 0x35
RXShortErrors 32 CoR 141 0x36
RXCarrierExtendError 32 CoR 141 0x37
RXSequenceErrors 32 CoR 141 0x38
RXSymbolErrors 32 CoR 141 0x39
Table 53. M AC TX Statistics Register Map (Sheet 1 of 2)
Register Bit Size Mode1Ref
Page Offset
MAC TX Statistics Registers (Port Index + Offset)
TXOctetsTotalOK 32 CoR 145 0x40
TXOctetsBad 32 CoR 145 0x41
TXUCPkts 32 CoR 145 0x42
TXMCPkts 32 CoR 145 0x43
TXBCPkts 32 CoR 145 0x44
TXPkts64Octets 32 CoR 145 0x45
TXPkts65to127Octets 32 CoR 145 0x46
TXPkts128to255Octets 32 CoR 145 0x47
TXPkts256to511Octets 32 CoR 145 0x48
TXPkts512to1023Octets 32 CoR 145 0x49
TXPkts1024to1518Octets 32 CoR 145 0x4A
TXPkts1519toMaxOctets 32 CoR 145 0x4B
TXDeferred 32 CoR 145 0x4C
TXTotalCollisions 32 CoR 145 0x4D
TXSingleCollisions 32 CoR 145 0x4E
TXMultipleCollisions 32 CoR 145 0x4F
TXLateCollisions 32 CoR 145 0x50
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
Table 52. M AC RX Statistics Register Map (Sheet 2 of 2)
Register Bit Size Mode1Ref
Page Offset
MAC RX St atistics Registers (Port Index + Offset)
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
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TXExcessiveCollisionErrors 32 CoR 145 0x51
TXExcessiveDeferralErrors 32 CoR 145 0x52
TXExcessiveLengthDrop 32 CoR 145 0x53
TXUnderrun 32 CoR 145 0x54
TXTagged 32 CoR 145 0x55
TXCRCError 32 CoR 145 0x56
TXPauseFrames 32 CoR 145 0x57
TXFlowControlCollisionsSend 32 CoR 145 0x58
Table 54. Global Status and Configuration Register Map
Register Bit Size Mode1Ref
Page Address
Globa l Status and Conf igur a t io n Re gis t e r s
“ Por t E na b l e ($ 0x 500) ” 32 R/W 149 0x500
Reserved 32 R – 0x501
“Link LED Enable ($ 0x502)” 32 R/W 150 0x502
Reserved 32 RO – 0x503
“Core Cloc k Soft Reset ($ 0x504)” 32 R/W 150 0x504
“ MAC Soft Res et ($ 0x505)” 32 R/W 151 0x505
Reserved 32 RO – 0x506
Reserved 32 R – 0x507
“CPU Interface ($ 0x508)” 32 R/W 151 0x508
“LED Contr ol ($ 0x509) ” 32 R/W 152 0x509
“LED Flash Rat e ($ 0x 50A)” 32 R/W 152 0x50A
“LED Fault Disable ( $ 0x50B)” 32 R/W 152 0x50B
“JTAG ID Revision ($ 0x50C)” 32 R/W 153 0x50C
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
Tab le 53. MAC TX Statistics Register Map (Sheet 2 o f 2)
Register Bit Size Mode1Ref
Page Offset
MAC TX Statistics Registers (Port Index + Offset)
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
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Table 55. RX Block Register Map
Register Bit Size Mode1Ref
Page Address
RX Block Registers
RX FIFO High Watermark Port 0 3 2 R/W 154 0x580
RX FIFO High Watermark Port 1 3 2 R/W 154 0x581
RX FIFO High Watermark Port 2 3 2 R/W 154 0x582
RX FIFO High Watermark Port 3 3 2 R/W 154 0x583
RX FIFO High Watermark Port 4 3 2 R/W 154 0x584
RX FIFO High Watermark Port 5 3 2 R/W 154 0x585
RX FIFO High Watermark Port 6 3 2 R/W 154 0x586
RX FIFO High Watermark Port 7 3 2 R/W 154 0x587
RX FIFO High Watermark Port 8 3 2 R/W 154 0x588
RX FIFO High Watermark Port 9 3 2 R/W 154 0x589
RX FIFO Low Watermark Port 0 32 R/W 155 0x58A
RX FIFO Low Watermark Port 1 32 R/W 155 0x58B
RX FIFO Low Watermark Port 2 32 R/W 155 0x58C
RX FIFO Low Watermark Port 3 32 R/W 155 0x58D
RX FIFO Low Watermark Port 4 32 R/W 155 0x58E
RX FIFO Low Watermark Port 5 32 R/W 155 0x58F
RX FIFO Low Watermark Port 6 32 R/W 155 0x590
RX FIFO Low Watermark Port 7 32 R/W 155 0x591
RX FIFO Low Watermark Port 8 32 R/W 155 0x592
RX FIFO Low Watermark Port 9 32 R/W 155 0x593
RX FIFO Number of Frames Remove d on Port 0 32 CoR 157 0x594
RX FIFO Number of Frames Remove d on Port 1 32 CoR 157 0x595
RX FIFO Number of Frames Remove d on Port 2 32 CoR 157 0x596
RX FIFO Number of Frames Remove d on Port 3 32 CoR 157 0x597
RX FIFO Number of Frames Remove d on Port 4 32 CoR 157 0x598
RX FIFO Number of Frames Remove d on Port 5 32 CoR 157 0x599
RX FIFO Number of Frames Remove d on Port 6 32 CoR 157 0x59A
RXFIFO Number of Frames Removed on Port 7 32 CoR 157 0x59B
RX FIFO Number of Frames Remove d on Port 8 32 CoR 157 0x59C
RX FIFO Number of Frames Remove d on Port 9 32 CoR 157 0x59D
“RX FIFO Port Reset ($ 0x59E)” 32 R/W 159 0x59E
“RX FIFO Errored Frame Drop Enable ($ 0x59F)” 32 R/W 160 0x59F
“R X FIFO Overflow Event ($ 0x5A0)” 32 CoR 161 0x5A0
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
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Table 56. TX Block Register Map (Sheet 1 of 2)
Register Bit Size Mode1Ref
Page Address
TX FIFO High Watermark Port 0 32 R/W 163 0x600
TX FIFO High Watermark Port 1 32 R/W 163 0x601
TX FIFO High Watermark Port 2 32 R/W 163 0x602
TX FIFO High Watermark Port 3 32 R/W 163 0x603
TX FIFO High Watermark Port 4 32 R/W 163 0x604
TX FIFO High Watermark Port 5 32 R/W 163 0x605
TX FIFO High Watermark Port 6 32 R/W 163 0x606
TX FIFO High Watermark Port 7 32 R/W 163 0x607
TX FIFO High Watermark Port 8 32 R/W 163 0x608
TX FIFO High Watermark Port 9 32 R/W 163 0x609
TX FIFO Low Watermark Port 0 32 R/W 163 0x60A
TX FIFO Low Watermark Port 1 32 R/W 164 0x60B
TX FIFO Low Watermark Port 2 32 R/W 164 0x60C
TX FIFO Low Watermark Port 3 32 R/W 164 0x60D
TX FIFO Low Watermark Port 4 32 R/W 164 0x60E
TX FIFO Low Watermark Port 5 32 R/W 164 0x60F
TX FIFO Low Watermark Port 6 32 R/W 164 0x610
TX FIFO Low Watermark Port 7 32 R/W 164 0x611
TX FIFO Low Watermark Port 8 32 R/W 164 0x612
TX FIFO Low Watermark Port 9 32 R/W 164 0x613
TX FIFO MAC Tra nsfer Threshold Port 0 32 R/W 166 0x614
TX FIFO MAC Tra nsfer Threshold Port 1 32 R/W 166 0x615
TX FIFO MAC Tra nsfer Threshold Port 2 32 R/W 166 0x616
TX FIFO MAC Tra nsfer Threshold Port 3 32 R/W 166 0x617
TX FIFO MAC Tra nsfer Threshold Port 4 32 R/W 166 0x618
TX FIFO MAC Tra nsfer Threshold Port 5 32 R/W 166 0x619
TX FIFO MAC Tra nsfer Threshold Port 6 32 R/W 166 0x61A
TX FIFO MAC Tra nsfer Threshold Port 7 32 R/W 166 0x61B
TX FIFO MAC Tra nsfer Threshold Port 8 32 R/W 166 0x61C
TX FIFO MAC Tra nsfer Threshold Port 9 32 R/W 166 0x61D
“TX FIFO Overflow Event ($ 0x61E)” 32 CoR 168 0x61E
Reserved 32 R – 0x61F
“TX FIFO D rain ($0x620)” 32 R/W 169 0x620
“TX FIFO In fo Out -of- Sequence ($ 0x62 1)” 32 CoR 170 0x621
TX FIFO Number of Frames Removed on Port 0 32 CoR 171 0x622
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
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TX FIFO Num ber of Frames Remo ved on Port 1 32 CoR 171 0x623
TX FIFO Num ber of Frames Remo ved on Port 2 32 CoR 171 0x624
TX FIFO Num ber of Frames Remo ved on Port 3 32 CoR 171 0x625
TX FIFO Num ber of Frames Remo ved on Port 4 32 CoR 171 0x626
TX FIFO Num ber of Frames Remo ved on Port 5 32 CoR 171 0x627
TX FIFO Num ber of Frames Remo ved on Port 6 32 CoR 171 0x628
TX FIFO Num ber of Frames Remo ved on Port 7 32 CoR 171 0x629
TX FIFO Num ber of Frames Remo ved on Port 8 32 CoR 171 0x62A
TX FIFO Num ber of Frames Remo ved on Port 9 32 CoR 171 0x62B
Table 57. S PI4-2 Block Register M ap
Register Bit Size Mode1Ref
Page Address
“S PI4- 2 RX Bu rst Size ($ 0x700 )” 32 R/W 173 0x700
“S PI4-2 RX Trai ning ($ 0x 701 )” 32 R/W 173 0x701
“SPI4-2 RX Calendar ($ 0x702)” 32 R/W 174 0x702
“SPI 4-2 TX Synch ronization ($ 0x703)” 32 R/W 175 0x703
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
Table 58. S erDes Bl ock Register Map
Register Bit
Size Mode1Ref
Page Address
Reserved 32 RO – 0x781
Reserved 32 RO – 0x782
Reserved 32 RO – 0x783
“SerDes Tx Driver Power Level Ports 0-6 ($ 0x784)” 32 RO – 0x784
“SerDes Tx Driver Power Level Ports 7-9 ($ 0x785)” 32 RO – 0x785
Reserved 32 RO – 0x786
“SerDes TX and RX Power-Down Ports 0-9 ($ 0x787)” 32 R/W 176 0x787
Reserved 32 RO – 0x793
Reserved 32 RO – 0x794
Reserved 32 RO – 0x795
Reserved 32 RO – 0x796
Reserved 32 RO – 0x797
Reserved 32 RO – 0x798
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
Table 56. TX Block Register M ap (Sheet 2 of 2)
Register Bit Size Mode1Ref
Page Address
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
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Table 59. Optical Module Interface Block Reg ister Map
Register Bit Size Mode1Ref
Page Address
“Optical Modul e Status Ports 0-9 ($ 0x799 )” 32 R 177 0x799
“Optical Modul e Control Port s 0-9 ($ 0x79A) ” 32 R/W 177 0x79A
“I2C Contr ol Ports 0-9 ($ 0x7 9B)” 32 R/W 178 0x79B
“I2C Data Ports 0-9 ($ 0x79C)” 32 R/W 178 0x79C
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
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8.5.1 MAC Control Registers
Table 60 through Table 76 on p age 140 prov ide de tai ls on the co ntrol a nd sta tus re gist ers a ssocia ted
with ea ch MAC port. The register address is ‘Port_index + 0x**’, where the port inde x is set at
any value from 0x000 through 0x500. All registers ar e 32 bits.
Table 60. Stati on Address Low ($ Port_Index + 0x00)
Bit Name Description Type1Default
31:0 S tation
Address L ow
Sou r c e MA C addr e s s bits 31-0.
This address is inserted in the source address field
when transmitt ing Pause fr ames, and is also use d to
c om pa re against unicast Pause fr ames at th e
receiving side.
R/W 0x00000000
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
Table 61. Station Address High ($ Port_Index + 0x01)
Bit Name Description Type1Default
31:16 Reserved Reserved R 0x0000
15:0 S tation
Addr ess High
Sou r c e MA C addr e s s bits 47-32.
This address is inserted in the source address field
when transmitt ing Pause fr ames, and is also use d to
c om pa re against unicast Pause fr ames at th e
receiving side.
R/W 0x0000
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
Tabl e 62. FDF C Type ($ Port_Ind ex + 0x03)
Bit Name Description Type1Default
31:16 Reserved Reserved R 0x0000
15 :0 FDFC Ty pe
Contains the value of the type field transmitted in an
internally generated fl ow control (pause) frame.
Internally generated flow control frames are
generated via the external pause interface or when
the RX FIFO exceeds its hi gh watermark.
R/W 0x8808
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
Table 63 . FC TX Timer Value ($ Port_ Index + 0x07)
Bit Name Description Type1Default
31:16 Reserved Reserved R 0x0000
15:0 FC TX Timer
Value The pause length sent to the receiving station in 512
bit times R/W 0x005E
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
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Table 64. FDFC Address Low ($ Port_Index + 0x08)
Bit Name Description Type1Default
31:0 FDFC Address
Low
Contains the value of the low est 32 bits of the
destination add ress field tran sm itted in an internally
generated flow control (pause) frame. Internally
generated flow co ntrol fr ames are gener ated via the
exter n al paus e int erface or when t he RX FIFO
e x ce eds it high water m a r k.
R/W 0xC2000001
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
Table 65. FDFC Address High ($ Port_Index + 0x09)
Bit Name Description Type1Default
31:16 Reserved Reserved R 0x0000
15:0 FDFC Address
High
Contains the value of the highe st 16 bits of th e
destination add ress filed transmitted in an internally
generated flow control (pause) frame. Internally
generated flow co ntrol fr ames are gener ated via the
exter n al paus e int erface or when t he RX FIFO
e x ce eds it high water m a r k.
R/W 0x0180
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
Table 66. IPG Tran smi t Time ($ Port_Index + 0x0C)
Bit Name Description Type1Default
31:10 Reserved Reserved R 0x0000
9:0 IPG Transmit
Time
IPG t ime for ba ck-to -back tran smissions (specifie d in
multiples of 8 b it ti m es) .
The value specified in this register is calculated as
follows: (register value + 4) *8 = IPG length in terms
of bit times. Therefore, the default value of 8 gives:
(8+4) *8 = 96 bit times.
96 bi t t imes is th e m in im um IP G. If a v alu e of 8 o r le ss
is written to this register , the IPG remains 96 bit
times.
R/W 0x0008
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
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Table 67. Pause Threshold ($ Port_Index + 0x0E)
Bit Name Description Type1Default
31:16 Reserved Reserved R 0x0000
15:0 Pause
Threshold
Whe n a p a use fra me i s se nt, an int ern al time r chec ks
when a new pa use frame must be scheduled for
transmission to keep the link partner in pause mode.
The p ause t hreshold valu e is the m inim um tim e to
send before the earlier pause frame is aged out
(specified in multiples of 512 bit times).
Note: T he valu e i n thi s reg i ster i s subt rac te d fr om the
valu e in the “FC TX T i mer Value ($ Port_Index +
0x07)” to set the internal pause threshold. This value
determin es how often a Pause fr ame i s sent out to
keep the link partner in pause mode.
R/W 0x002F
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
Tabl e 68. M ax Frame Size ($ Port_I nde x + 0x0F)
Bit Name Description Type1Default
31:14 Reserved Reserved R 0x0000
13:0 Max Frame
Size
The maximum frame size the MAC can receive or
tr ansmi t without activating any er ror counters, and
withou t trunc ati on.
The maximum frame size is internally adjusted by +4
if VLAN is tagged.
R/W 0x05EE
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
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Table 69. FC Enable ($ Port_Index + 0x12)
Bit Name Description Type1Default
Register Description : Indicates which flow control mode is used for the RX and TX MAC. 0x00000007
31:2 Reserved Reserved R 0x00000000
1 TX FDFC
0 = Disable TX full-duplex flow control [th e M AC
wil l not gene rate internally any flow control
fr am es based on the RX FIFO watermarks or
the Transmit Pause Control interface
1 = Enable TX full-duplex flow co ntrol [enables
the MAC to send flow control frames to the
l ink par tn er ba sed on th e RX FIF O
progra m m able watermarks or the Transmit
Pause Control interface]
R/W 1
0RX FDFC
0 = Disable RX full-duplex flow control [the MAC
will not respond to flow control frames sent to
it by the lin k partner]
1 = Enable RX full-duplex flow control [M AC will
res pond to f low cont rol fra mes sen t by the li nk
partner and will stop packet transmission for
the time specified in the flow control frame]
R/W 1
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 70. Discard Unknown Con trol Frame ($ Port_Index + 0x15)
Bit Name Description Type1Default
31:1 Reserved Reserved R 0x00000000
0Discard Unknown
Control Frame 0 = Keep un known contr ol fra m es
1 = Discard unknown control frames. R/W 0
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
Table 71. RX Config Word ($ Port_Index + 0x16) (Sheet 1 of 2)
Bit Name Description Type1Default
Register Description : This register is used in t he IXF1110 only for auto- nego tiation. Register
bits 15:0 are the “config_word” received from the link partner, as described in IEEE 802.3, Sub
clause 37.2.1. 0x00000000
31:22 Reserved RO 0
21 An_complete
Auto-negotiation complete. This bit remains cleared
from the time auto-negotiation is reset until auto-
negotiation reaches the “LINK_OK” state. It remains
set until auto-negotiation is disabled or restarted.
(This bit is only valid if au to-negotiation is ena bled .)
R0
20 RX Syn c 0 = Loss of synchroni zation
1 = Bit synchronization (b it remains Low until regist er
is read) CoR 0
19 RX Config 0 = Receiving idle/data stream
1 = R ecei ving /C / ordere d sets R
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 137
18 Config Chang ed 0 = RxConfigWord has changed since last read
1 = R xConfigW ord has not changed since last read
(Th is bit r emai ns High unti l register is read) CoR 0
17 Invalid Word 0 = Have not received an inva lid sy m bol
1 = Have received an inv alid symbol
(This bit remains High until r egister is read) CoR 0
16 Carrier Sens e 0 = Devic e is not receiving idle c haracters (carrier
sense is true).
1 = Device is receiving idle ch aracters (carrie r s ense
is false) .
R0
15 Next Page Next Page request R 0
14 Reserved Reserved R 0
13:12 RemoteFault[1:0]
Remote Fault Definitions:
00 =No e rr or, lin k okay
01 =Offli ne
10 =Link failure
11 =Auto-negotiation_ Erro r
R00
11:9 Reserved Reserved R 000
8 Asym Pause Asym Pause (ability to send pause frames) R 0
7 Sym Pause Sym Pause (ability to send and receive paus e frames) R 0
6 Hal f D upl ex Half-duplex R 0
5 Full Duplex Full-duplex R 0
4:0 Reserved Reserved R 00000
Tabl e 72. TX Con fig Word ($ Port_Index + 0x17) (Sheet 1 of 2)
Bit Name Description Type1Default
Register Description: This register is us ed in the I XF111 0 for auto- negotiation onl y. The
contents of this register are sent as the config_word. 0x000001A0
31:16 Reserved Reserved R 0x0000
15 NextP age Next Page request R/ W 0
14 Reserved3Write as 0, ignore on Read R/W 0
13:122Remote Fault
[1:0]
Remo te fault defi nitio ns :
00 = No error, link okay
01 =Offline
10 =Link failure
11 = A ut o- n eg otiat io n_ E rr o r
R/W 00
11:9 Reserved3Write as 0, ignore on Read R/W 000
8 Asym Pause Ability to send pause frames R/W 1
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. There is no way to automatically update the state of the Remote Fault bits for transmission. The state of
these bits m ust be set by the system control ler th rough the uP interface prior to enab ling auto-negotiation.
3. Reserved bits must be written to ‘0’ to prevent illegal advertisement.
Table 71. RX Config Word ($ Port_Index + 0x16) (Sheet 2 of 2 )
Bit Name Description Type1Default
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
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7 Sym Paus e Ability to s end an d receive pause fram es R/W 1
6 Half Dup lex Half-duplex R/W 0
5 Full Duplex Full-duplex R/W 1
4:0 Reserved3Write as 0, ignore on R ead R/W 00000
Table 73. Diverse Config ($ Port_Index + 0x18)
Bit Name Description Type1Default
Register Description : This register contains various configuration bits for general use. 0x0000110D
31:19 Reserved Reserved R 0x0000
18:13 Reserved Write as 0, ignore on Read R/W 000000
12 Reserved2Write as 1, ignore on Read R/W 1
11:9 Reserved2Write as 0, ignore on Read R/W 000
8 Reserved2Write as 1, ignore on Read R/W 1
7 pad_enable Enable padding of undersized packets R/W 0
6 crc_add Enable automatic CRC appending R/W 0
5 AN_enable
Auto-negotiation enab le:
1 = Setting this bit to 1 puts the port in an
auto-negotiation mode a nd st arts auto-
negotiation.
0 = Setting this bit to 0 disables auto-
negotiati on an d puts the IXF 1110 in
forced mode.
Note: Since default = 0, this bit must be
change d to a 1 via the C PU to enable auto-
negotiat io n. A ut o- n egotiat io n ca n be
restarted by de-asserting this bit, then re-
asserting.
R/W 0
42Reserved Write as 0, ignore on Read R/W 0
3:22Reserved Write as 1, ignore on Read R/W 11
12Reserved Write as 0, ignore on Read R/W 0
02Reserved Write as 1, ignore on Read R/W 1
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
2. Reserved bits m ust be written to t he default value for prop er oper ation
Table 72. TX Config Wo rd ($ Port_Ind ex + 0x17) (Sheet 2 of 2)
Bit Name Description Type1Default
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
2. There is no way to automatically update the state of the Remote Fault bits for transmission. The state of
these bits must be set by the system co ntroller through the uP i nterf ace prior to enabling auto- nego tiation.
3. Reserved bits m ust be written to ‘ 0’ to pr event ill egal adverti sement.
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 139
Table 74. RX Packet Filter Control ($ Port_Index + 0x19) (Sheet 1 of 2)
Bit Name Description Type1Default
Register Description: This register allows for specific packet types to be marked for filtering,
and is used in conjunction with the RX FIFO Errored Frames Drop Enable Register 0x00000000
31:6 Reserved Reserved R 0x000000
5 CRC Error Pass 2
This b it enable s a G lob al filter on frames wit h a CR C
Error.
When CRCErrorPASS = 0, all frames with a CRC
Er ror are mar ked as ba d.
NOTE: When used in conjunction with the RX FIFO
ErroredFrameDropEnable[9:0] Register (see T a ble 92
on page 160). T his allows the fr ame t o be droppe d in
the RX FIFO. Otherwise, the fram e is se nt ac ross the
SPI4-2 interface but marked as an EOP Abort frame.
When the CRC Error Pass Filter bit = 0, it takes
preceden ce over the other fi lter bits. Any packet
regardless if it is a Pause, Unicast, Multicast or
Broadcast packet with a CRC error will be marked as
bad frames when CRC Error Pass = 0
When CRCErrorPASS = 1, frames with a CRC Error
are not m arked as ba d and are passed to the SPI4-2
interface for transfer as good fr ames, regard less o f
the state of the F rame Drop En[9:0] bi ts .
R/W 0
4Pause Frame
Pass
This b it enable s a G lob al filter o n Pause frames.
When PauseFramePass = 0, all Pause frames are
marked as bad.
NOTE: When used in conjunction with the RX FIFO
ErroredFrameDropEnable[9:0] Register (see T a ble 92
on page 160). T his allows the fr ame t o be droppe d in
the RX FIFO. Otherwise, the fram e is se nt ac ross the
SPI4-2 interface but marked as an EOP Abort frame.
NOTE: When PauseFramePass = 1, all Pause
frames are not m arked as ba d and are
passed to the SPI4-2 interface for transfer as
good frames, regardless of the state of the
FrameDropEn[9:0 ] bits.
R/W 0
3 VLAN Drop En2
This b it enable s a G lob al filter on VLAN frames.
When VLANDropEn = 0, all VLAN frames are passed
to the SPI4-2 Interface.
When VLANDropEn = 1, all VLAN frames are
dropped.3
R/W 0
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. Jumbo frames (1519 - 9600 bytes), matching the filter conditions, which would cause the frame to be
dropped b y th e RX F IFO, will not be dropped. Instead, jumb o frames that are marked to be dropped by the
RX FIFO, based on the filter setting in this register, will still be sent across the SPI4-2 interface, but will be
marked as an EOP abort frame. Thus, jumbo frames matching the filter conditions will not be counted in the
RX FIFO Number of Frames Removed Register because they are not removed by the RX FIFO. Only
standard packet sizes (64 - 1518 bytes) meeting the filter conditions set in this register will actually be
dropped by the RX FIFO and counted in the RX FIFO Number of Frames Removed.
3. Frames are dropped only when the appropriate bits are set in the RX FIFO Errored Frame Drop Enable
Regist er (Table 92 on page 160). Whe n the appropriate bi ts a re not set, the frames are sent across the
SPI4-2 interface and marked as EOP abort frames.
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07-Oct-2005 Datasheet
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2 B/Cast Drop En2
This bit enabl es a Global filt er on Br oadcast frames.
W he n B/ Cast Dr op E n = 0, all br oa dc as t fr am e s ar e
passed to the SPI4-2 Interface.
W he n B/ Cast Dr op E n = 1, all br oa dc as t fr am e s ar e
dropped.3
R/W 0
1 M/Cast Ma tch En 2
This bit enables a filter on multicast frames. If this bit =
0, al l mu lt ica st fram es a r e good and are p as se d to the
SPI4-2 Interface.
If this bit = 1, only multicast frames with a destination
address that matches the PortMulticastAddress is
forwarded . All ot her multicast frames are dropped.3
R/W 0
0 U/Cast Match En2
This bit enables a filter on unicast frames.
If t his bi t = 0, all unic ast fr ames are good and are
pa ssed to th e SPI4-2 inter fac e.
If this bit = 1, only unicast frames with a destination
address that matches the Station Addre ss is
forwarded . All ot her unicast frames are dropped.3
NOTE: The VLAN filter overrides the Unicast filter.
Thus , a VL AN fr am e ca nnot be fi lt ere d ba se d
on the Unicast address .
R/W 0
Table 75. Port Multicast Address Lo w ($ Port_Index + 0x1A)
Bit Name Description Type1Default
31:0 Po rt Multicast
Address Low
This address is us ed to c ompa re agains t
multicast frames at the receiving side if multicast
filtering is enabled.
This register contains bits 31:0 of the address.
R/W 0x00000000
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
Tab le 76. Port Multicast Address High ($ Port_Index + 0x1B)
Bit Name Description Type1Default
31:16 Reserved Reserved R 0x0000
15:0 Po rt Multicast
Address High
This address is us ed to c ompa re agains t
multicast frames at the receiving side if Multicast
filtering is enabled.
This register contains bits 47:32 of the address.
R/W 0x0000
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
Table 74. RX Packet Filter Co ntro l ($ Port_Index + 0x19) (Sheet 2 of 2)
Bit Name Description Type1Default
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
2. Jumbo fr ames (1519 - 9600 bytes), matching the filter cond itions, which would cause the frame to be
dropped by the RX FIFO, will not be dropped. Instead, jumbo frames that are marked to be dropped by the
RX FIFO, based on the filter setting in this register, will still be sent across the SPI4-2 interface, but will be
mark ed as an EOP a bo rt f ra me. T hus, ju mb o fr ame s m at chin g t he fil ter co ndit i ons wi ll no t be count e d in t h e
RX F IFO Numbe r of Frames Removed Register becaus e they are not removed by the RX FIFO. Only
st an da r d pac k et si ze s (64 - 1518 bytes ) mee ting t he filter co nd itions se t in this r eg is t e r wil l ac tually be
dropped by the RX FIFO and counted in the RX FIFO Numb er of Fr ames Removed .
3. Frames are dropped only when the appropriate bits are set in the RX FIFO Errored Fram e Drop Enab le
Re gister (Table 92 on page 160). When the appr opriat e bits are not set, the fram es are sen t across the
SPI 4-2 interface and marked as EOP abort fr ames.
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 141
8.5.2 MAC RX Statistics Register Overview
The MAC RX Statistics Registers contain the MAC receiver statistic counters and are cleared when
read. The software polls these registers and accumulates values to ensure that the counters do not
wrap. The 32-bit counte rs wrap aft er approximate ly 30 seconds.
Table 77 cove r s the MAC RX S tat istics Registers for all 10 MAC por ts. Th e addre ss is identical to
the port numbe r.
Table 77. MAC RX St ati stics ($ Port_Index + 0x20 - Port_Index + 0x39) (Sheet 1 of 4)
Name Description Address Type1Default
RxOctetsTotalOK Counts the bytes received in all legal frames,
includ ing a ll bytes from the des tination MAC
address to and including the CRC. The initial
preamble an d SFD b ytes are not counted.
Port_Index
+ 0x 20 CoR 0x00000000
RxOctetsBAD2
Counts the bytes received in all bad frames of a
size greater than or equal to 64 bytes. A bad
frame is defined as a properly framed packet
containing a CRC, alignment error, or code
violation. T he 64-byte value is measured from
the des tination address, up to and in cluding
CRC. The initial preamble and SFD are not
included in this value.
Note: This register does not incr ement th e Bad
Oct et count on under size d r eceive pa ckets.
Port_Index
+ 0x 21 CoR 0x00000000
RxUCPkts
Th e tota l nu mb er of un ic ast packe t s rec eiv ed
(excluding bad packets)
Note: Thi s coun t incl udes non-p aus e control and
VLAN p ackets, which are also counted in other
coun te rs. Th ese p ack et type s are cou nt ed tw ice.
Take care when summing register counts for
reporting MIB information.
Port_Index
+ 0x 22 CoR 0x00000000
RxMCPkts
The total numbe r of multicast packets received
(excluding bad packets)
Note: Thi s count inclu des pa use co ntrol pa ckets ,
which are also counted in the PauseMacControl-
ReceivedCounter. These packet types are
coun te d twic e. Take c are w hen su mmi ng re gist er
counts for reporting MIB information.
Port_Index
+ 0x 23 CoR 0x00000000
RxBCPkts The total num ber of B roadcast pack ets received
(excluding bad packets) Port_Index
+ 0x 24 CoR 0x00000000
RxPkts64Octets The total number of packets received (including
bad packets) that were 64 octets in length.
Incremented for tagged packets with a length of
64 bytes, including tag field
Port_Index
+ 0x 25 CoR 0x00000000
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. When sending in large frames, the counters can only deal with certain limits. The behavior of the
LongErrors and VeryLongErrors counters is as follows: VeryLongErrors counts frames that are
2*MaxFra m eS ize, depe nden t on where the MaxFr am eS ize varia bl e is set. If M axF rame Siz e sets greate r
than half of the availa ble co unt in RxOctet sBad (2^14-1) , VeryLongErrors is nev er incremented, but
LongErrors is incremented. This is due to a limitation in the counter size, which means that an accurate
c ount will n ot occur in the RxOctetsBAD co unter if the f rame is larger t han 2^ 14-1. MaxFrameSize is
deter mi ned by the setti ngs in the “Max Frame Size ($ Port _Index + 0x0F)” on page 135.
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
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142 Order N umber: 25 0210 , Revision: 009
RxPkts65to127
Octets
The total numbe r of packets received (including
bad packets) that were [65-127] octets in length.
Incremented for tagged packets with a length of
65 - 127 bytes, includ ing tag field
Port_Index
+ 0x26 CoR 0x00000000
RxPkts128to255
Octets
The total numbe r of packets received (including
bad packets) that were [128-255] octets in
length. Incremented for tagged packets with a
length of 128-255 bytes, including tag field
Port_Index
+ 0x27 CoR 0x00000000
RxPkts256to511
Octets
The total numbe r of packets received (including
bad pack et s) th at w ere [2 56 - 5 11] oc tets i n
length. Incremented for tagged packets with a
length of 256 - 511 bytes, including tag field
Port_Index
+ 0x28 CoR 0x00000000
RxPkts512to1023
Octets
The total numbe r of packets received (including
bad pack et s) th at w ere [5 12 - 1 02 3] oc te ts in
length. Incremented for tagged packets with a
length of 512 - 1023 bytes, including tag field
Port_Index
+ 0x29 CoR 0x00000000
RxPkts1024to1518
Octets
The total numbe r of packets received (including
bad packets) that were [1024-1518] octets in
length. Incremented for tagged packet with a
length between 1024-1522, including the tag
Port_Index
+ 0x 2A CoR 0x00000000
RxPkts1519toMax
Octets
The total numbe r of packets received (including
bad packets) that were >1518 octets in length.
Incremented for tagged packet with a length
between 1523-max frame size, includin g the tag
Port_Index
+ 0x 2B CoR 0x00000000
RxFCSErrors
Num b er of fr am e s r ec ei ved wit h legal size, but
with wrong CRC field (also called FCS field)
Note: Legal size is 64 bytes through the v alue
st ored in th e “Max Frame Size ($ Port_Index +
0x0F)” on page 135.
Port_Index
+ 0x 2C CoR 0x00000000
RxTagged Num b er of frames with VLAN tag
(Type field = 0x8100) Port_Index
+ 0x 2D CoR 0x00000000
RxDataError
Num b er of fr am e s rec eived wit h legal length,
c ontaining a co de vio lation (signaled with
RX_ERR on RGMII)
NOTE: The IXF1 1 10 does not support an RGMII
interface; thus, this counter is not
applicable to the IXF1110.
Port_Index
+ 0x 2E CoR 0x00000000
RxAlignErrors
NOTE: Numb er of fr am e s w ith a lega l f ram e
s ize, but containing less than 8
additio na l bits. This oc c ur s wh en a
frame is not byte-aligned. The CRC of
the frame is wrong when the additional
bit s are stripped. If the CRC is OK, the
frame is not coun ted, but tr eated as an
OK frame.The IXF1110 does not
s upport an RGMII inter fac e; thus, this
c ounter is not applicable to the IXF1110
Port_Index
+ 0x 2F CoR 0x00000000
Table 77. MAC RX Statistic s ($ Port_Index + 0x20 - Port_Index + 0x39 ) (Sheet 2 of 4 )
Name Description Address Type1Default
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
2. When sending in lar ge frames, the counter s can o nly de al wit h certain limits. The behavio r of the
LongErrors and VeryLongErrors counters is as follows: VeryLongErrors counts frames that are
2*MaxFr ameSize, dependent on whe re the MaxFram eSize variabl e is set. If MaxFrameSize sets great er
than half of the available c ount in RxO c tetsBad (2^14-1), VeryLongErrors is neve r incremented, but
LongErrors is incremented. This is due to a limitation i n the c ounte r size, wh ich means that an accurate
count will not occur in the RxOctetsBAD counter if the frame is larger than 2^14-1. MaxFrameSize is
determined by the settings in the “Max Frame Size ($ Port_Index + 0x0F)” on page 135.
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 143
RxLongErrors2
Frames bigg er than the maxim um al lowed, with
both OK CRC and the integral number of octets
Def ault maxi mum allowed is 1518 byt es
untagged a nd 152 2 bytes tagged, but the value
can be cha nged by a register
Frames bigger than the larger of
2* Ma x F rame Si z e and 50 000 bit s are not
counted here, but counted in the VeryLongError
counter.
Port_Index
+ 0x 30 CoR 0x00000000
RxJabberErrors
Frames bigg er than the maxim um al lowed, with
either a ba d CRC or a non -integral number of
octets. The default maximum allowed is 1518
by tes untagged and 152 2 bytes tagged , but the
value ca n be ch anged by a register.
Frames bigger than the larger of
2* Ma x F rame Si z e and 50 000 bit s are not
counted here, but counted in the VeryLongError
counter.
Port_Index
+ 0x 31 CoR 0x00000000
RxPauseMac
ControlCounter
Number of Pause MAC control frames received
This statistic register increments on any valid
64byte Pause frame with valid CRC and will also
increment on 64byte Pause Frames with an
invalid CRC if bit 5 of the “R X Pack et Filte r
Co ntrol ($ Port_I nd ex + 0x19 ) ” is set to 1.
Port_Index
+ 0x 32 CoR 0x00000000
RxUnknownMac
ControlFrame
Counter
Number of MAC control frames received with an
op code different from 0001 (Pause) Port_Index
+ 0x 33 CoR 0x00000000
RxVeryLongErrors2Fra m es bi gger than the lar ger of
2* Ma x F ra me S iz e and 50 000 bit s Port_Index
+ 0x 34 CoR 0x00000000
RxRuntErrors
The total number of packets received that are
les s than 64 octets in leng th , but long er tha n or
equal to 96 bit times.
Note: RxRuntErrors is not supported in the
IXF 1110. Any run t or short packets receiv ed are
not coun te d in this registe r.
Note: The “Shor tRuntsThreshold” R egister
controls the byte count used to determine the
difference between Run ts and Shorts, and
th eref o r e co ntr ol s w hich counter is in cr e m ent ed
for a given frame size. This counter is only
updated after receipt of two good frames.
Port_Index
+ 0x 35 CoR 0x00000000
Table 77. MAC RX St ati stics ($ Port_Index + 0x20 - Port_Index + 0x39) (Sheet 3 of 4)
Name Description Address Type1Default
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. When sending in large frames, the counters can only deal with certain limits. The behavior of the
LongErrors and VeryLongErrors counters is as follows: VeryLongErrors counts frames that are
2*MaxFra m eS ize, depe nden t on where the MaxFr am eS ize varia bl e is set. If M axF rame Siz e sets greate r
than half of the availa ble co unt in RxOctet sBad (2^14-1) , VeryLongErrors is nev er incremented, but
LongErrors is incremented. This is due to a limitation in the counter size, which means that an accurate
c ount will n ot occur in the RxOctetsBAD co unter if the f rame is larger t han 2^ 14-1. MaxFrameSize is
deter mi ned by the setti ngs in the “Max Frame Size ($ Port _Index + 0x0F)” on page 135.
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
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RxShortErrors
The total numbe r of packets received that ar e
less than 96 bit times, which corresponds to a 4-
byte frame with a well formed preamble and
SFD. Thi s counter in dicates fragment sizes
ill e gal in al l mo des , an d is on ly ful l y u pda ted a ft er
reception of a good frame following a fragment.
Note: RxShortErrors is not supported in the
IXF1 110. Any runt or short packets received are
not counted in this register.
Port_Index
+ 0x36 CoR 0x00000000
RxCarrierExtend
Error Gig ab it half- d up lex eve nt on ly
Note: N/A - half-duplex only Port_Index
+ 0x37 CoR 0x00000000
RxSequenceErrors Records the number of sequencing errors that
occur. Port_Index
+ 0x38 CoR 0x00000000
RxSymbolErrors Records the number of symbol errors
encountered. Port_Index
+ 0x39 CoR 0x00000000
Table 77. MAC RX Statistic s ($ Port_Index + 0x20 - Port_Index + 0x39 ) (Sheet 4 of 4 )
Name Description Address Type1Default
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
2. When sending in lar ge frames, the counter s can o nly de al wit h certain limits. The behavio r of the
LongErrors and VeryLongErrors counters is as follows: VeryLongErrors counts frames that are
2*MaxFr ameSize, dependent on whe re the MaxFram eSize variabl e is set. If MaxFrameSize sets great er
than half of the available c ount in RxO c tetsBad (2^14-1), VeryLongErrors is neve r incremented, but
LongErrors is incremented. This is due to a limitation i n the c ounte r size, wh ich means that an accurate
count will not occur in the RxOctetsBAD counter if the frame is larger than 2^14-1. MaxFrameSize is
determined by the settings in the “Max Frame Size ($ Port_Index + 0x0F)” on page 135.
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 145
8.5.3 MAC TX Statistics Register Overview
The M AC TX Statisti cs Reg isters contain all the MA C tr ans mit statistic counters an d are cleared
when re ad. T he softwa re must p oll thes e regi ster s to a ccumula te va lue s and ens ure t hat the count ers
do not wrap. The 32-bit counters wrap after approximately 30 seconds.
Table 78 covers the MAC TX Statistics Registers for all 10 MAC ports. The address is identical to
the port numbe r.
Table 78. MAC TX Statistics ($ Po rt_Ind ex + 0x40 - Port_Index + 0x58) (Sheet 1 of 4)
Name Description Address Type1Default
TXOctetsTotalOK
Counts the bytes transmitted in all legal
fra m es. The count includes all bytes
from the destination MAC address to
and incl uding the CRC. The initial
preamb le an d SFD bytes are no t
counted.
Port_Index +
0x40 CoR 0x00000000
TXOctetsBad
Counts the bytes transmitted in all bad
fra m es. The count includes all bytes
from the destination MAC address to
and incl uding the CRC. The initial
preamb le an d SFD bytes are no t
counted.
TX underrun counted: The count is
ex pected to m atch the num ber of by tes
actually transmitted before the frame is
discarded.
TX CRC error counted: All bytes not
sent with succ ess are counted by this
counter
Port_Index +
0x41 CoR 0x00000000
TXUCPkts The total number of unicast packets
tra nsmitted (excluding bad p ackets) Port_Index +
0x42 CoR 0x00000000
TXMCPkts
The total number of multicast packets
tra nsmitted (excluding bad p ackets)
Note: This count includes pause
control pa ckets which are also counted
in the TxPauseFrames Counter . Thus,
these types of packets are counted
twice. Take care when summing
regist er counts for reporting MIB
information.
Port_Index +
0x43 CoR 0x00000000
TXBCPkts The total number of broadcast packets
tra nsmitted (excluding bad p ackets) Port_Index +
0x44 CoR 0x00000000
TXPkts64Octets
The total number of packets
tra nsmitte d (incl udi ng bad p acke ts) t hat
were 64 octets in length. Incremented
for tagged packets with a length of 64
by tes, includin g tag field
Port_Index +
0x45 CoR 0x00000000
TXPkts65to127Octets
The total number of packets
tra nsmitte d (incl udi ng bad p acke ts) t hat
wer e [65-127] octets in length.
Incremented for tagged packets with a
length of 65 - 127 bytes, including tag
field
Port_Index +
0x46 CoR 0x00000000
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
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TXPkts128to255Octets
Th e total num ber of pac ket s
tr ansmitted ( includi ng bad pack ets ) that
were [128-255] octets in length.
Incremented for tagged packets with a
length of 128 - 255 bytes, including tag
field
Po rt_I ndex +
0x47 CoR 0x00000000
TXPkts256to511Octets
Th e total num ber of pac ket s
tr ansmitted ( includi ng bad pack ets ) that
were [256-511] octets in length.
Incremented for tagged packets with a
length of 256 - 511 bytes, including tag
field
Po rt_I ndex +
0x48 CoR 0x00000000
TXPkts512to1023Octets
Th e total num ber of pac ket s
tr ansmitted ( includi ng bad pack ets ) that
were [512 - 1023] octets in length.
Incremented for tagged packets with a
length of 512 - 1023 bytes, including
tag field
Po rt_I ndex +
0x49 CoR 0x00000000
TXPkts1024to1518Octets
Th e total num ber of pac ket s
tr ansmitted ( includi ng bad pack ets ) that
were [1024-1518] octets in length.
Incremented for tagged packet with a
length between 1024-1522, including
the tag
Po rt_I ndex +
0x4A CoR 0x00000000
TXPkts1519toMaxOctets
Th e total num ber of pac ket s
tr ansmitted ( includi ng bad pack ets ) that
were >1518 octets in length.
Incremented for tagged packet with a
length betw een 15 23-max frame size,
incl udin g the tag
Po rt_I ndex +
0x4B CoR 0x00000000
TXDeferred
Number of times the initial transmission
attempt of a frame is postponed due to
another frame already being
tr ansmitted on the Ethernet netw ork.
Note: N/A - half-duplex only
Po rt_I ndex +
0x4C CoR 0x00000000
TXTotalCollisions Sum of all collision events
Note: N/A - half-duplex only P ort_ Index +
0x4D CoR 0x00000000
TXSingleCollisions
A count of succe ssfully transmitted
frames on a p articular int erface where
the transmission is inhibited by exactly
one collisio n. A fr am e that is coun t e d
by an instanc e of this ob ject is als o
counted by the corresponding instance
of either the UnicastPkts,
MulticastPkts, or BroadcastPkts, and is
not counted by the corresponding
instance of the MultipleCollisionFrames
object.
Note: N/A - half-duplex only
Po rt_I ndex +
0x4E CoR 0x00000000
Table 78. MAC TX Statistics ($ Por t_Index + 0x40 - Port_Index + 0x58) (Sheet 2 of 4)
Name Description Address Type1Default
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
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TXMultipleCollisions
A co unt of succ essf u ll y tr an smit ted
frames on a particular interface for
whi ch tr ansm issi on is i nh ibi te d by mor e
than on e collision. A frame that is
counted by a n in stance of this object is
also cou nted by the corresponding
instance of either the UnicastPkts,
Mult ic as tPkt s, or B roa dc ast Pkt s , an d i s
not counted by the corresponding
instance of the SingleCollisionFrames
object.
Note: N/A - half-duplex only
Port_Index +
0x4F CoR 0x00000000
TXLateCollisions
The number of times a c ollision is
detected on a partic ular inter fac e later
than 512 bi t-t i mes int o the t ran sm iss ion
of a packet. Such frame are terminated
and disc arded.
Note: N/A - half-duplex only
Port_Index +
0x50 CoR 0x00000000
TXExcessiveCollisionErrors
A count of frames , w hich co llid es 16
times and is then discarded by the
MAC. Not effecting xMultipleCollisions
Note: N/A - half- dupl ex only
Port_Index +
0x51 CoR 0x00000000
TXExcessiveDeferralErrors
Number of times frame transmission is
postponed more than 2*MaxFrameSize
due to anoth er fram e already bein g
tra nsmitted on the Eth ernet network.
This causes the MAC to discard the
frame.
Note: N/A - half-duplex only
Port_Index +
0x52 CoR 0x00000000
TXExcessiveLengthDrop
F ram e t rans mis sions abor ted by the
MA C be cause the f ram e is longer than
max imum frame size. These fr am es
are tr unca ted by the MAC whe n the
maximum frame size vio lation is
detected by the MAC .
Port_Index +
0x53 CoR 0x00000000
TXUnderrun
Internal TX error which causes the
MAC to end the transmission before
the en d of the fr am e becau se the MAC
did not get the needed data in time for
tra nsmission. The fra m es are lost and
a fragment or a CRC error is
transmitted.
Port_Index +
0x54 CoR 0x00000000
TXTagged Number of OK frames with VLAN tag.
(Type f ield = 0x81 00). Port_Index +
0x55 CoR 0x00000000
Table 78. MAC TX Statistics ($ Po rt_Ind ex + 0x40 - Port_Index + 0x58) (Sheet 3 of 4)
Name Description Address Type1Default
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
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TXCRCError Number of fr ames transmitted with a
legal size, but with the wrong CRC field
(a ls o ca lle d FCS fie ld )
Po rt_I ndex +
0x56 CoR 0x00000000
TXPauseFrames N um b er of pau se MA C f ram es
transmitted Po rt_I ndex +
0x57 CoR 0x00000000
TXFlowControlCollisions
Send
Collisions ge nerated on purpose o n
incoming fr ames, to avoid reception of
tr affic, while the port is in ha lf-duplex
and has f lo w con tr o l enabled, an d do
not have sufficient memory to receive
more frames.
Note: Due to the int ernal counting
technique, a last frame might have to
be transmitted after last flow control
collision send to get the correct
statistic.
Note: N/A - half-duplex only
Po rt_I ndex +
0x58 CoR 0x00000000
Table 78. MAC TX Statistics ($ Por t_Index + 0x40 - Port_Index + 0x58) (Sheet 4 of 4)
Name Description Address Type1Default
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
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8.5.4 Global Status and Configuration Register Overview
Table 79 through Table 86 on page 152 provide an overview of the Global Control and Status
Registers.
Tabl e 79. P ort Enab le ($ 0x500)
Bit Name Description Type1Default
Register Description: A control register for each port in the IXF11 10. Port ID = bit position in
the register. To make a port active, the bit must be set High (for example, port 4 active implies
register value = 0001.000 0). Se tting the bit to 0 disab les the port . Th e default state for this
register i s for all 10 port s to be active. 0x000003FF
31:10 Reserved Reserved R 0x00000
9 Port 9 Enable Port 9
0 = Disable
1 = Enable R/W 1
8 Port 8 Enable Port 8
0 = Disable
1 = Enable R/W 1
7 Port 7 Enable Port 7
0 = Disable
1 = Enable R/W 1
6 Port 6 Enable Port 6
0 = Disable
1 = Enable R/W 1
5 Port 5 Enable Port 5
0 = Disable
1 = Enable R/W 1
4 Port 4 Enable Port 4
0 = Disable
1 = Enable R/W 1
3 Port 3 Enable Port 3
0 = Disable
1 = Enable R/W 1
2 Port 2 Enable Port 2
0 = Disable
1 = Enable R/W 1
1 Port 1 Enable Port 1
0 = Disable
1 = Enable R/W 1
0 Port 0 Enable Port 0
0 = Disable
1 = Enable R/W 1
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. If a port i s disa bled m id-packet on the receive side in Ser Des m ode, the RX Stats will not update for that
packe t due to power -dow n of Ser Des wh en the port is disabled.
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Table 80. Link LED Enable ($ 0 x502)
Bit Name Description Type1Default
Register Description: Per-port bit should be set upon detection of link by system CPU to
enable proper operation of th e link LEDs. 0x00000000
31:10 Reserved Reserved R 0x00000
9 Link LED Enable Port 9 Port 9 link
0 = No link
1 = Li nk R/W 0
8 Link LED Enable Port 8 Port 8 link
0 = No link
1 = Li nk R/W 0
7 Link LED Enable Port 7 Port 7 link
0 = No link
1 = Li nk R/W 0
6 Link LED Enable Port 6 Port 6 link
0 = No link
1 = Li nk R/W 0
5 Link LED Enable Port 5 Port 5 link
0 = No link
1 = Li nk R/W 0
4 Link LED Enable Port 4 Port 4 link
0 = No link
1 = Li nk R/W 0
3 Link LED Enable Port 3 Port 3 link
0 = No link
1 = Li nk R/W 0
2 Link LED Enable Port 2 Port 2 link
0 = No link
1 = Li nk R/W 0
1 Link LED Enable Port 1 Port 1 link
0 = No link
1 = Li nk R/W 0
0 Link LED Enable Port 0 Port 0 link
0 = No link
1 = Li nk R/W 0
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
Tab le 81. Core Clock Soft Reset ($ 0x504)
Bit Name Description Type1Default
Register Description : A soft reset regist er for the cor e clock system ( for example, the
SYS125 clock). 0x00000000
31:1 Reserved Reserved R 0x00000000
0Core Soft
Reset 0 = CoreSoftReset reset is inactive
1 = CoreSoftReset reset is active R/W 0
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
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Table 82. MAC Soft Reset ($ 0x505)
Bit Name Description Type1Default
Register Description: Per-port softwar e activated re set of t he MAC co re. 0x00000000
31:10 Reserved Reserved R 0x00000
9 MAC Soft Reset Port 9 Port 9
0 = Reset inactive
1 = Reset active R/W 0
8 MAC Soft Reset Port 8 Port 8
0 = Reset inactive
1 = Reset active R/W 0
7 MAC Soft Reset Port 7 Port 7
0 = Reset inactive
1 = Reset active R/W 0
6 MAC Soft Reset Port 6 Port 6
0 = Reset inactive
1 = Reset active R/W 0
5 MAC Soft Reset Port 5 Port 5
0 = Reset inactive
1 = Reset active R/W 0
4 MAC Soft Reset Port 4 Port 4
0 = Reset inactive
1 = Reset active R/W 0
3 MAC Soft Reset Port 3 Port 3
0 = Reset inactive
1 = Reset active R/W 0
2 MAC Soft Reset Port 2 Port 2
0 = Reset inactive
1 = Reset active R/W 0
1 MAC Soft Reset Port 1 Port 1
0 = Reset inactive
1 = Reset active R/W 0
0 MAC Soft Reset Port 0 Port 0
0 = Reset inactive
1 = Reset active R/W 0
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
Table 83. CPU Interface ($ 0x508)
Bit Name Description Type1Default
Register Description: CPU interface Endian select. This register allows the user to select the
Endian of the CPU i nterf ace t o allow various different CPU s to be conne cted to the I XF1110. 0x00000000
31:1 Reserved Reserved R 0x00000000
0Endian 0 = Lit tle E nd ian
1 = Big Endian R/W 0
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
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Table 84. LED Control ($ 0x509)
Bit Name Description Type1Default
Register Description : Globally selects and enables the LED mode. 0x00000000
31-2 Reserved Reserved R 0x00000000
1 LED Enable 0 = Disable LEDs
1 = Enable LEDs R/W 0
0 LED_SEL_MODE 0 = Enable LED Mode 0 for use with SGS
Thompson M 5450 LED driver (Defau lt)
1 = LED Mode 1 for use with Standard Octal
Shift Register R/W 0
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
Tab le 85. LED Flash Rate ($ 0x 50A)
Bit Name Description Type1Default
Register Description : Globally selects and enables the flash rate. 0x00000000
31:3 Reserved Reserved R 0x00000000
2:0 LED Flash Rate
000 = 100 ms flash rate
001 = 200 ms flash rate
010 = 300 ms flash rate
011 = 400 ms flash rate
100 = 500 ms flash rate
101 = Reserved
110 = Reserved
111 = Reserved
R/W 000
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
Tab le 86. LED Fault Disable ($ 0x50B) (Sheet 1 of 2)
Bit Name Description Type1Default
Register Description : Per-port fault disable: Disables the LED flashing for local or remote
faults 0x00000000
31:10 Reserved Reserved R 0x000000
9LED Fau lt
Disable Port 9
Port 9
0 = Fault enabled
1 = Fault disabled R/W 0
8LED Fau lt
Disable Port 8
Port 8
0 = Fault enabled
1 = Fault disabled R/W 0
7LED Fau lt
Disable Port 7
Port 7
0 = Fault enabled
1 = Fault disabled R/W 0
6LED Fau lt
Disable Port 6
Port 6
0 = Fault enabled
1 = Fault disabled R/W 0
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
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5LED Fault
Disable Port 5
Port 5
0 = Fault enabled
1 = Fault disabled R/W 0
4LED Fault
Disable Port 4
Port 4
0 = Fault enabled
1 = Fault disabled R/W 0
3LED Fault
Disable Port 3
Port 3
0 = Fault enabled
1 = Fault disabled R/W 0
2LED Fault
Disable Port 2
Port 2
0 = Fault enabled
1 = Fault disabled R/W 0
1LED Fault
Disable Port 1
Port 1
0 = Fault enabled
1 = Fault disabled R/W 0
0LED Fault
Disable Port 0
Port 0
0 = Fault enabled
1 = Fault disabled R/W 0
Table 87. JTAG ID Revision ($ 0x50C)
Bit Name Description Type Default
Register Description: The value of this register follow s the same schem e as the
device identification register found in the IEEE 1 149.1 specification. The upper 4 bits
correspond to silicon stepping. The next 16 bits store a Part ID Number . The next 1 1
bits contain a JEDEC Manufacturer ID. Bit zero = 1 if the chip is the first in a stack.
The en codi ng scheme used for th e Product ID field is impleme ntation dependent.
0x40456013
31:28 Version2Version2R0100
27:12 Part ID Par t ID R 0000010001010110
11:8 JEDEC Cont. JEDEC Cont. R 0000
7:1 JEDEC ID JEDEC ID R 0001001
0 Reserved Reserved R 1
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. Se e the IXF1110 Specification Upate for the lates t version .
Table 86. LED Fau lt Disable ($ 0x50B) (Sheet 2 of 2)
Bit Name Description Type1Default
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
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8.5.5 Global RX Block Register Overview
Table 88 th rough Table 93 on page 161 provide an overvi ew of the RX Bloc k Registers, which
include the RX FIFO High and Low waterm arks.
Table 88. RX FIFO H igh Wa termark P orts 0 to 9 ($ 0x580 - 0 x589) (Sheet 1 of 2)
Name2Description Address Type1Default
RX FIFO High
W atermark Port 0
High watermark for RX FIFO port 0. The default
value is 1856 bytes. When the amount of data
stored in the FIFO exceeds this value, a flow
cont rol co mma nd is sent t o the co rresp on di ng TX
MAC.
0x580 R/W 0x00000740
RX FIFO High
W atermark Port 1
High watermark for RX FIFO port 1. The default
value is 1856 bytes. When the amount of data
stored in the FIFO exceeds this value, a flow
cont rol co mma nd is sent t o the co rresp on di ng TX
MAC.
0x581 R/W 0x00000740
RX FIFO High
W atermark Port 2
High watermark for RX FIFO port 2. The default
value is 1856 bytes. When the amount of data
stored in the FIFO exceeds this value, a flow
cont rol co mma nd is sent t o the co rresp on di ng TX
MAC.
0x582 R/W 0x00000740
RX FIFO High
W atermark Port 3
High watermark for RX FIFO port 3. The default
value is 1856 bytes. When the amount of data
stored in the FIFO exceeds this value, a flow
cont rol co mma nd is sent t o the co rresp on di ng TX
MAC.
0x583 R/W 0x00000740
RX FIFO High
W atermark Port 4
High watermark for RX FIFO port 4. The default
value is 1856 bytes. When the amount of data
stored in the FIFO exceeds this value, a flow
cont rol co mma nd is sent t o the co rresp on di ng TX
MAC.
0x584 R/W 0x00000740
RX FIFO High
W atermark Port 5
High watermark for RX FIFO port 5. The default
value is 1856 bytes. When the amount of data
stored in the FIFO exceeds this value, a flow
cont rol co mma nd is sent t o the co rresp on di ng TX
MAC.
0x585 R/W 0x00000740
RX FIFO High
W atermark Port 6
High watermark for RX FIFO port 6. The default
value is 1856 bytes. When the amount of data
stored in the FIFO exceeds this value, a flow
cont rol co mma nd is sent t o the co rresp on di ng TX
MAC.
0x586 R/W 0x00000740
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
2. For all RX FIFO High Watermark Registers, the following bit definitions apply to all ports (0:9):
Bit s 31:15 - Re served and R.
Bits 14:0 - Described above.
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
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RX FIFO High
Waterma rk Port 7
High watermark for RX FIFO port 7. The default
value is 1856 by tes. When the am ount of data
stored in the FIFO exce eds this val ue, a flow
control command is sent to the corresponding TX
MAC.
0x587 R/W 0x00000740
RX FIFO High
Waterma rk Port 8
High watermark for RX FIFO port 8. The default
value is 1856 by tes. When the am ount of data
stored in the FIFO exce eds this val ue, a flow
control command is sent to the corresponding TX
MAC
0x588 R/W 0x00000740
RX FIFO High
Waterma rk Port 9
High watermark for RX FIFO port 9. The default
value is 1856 by tes. When the am ount of data
stored in the FIFO exce eds this val ue, a flow
control command is sent to the corresponding TX
MAC.
0x589 R/W 0x00000740
Table 89. RX FIFO Low Wa termark P orts 0 to 9 ($ 0x58A - 0 x593) (Sheet 1 of 2)
Name2Description Address Type1Default
RX FIFO Low
Waterma rk Port 0
Low watermark for RX FIFO port 0. The default
value is 1840 bytes. When the port is in flow
cont rol , and the am ou nt of dat a st ore d i n the F I FO
goes below thi s valu e, the flow co ntrol comm and
is terminated in the corresponding TX MAC.
0x58A R/W 0x00000730
RX FIFO Low
Waterma rk Port 1
Low watermark for RX FIFO port 1. The default
value is 1840 bytes. When the port is in flow
control and the amount of data stored in the FIFO
goes below thi s valu e, the flow co ntrol comm and
is terminated in the corresponding TX MAC.
0x58B R/W 0x00000730
RX FIFO Low
Waterma rk Port 2
Low watermark for RX FIFO port 2. The default
value is 1840 bytes. When the port is in flow
control and the amount of data stored in the FIFO
goes below thi s valu e, the flow co ntrol comm and
is terminated in the corresponding TX MAC.
0x58C R/W 0x00000730
RX FIFO Low
Waterma rk Port 3
Low watermark for RX FIFO port 3. The default
value is 1840 bytes. When the port is in flow
control and the amount of data stored in the FIFO
goes below thi s valu e, the flow co ntrol comm and
is terminated in the corresponding TX MAC.
0x58D R/W 0x00000730
RX FIFO Low
Waterma rk Port 4
Low watermark for RX FIFO port 4. The default
value is 1840 bytes. When the port is in flow
control and the amount of data stored in the FIFO
goes below thi s valu e, the flow co ntrol comm and
is terminated in the corresponding TX MAC.
0x58E R/W 0x00000730
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. Fo r all RX FIFO Low W atermark Regi sters, th e following bit definitions apply to all ports (0:9):
Bits 31: 1 5 - Res e r ve d an d R .
Bits 14:0 - Described above.
Table 88. RX FIFO High Watermark Ports 0 to 9 ($ 0x580 - 0x589) (Sheet 2 of 2)
Name2Description Address Type1Default
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. For all RX FIFO High Watermark Registers, the following bit definitions apply to all ports (0:9):
Bits 31: 1 5 - Res e r ve d an d R .
Bits 14:0 - Described above.
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
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RX FIFO Low
W atermark Port 5
Low watermark for RX FIFO port 5. The default
v alue is 1840 bytes. When the port is in flow
control and the amount of data stored in the FIFO
goes below this value, the flow control command
is terminated in the corresponding TX MAC.
0x58F R/W 0x00000730
RX FIFO Low
W atermark Port 6
Low watermark for RX FIFO port 6. The default
v alue is 1840 bytes. When the port is in flow
control and the amount of data stored in the FIFO
goes below this value, the flow control command
is terminated in the corresponding TX MAC.
0x590 R/W 0x00000730
RX FIFO Low
W atermark Port 7
Low watermark for RX FIFO port 7. The default
v alue is 1840 bytes.When the port is in flow
control and the amount of data stored in the FIFO
goes below this value, the flow control command
is terminated in the corresponding TX MAC.
0x591 R/W 0x00000730
RX FIFO Low
W atermark Port 8
Low watermark for RX FIFO port 8. The default
v alue is 1840 bytes. When the port is in flow
control and the amount of data stored in the FIFO
goes below this value, the flow control command
is terminated in the corresponding TX MAC.
0x592 R/W 0x00000730
RX FIFO Low
W atermark Port 9
Low watermark for RX FIFO port 9. The default
v alue is 1840 bytes. When the port is in flow
control and the amount of data stored in the FIFO
goes below this value, the flow control command
is terminated in the corresponding TX MAC.
0x593 R/W 0x00000730
Table 89. RX FIFO Low Watermark Ports 0 to 9 ($ 0x58A - 0x593) (Sheet 2 of 2)
Name2Description Address Type1Default
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
2. For al l RX FIFO Low Waterm ark R egis ters, the follow ing bit definit ion s apply to all ports (0 :9):
Bit s 31:15 - Re served and R.
Bits 14:0 - Described above.
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Table 90. RX FIFO Numb er of Frame s Removed Ports 0 to 9 ($ 0x594 - 0x59D) (Sheet 1 of 2)
Name2Description Address Type1Default
RX FIFO Number
of Frames
Removed on Port 0
This register counts all frames removed from
the RX FI FO for port 0 b y m e eting on e of the
following cond itions:
• The RX FIFO on this port becomes full
• Frames ar e removed in conjunction with
the RX FIFO Errored Frame Drop Enable
Regist er (Table 92 on page 160)
• Frames are greater than the
MaxFrameSize (Table 68 on page135)
0x594 CoR 0x00000000
RX FIFO Number
of Frames
Removed on Port 1
This register counts all frames removed from
the RX FI FO for port 1 b y m e eting on e of the
following cond itions:
• The RX FIFO on this port becomes full
• Frames ar e removed in conjunction with
the RX FIFO Errored Frame Drop Enable
Regist er (Table 92 on page 160)
• Frames are greater than the
MaxFrameSize (Table 68 on page135)
0x595 CoR 0x00000000
RX FIFO Number
of Frames
Removed on Port 2
This register counts all frames removed from
the RX FI FO for port 2 b y m e eting on e of the
following cond itions:
• The RX FIFO on this port becomes full
• Frames ar e removed in conjunction with
the RX FIFO Errored Frame Drop Enable
Regist er (Table 92 on page 160)
• Frames are greater than the
MaxFrameSize (Table 68 on page135)
0x596 CoR 0x00000000
RX FIFO Number
of Frames
Removed on Port 3
This register counts all frames removed from
the RX FI FO for port 3 b y m e eting on e of the
following cond itions:
• The RX FIFO on this port becomes full
• Frames ar e removed in conjunction with
the RX FIFO Errored Frame Drop Enable
Regist er (Table 92 on page 160)
• Frames are greater than the
MaxFrameSize (Table 68 on page135)
0x597 CoR 0x00000000
RX FIFO Number
of Frames
Removed on Port 4
This register counts all frames removed from
the RX FI FO for port 4 b y m e eting on e of the
following cond itions:
• The RX FIFO on this port becomes full
• Frames ar e removed in conjunction with
the RX FIFO Errored Frame Drop Enable
Regist er (Table 92 on page 160)
• Frames are greater than the
MaxFrameSize (Table 68 on page135)
0x598 CoR 0x00000000
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write.
2. For all Number of Frames Removed Registers, the following bit definitions apply to all ports (0:9):
Bits 31: 2 2 - Res e r ve d an d R .
Bits 21:0 - Described above.
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RX FIFO Number
of Fram es
Removed on Por t 5
This register counts all f rames rem oved from
the RX FIFO for port 5 by meeting one of the
follo w in g co nd ition s :
• The RX FIFO on this port becomes full
• Fra m es are rem oved in conjunction with
the RX FI FO Errored Frame Drop E nable
Re gister (Table 92 on page 160)
• Frames are gr eate r than the
MaxFrameSize (Table 68 on page 135)
0x599 CoR 0x00000000
RX FIFO Number
of Fram es
Removed on Por t 6
This register counts all f rames rem oved from
the RX FIFO for port 6 by meeting one of the
follo w in g co nd ition s :
• The RX FIFO on this port becomes full
• Fra m es are rem oved in conjunction with
the RX FI FO Errored Frame Drop E nable
Re gister (Table 92 on page 160)
• Frames are gr eate r than the
MaxFrameSize (Table 68 on page 135)
0x59A CoR 0x00000000
RX FIFO Number
of Fram es
Removed on Por t 7
This register counts all f rames rem oved from
the RX FIFO for port 7 by meeting one of the
follo w in g co nd ition s :
• The RX FIFO on this port becomes full
• Fra m es are rem oved in conjunction with
the RX FI FO Errored Frame Drop E nable
Re gister (Table 92 on page 160)
• Frames are gr eate r than the
MaxFrameSize (Table 68 on page 135)
0x59B CoR 0x00000000
RX FIFO Number
of Fram es
Removed on Por t 8
This register counts all f rames rem oved from
the RX FIFO for port 8 by meeting one of the
follo w in g co nd ition s :
• The RX FIFO on this port becomes full
• Fra m es are rem oved in conjunction with
the RX FI FO Errored Frame Drop E nable
Re gister (Table 92 on page 160)
• Frames are gr eate r than the
MaxFrameSize (Table 68 on page 135)
0x59C CoR 0x00000000
RX FIFO Number
of Fram es
Removed on Por t 9
This register counts all f rames rem oved from
the RX FIFO for port 9 by meeting one of the
follo w in g co nd ition s :
• The RX FIFO on this port becomes full
• Fra m es are rem oved in conjunction with
the RX FI FO Errored Frame Drop E nable
Re gister (Table 92 on page 160)
• Frames are gr eate r than the
MaxFrameSize (Table 68 on page 135)
0x59D CoR 0x00000000
Table 90. RX FIFO N umbe r of Frames Remo ved Ports 0 to 9 ($ 0x594 - 0x59D) (Sheet 2 of 2)
Name2Description Address Type1Default
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write.
2. For all Number of Frames Removed Registers, the following bit definitions apply to all ports (0:9):
Bit s 31:22 - Re served and R.
Bits 21:0 - Described above.
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Table 91. RX FIFO Port Reset ($ 0x59E)
Bit Name Description Type1Default
Register Description: The soft reset register for each port in the RX block. Port ID = bit
position in the register. To make the reset active, the bit must be set High. For example, reset
of port 4 implies register value = 0001.0000. Setting the bit to 0 de-asserts the reset. 0x00000000
31:10 Reserved Reserved R 0x000000
9RXFIFOPort 9
Reset
Port 9
0 = D e-assert re set
1 = Reset R/W 0
8RXFIFOPort 8
Reset
Port 8
0 = D e-assert re set
1 = Reset R/W 0
7RXFIFOPort 7
Reset
Port 7
0 = D e-assert re set
1 = Reset R/W 0
6RXFIFOPort 6
Reset
Port 6
0 = D e-assert re set
1 = Reset R/W 0
5RXFIFOPort 5
Reset
Port 5
0 = D e-assert re set
1 = Reset R/W 0
4RXFIFOPort 4
Reset
Port 4
0 = D e-assert re set
1 = Reset R/W 0
3RXFIFOPort 3
Reset
Port 3
0 = D e-assert re set
1 = Reset R/W 0
2RXFIFOPort 2
Reset
Port 2
0 = D e-assert re set
1 = Reset R/W 0
1RXFIFOPort 1
Reset
Port 1
0 = D e-assert re set
1 = Reset R/W 0
0RXFIFOPort 0
Reset
Port 0
0 = D e-assert re set
1 = Reset R/W 0
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
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Table 92. RX FIFO Errored Frame Dro p Enab le ($ 0x59F) (Sheet 1 of 2 )
Bit Name Description Type1Default
Register Description : This regist er is used i n conjunction w ith the RX Packet Filter Control
Register bits to select whether errored or filtered frames are to be dropped. 0x00000000
31:10 Reserved Reserved R 0x000000
9RX FIFO
Errored Frame
Drop Enable
Port 9
These bits are used in conj unction with t he “RX
Packet Filter Co ntrol ($ Po rt_I ndex + 0x1 9)” bits,
allowing the user to select whether errored or filtered
frames are to be dropped or not.
Port 9:
0 = Do no t drop frames
1 = Drop frames
R/W 0
8RX FIFO
Errored Frame
Drop Enable
Port 8
These bits are used in conj unction with t he “RX
Packet Filter Co ntrol ($ Po rt_I ndex + 0x1 9)” bits,
allowing the user to select whether errored or filtered
frames are to be dropped or not.
Port 8:
0 = Do no t drop frames
1 = Drop frames
R/W 0
7
RX FIFO
Errored Frame
Drop Enable
Port 7
These bits are used in conj unction with t he “RX
Packet Filter Co ntrol ($ Po rt_I ndex + 0x1 9)” bits,
allowing the user to select whether errored or filtered
frames are to be dropped or not.
Port 7:
0 = Do no t drop frames
1 = Drop frames
R/W 0
6RX FIFO
Errored Frame
Drop Enable
Port 6
These bits are used in conj unction with t he “RX
Packet Filter Co ntrol ($ Po rt_I ndex + 0x1 9)” bits,
allowing the user to select whether errored or filtered
frames are to be dropped or not.
Port 6:
0 = Do no t drop frames
1 = Drop frames
R/W 0
5
RX FIFO
Errored Frame
Drop Enable
Port 5
These bits are used in conj unction with t he “RX
Packet Filter Co ntrol ($ Po rt_I ndex + 0x1 9)” bits,
allowing the user to select whether errored or filtered
frames are to be dropped or not.
Port 5:
0 = Do no t drop frames
1 = Drop frames
R/W 0
4RX FIFO
Errored Frame
Drop Enable
Port 4
These bits are used in conj unction with t he “RX
Packet Filter Co ntrol ($ Po rt_I ndex + 0x1 9)” bits,
allowing the user to select whether errored or filtered
frames are to be dropped or not.
Port 4:
0 = Do no t drop frames
1 = Drop frames
R/W 0
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
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3
RX FIFO
Errored Frame
Drop Enable
Port 3
These bits are used in conjunction with the “RX
Packet Filter Control ($ Port_Index + 0x19)” bits,
allowing the us er to select whether err ored or fi lte red
frames are to be dr oppe d or not.
Port 3:
0 = Do not drop frames
1 = Drop frames
R/W 0
2RX FIFO
Errored Frame
Drop Enable
Port 2
These bits are used in conjunction with the “RX
Packet Filter Control ($ Port_Index + 0x19)” bits,
allowing the us er to select whether err ored or fi lte red
frames are to be dr oppe d or not.
Port 2:
0 = Do not drop frames
1 = Drop frames
R/W 0
1
RX FIFO
Errored Frame
Drop Enable
Port 1
These bits are used in conjunction with the “RX
Packet Filter Control ($ Port_Index + 0x19)” bits,
allowing the us er to select whether err ored or fi lte red
frames are to be dr oppe d or not.
Port 1:
0 = Do not drop frames
1 = Drop frames
R/W 0
0RX FIFO
Errored Frame
Drop Enable
Port 0
These bits are used in conjunction with the “RX
Packet Filter Control ($ Port_Index + 0x19)” bits,
allowing the us er to select whether err ored or fi lte red
frames are to be dr oppe d or not.
Port 0:
0 = Do not drop frames
1 = Drop frames
R/W 0
Table 93. RX FIFO Overflow Event ($ 0x5A0) (Sheet 1 of 2)
Bit Name Description Type1De fault
Register Description: This register provides a status if a FIFO-full situation has occurred (for
ex ample, a F IFO overf low) . The bit position equal s the p ort number.
This register is cleared on Read. 0x00000000
31:10 Reserved Reserved R 0x000000
9RX FIFO Overflow
Even t Port 9
Port 9
0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred CoR 0
8RX FIFO Overflow
Even t Port 8
Port 8
0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred CoR 0
7RX FIFO Overflow
Even t Port 7
Port 7
0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred CoR 0
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
Table 92. RX FIFO Errored Frame Drop Enable ($ 0x59F) (Sheet 2 of 2)
Bit Name Description Type1Default
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
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6RX FIF O Overfl ow
Eve nt Port 6
Port 6
0 = FIFO overflo w event did not occur
1 = FIFO overflow ev ent occurred CoR 0
5RX FIF O Overfl ow
Eve nt Port 5
Port 5
0 = FIFO overflo w event did not occur
1 = FIFO overflow ev ent occurred CoR 0
4RX FIF O Overfl ow
Eve nt Port 4
Port 4
0 = FIFO overflo w event did not occur
1 = FIFO overflow ev ent occurred CoR 0
3RX FIF O Overfl ow
Eve nt Port 3
Port 3
0 = FIFO overflo w event did not occur
1 = FIFO overflow ev ent occurred CoR 0
2RX FIF O Overfl ow
Eve nt Port 2
Port 2
0 = FIFO overflo w event did not occur
1 = FIFO overflow ev ent occurred CoR 0
1RX FIF O Overfl ow
Eve nt Port 1
Port 1
0 = FIFO overflo w event did not occur
1 = FIFO overflow ev ent occurred CoR 0
0RX FIF O Overfl ow
Eve nt Port 0
Port 0
0 = FIFO overflo w event did not occur
1 = FIFO overflow ev ent occurred CoR 0
Tab le 93. RX FIFO Overflow Event ($ 0x5A0) (Sheet 2 of 2 )
Bit Name Description Type1Default
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
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8.5.6 TX Block Register Overview
Table 94 through Table 100 on page 171 provide an overview of the TX Block Regi sters, whic h
include the TX FIFO High and Low Watermark.
Table 94. TX FIFO High Watermark Ports 0 to 9 ($ 0x600 - 0x609) (Sheet 1 of 2)
Name2Description Address Type1Default
TX FIFO High
W atermark Port 0
High watermark for TX FIFO port 0. The default
value is 1584 by tes. When the am ount of data
stored in the FIFO exceeds this v alue , the TX
FIFO indicates “SATISFIED.” This implies
further up in the system that no more data must
be sent to this port.
0x600 R/W 0x00000630
TX FIFO High
W atermark Port 1
High watermark for TX FIFO port 1. The default
value is 1584 by tes. When the am ount of data
stored in the FIFO exceeds this v alue , the TX
FIFO indicates “SATISFIED.” This implies
further up in the system that no more data must
be sent to this port.
0x601 R/W 0x00000630
TX FIFO High
W atermark Port 2
High watermark for TX FIFO port 2. The default
value is 1584 by tes. When the am ount of data
stored in the FIFO exceeds this v alue , the TX
FIFO indicates “SATISFIED.” This implies
further up in the system that no more data must
be sent to this port.
0x602 R/W 0x00000630
TX FIFO High
W atermark Port 3
High watermark for TX FIFO port 3. The default
value is 1584 by tes. When the am ount of data
stored in the FIFO exceeds this v alue , the TX
FIFO indicates “SATISFIED.” This implies
further up in the system that no more data must
be sent to this port.
0x603 R/W 0x00000630
TX FIFO High
W atermark Port 4
High watermark for TX FIFO port 4. The default
value is 1584 by tes. When the am ount of data
stored in the FIFO exceeds this v alue , the TX
FIFO indicates “SATISFIED.” This implies
further up in the system that no more data must
be sent to this port.
0x604 R/W 0x00000630
TX FIFO High
W atermark Port 5
High watermark for TX FIFO port 5. The default
value is 1584 by tes. When the am ount of data
stored in the FIFO exceeds this v alue , the TX
FIFO indicates “SATISFIED.” This implies
further up in the system that no more data must
be sent to this port.
0x605 R/W 0x00000630
TX FIFO High
W atermark Port 6
High watermark for TX FIFO port 6. The default
value is 1584 by tes. When the am ount of data
stored in the FIFO exceeds this v alue , the TX
FIFO indicates “SATISFIED.” This implies
further up in the system that no more data must
be sent to this port.
0x606 R/W 0x00000630
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. For all TX FIFO High Watermark Registers, the following bit definitions apply to all ports (0:9):
Bits 31: 1 3 - Res e r ve d an d R .
Bits 12:0 - Described above.
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TX FIFO High
W atermark Port 7
High watermark for TX FIFO port 7. The default
value is 1584 byt es. When the amo unt of data
stor ed in the FI FO exce eds this value, th e TX
FIFO indicates “SATISFIED.” This implies
further up in the system that no more data must
be sent to this port.
0x607 R/W 0x00000630
TX FIFO High
W atermark Port 8
High watermark for TX FIFO port 8. The default
value is 1584 byt es. When the amo unt of data
stor ed in the FI FO exce eds this value, th e TX
FIFO indicates “SATISFIED.” This implies
further up in the system that no more data must
be sent to this port.
0x608 R/W 0x00000630
TX FIFO High
W atermark Port 9
High watermark for TX FIFO port 9. The default
value is 1584 byt es. When the amo unt of data
stor ed in the FI FO exce eds this value, th e TX
FIFO indicates “SATISFIED.” This implies
further up in the system that no more data must
be sent to this port.
0x609 R/W 0x00000630
Table 95. TX FIFO Low Waterm ark P orts 0 to 9 ($ 0x60A - 0x613) (Sh eet 1 of 2)
Name2Description Address Type1Default
TX FIFO Low
W atermark Port 0
Low watermark for TX FIFO port 0. The default
value is 464 bytes. When the amount of data
fall s be lo w this value , the TX FIF O status
indica tes “STARV ING”. This implies furthe r up
in the system that mor e data mus t be sent to
this port to prevent an underrun.
0x60A R/W 0x000001D0
TX FIFO Low
W atermark Port 1
Low watermark for TX FIFO port 1. The default
value is 464 bytes. When the amount of data
fall s be lo w this value , the TX FIF O status
indica tes “STARV ING”. This implies furthe r up
in the system that mor e data mus t be sent to
this port to prevent an underrun.
0x60B R/W 0x000001D0
TX FIFO Low
W atermark Port 2
Low watermark for TX FIFO port 2. The default
value is 464 bytes. When the amount of data
fall s be lo w this value , the TX FIF O status
indica tes “STARV ING”. This implies furthe r up
in the system that mor e data mus t be sent to
this port to prevent an underrun.
0x60C R/W 0x000001D0
TX FIFO Low
W atermark Port 3
Low watermark for TX FIFO port 3. The default
value is 464 bytes. When the amount of data
fall s be lo w this value , the TX FIF O status
indica tes “STARV ING”. This implies furthe r up
in the system that mor e data mus t be sent to
this port to prevent an underrun.
0x60D R/W 0x000001D0
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
2. For al l TX FIF O Low Watermark R egisters, the follow ing bit definitions app ly to all ports ( 0:9):
Bit s 31:13 - Re served and R.
Bits 12:0 - Described above.
Table 94. TX F IFO High Watermark Ports 0 to 9 ($ 0x6 00 - 0x609) (Sheet 2 of 2)
Name2Description Address Type1Default
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
2. For al l TX FIF O High Wate rmark Register s, the following bit def ini tions apply to all port s (0:9):
Bit s 31:13 - Re served and R.
Bits 12:0 - Described above.
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TX FIFO Low
W atermark Port 4
Low watermark for TX FIFO port 4. The default
value is 464 bytes. When the amount of data
falls below this value, the TX FIFO status
in dicates “STARVING ”. This implies fur the r up
in the system that more data must be sent to
this port to prevent an underrun.
0x60E R/W 0x000001D0
TX FIFO Low
W atermark Port 5
Low watermark for TX FIFO port 5. The default
value is 464 bytes. When the amount of data
falls below this value, the TX FIFO status
in dicates “STARVING ”. This implies fur the r up
in the system that more data must be sent to
this port to prevent an underrun.
0x60F R/W 0x000001D0
TX FIFO Low
W atermark Port 6
Low watermark for TX FIFO port 6. The default
value is 464 bytes. When the amount of data
falls below this value, the TX FIFO status
in dicates “STARVING ”. This implies fur the r up
in the system that more data must be sent to
this port to prevent an underrun.
0x610 R/W 0x000001D0
TX FIFO Low
W atermark Port 7
Low watermark for TX FIFO port 7. The default
value is 464 bytes. When the amount of data
falls below this value, the TX FIFO status
in dicates “STARVING ”. This implies fur the r up
in the system that more data must be sent to
this port to prevent an underrun.
0x611 R/W 0x000001D0
TX FIFO Low
W atermark Port 8
Low watermark for TX FIFO port 8. The default
value is 464 bytes. When the amount of data
falls below this value, the TX FIFO status
in dicates “STARVING ”. This implies fur the r up
in the system that more data must be sent to
this port to prevent an underrun.
0x612 R/W 0x000001D0
TX FIFO Low
W atermark Port 9
Low watermark for TX FIFO port 9. The default
value is 464 bytes. When the amount of data
falls below this value, the TX FIFO status
in dicates “STARVING ”. This implies fur the r up
in the system that more data must be sent to
this port to prevent an underrun.
0x613 R/W 0x000001D0
Tabl e 95. TX FIFO Low Watermark Ports 0 to 9 ($ 0x60A - 0x613) (Sheet 2 of 2)
Name2Description Address Type1Default
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. Fo r all TX FIFO Low Watermar k Register s, the followi ng bit definitions apply to all por ts (0:9):
Bits 31: 1 3 - Res e r ve d an d R .
Bits 12:0 - Described above.
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Table 96. TX F IFO M AC Tr ansfer Thres hold Ports 0 to 9 ($ 0x614 - 0x61D) (Sheet 1 of 3)
Name2Description3Address Type1Default
TX FIFO MAC
Transfer
T hreshold P ort 0
Sets the value at which the FIFO begins to
transfer data to the MAC. The bottom 3 bits of
this register are ignored, and the threshold is
set in increments of 8-byte steps.
If t his register is s et above the standard p acket
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the c ount value in
this register is exceeded or an End-of-Frame is
received.
0x614 R/W 0x00000100
TX FIFO MAC
Transfer
T hreshold P ort 1
Sets the value at which the FIFO begins to
transfer data to the MAC. The bottom 3 bits of
this register are ignored, and the threshold is
set in increments of 8-byte steps.
If t his register is s et above the standard p acket
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the c ount value in
this register is exceeded or an End-of-Frame is
received.
0x615 R/W 0x00000100
TX FIFO MAC
Transfer
T hreshold P ort 2
Sets the value at which the FIFO begins to
transfer data to MAC. The bottom 3 bits of this
register are ignored, thus the threshold is set in
increments of 8 byte steps.
If t his register is s et above the standard p acket
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the c ount value in
this register is exceeded or an End-of-Frame is
received.
0x616 R/W 0x00000100
TX FIFO MAC
Transfer
T hreshold P ort 3
Sets the value at which the FIFO begins to
transfer data to MAC. The bottom 3 bits of this
register are ignored, thus the threshold is set in
increments of 8 byte steps.
If t his register is s et above the standard p acket
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the c ount value in
this register is exceeded or an End-of-Frame is
received.
0x617 R/W 0x00000100
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
2. For al l MAC Tra nsfer Thr eshol d Register s, the following bit definiti ons ap ply to all ports (0:9):
Bit s 31:13 - Re served and R.
Bits 12:0 - Described above.
3. Fo r pr oper op era tion of the IX F1110, the MAC t ran sf er th res ho ld m ust be set to gr eat er th an the Max B urst 1
on the SPI4-2.
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
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TX FIFO MAC
Transfer
Threshold P ort 4
Sets the value at which the FIFO begins to
transfer data to MAC. The bottom 3 bits of this
register are ignored, thus the threshold is set in
increments of 8 byte steps.
If this register is set above the standard packet
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the count value in
this register is exceeded or an End-of-Frame is
received.
0x618 R/W 0x00000100
TX FIFO MAC
Transfer
Threshold P ort 5
Sets the value at which the FIFO begins to
transfer data to MAC. The bottom 3 bits of this
register are ignored, thus the threshold is set in
increments of 8 byte steps.
If this register is set above the standard packet
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the count value in
this register is exceeded or an End-of-Frame is
received.
0x619 R/W 0x00000100
TX FIFO MAC
Transfer
Threshold P ort 6
Sets the value at which the FIFO begins to
transfer data to MAC. The bottom 3 bits of this
register are ignored, thus the threshold is set in
increments of 8 byte steps.
If this register is set above the standard packet
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the count value in
this register is exceeded or an End-of-Frame is
received.
0x61A R/W 0x00000100
Table 96. TX FIFO MAC Tran sfer Thresho ld Po rts 0 to 9 ($ 0x614 - 0x61D) (Sheet 2 of 3)
Name2Description3Address Type1Default
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. For all MAC Transfer Threshold Registers, the following bit definitions apply to all ports (0:9):
Bits 31: 1 3 - Res e r ve d an d R .
Bits 12:0 - Described above.
3. For proper operation of the IXF11 10, the MAC transfer threshold must be set to greater than the MaxBurst1
on the SPI4-2.
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TX FIFO MAC
Transfer
T hreshold P ort 7
Sets the value at which the FIFO begins to
transfer data to MAC. The bottom 3 bits of this
register are ignored, thus the threshold is set in
increments of 8 byte steps.
If t his register is s et above the standard p acket
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the c ount value in
this register is exceeded or an End-of-Frame is
received.
0x61B R/W 0x00000100
TX FIFO MAC
Transfer
T hreshold P ort 8
Sets the value at which the FIFO begins to
transfer data to the MAC. The bottom 3 bits of
this register are ignored, thus the threshold is
set in increments of 8 byte steps.
If t his register is s et above the standard p acket
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the c ount value in
this register is exceeded or an End-of-Frame is
received.
0x61C R/W 0x00000100
TX FIFO MAC
Transfer
T hreshold P ort 9
Sets the value at which the FIFO begins to
transfer data to the MAC. The bottom 3 bits of
this register are ignored, thus the threshold is
set in increments of 8 byte steps.
If t his register is s et above the standard p acket
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the c ount value in
this register is exceeded or an End-of-Frame is
received.
0x61D R/W 0x00000100
Table 97. TX F IFO Ove rflow Ev ent ($ 0x61E) (Sheet 1 of 2)
Bit Name Description Type1Default
Reg ist er D esc ri pti on: This register provides status that a FIFO- full situation has occurred (for
ex am ple , a FIFO ov erflow). The bit position equals the port number.
This register is cleared on Read. 0x00000000
31:10 Reserved Reserved R 0x000000
9TX FIFO Overflow
Event Port 9
Port 9
0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred CoR 0
8TX FIFO Overflow
Event Port 8
Port 8
0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred CoR 0
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
Table 96. TX F IFO M AC Tr ansfer Thres hold Ports 0 to 9 ($ 0x614 - 0x61D) (Sheet 3 of 3)
Name2Description3Address Type1Default
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
2. For al l MAC Tra nsfer Thr eshol d Register s, the following bit definiti ons ap ply to all ports (0:9):
Bit s 31:13 - Re served and R.
Bits 12:0 - Described above.
3. Fo r pr oper op era tion of the IX F1110, the MAC t ran sf er th res ho ld m ust be set to gr eat er th an the Max B urst 1
on the SPI4-2.
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
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Order Number: 250210, Revision: 009 169
7TX FIFO Overfl ow
Even t Port 7
Port 7
0 = FIFO overflow event did not oc cur
1 = FIFO overflow even t occurred CoR 0
6TX FIFO Overfl ow
Even t Port 6
Port 6
0 = FIFO overflow event did not oc cur
1 = FIFO overflow even t occurred CoR 0
5TX FIFO Overfl ow
Even t Port 5
Port 5
0 = FIFO overflow event did not oc cur
1 = FIFO overflow even t occurred CoR 0
4TX FIFO Overfl ow
Even t Port 4
Port 4
0 = FIFO overflow event did not oc cur
1 = FIFO overflow even t occurred CoR 0
3TX FIFO Overfl ow
Even t Port 3
Port 3
0 = FIFO overflow event did not oc cur
1 = FIFO overflow even t occurred CoR 0
2TX FIFO Overfl ow
Even t Port 2
Port 2
0 = FIFO overflow event did not oc cur
1 = FIFO overflow even t occurred CoR 0
1TX FIFO Overfl ow
Even t Port 1
Port 1
0 = FIFO overflow event did not oc cur
1 = FIFO overflow even t occurred CoR 0
0TX FIFO Overfl ow
Even t Port 0
Port 0
0 = FIFO overflow event did not oc cur
1 = FIFO overflow even t occurred CoR 0
Table 98. TX FIFO Drain ($0x620) (Sheet 1 of 2)
Bit Name Description Type1Default
Register Description: This register enables the TX FIFO d rain mode for the selec ted port by
holding the TX FIFO for that port in reset. All data stored in the TX FIFO is lost when this bit is
set to 1. When this bit is set to 1, the TX FIFO status for the selected port is STARVING. 0x00000000
31:10 Reserved Reserved R 0x000000
9TX FIF O Dra i n
Port 9
Port 9
0 = Disable TX FIFO drain mode
1 = Enable TX FIFO drain mode R/W 0
8TX FIF O Dra i n
Port 8
Port 8
0 = Disable TX FIFO drain mode
1 = Enable TX FIFO drain mode R/W 0
7TX FIF O Dra i n
Port 7
Port 7
0 = Disable TX FIFO drain mode
1 = Enable TX FIFO drain mode R/W 0
6TX FIF O Dra i n
Port 6
Port 6
0 = Disable TX FIFO drain mode
1 = Enable TX FIFO drain mode R/W 0
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
Table 97. TX FIFO Overflow Event ($ 0x61E) (Sheet 2 of 2)
Bit Name Description Type1Default
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
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5TX FIFO Drain
Port 5
Port 5
0 = Disable TX FIFO drain mode
1 = Enable TX FIFO drain mode R/W 0
4TX FIFO Drain
Port 4
Port 4
0 = Disable TX FIFO drain mode
1 = Enable TX FIFO drain mode R/W 0
3TX FIFO Drain
Port 3
Port 3
0 = Disable TX FIFO drain mode
1 = Enable TX FIFO drain mode R/W 0
2TX FIFO Drain
Port 2
Port 2
0 = Disable TX FIFO drain mode
1 = Enable TX FIFO drain mode R/W 0
1TX FIFO Drain
Port 1
Port 1
0 = Disable TX FIFO drain mode
1 = Enable TX FIFO drain mode R/W 0
0TX FIFO Drain
Port 0
Port 0
0 = Disable TX FIFO drain mode
1 = Enable TX FIFO drain mode R/W 0
Table 99. TX F IFO Info Ou t-of-Seque nce ($ 0x621) (Sheet 1 of 2)
Bit Name Description Type1Default
Register Description : This register signals when out-of-sequence data is detected in the TX
FIFO. Events such as SOP followed by another SOP cause this bit to be set and remain so
until read. This register is cleared on Read. 0x00000000
31:10 Reserved Reserved R 0x000000
9TX FIFO Info
Out-of-
Sequence Port 9
Port 9
0 = FIFO out-of-sequence event did not
occur
1 = FIFO ou t- o f -s equenc e event oc cu r red
CoR 0
8TX FIFO Info
Out-of-
Sequence Port 8
Port 8
0 = FIFO out-of-sequence event did not
occur
1 = FIFO ou t- o f -s equenc e event oc cu r red
CoR 0
7TX FIFO Info
Out-of-
Sequence Port 7
Port 7
0 = FIFO out-of-sequence event did not
occur
1 = FIFO ou t- o f -s equenc e event oc cu r red
CoR 0
6TX FIFO Info
Out-of-
Sequence Port 6
Port 6
0 = FIFO out-of-sequence event did not
occur
1 = FIFO ou t- o f -s equenc e event oc cu r red
CoR 0
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
Table 98. TX F IFO Drai n ($0x62 0) (Sheet 2 of 2)
Bit Name Description Type1Default
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
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5TX FIF O In fo
Out-of-
Sequence Port 5
Port 5
0 = FIFO out-of- sequenc e event did not
occur
1 = FIFO out-of-s equence even t occurred
CoR 0
4TX FIF O In fo
Out-of-
Sequence Port 4
Port 4
0 = FIFO out-of- sequenc e event did not
occur
1 = FIFO out-of-s equence even t occurred
CoR 0
3TX FIF O In fo
Out-of-
Sequence Port 3
Port 3
0 = FIFO out-of- sequenc e event did not
occur
1 = FIFO out-of-s equence even t occurred
CoR 0
2TX FIF O In fo
Out-of-
Sequence Port 2
Port 2
0 = FIFO out-of- sequenc e event did not
occur
1 = FIFO out-of-s equence even t occurred
CoR 0
1TX FIF O In fo
Out-of-
Sequence Port 1
Port 1
0 = FIFO out-of- sequenc e event did not
occur
1 = FIFO out-of-s equence even t occurred
CoR 0
0TX FIF O In fo
Out-of-
Sequence Port 0
Port 0
0 = FIFO out-of- sequenc e event did not
occur
1 = FIFO out-of-s equence even t occurred
CoR 0
Table 100. TX FIFO Number of Frames Remov ed P orts 0-9 ($ 0x622 - 0x62B) (Sheet 1 of 2 )
Name Description Address Type1Default
TX FIFO Number
of Frames
Removed on Port 0 This register cou nts the number of fra mes
removed on port 0 due to a TX FIFO overflow. 0x622 CoR 0x00000000
TX FIFO Number
of Frames
Removed on Port 1 This register cou nts the number of fra mes
removed on port 1 due to a TX FIFO overflow. 0x623 CoR 0x00000000
TX FIFO Number
of Frames
Removed on Port 2 This register cou nts the number of fra mes
removed on port 2 due to a TX FIFO overflow. 0x624 CoR 0x00000000
TX FIFO Number
of Frames
Removed on Port 3 This register cou nts the number of fra mes
removed on port 3 due to a TX FIFO overflow. 0x625 CoR 0x00000000
TX FIFO Number
of Frames
Removed on Port 4 This register cou nts the number of fra mes
removed on port 4 due to a TX FIFO overflow. 0x626 CoR 0x00000000
TX FIFO Number
of Frames
Removed on Port 5 This register cou nts the number of fra mes
removed on port 5 due to a TX FIFO overflow. 0x627 CoR 0x00000000
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
Table 99. TX FIFO Info Out-of-Sequence ($ 0x621) (Sheet 2 of 2 )
Bit Name Description Type1Default
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
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TX FIFO Number
of Fram es
Removed on Por t 6
This register co unts the n um ber of fram es
removed on port 6 due to a TX FIFO overfl ow. 0x628 CoR 0x00000000
TX FIFO Number
of Fram es
Removed on Por t 7 This regist er counts the n um ber of fram es
removed on port 7 due to a TX FIFO overfl ow. 0x629 CoR 0x00000000
TX FIFO Number
of Fram es
Removed on Por t 8
This register co unts the n um ber of fram es
remov ed on p ort 8 due to a TX FIFO overflow 0x62A CoR 0x00000000
TX FIFO Number
of Fram es
Removed on Por t 9 This regist er counts the n um ber of fram es
removed on port 9 due to a TX FIFO overfl ow. 0x62B CoR 0x00000000
Table 100. TX FIFO Number of Fra mes Rem oved Po rts 0-9 ($ 0x622 - 0x62B) (Sheet 2 of 2)
Name Description Address Type1Default
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
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8.5.7 SPI4-2 Block Register Overview
Table 101 through Table 104 on page 175 provide an overv iew of the SPI4-2 Bloc k Registers.
Table 101. SPI4-2 RX Burst Size ($ 0x700)
Bit Name Description Type1Default
Register Description: SPI4-2 RX interface start-up parameters for burst size. 0x00060002
31 idles
0 = Zero idle insertion between transfer
bursts
1 = Inserts four idle control words between
each bu rst. (This occurs not only on an
EO P, but also at th e end o f every
MaxBurs t1 or MaxBurst2.
R/W 0x0
30:25 Reserved Reserved R 0x00
24:16 MaxBurst1
Maximum number of 16-byte blocks that the
FIFO in the receive pa th, external to the
IXF1 110, can accept when the FIFO Status
channel indic ates STARVING.
NOTE: Do n ot program these bits belo w 0x2
(32 byte burst).
R/W 0x006
15:9 Reserved Reserved R 0x00
8:0 MaxBurst2
Maximum number of 16-byte blocks that the
FIFO in the receive pa th, external to the
IXF1 110, can accept when the FIFO Status
channel indicates HUNGRY.
NOTE: Do n ot program these bits belo w 0x2
(32 byte burst).
R/W 0x002
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
Table 102. SP I4-2 RX Training ($ 0x701)
Bit Name Description Type1Default
Register Description: SPI4-2 RX interface start-up parameters for training sequences 0x00000000
31:24 Reserved Reserved R 0x00
23:16 REP_T Num ber of rep etiti ons of the data training
sequence that m ust be scheduled every
DATA_MAX_T cycles R/W 0x00
15:0 DATA_MAX_T2
Maximu m interva l (in numb er of cycles)
betw een sc hedu ling of training seq uence s on
receive data path interface
An all zero value disables periodic tra ining
sequences.
R/W 0x0000
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. Th e valu e of DATA_MAX_T is the Most Si gnifican t 16 bits of a 24-bit counter value. The Leas t S ign ificant 8
bits are always 0x0 0. This allows for a much larger D AT_MAX_ T tim e-out period and provides a more t han
adequat e gra nu la r ity of se le ction.
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Table 103. SPI4-2 RX Calendar ($ 0x702)
Bit Name Description Type1Default
Value
Register Description : SPI4-2 RX interface start-up parameters for FIFO status calendar
operation. 0x00010300
31:30 RX Train Test
Modes
00 = Normal mode
01 = Do not enter training based on a
re p eating “ 11” pattern on RS TAT[1:0]
1x = Train continuously
R/W 0x0
29 RSCLK_invert
0 = The F IFO status is captured on the
rising edge of the R SCLK as per the
SPI4-2 spe c ification
1 = The F IFO status is captured on the
falling edge of RSCLK
NOTE: For proper operation, set this bi t to
the desired setting before the
RSCLK is applied to the device.
R/W 0
28 TSCLK_invert
0 = The FIFO status is launched on the
rising edge of the TSCLK as per the
SPI4-2 spe c ification
1 = The FIFO status is launched on the
falling edge of TSCLK
R/W 0
27:21 Reserved Reserved R 0x000
20 DIP2_Error Set based on an incorrect RX DIP2 result.
This bit is cleared upon a read CoR 0x0
19:16 DIP-2_Thr Defines how many con s ecutive co rrect DIP -
2s are required to disable sending of training
sequences on the RX SPI4-2. R/W 0x1
15:14 Reserved Reserved R 00
13 RX SPI4-2 Sync 0 = RX SP I4 In Training (RDAT = t raining)
RX SPI4 Out Of Training (RDA T = idles) R0
12 TX SPI4 Sync
0 = TX SPI4-2 Calendar is in constant
Framing
The TX SPI4-2 has received the valid
training patterns on TDAT and is now
sending a 10 port Calendar on TSAT with
valid FIFO information
R0
11:8 Loss_of_Sync
Loss-of-Sync is a parameter specifying the
number of consecutive framing calendar
cycles required to indicate a loss of
synchronization and res tart trai ning
sequences.
R/W 0x3
7:4 Reserved Reserved R 0x0
3:0 Res erved Write as 0, ig nore on Read. R/W 0x0
1. R = Read Only; CoR = Clear on Read; W = W rite only; R/W = Read/Write
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
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8.5.8 SerDes Register Overview
Table 105 through Table 107 on page 176 define the co ntents of the SerDes Register
Block at base location 0x780 which contain the control and status for the ten SerDes interfaces on
the IXF1110.
Table 104. SP I4-2 TX Synchron ization ($ 0x703)
Bit Name Description Type1Default
Register Description: SPI4 -2 synchronization DI P-4 counters. 0x000 00420
31:16 DIP4_Errors DIP4_ Erro rs is the total numb er of DIP4
e rr ors det ec ted since t hi s r eg ist e r was l as t
read. CoR 0x0000
15:8 DIP4_UnLock2
DIP-4_Unlock is a SPI4-2 parameter
specifying the number of incor rect DIP4
fi elds to be de t ec te d to de clar e l os s of
synchronization and drive the TSTAT[1:0]
bus with fr aming.
R/W 0x04
7:0 DIP4_Lock Number of consecutive corre c t DIP4 results
to achieve synchronization and end training R/W 0x20
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. When Periodic Training is enabled, the actual count of DIP4 errors required to lose synchronization is 1
less than the programm ed va lue in this register. Therefore, t his va lue sh ould always be programm ed to be
1 more than the desired value and should never be programmed to either 0 or 1.
Table 105. SerDes Tx Driver Power Level Ports 0-6 ($ 0x784)
Bit Name Description Type1Default
Register Description: Allows selection of various programmable drive strengths on each of
the Ser D es ports.
NOTE: Ref er to Table 21, “SerDes Driver TX Power Levels” on page 72 for valid SerDes
pow er le ve ls . 0X00000000
31:28 Reserved Reserved R 0x0
27:25 DRVPWR6[3:0] Encod e d input t h at sets Powe r Level fo r Po rt 6 R /W 1101
24:21 DRVPWR5[3:0] Encod e d input t h at sets Powe r Level fo r Po rt 5 R /W 1101
20:16 DRVPWR4[3:0] Encod e d input t h at sets Powe r Level fo r Po rt 4 R /W 1101
15:12 DRVPWR3[3:0] Encod e d input t h at sets Powe r Level fo r Po rt 3 R /W 1101
11:8 DRVPW R2 [3:0] Encoded inp ut that s e ts Power Level for Port 2 R/W 11 0 1
7 :4 DRVPWR 1[3:0] Encod e d input t h at sets Powe r Level fo r Po rt 1 R /W 1101
3 :0 DRVPWR 0[3:0] Encod e d input t h at sets Powe r Level fo r Po rt 0 R /W 1101
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
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Ta b le 106. SerDes Tx Dri ver Power Level Po rts 7-9 ($ 0x785)
Bit Name Description Type1Default
Register Description : Allow s sele ction of various prog ramm able drive stre ngths on eac h of
the SerDes ports.
NOTE: Refer to Table 21, “Se rDes Driver TX Power Levels ” on page 72 for valid SerDe s
po wer leve ls. 0X00000000
31:12 Reserved Reserved R 0x00000
11:8 DRVPWR9[3:0] Encoded input that sets Power Level for Port 9 R/W 1101
7:4 DRVPWR8[3:0] Encoded input that sets Power Level for Port 8 R/W 1101
3:0 DRVPWR7[3:0] Encoded input that sets Power Level for Port 7 R/W 1101
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
Table 107 . SerDes TX and RX Power -D own Po rts 0-9 ($ 0x787)
Bit Name Description Type1Default
Register Description : Tx and Rx power-down bits to allow per-port power-down of unused
ports 0x00000000
31:20 Reserved Reserved R 0x000
19:10 TPWRDWN[9:0] Tx power-down for Ports 0-9
(1 = Powe r-down) R/W 0000000000
9:0 RPWRDWN[9:0] Rx power-down for Ports 0-9
(1 = Powe r-down) R/W 0000000000
1. R = Read Only; CoR = Clear on Read; W = W rite; R/W = Read/Write
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
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8.5.9 Optical Module Interface Block Register Overview
Table 108 through Table 111 provide a n overvie w of the Optic al Module Inte rface Bloc k Re gister s.
These registers provi de a means to control and monitor the interface to the opt ical modules.
Tabl e 108. Optical Modu le Status Ports 0-9 ($ 0x799)
Bit Name Description Type1Default
Register Description: This register provides optical mo dule statu s information. 0x 0000 0000
31:30 Reserved Reserved R 00
29:20 RX_ LOS_ 9:0 RX_LOS inpu ts for Ports 0-9 R 0000000000
19 :10 TX_FAULT_9:0 TX _FAULT inpu ts for Por ts 0-9 R 00000 00000
9: 0 MOD _ D EF_9:0 MOD _ DE F input s for P or ts 0-9 R 00 00000 000
1. R = Read Only; CoR = Clear on Read; W = Write only; R/W = Read/W rite
Table 109. Op tical Modu le Contro l Ports 0-9 ($ 0x79A)
Bit Name Description Type1Default
Register Description: This register pro v ides access to optic al mo dule interrupt enables and
sets the TX_DISABLE outputs. 0x00000000
31:13 Reserved Reserved R 0000000000
000000000
12 RX_LOS_En Enable for RX_LOS_Int operation
0 = Disable d
1 = Enabled R/W 0
11 TX_FAULT_En Enable for TX _FAULT_Int operation
0 = Disable d
1 = Enabled R/W 0
10 MOD_DEF_En Enable for MOD _DEF_Int oper ation
0 = Disable d
1 = Enabled R/W 0
9:0 TX_DISABLE_9:0 TX_DISABLE outputs for Ports 0-9 R/W 0000000000
1. R = Read Only; CoR = Clear on Read; W = Write only; R/W = Read/W rite
Table 110. I2C Co ntro l Ports 0-9 ($ 0x79B) (Sheet 1 of 2)
Bit Name Description Type1Default
Register Description: This register controls I2C Reads and Write s . 0x000 00000
31:29 Reserved Reserved R 000
28 Port Address
Error Po rt Addr ess Error is set t o 1 when an access is
requested to por t address > 0x9. R0
27 WP_Err Write Protect error is set to 1 when a write access is
requested to Dev ice ID = 0xA and R egis ter Address
[10:8] = 0. T his ad dress combi nation i s used solely
for the read only optical module.
R0
1. R = Read Only; CoR = Clear on Read; W = Write only; R/W = Read/W rite
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26 no_ack-err This bit is set to 1 when a optical module has failed
to assert an ackn ow led ge cyc le. This signal should
be used to validate the data being read. Data is only
valid if this bit is equal to zero. R0
25 I2CEnable Enables device wide I2C Accesses (Enabled = 1) R/W 0
24 I2C Start I2C S tart = 1 will initiate the I2C cycle. This bit is clear
on read. CoR 0
23 Reserved Reserved R 0
22 Write Complete Write Complete is set to a 1 when the byte write
cycle ha s co mple ted. R0
21 Reserved Reserved R 0
20 Read Valid Read Vali d is set to a 1 w hen v alid data is ava ila ble
in the DataRead7:0 field. R0
19:16 Port Add ress
Select 3:0 IXF1110 port address to be accessed R/W 0x0
15 Read/Write 0 = Writ e
1 = Rea d R/W 1
14:11 Device ID Most significant 4 bits of Device ID/Address field. R/W 0xA
10:0 Register
Address
Bits 10:8 define least significant 3 bits of Device ID/
Addr ess field.
Bit s 7:0 define the regi ster addre ss. R/W 00000000000
Table 111. I2C Data Po rts 0-9 ($ 0x79C)
Bit Name Description Type1Default
Register Description : This register provi des I2C Re ads an d Writes. 0x00000000
31:24 Reserved Reserved R 0x00
23:1 6 Writ e Data Writ e_ Dat a co nt a ins t he dat a t o be writ t en dur ing th e
I2C byte write cycle. R/W 0x00
15:8 Reserved Reserved R 0x00
7:0 Read_Data Read_Data contains the byte received during the
la s t I2C Read Cycle. R0x00
1. R = Read Only; CoR = Clear on Read; W = W rite only; R/W = Read/Write
Table 110. I2C Control Ports 0-9 ($ 0x79B) (Sheet 2 o f 2)
Bit Name Description Type1Default
1. R = Read Only; CoR = Clear on Read; W = W rite only; R/W = Read/Write
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 179
9.0 Mechanical Specif ications
CBGA packa ges are suite d for applications requiring high I/O counts and high ele ctrical
performance. They are recommended for high-p ower ap plicatio ns, having high nois e immunity
requirements.
9.1 Features
•Fli p chip die a ttach; su rfac e m ount second- level interconnect
•Hi gh el ec tr i cal p er f o rm an ce
•High I/O counts
•Area arr ay I/O options
•Multiple power zon e offering s upports core and four ad ditional voltages
•JEDEC-compliant package
9.2 IXF1110 MAC Package Speci f ic s
The IXF1110 MAC uses the following packaging (see Figure 45, “552-Ceramic Ball Grid A rray
(CBGA) Package Specifications” on page 181):
•576-ball BGA package with 6 balls removed diagonally from each corner, for a tota l of 552
balls used measuring 25 mm x 25 mm
•Ball pitch of 1.0 mm
•Overall package dimensions of 25 mm x 25 mm
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
180 Order N umber: 25 0210 , Revision: 009
9.2.1 Markings
Figure 44 illu strates the IXF1110 MAC top la bel marking.
I n contrast to the Pb-Free (RoHS-compliant) package, the non-RoHS -compliant package does not
have the “e1” symbol.
Figu re 44. M ark i ng s
Character Font
Size
0.04 - 0.10”
0.06 - 0.10”
25.0 mm
9.67 x 9.6 mm
25. 0 mm
Pin 1 mark
AAA000AAA
= Intel Pro duc t Nu mber
0.19 - 0.24”
®
0.07 - 0.12”
R
NOTE: * "Pin 1 " does mean a Pin 1 indicator, not an actual mark .
Country
XX
= Intel Silicon revision number, A0, A1, B0 …
Note: Diameter of Tr ademar k Cir cle s are 70 mils.
Height of circles surrounding Pb- r edc e d sy m bo l ar e
equal to overall character height
Substrate PN
= Subs t rate mat erial number (barely v isible )
JJJJJJJJ
= Manufacturing Lot Number
Syww9001
= Intel Finished Process Order (FPO) numbe
r
Country
= Assy plant Country of Or igin
Topside fields not to scale
Diameter of Pin 1 mark is 70 mils,
and is located opposite t he top-side
substrate “Pin 1” identif ier.
QQ
= Qual ity L evel ,
P: Pro to Ty pe, PQ: Potent i al Q ua l ’ab le,
“ ”: Produc t ion (no mar ki n g)
++
++
= Re wo r k In d icator
Syww9001
Back of the die
(Bare Silicon)
Substrate PN
e
1
e
1
= Pb- Reduced indicator (Same as Jedec)
B5304-01
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 181
Figure 45. 552-Ceram ic Ball Grid Array (CBGA) Package Specifications
B0612-01
4.8
4.835
Chip
Substrate
9.6
9.67
(25 ± 0.2)
(25 ± 0.2)
47P6802
Note: All dimensions are in mm.
B0611-02
1
B
2
(25 ± 0.2)
(23)
(25 ± 0.2)
(23)
(23x) TYP
Chip Carrier
A01 Corner
(23x) TYP
(0.91 MAX)
(0.33 MIN)
(Reference)
(0.91 MAX)
(0.33 MIN)
(575X) (ø0.8 ± 0.05)
(I/O Pads)
(Reference)
ø0.20 DA
L S BS
Note: All dimensions are in mm.
= Ball
= No ball
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
07-Oct-2005 Datasheet
Intel® IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
182 Order N umber: 25 0210 , Revision: 009
Figure 46. CBGA Package Side View Diagram
B0610-01
Seating Plane
0.15 C
(4.237 Max)
(3.519 Min)
(3.327 Max)
(2.809 Min)
(2.47 Max)
(2.03 Min)
0.81 ± 0.1
(0.857 Max)
(0.779 Min)
Chip
C4 Encapsulant
Fillet
45L4867 (552)
Solder ball
Note: All dimensions are in mm.
Intel® IXF1110 10-Port 1000 Mbps Ethern et Media Access Controller
Datasheet 07-Oct-2005
Intel® IXF1110 10-Port 1000 M bps Et hernet Media Access Controller
Order Number: 250210, Revision: 009 183
10.0 Product Ordering In fo r m a tion
Ta bl e 112 . Produc t Orderi ng I nf orm at io n
Number Re vi sion S hip Media RoHS-Compli ant
HFIXF1110CC B2 B2 Tra y N
WFIXF1110CC B2 B2 Tray Y
Figure 47. Ordering Information - Sample
HF C1110 CIXF B2
Product Revision
xn = 2 Alphanumeric characters
Temperature Range
A = Ambient (0 – 550C)
C = Commercial (0 – 700C)
E = Extended (-40 – 850C)
Internal Package Designator
L = LQFP
P = PLCC
N = DIP
Q = PQFP
H = QFP
T = TQFP
B = BGA
C = CBGA
E = TBGA
K = HSBGA (BGA with heat slug
Product Code
xxxxx = 3-5 Digit alphanu mer i c
IXA Product Prefix
LXT = PHY layer device
IXE = Switching engine
IXF = Formatting device (MAC/Framer)
IXP = Network processor
Intel Package Designator
B2577-02
