SN54AHCT573, SN74AHCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS243N – OCTOBER 1995 – REVISED JULY 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Inputs Are TTL-Voltage Compatible
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
The ’AHCT573 devices are octal transparent
D-type latches. When the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs.
When LE is low, the Q outputs are latched at the
logic levels of the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low) or the high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
interface or pullup components.
To ensure the high-impedance state during power
up or power down, OE should be tied to VCC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP – N Tube SN74AHCT573N SN74AHCT573N
SOIC DW
Tube SN74AHCT573DW
AHCT573
SOIC
–
DW
Tape and reel SN74AHCT573DWR
AHCT573
40°Cto85°C
SOP – NS Tape and reel SN74AHCT573NSR AHCT573
–
40°C
to
85°C
SSOP – DB Tape and reel SN74AHCT573DBR HB573
TSSOP PW
Tube SN74AHCT573PW
HB573
TSSOP
–
PW
Tape and reel SN74AHCT573PWR
HB573
TVSOP – DGV Tape and reel SN74AHCT573DGVR HB573
CDIP – J Tube SNJ54AHCT573J SNJ54AHCT573J
–55°C to 125°CCFP – W Tube SNJ54AHCT573W SNJ54AHCT573W
LCCC – FK Tube SNJ54AHCT573FK SNJ54AHCT573FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54AHCT573 ...J OR W PACKAGE
SN74AHCT573 . . . DB, DGV, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54AHCT573 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
3212019
910111213
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2D
1D
OE
8Q
7Q 1Q
8D
GND
LE VCC
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54AHCT573, SN74AHCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS243N – OCTOBER 1995 – REVISED JULY 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each latch)
INPUTS OUTPUT
OE LE D Q
L H H H
LHL L
LLX Q
0
H X X Z
logic diagram (positive logic)
OE
To Seven Other Channels
1
11
219
LE
1D
C1
1D 1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 92°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54AHCT573, SN74AHCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS243N – OCTOBER 1995 – REVISED JULY 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54AHCT573 SN74AHCT573
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 0 5.5 0 5.5 V
VOOutput voltage 0 VCC 0 VCC V
IOH High-level output current –8–8 mA
IOL Low-level output current 8 8 mA
∆t/∆vInput transition rise or fall rate 20 20 ns/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C SN54AHCT573 SN74AHCT573
UNIT
PARAMETER
TEST
CONDITIONS
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
VOH
IOH = –50
m
A
45V
4.4 4.5 4.4 4.4
V
V
OH IOH = –8 mA
4
.
5
V
3.94 3.8 3.8
V
VOL
IOL = 50
m
A
45V
0.1 0.1 0.1
V
V
OL IOL = 8 mA
4
.
5
V
0.36 0.44 0.44
V
IIVI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1* ±1
m
A
IOZ VO = VCC or GND 5.5 V ±0.25 ±2.5 ±2.5
m
A
ICC VI = 5.5 V or GND, IO = 0 5.5 V 4 40 40
m
A
∆ICC†One input at 3.4 V,
Other inputs at VCC or GND 5.5 V 1.35 1.5 1.5 mA
CiVI = VCC or GND 5 V 2.5 10 10 pF
CoVO = VCC or GND 5 V 3 pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
†This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range, Vcc = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54AHCT573 SN74AHCT573
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
twPulse duration, LE high 5 5 5 ns
tsu Setup time, data before LE↓3.5 3.5 3.5 ns
thHold time, data after LE↓1.5 1.5 1.5 ns
SN54AHCT573, SN74AHCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS243N – OCTOBER 1995 – REVISED JULY 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD TA = 25°C SN54AHCT573 SN74AHCT573
UNIT
PARAMETER
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
UNIT
tPLH
D
Q
CL=15
p
F
4.2* 6* 1* 6.5* 1 6.5
ns
tPHL
D
Q
C
L =
15
pF
5.1* 7* 1* 9* 1 9
ns
tPLH
LE
Q
CL=15
p
F
4.7* 6.5* 1* 7.5* 1 7.5
ns
tPHL
LE
Q
C
L =
15
pF
5.6* 7.5* 1* 9* 1 9
ns
tPZH
OE
Q
CL=15
p
F
4.1* 6.5* 1* 7* 1 7
ns
tPZL
OE
Q
C
L =
15
pF
5.5* 7.5* 1* 10* 1 10
ns
tPHZ
OE
Q
CL=15
p
F
5.5* 8* 1* 11* 111
ns
tPLZ
OE
Q
C
L =
15
pF
5.4* 8* 1* 9.5* 1 9.5
ns
tPLH
D
Q
CL=50
p
F
5.2 7 1 7.5 1 7.5
ns
tPHL
D
Q
C
L =
50
pF
6.1 8 1 10 1 10
ns
tPLH
LE
Q
CL=50
p
F
5.7 7.5 1 8.5 1 8.5
ns
tPHL
LE
Q
C
L =
50
pF
6.6 8.5 1 10 1 10
ns
tPZH
OE
Q
CL=50
p
F
5.1 7.5 1 8 1 8
ns
tPZL
OE
Q
C
L =
50
pF
6.5 8.5 1 11 111
ns
tPHZ
OE
Q
CL=50
p
F
6.7 9 1 12 1 12
ns
tPLZ
OE
Q
C
L =
50
pF
6.4 9 1 10.5 1 10.5
ns
tsk(o) CL = 50 pF 1.5** 1.5 ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
** On products compliant to MIL-PRF-38535, this parameter does not apply.
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 16 pF
SN54AHCT573, SN74AHCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS243N – OCTOBER 1995 – REVISED JULY 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
3 V
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
W aveform 1
S1 at VCC
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC VOL + 0.3 V
50% VCC ≈0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST S1
3 V
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
From Output
Under Test CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1 VCC
RL = 1 kΩGND
From Output
Under Test CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
VOH – 0.3 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V1.5 V 1.5 V
Figure 1. Load Circuit and Voltage Waveforms
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AHCT573DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74AHCT573DGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74AHCT573DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
SN74AHCT573PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74AHCT573PWRG4 TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Jun-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHCT573DBR SSOP DB 20 2000 367.0 367.0 38.0
SN74AHCT573DGVR TVSOP DGV 20 2000 367.0 367.0 35.0
SN74AHCT573DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74AHCT573PWR TSSOP PW 20 2000 364.0 364.0 27.0
SN74AHCT573PWRG4 TSSOP PW 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Jun-2013
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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