TDC1041 7 IXY TDC1041 Monolithic Digital To Analog Converter 10 Bit, 20Msps, 12ns Settling Time The TDC1041 is a TTL compatible, 10-bit monolithic D/A converter capable of converting digital data into an analog current or voltage at data rates in excess of 20 Mega- samples-per second (Msps). The analog circuitry has been optimized for dynamic performance, with very low glitch energy. The output is able to drive a 50Q load with a 1 Volt output level while maintaining low harmonic distortion. Data registers are incorporated on the TDC1041. This eliminates data skew encountered with external registers and latches and minimizes the glitches that can adversely affect many applications. Features e 10-Bit Resolution 20 Msps Data Rate e TTL Inputs @ Very Low-Glitch With No Track And Hold Circuit Needed Dual +4dBm (1V Into 50Q) Outputs Make Output Amplifiers Unnecessary In Many Applications TB Applications Test Signal Generation Arbitrary Waveform Synthesis Broadcast And Studio Video e High-Resolution A/D Converters Interface Diagram 1 | | D, (MSB) De Dg Dg D, 5 TDC1041 WLLL Djo (LSB) CONV FT VEEA REF+ REF- COMP Agnn Ognp oc OUT+ OUT- Poot | Veep _ 24078A 15 TRW LSI Products Inc. P.0. Box 2472 La Jolla, CA 92038 Phone: (619) 457-1000 FAX: (619) 455-6314 TRW Inc. 1990 40G06718 Rev. B - 9/90 Printed in the U.S.A.TDC1041 7 IX Functional Block Diagram REF+ REFERENCE AMPLIFIER REF- COMP 0, (MSB) 63 MSB DECODE REGISTER CONV LSB DATA REGISTER D4p (88) | CURRENT ; SWITCH ARRAY SEGMENT REFERENCE VOLTAGE 63 UNIFORMLY WEIGHTED MSB CURRENT SWITCHES 6 BINARY WEIGHTED LSB CURRENT SWITCHES 21137B Pin Assignments a 2 SITIOS SLEL RSESNSRS Voc 26 1 18 NC CONV 27 17 Denn FT 28 1} 16 NC Veca 1 15 OUT- REF- 2 11 14 OUT+ REF+ 3 13 Agu COMP 4 1 12 NC SS gree 222 > as a 24080A 28 Leaded Plastic Chip Carrier R3 Package 76 Functional Description General Description The TDC1041 consists of five major circuit Sections: the LSB data register, the MSB decode biock, the decoded MSB register, the current switch array, and the reference amplifier. All data bits are registered just before the current switches to minimize the temporal skew that would generate glitches. Power, Grounds The TDC1041 requires a 5.2V power supply and a +5.0V power supply. The anatog (VEEA) and digital (VEEp) supply voltages should be decoupled from each other, as shown in the Typical Interface Circuit. The Vcc pin should be considered a digital power supply. The 0.1pF decoupling capacitors should be placed as close as possible to the power pins. The inductors are simple ferrite beads and are neither critical in value nor always required. TRW LSI Products Inc.TDC1041 7mItvy Reference and Compensation The TDC 1041 has two reference inputs: REF+ and REF These are the inverting and noninverting inputs of the internal reference amplifier. An externally generated reference voltage is applied to the REF- pin. Current flows into the REF+ pin through an external current setting resistor (RREF). This current is the reference current (IREF) which serves as an internal reference for the current source array. The output current for an input code N from OUT+ is related to IRFF through the following relationship: IREF | =Nx OUT 6 Where N is the value of the input code. This means that with an REF that is nominally 625pA, the full-scale output is 40mA, which will drive a 50Q load in parallel with a 50Q transmission line (25Q total load) with a 1V peak to peak signal. The impedance seen by the REF and REF+ pins should be approximately equal so that the effect of amplifier input bias current is minimized. When driving a 75Q foad, the reference current must be reduced. This can be done by increasing the value of the resistor from REF+ to ground. The internal reference amplifier is externally compensated to ensure stability. A 0.1pF capacitor should be connected between the COMP pin and VEEA. Digital Inputs The data inputs are TTL compatible. One of the effects that leads to degradation of the dynamic performance of the device is the capacitive feedthrough from the digital inputs to the analog output of the device. One method of reducing the effect of capacitive coupling is to slow down the slew rates of the digital inputs. This can be done in many ways, starting with the selection of a jogic family that is no faster than what is needed, and can include the addition of 50Q series resistors to the data lines. TRW LS! Products Inc. Clock and Feedthrough Control The TDC1041 requires a TTL clock signal (CONV). Data is synchronously entered on the rising edge of CONV. The CONV input is ignored in the Feedthrough (FT = HIGH) mode. The Feedthrough (FT) pin is normally held LOW, where the TDC1041 operates in a clocked mode (the output changes only after a clock rising edge). An internal pull- down resistor is provided, and this pin may be left open for clocked operation. For certain applications, such as high-precision successive approximation A/D converters, throughput delay may be more important than glitch performance. In these cases, the FT pin may be brought HIGH, which makes the input registers transparent. This allows the analog output to change immediately and asynchronously in response to the digital inputs. Since skew in the bits of the input word will result in glitches, and will affect settling time, it is recommended that the TDC 1041 be operated in clocked mode for most applications. Analog Outputs Two simultaneous and complementary analog outputs are provided. Both of these outputs are full-power current sources. By loading the current source outputs with a resistive load, they may be used as voltage outputs. QUT+ provides a 0 to -40mA output current (0 to -1V when terminated in 25Q) as the input code varies from 00 0000 0000 to 11 1111 1111. OUT varies ina complemenitary manner from 40 to OmA (-1 to OV when terminated with 25Q) over the same code range. (See the Input Coding Table.) The output current is proportional to the reference current and the input code. No Connect These pins have no internal connection and should be left open for optimal performance. 71 Guap ee TDC1041 artwe Package Interconnections Signal Signal Function Value R3 Package Type Name Pins Power AGND Analog Ground 0.0V 13 OGNOD Digital Ground 0.0V V7 VEEA Analog Supply Voltage -5.2V 1 VEED Digital Supply Voltage .2V 5 VEED Digital Supply Voltage -5.2V 26 Reference REF-- Reference Voltage Input -1.0V 2 REF+ Reference Current Input -625pA 3 COMP Compensation Capacitor O.1pF, see text 4 Data Inputs D1 (MSB) Mast Significant Bit TTL 24 D2 TTL 23 D3 TTL 22 D4 TL 21 D5 TTL 20 De TTL 19 D7 TTL 6 Dg TTL 7 Dg TTL 8 D19 (LSB) Least Significant Bit TTL Feedthrough FT Feedthrough Mode Control TTL 28 Convert CONV Convert (Clock} Input TTL 27 Analog Output OUT+ Analog Output Oto 40mA 4 OUT- Analog Output 40 to OmA 15 No Connect NC No Internal Connection Qpen 10,11,12,16,18,25 Input Coding Table! Input Data MSB LSB OUT+ (mA) VouT+(mvV) OUT- (mA) VouT-(mv) 00 0000 0000 0.000 0.00 40.000 -1000.00 00 0000 0001 0.039 -0.97 39.961 998.05 00 0000 0010 0.078 ~1,95 39.922 ~998.05 e eo e Ort it 19.961 499.03 20.000 800.00 1000 0000 00 20.000 500.00 19.961 499.03 e e e e e e e oe . e e a cf a e 1117:111101 39.922 -998.05 0.078 ~1.95 11171171 10 39.961 999.03 0.039 0.97 W4414111 11 40.000 ~1000.00 0.000 0.0 Note: 1. IREF = 625pA, RLOAD = 252 78 TRW LSI Products Inc.TDC1041 Figure 1. Timing Diagram [ae tgp) ae aa ree tHe tg >e ty INPUT (04.42) CONV \ 'pwH tow, > FT >| toc pe ~< wv 1LSB Se | OUT - )\ 1 [> pv ~W 4 tser mm 1/2 LSB t set 240778 Figure 2. Equivalent Reference and Output Circuits CONVERT, FT & DATA (D4 . 49) Voc Veep INPUT 770 Denn DyReF Veep REF- O- REF+ 1.3V REFERENCE SEGMENT SWITCH Agno TRW LSI Products Inc. VEEA 21139A 79TDC1041 7 Ite Figure 3. Simplified Reference and Output Circuits CURRENT SINK #1 CURRENT SINK #N Figure 4. Output Test Load ~1L_o out. TEST LOAD: +0 OUT REFERENCE REFERENCE oq OUT+ 4 . AMPLIFIER CURRENT d OUT - 070-1 voLT REF "1 5 , : 1 REF - 1 3 ! 21346A Lobos VEEA COMP 21345A Absolute maximum ratings (beyond which the device may be damaged)! Supply Voltages Vcc (measured to Dgnp) -0.5 to +7.0V VEEA (measured to AGND) -7.0 to +0.5V VEEA (measured to VEED) 50 to +50mV VEED (measured to Denp} ~7.0 to +0.5V AGND (measured to Dgno} 0.5 te +0.5V Inputs CONV, FT, 01-19 (measured te DgnpD)2 Vcc +0.5 to -0.5V CONV, FT, D1-19 Current, externally forced3 +3mA REF+, REF-,applied voltage (measured to Agnp!3 VEEA to +0.5V REF+, REF-, current, externally forced3 +3mA Outputs OUT+, OUT-, applied voltage (measured to AGnD)2 2.0 to +2.0V OUT+, OUT-, current, externally forced3 +50mMA Short-circuit duration {single output to GND) unlimited Temperature Operating, ambient (Plastic Package) 20 to +90C (Ceramic Package)........... ~60 to +150C Junction (Plastic Package) +140C (Ceramic Package) +200C Lead, soldering (10 seconds) +300C Storage -65 to +150C Notes: TRW LSI Products Inc. . Abdsolute maximum ratings are limiting values applied individually while other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. Device performance and reliability are guaranteed only if the Operating Conditions are nat exceeded. . Applied voltage must be current limited to specified range. . Forcing voltage must be limited to specified range. Current is specified as conventional current flowing into the device.TDC1041 are f if Operating conditions Temperature Range Standard Parameter Min Nom Max Units Vcc Positive Supply Voltage (Measured to Danp) 475 5.0 5.25 V VEED Negative Supply Voltage (Measured to Denp) 49 6.2 55 Vv VEEA Negative Supply Voltage (measured to AGND) ~49 $8.2 5.5 V VAGND Analog Ground Voltage (Measured to Dgnp) 0.1 0.0 0.1 V VEEA Negative Supply Voltage (Measured to Veep)! -20 0 20 mV tPWL CONV Pulse Width LOW (to Meet Specification) 20 ns tPWH CONV Pulse Width HIGH (to Meet Specifications) 20 ns ts Setup Time, Data to CONV (to Meet Specification) 25 ns tH Hold Time (to Meet Specifications} 1 ns tSF Setup Time, Data to FT 5 ns tHE Hoid Time, Data to FT 28 ns VIL Input Voltage, Logic LOW 0.8 Vv VIH Input Voltage, Logic HIGH 2.0 V VREF Reference Voltage (REF-) 07 1.0 -13 V IREF Reference Current (REF+) 400 625 700 pA Cc Compensation Capacitor 0.01 0.1 uF Ta Ambient Temperature, Still Air 0 70 C Note: 1. A common power supply isolated with ferrite bead inductors is recommended for Vega and VEED. This is shown in the Typical Interface Circuit. Electrical characteristics within specified operating conditions Temperature Range Standard Parameter Test Conditions Min Max Units IEEA+IEED VEEA=VEED=Max, static -180 mA Ta=0 to 70C Ta=70C -150 mA lec Vcc=Max, Static 25 mA Ta=0 to 70C Ta=70C 20 mA Crer Reference Input Capacitance 15 pF Cy Digital Input Capacitance 15 pF Voc Compliance Voltage -1.2 1.2 V Ro Output Resistance 12 kQ Co Output Capacitance 45 pF lo Full-Scale Output Current IREF=Nominal 40 mA lit Input Current, Logic LOW Vcc. VEE=Max , Vj=0.4V -10 50 pA UH Input Current, Logic HIGH Vcc. Vee=Max, V\=2.4V -10 100 pA lIM Input Current, Max Input Voltage Vec.Vee=Max, Vi=Vcc Max ~10 100 pA VtH Logic Input Threshold Voltage,Typical Vec. Veg=Nom, Ta=28C 1.25 1.55 V TRW LSI Products Inc.TDC1041 artwe Switching characteristics Temperature Range Standard Parameter Test Conditions Min Typ Max Units Fo Maximum Data Rate VEEA, VEED. Vc=Min 20 25 MHz toc Clock to Output Delay VEEA, VEED. Vec=Min, FT=-LOW 17 ns tpD Data to Output Delay Veea. VEED. Vec=Min, FT=HIGH 35 ns tDF FT to Output Delay VEEA. VEED, VCc=Min 35 ns tR Risetime 90% to 10% of FSR, FT=LOW 4 ns tf Falltime 10% to 90% of FSR, FT=LOW 4 ns tSET Settling Time, Voitage FT=LOW, Full-Scale Voltage 20 30 ns transition on [QUT to +0.0188%FSR System performance characteristics Temperature Range Standard Parameter Test Conditions Min Typ Max Units ELp Differential Linearity Error VeeA. VEED. [REF = Nom! TDC1041 +0.1 % TDC1041-1 +0.05 % Ey {Integral Linearity Error VEEA, VEED. IREF = Nom! TDC1041 +0.1 % TDC1041-1 10.05 % Vos REF+ to REF- Offset Voltage -10 +10 mV \B REF- input Bias Current 5 pA Eg Absolute Gain Error VEEA. VEED. VCC, IREF= Nom -5 5 % lor Output Offset Current VEEA. VEED. VCc= Min, D1-19=LOW| = -5 +5 A PSRR Power Supply Rejection Ratio VeeA, VEED. Vec.IREF= Nom2 -50 dB PSs Power Supply Sensitivity Vec, VEEA. VEED=4%, IREF= Nom -140 pAN GA Peak Glitch Area 25 45 pV-sec SFOR Spurious Free Dynamic Range IREF=Nom, 20 Msps, 60 dBc 10MHz bandwidth Fout=6MHz Fout=5MHz 70 dBc Fout=2MHz 75 dBc Fout=1MHz 78 dBc Note: 1. OUT-connected to AgNp, OUT driving virtual ground. 2. 120Hz, 0.6Vp-p ripple on Vega and Veep. dB relative to 0.6Vp-p ripple input. 82 TRW LSI Products Inc.TDC1041 7 IXY Applications Information There are three major D/A architectures: segmented, weighted current sources, and R-2R. In segmented there is one current source for each possible output level. The current sources are equally weighted and for an input code of N, N current sources are turned on. An N bit segmented D/A has 2N current sources. A weighted current source D/A has one current source for each bit of input with a binary weighting for the current sources. In an R-2R D/A, there is one current source per bit, and a resistor network which scales the current sources to have a binary weighting. When transitioning from a code of 0111111111 to 100000000000, both the R-2R D/A and Binary weighted D/A are turning some current sources on while turning others off. If the timing is not perfect, there is a moment where all current sources are either on or off, resulting in a glitch. In a segmented architecture, 511 of the current sources remain on, and one more is turned on to increment the output no possibility of a glitch. The TDC1041 uses a hybrid architecture with the 6 MSBs segmented, and the 4 LSBs from a R-2R network. The result is a converter which has very low-glitch energy, and a moderate die size. Layout, Power and Grounding The layout of grounds in any system is an important design consideration. Separate analog and digital grounds are provided at the TDC1041. All ground pins should be connected to a common low-noise, low-impedance groundplane. This groundplane should be common for the TDC1041 and all of its immediate interface circuitry, which includes all of the reference circuitry, the output load circuitry, and all of the power supply decoupling components. The digital driving logic should use a separate system ground, and this ground shauld be connected (typically through a ferrite bead inductor} to the analog groundplane in only one place. The analog and digital grounds may be connected in other ways if required by the user's system grounding plan, however, the voltage differential between the AGND and Denp pins must be held to within 40.1 Volts. Direct Digital Synthesis Applications There are many factors that can influence the system performance of a direct digital synthesizer. The following TRW LSI Products Inc. comments are directed at getting the best possible performance from the TDC1041, as measured by Spurrious Free Dynamic Range (SFDR). The termination of the output pins has an effect on DAC performance. For most synthesis applications, optimum signal purity is obtained with the use of a balun (a simple RF transformer made by wrapping a few turns of wire around a ferrite core). This configuration has the benefit of cancelling common mode distortion. Harmonic distortion may improve even further with reduced @m AC termination impedance values, at the expense of lowered output voltage. An output amplifier is not recommended because any amplifier will add extra distortion of its own, which is likely to be rnuch greater than that present from the direct outputs of the TDC1041. One detrimental! effect in DAC performance is capacitive coupling of the digital data into the output terminal. The actual digital-data waveform which represents a sine wave contains strong harmonics of that sine wave. This can be seen by connecting a digital data line to the input of an analog spectrum analyzer. Therefore data feedthrough to the analog output of a system due to improper board jayout or system shielding and grounding will appear as additional harmonic distortion, adversely affecting SFDR. The strict acherence to at least the minimum input data setup and hold times is important for the realization of the optimal performance. Spur levels may decrease as setup and hold times are increased. It is possible to achieve even higher performance in some instances by carefully tuning the input data setup and hold times (slightly delaying or advancing the CONV signal in relation to the data) fed to the TDC1041. The Operating conditions table has two sets of data for ts and ty, one which guarantees performance of the device in most applications, and one, more conservative specification which has been found to be optimal for DDS applications. The purity of the output of the TDC1041 is greater than that which can be measured by many spectrum analyzers. The spectral plots shown in this data sheet were generated with an HP8568B, which has a noise floor barely below that of the TDC1041, once the TDC1041 performance has been optimized. When making spectral measurements it is important to remember that the TDC1041 output power is +4dBm, which is greater power than many analyzers areTDC1041 fmt equipped to handle without adding distortion of their own. Accordingly, it may be necessary to introduce an attenuator to the input of the spectrum analyzer to see the true DAC perfarmance. Output Termination The recommended output termination is 25Q. This can be provided by placing a 50Q source resistor between the output pin and ground, then driving a 50Q transmission line. With this load, the output valtage range of the converter is 0 to -1.0V. If a load is capacitively coupled to the TDC 1041, it is recommended that a 25Q load at DC, as seen by the TDC1041, continue to be maintained. The output voltage should be kept within the output compliance voltage range, Vgc, as specified in the Electrical Characteristics table, or the accuracy may be impaired. Optimum DC linearity is obtained by using a differential output either with a balun, or an operational amplifier in the differential mode. ff it is desired that the 1DC1041 be operated in a single ended fashion, the unused output should be connected directly to ground as is shown in Figure 5. The CONV signal provided to the TDC1041 must be as free from clock jitter as possible. Ctock jitter is the random cycle-to- cycle variation in clock period. CONV clock jitter will effectively appear at the output as phase noise. A value of 10ps or less for clack jitter is recommended for the highest performance applications. Ordinary crystal oscillators are satisfactory. High- performance synthesizers, such as the HP8662, used to trigger a precision pulse generator, are also satisfactory, although not as jitter free as a crystal oscillator. Driving a 75Q Transmission line The TDC1041 has been optimized to operate with a reference current of 625pA. Significantly increasing or decreasing this current may degrade the performance of the device. If it is desired that the device drive a 37.52 load (75Q source termination driving 75Q transmission line) rather than the 25Q suggested load, then VRFF should be held at 1V and IREF reduced to 417pA. This will result in a 1V p-p voltage being generated at the DAC output. TRW LSI Products Inc.TDC1041 arty Figure 5. Typical Interface Circuit 22K TDC4611 1.5K D, (MSB) ~5V 74US8377 Tpc1041 Dg D4p (LSB) louT- FT Veep Yeea OGnp Acnp 7ALS377 24091A GND TRW LSI Products Inc. 85TDC1041 7 mtvy Ordering Information Product Number Temperature Range Screening Package Package Marking JTDC1041R3C Ta=0C to 70C Commercial Plastic Chip Carrier 1041R3C TDC1041R3C1 Ta=0C to 70C Commercial Plastic Chip Carrier 1041R3C1 All parameters contained in this specification are guaranteed by design, characterization, sample testing or 100% testing as appropriate. TRW reserves the right to change products and specifications without notice. This information does not convey any license under patent rights of TRW Inc. or others. Life Support Policy TRW LSI Praducts Inc. components are not designed for use in life support applications, wherein a failure or malfunction of the component can reasonably be expected to result in personal injury. The user of TRW LSI Products Inc. components in life support applications assumes all risk of such use and indemnifies TRW LSI Praducts Inc. against all damages. Absalute maximum ratings are limiting values applied individually while other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. Device performance and reliability are guaranteed only if the Operating Conditions are not exceeded. Applied voitage must be current limited to specified range. Forcing voltage must be limited to specified range. Current is specified as conventional current flowing into the device. TRW LS! Products Inc.