24AA64XT/ST - Microchip Technology, Inc.

 2000 Microchip Technology Inc. DS21189D-page 1

DEVICE SELECTION TABLE

FEATURES

• Low power CMOS technology

- Maximu m w rite curr ent 3 mA at 5.5V

- Maximum read current 400 µA at 5.5V

- Standby current 100 nA typical at 5.5V

• 2-w ire serial int erfa ce b u s , I2C compatible

• Cascadable for up to eight devices

• Self-timed ERASE/WRITE cycle

• 32-byte page or byte write modes available

• 5 ms max write cycle time

• Hardware write protect for entire array

• Output slope control to eliminate ground bounce

• Schmitt trigger inputs for noise suppression

• 1,000,000 erase/write cycles guaranteed

• Electrostatic discharge protection > 4000V

• Data retention > 200 years

• 8-pin PDIP, SOIC (150 and 208 mil) and TSSOP

packages

• Tempera ture range s:

DESCRIPTION

The Microchip Technology Inc. 24AA64/24LC64

(24xx64*) is a 8K x 8 (64K bit) Serial Electrically Eras-

able PROM capable of operation across a broad volt-

age range (1.8V to 5.5V). It has been developed for

advanced, low power applications such as personal

communications or data acquisition. This device also

has a page-write capability of up to 32 bytes of data.

This device is capable of both random and sequential

reads up to the 64K bound ary. Functional add ress lines

allo w up to eigh t devi ces on the s ame bus , for up to 51 2

Kbits address space. This device is available in the

standard 8-pin plastic DIP, 8-pin SOIC (150 and

208 mil), and 8-pin TSSOP.

PACKAGE TYPE

BLOCK DIAGRAM

Part

Number Vcc

Range Max Clock

Frequency Temp

Ranges

24AA64 1.8-5.5V 400 kHz †C

24LC64 2.5-5.5V 400 kHz I, E

†100 kHz for Vcc < 2.5V.

- Commercial (C): 0°to 70°C

- Industrial (I): -40°Cto +85°C

- Automotive (E) -40°C to +125°C

Vss

Vcc

SCL

SDA

24xx64 24xx64

8-LEAD PDIP

8-LEAD TSSOP

Vcc

SCL

SDA

Vss

Vcc

SCL

SDA

24xx64

8-LEAD SOIC

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

I/O

CONTROL

LOGIC

A0 A1 A2 WP

SDA

SCL

VCC

VSS

I/O

MEMORY

CONTROL

LOGIC

I2C is a trademark of Philips Corporation.

*24xx64 is used in this document as a generic part number for the 24AA64/24LC64 devices.

24AA64/24LC64

64K I2C™CMOS Serial EEPROM

24AA64/24LC64

DS21189D-page 2  2000 Microchip Technology Inc.

1.0 ELECTRICAL

CHARACTERISTICS

1.1 Maximum Ratings*

Vcc.................................................................................................7.0V

All inputs and outputs w.r.t. Vss ..............................-0.6V to Vcc +1.0V

Storage temperature ...................................................-65°C to +150°C

Ambient temp. with power applied ..............................-65°C to +125°C

Soldering temperature of leads (10 seconds)...........................+300°C

ESD protec ti on on all pins .................................................................≥ 4 kV

*Notice: Stresses above those listed under “Maximum Ratings” may

cause permanent damage to the device. This is a stress rating only and

functional operation of the device at those or any other conditions

above those indicated in the operati onal listin gs of this spe cificat ion is

not implied. Exposure to maximum rating conditions for extended peri-

ods may affect device reliability.

TABLE 1-1 PIN FUNCTION TABLE

FIGURE 1-1: BUS TIMING DATA

Name Function

A0,A1,A2 User Configurable Chip S elect s

VSS Ground

SDA Serial Da ta

SCL Serial Clock

WP Write Protect Input

VCC +1.8 to 5.5V (24AA64)

+2.5 to 5.5V (24LC64)

TABLE 1-2 DC CHARACTERISTICS

All parameters apply across the rec-

ommended operating ranges unless

otherwise noted.

Commercial (C): VCC = +1.8V to 5.5V Tamb = 0°C to +70°C

Industrial (I): VCC = +2.5V to 5.5V Tamb = -40°C to +85°C

Automotive (E): VCC = +2.5V to 5.5V Tamb = -40°C to 125°C

Parameter Symbol Min Max Units Conditions

A0, A1, A2,

SCL, SDA, and WP pins:

High level in put volta ge VIH 0.7 VCC —V

Low level input vol tage VIL —0.3 VCC

0.2 VCC V

VVCC ≥ 2.5V

VCC < 2.5V

Hysteresis of Schmitt Trigger

inputs (SDA, SCL pins) VHYS 0.05 VCC —VVCC > 2.5V (Note)

Low level outpu t voltag e VOL —0.40 V IOL = 3.0 mA @ VCC = 4.5V

IOL = 2.1 mA @ VCC = 2.5V

Input leakage current ILI -10 10 µAVIN = Vss to VCC, WP = VSS

VIN = Vss or VCC, WP = VCC

Output lea kage curre nt ILO -10 10 µAVOUT = Vss to VCC

Pin capacitance

(all inputs /ou tpu ts) CIN, COUT —10 pF VCC = 5.0V (Note)

Tamb = 25°C, fc= 1 MHz

Operat ing current ICC Write —3mAVCC = 5.5V

ICC Read —400 µA VCC = 5.5V, SCL = 400 kHz

Standby current ICCS —1 µA SCL = SDA = VCC = 5.5V

A0, A1, A2, WP = VSS

Note: This parameter is periodically sampled and not 100% tested.

WP (unprotected)

(protected) TSU:WP THD:WP

SCL

SDA

TSU:STA

SDA

OUT

THD:STA

TLOW

THIGH TR

TBUF

TAA

THD:DAT TSU:DAT TSU:STO

TSP

TFVHYS

 2000 Microchip Technology Inc. DS21189D-page 3

24AA64/24LC64

TABLE 1-3 AC CHARACTERISTICS

All parameters apply across the spec-

ified operating ranges unless other-

wise noted.

Commercia l (C): VCC = +1.8V to 5.5V Tamb = 0°C to +70°C

Industrial (I): VCC = +2.5V to 5.5V Tamb = -40°C to +85°C

Automotive (E): VCC = +2.5V to 5.5V Tamb = -40°C to 125°C

Parameter Symbol Min Max Units Conditions

Clock frequency FCLK —

—100

400 kHz 1.8V ≤ VCC ≤ 2.5V

2.5V ≤ VCC ≤ 5.5V

Clock high time THIGH 4000

600 —

—ns 1.8V ≤ VCC ≤ 2. 5V

2.5V ≤ VCC ≤ 5.5V

Clock low time TLOW 4700

1300 —

—ns 1.8V ≤ VCC ≤ 2. 5V

2.5V ≤ VCC ≤ 5.5V

SDA and SCL rise time

(Note 1) TR—

—1000

300 ns 1.8V ≤ VCC ≤ 2. 5V

2.5V ≤ VCC ≤ 5.5V

SDA and SCL fall time TF—300 ns (Note 1)

START condition hold time THD:STA 4000

600 —

—ns 1.8V ≤ VCC ≤ 2. 5V

2.5V ≤ VCC ≤ 5.5V

START condition setup time TSU:STA 4700

600 —

—ns 1.8V ≤ VCC ≤ 2. 5V

2.5V ≤ VCC ≤ 5.5V

Data input hold time THD:DAT 0—ns (Note 2)

Data input setup time TSU:DAT 250

100 —

—ns 1.8V ≤ VCC ≤ 2. 5V

2.5V ≤ VCC ≤ 5.5V

STOP condition setup time TSU:STO 4000

600 —

—ns 1.8V ≤ VCC ≤ 2. 5V

2.5V ≤ VCC ≤ 5.5V

WP setup time TSU:WP 4000

600 —

—ns 1.8V ≤ VCC ≤ 2. 5V

2.5V ≤ VCC ≤ 5.5V

WP hold time THD:WP 4000

1300 —

—ns 1.8V ≤ VCC ≤ 2. 5V

2.5V ≤ VCC ≤ 5.5V

Output valid from clock

(Note 2) TAA —

—3500

900 ns 1.8V ≤ VCC ≤ 2. 5V

2.5V ≤ VCC ≤ 5.5V

Bus free tim e : Tim e the bus must be

free before a new transmission can

start

TBUF 4700

1300 —

—ns 1.8V ≤ VCC ≤ 2. 5V

2.5V ≤ VCC ≤ 5.5V

Output fa ll time from VIH

minimum to VIL maximum TOF 10 250 ns CB ≤ 100 pF (Note 1)

Input filter spike suppression

(SDA and SCL pins) TSP —50 ns (Notes 1 and 3)

Write cycle time (byte or page) TWC —5ms

Endurance 1M —cycles 25°C, VCC = 5.0V, Block Mode (Note 4)

Note 1: Not 100% tested. CB = t ot al capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum

300 ns) of the falling edge of SCL to av oid unintended generation of START or ST OP conditions.

3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike

suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but guarant eed by characterization. For endurance estimates in a specific application, please

consult the Total Endurance Model which can be obtained on Microchip’s BBS or website.

24AA64/24LC64

DS21189D-page 4  2000 Microchip Technology Inc.

2.0 PIN DESCRIPTIONS

2.1 A0, A1, A2 Chip Address Inputs

The A0,A1,A2 inputs are used by the 24xx64 for multi-

ple device operation. The levels on these inputs are

compared with the corresponding bits in the slave

address. The chip is selected if the compare is true.

Up to ei ght de vic es may be conn ected t o the sa me b u s

by using different chip select bit combinations. These

inputs must be connected to either VCC or VSS.

2.2 SDA Serial Data

This is a bi-directional pin used to transfer addresses

and data into and data out of the device. It is an open-

drain te rminal, ther efore, the SD A b us requires a pullup

resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for

400 kHz)

F or normal data transfe r SD A is allo wed to change onl y

during SCL low. Changes during SCL high are

reserved for indicating the START and STOP condi-

tions.

2.3 SCL Serial Clock

This i nput i s us ed to synch roniz e th e dat a tr ansfer from

and to the device.

2.4 WP

This pin can be connected to either Vss, Vcc or left

floating. An internal pull-down resistor on this pin will

keep the device in the unprotected state if left floating.

If tied to Vss or left floating, normal memory operation

is enabled (read/write the entire memory 0000-1FFF).

If tied to VCC, WRITE operations are inhibited. Read

operations are not affected.

3.0 FUNCTIONAL DESCRIPTION

The 24xx64 supports a bi-directional 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as a transmitter, and a device

receiving data as a receiver. The bus must be con-

trolled by a master device which generates the serial

clock (SCL), controls the bus access, and generates

the START and STOP conditions while the 24xx64

works as a slave. Both master and slave can operate as

a transmitter or receiver but the master device deter-

mines which mode is activated.

4.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

•Data transfer may be initiated only when the bus

is not busy.

•During data transfer, the data li ne must remain

stable whene ver the clo ck line is HI GH. C han ges

in the data line whil e t he clock line is HIGH will be

interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been

defined (Fig ure 4-1).

4.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

4.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

comma nds mu st be preced ed b y a START condi tion .

4.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the

clock (S CL ) i s HI G H de term in es a S TOP cond it ion . All

operations must end with a STOP condition.

4.4 Data Val id (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the cl oc k si gnal. T here is on e clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP conditio n. T he n um ber of

the data bytes transferred between the START and

STOP conditions is det erm ined by the master device.

4.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge signal after the reception of

each byte. The master device must generate an extra

clock pulse which is associated with this acknowledge

bit.

A device that acknowledges must pull down the SDA

line during the acknowledge clock pulse in such a way

that the SD A line is stab le LO W during the HIGH period

of the acknowledge related clock pulse. Of course,

setup and hold times must be taken into account. Dur-

ing reads, a master must signal an end of data to the

slave by NO T generating an acknowledge bit on the last

by te that has been cloc ked out of the slav e. In this case ,

the slave (24xx64) will leave the data line HIGH to

enable the master to generate the STOP condition.

Note: The 24xx64 does not generate any

acknowledge bits if an internal program-

ming cyc le is in prog r ess.

 2000 Microchip Technology Inc. DS21189D-page 5

24AA64/24LC64

FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 4-2: ACK NOWLEDGE TIMING

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

START

CONDITION

SCL

SDA

(A) (B) (D) (D) (C) (A)

SCL 987654321 123

Transmitter must release the SDA line at this point

allowing the Receiver to pull the SDA line low to

acknowledge the previous eight bits of data.

Receiver must release the SDA line at this point

so the Transmitter can continue sending data.

Data from transmitter Data from transmitter

SDA

Acknowledge

Bit

24AA64/24LC64

DS21189D-page 6  2000 Microchip Technology Inc.

5.0 DEVICE ADDRESSING

A control byte is the first byte received following the

start condit ion from t he master devi ce (Figu re 5-1). Th e

control byte consists of a four bit control code; for the

24xx64 this is set as 1010 binary for read and write

operations. The next three bits of the control byte are

the chip select bits (A2, A1, A0). The chip select bits

allow the use of up to eight 24xx64 devices on the

same bus and are used to select which device is

access ed . Th e ch ip se lect b its in t h e con t rol byte must

corresp ond to the l ogic le v els o n the correspo nding A2,

A1, a nd A0 pi ns for th e devic e to res pond. T hese bi ts

are in effect the three most significant bits of the word

address.

The last bit of the control byte defines the operation to

be performed. When set to a one a read operation is

selected, and when set to a zero a write operation is

selected. The next two bytes received define the

address of the first data byte (Figure 5-2). Because

only A12...A0 are used, the upper three address bits

are don’t care bits. The upper address bits are trans-

ferred first, followed by the less significant bits.

Fol lowing the star t c ondition , the 24xx64 m onitor s the

SDA bus checking the device type identifier being

tra nsmit ted. Up on rece iving a 1010 co de and ap propri-

ate device select bits, the slave device outputs an

acknowledge signal on the SD A line. Depending on the

state of the R/W bit, the 24xx64 will select a read or

write operation.

FIGURE 5-1: CONTROL BYTE FORMAT

5.1 Contiguous Addressing Across

Multiple Devices

The chip select bits A2, A1, A0 can be used to expand

the contiguous address space for up to 512K bits by

adding up to eight 24xx64's on the same bus. In this

case, software can use A0 of the control byte as

address bit A13, A1 as address bit A14, and A2 as

address bit A15. It is not possible to sequentially read

across device boundaries.

FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS

1 0 1 0 A2 A1 A0SACKR/W

Control Code Chip Select

Bits

Slave Addr ess

Acknowledge Bit

Start Bit

Read/Write Bit

1010A

0R/W XXX A

11 A

10 A

8••••••

CONTROL BYTE ADDRESS HIGH BYTE ADDRESS LOW BYTE

CONTROL

CODE CHIP

SELECT

BITS X = Don’t Ca re Bi t

 2000 Microchip Technology Inc. DS21189D-page 7

24AA64/24LC64

6.0 WRITE OPERATIONS

6.1 Byte Write

Following the start condition from the master, the

control code (four bits), th e chi p sel ec t (three bits), an d

the R/W bi t (which is a logic low) are clocked onto the

bus by the master transmitter. This indicates to the

address ed sla ve receiv er that the address high b yte will

follo w af ter i t has generated an acknowled ge b it d uring

the ninth cl oc k cycle. Therefore , the ne x t by te trans mit-

ted by the master is the high-order byte of the word

address and will be written into the address pointer of

the 24xx64. The next byte is the least significant

address byt e. After re ceiving another ac kno wledge sig-

nal from the 24xx64 the master device will transmit the

data word to be written into the addressed memory

location. The 24xx64 acknowledges again and the

master generates a stop condition. This initiates the

internal write cy cle, and during t his time the 24xx6 4 will

not generate acknowledge signals (Figure 6-1). If an

attempt is made to write to the array with the WP pin

held high, the device will acknowledge the command

but no write cycle w i ll oc cu r, no data w i ll be written an d

the device will immediately accept a new command.

After a byte write command, the internal address

counter will point to the address location following the

one that was just written.

6.2 Page Wr ite

The write control byte, word address and the first data

byte are transmitted to the 24xx64 in the same way as

in a byte write. But instead of generating a stop condi-

tion, the master transmits up to 31 additional bytes

which are te mp orarily st ored in the on-chi p page buff er

and will be written into memory after the master has

tran smitted a sto p condition. A fter receipt of ea ch word,

the five lower addres s pointer bits are internally incre-

mented by one . If the master shou ld transmi t more than

32 bytes prior to generating the stop condition, the

address counter will roll over and the previously

received data will be overwritten. As with the byte write

oper ation , once the stop condi tion i s rece iv ed, an int er-

nal write cycle will begin (Figure 6-2). If an attempt is

made to write to the arr ay with the WP pin held high, the

device will acknowledge the command but no write

cycle will occur, no data will be written and the device

will immediately accept a new command.

6.3 Write Protection

The WP pin allows the user to write protect the entire

array (0000-1FFF) w hen the pin is tied to Vcc. If tied to

VSS or left floati ng, the write p rote ction is disa bl ed. Th e

WP pin is sam pled at the ST O P bit for e v ery write com-

mand (Figu re 1-1) Toggling the WP pin aft er the STOP

bit will have no effect on the e xecution of the write cycle.

FIGURE 6-1: BYTE WRITE

FIGURE 6-2: PAGE WRITE

XXX

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE ADDRESS

HIGH BYTE ADDRESS

LOW BYTE DATA

X = don ’t care bit

S1010 0

XXX

BUS ACTIVITY

MASTER

SD A LINE

BUS ACTIVITY

CONTROL

BYTE ADDRESS

HIGH BYTE ADDRESS

LOW BYTE D ATA BYTE 0

D ATA BYTE 31

X = don’t care bit

S1010 0

24AA64/24LC64

DS21189D-page 8  2000 Microchip Technology Inc.

7.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the master, the device ini-

tiates the internally timed write cycle. ACK polling can

be initi ated immedi ately. This inv olv es the mas ter send-

ing a star t condition followed by the control byte for a

write comm and (R/W = 0). If the device is still busy with

the write cy cle, th en no A CK will be ret urned. If no A CK

is returned, then the start bit and control byte must be

re-sent. If the cycle is complete, then the device will

return the ACK and the master can then proceed with

the next read or write command. See Figure 7-1 for

flow diagram.

FIGURE 7-1: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did De vice

Acknowledge

(ACK = 0)?

Operation

YES

 2000 Microchip Technology Inc. DS21189D-page 9

24AA64/24LC64

8.0 READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

control byte is set to one. There are three basic types

of read operations: current address read, random read,

and sequential read.

8.1 Current Address Read

The 24xx64 contains an address counter that main-

tains the address of the last word accessed, intern ally

incremented by one. Therefore, if the previous read

access was to address n (n is any legal address), the

ne xt curren t addres s read oper ation w ould acce ss data

from address n + 1.

Upon rec eipt of the cont rol b yte with R/W bi t set to one ,

the 24xx64 issues an acknowledge and transmits the

eight bit data word. The master will not acknowledge

the tr ansf er b ut does gener at e a sto p cond ition a nd the

24xx64 discontinues transmission (Figure 8-1).

FIGURE 8-1: CURRENT ADDRESS READ

8.2 Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, first the word address must

be set. This is done b y sending the w ord addres s to the

24xx64 as part of a write operation (R/W bit set to 0).

After the word address is sent, the master generates a

start condition following the acknowledge. This termi-

nates the write operation, but not before the internal

address pointer is set. Then the master issues the

control b yte again b ut with the R/W bit set to a one. The

24xx64 will then issue an acknowledge and transmit

the 8-bit data word. The master will not acknowledge

the transfer but does generate a stop condition which

causes the 24xx64 to discontinue transmission

(Figure 8-2). After a random read command, the inter-

nal address counter will point to the address location

following the one that was just read.

8.3 Sequential Read

Sequenti al reads are initiated in the same wa y as a ran-

dom read except that after the 24xx64 transmits the

first data byte, the master issues an acknowledge as

oppos ed to the stop conditi on us ed in a rand om re ad.

This acknowledge directs the 24xx64 to transmit the

next sequentially addressed 8-bit word (Figure 8-3).

Following the final byte transmitted to the master, the

master w ill NO T generate an ac knowl edge b ut will gen-

erate a stop condition. To provide sequential reads the

24xx64 contains an internal address pointer which is

incremented by one at the completion of each opera-

tion. This address pointer allows the entire memory

contents to be serially read during one operation. The

internal addres s pointe r will auto matical ly roll o ve r from

address 1FFF to address 0000 if the master acknowl-

edges the byte received from the array address 1FFF.

FIGURE 8-2: RANDOM READ

FIGURE 8-3: SEQUENTIAL READ

BUS ACTI VITY

MASTER

SD A LINE

BUS ACTI VITY

CONTROL

BYTE

DATA

1100

AAA1

BYTE

210

XXX

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY A

CONTROL

BYTE ADDRESS

HIGH BYTE ADDRESS

LOW BYTE CONTROL

BYTE DATA

BYTE

X = Don’t Care Bi t

S1010AAA0

210 S1010AAA1

210 P

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X

24AA64/24LC64

DS21189D-page 10  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. DS21189D-page 11

24AA64/24LC64

24xx64 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Sales and Support

Package: P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body, EIAJ standard), 8-lead

SM = Plastic SOIC (208 mil Body, EIAJ standard), 8-lead

ST = TSSOP, 8-lead

Temperature

Range: Blank = 0°C to +70°C

I=-40°C to +85°C

E=-40°C to +125°C

Device:

24AA64 64K bit 1.8V I2C Serial EEPROM

24AA64T 64K bit 1.8V I2C Serial EEPROM (Tape and Reel)

24AA64X 64K bit 1.8V I2C Serial EEPROM

in alternate pinout (ST only)

24AA64XT 64K bit 1.8V I2C Serial EEPROM

in alternate pinout (ST only)

24LC64 64K bit 2.5V I2C Serial EEPROM

24LC64T 64K bit 2.5V I2C Serial EEPROM (Tape and Reel)

24LC64X 64K bit 2.5V I2C Serial EEPROM

in alternate pinout (ST only)

24LC64XT 64K bit 2.5V I2C Serial EEPROM

in alternate pinout (ST only)

24xx64 — /P

Data Sheets

Products supported b y a preliminary Data Sheet ma y have an errata sheet describing minor operational differences and recom-

mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U. S. FAX: (480) 786-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

 2002 Microchip Technology Inc.

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applications and the like is intended through sug gestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

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assumed by Microc hip Technology Inc orporated with respect

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Trademarks

The Microchip name and logo, the Microchip logo, FilterLab,

KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,

PICSTART, PRO MATE, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip T ech-

nology Incorporated in the U.S.A. and other countries.

dsPIC, ECONOMONITOR, FanSense, FlexRO M, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, microPort,

Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,

MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode

and Total Endurance are trademarks of Microchip Technology

Incorporated in the U.S.A.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorpora ted in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and T empe, Arizona in July 1999. The

Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro® 8-bit MCUs, KEELOQ® code ho pp in g

devices, Serial EEPROMs and microperipheral

products. In addition, Microchip’s quality

system for the design and manufacture of

development systems is ISO 9001 certified.

Note the following details of the code protection feature on PICmicro® MCUs.

•The PICmicro family meets the specifications contained in the Microchip Data Sheet.

•Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,

when used in the intended manner and under normal conditions.

•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-

edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.

The person doing so may be engaged in theft of intellectual property.

•Microchip is willing to work with the customer who is concerned about the integrity of their code.

•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable”.

•Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of

our product.

If you have any further questions about this matter, please contact the local sales office nearest to you.

 2002 Microchip Technology Inc.

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200 Fax: 480-792-7277

Technical Support: 480-792-7627

Web Address: http://ww w.microchip .com

Rocky Mountain

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7966 Fax: 480-792-7456

Atlanta

500 Sugar Mill Road, Suite 200B

Atlanta, GA 30350

Tel: 770 -6 40- 003 4 Fax: 770- 640 -03 07

Boston

2 Lan Drive, Suite 120

Westford, MA 01886

Tel: 978 -6 92- 384 8 Fax: 978- 692 -38 21

Chicago

333 Pierce Road, Suite 180

Itasca, IL 60143

Tel: 630-285-0071 Fax: 630-285-0075

Dallas

4570 Westgrove Drive, Suite 160

Addison, TX 7500 1

Tel: 972 -8 18- 742 3 Fax: 972- 818 -29 24

Detroit

Tri-Atria Office Building

32255 Northwestern Highway, Suite 190

Farmington Hills, MI 48334

Tel: 248-538-2250 Fax: 248-538-2260

Kokomo

2767 S. Albright Road

Kokomo, Indiana 46902

Tel: 765-864-8360 Fax: 765-864-8387

Los A n ge les

18201 Von Karman, Suite 1090

Irvine, CA 92612

Tel: 949 -2 63- 188 8 Fax: 949- 263 -13 38

New York

150 Motor Parkway, Suite 202

Hauppauge, NY 11788

Tel: 631 -2 73- 530 5 Fax: 631- 273 -53 35

San Jose

Microchip Technology Inc.

2107 North First Street, Suite 590

San Jose, CA 95131

Tel: 408 -4 36- 795 0 Fax: 408- 436 -79 55

Toronto

6285 Northam Drive, Suite 108

Mississ aug a, Ontario L4V 1X5, C ana da

Tel: 905-673-0699 Fax: 905-673-6509

ASIA/PACIFIC

Australia

Microchip Technology Australia Pty Ltd

Suite 22, 41 Rawson Street

Epping 212 1, NSW

Australia

Tel: 61-2-9868-6733 Fax: 61-2-9868-6755

China - Be ijing

Microchip Technology Consulting (Shanghai)

Co., Ltd., Beijing Liaison Office

Unit 915

Bei Hai Wa n Tai Bldg.

No. 6 Chaoyangmen Beidajie

Beijing, 100027, No. China

Tel: 86-10-85282100 Fax: 86-10-85282104

China - Chengdu

Microchip Technology Consulting (Shanghai)

Co., Ltd., Chengdu Liaison Office

Rm. 2401, 24th Floor,

Ming Xing Financial Tower

No. 88 TIDU Street

Cheng du 610 016 , Chi na

Tel: 86-28-6766200 Fax: 86-28-6766599

China - Fuzhou

Microchip Technology Consulting (Shanghai)

Co., Ltd., Fuzhou Liaison Office

Unit 28F, World Trade Plaza

No. 71 Wusi Road

Fuzhou 350001, China

Tel: 86-591-7503506 Fax: 86-591-7503521

China - Shanghai

Microchip Technology Consulting (Shanghai)

Co., Ltd.

Room 701, Bldg. B

Far East International P laza

No. 317 Xian Xia Road

Shanghai, 200051

Tel: 86-21-6275-5700 Fax: 86-21-6275-5060

China - Shenzhen

Microchip Technology Consulting (Shanghai)

Co., Ltd., Shenzhen Liaison Office

Rm. 1315, 13/F, Shenzhen Kerry Centre,

Renminnan Lu

Shenzhen 518001, China

Tel: 86-755-2350361 Fax: 86-755-2366086

Hong Kong

Microchip Technology Hongkong Ltd.

Unit 901-6, Tower 2, Metroplaza

223 Hing Fong Road

Kwai Fong, N.T., Hong Kong

Tel: 852-2401-1200 Fax: 852-2401-3431

India

Microchip Technology Inc.

India Liaiso n Office

Divyasree Chambers

1 Floor, Wing A (A3/A4)

No. 11, O’Shaugnessey Road

Bangalore, 560 025, India

Tel: 91-80-2290061 Fax: 91-80-2290062

Japan

Microchip Technology Japan K.K.

Benex S-1 6F

3-18-20, Shinyokohama

Kohoku-Ku, Yokohama-shi

Kanagawa, 222-0033, Japan

Tel: 81-45-471- 6166 Fax: 81-45-471-6122

Korea

Microc hip Technolo gy Korea

168-1, You ng bo Bld g. 3 Floor

Samsung-Dong, Kangnam-Ku

Seoul, Ko re a 135- 88 2

Tel: 82-2-554-7200 Fax: 82-2-558-5934

Singapore

Microchip Technology Singapore Pte Ltd.

200 Midd le Ro ad

#07-02 Prime Centre

Singapore, 188980

Tel: 65-334-8870 Fax: 65-334-8850

Taiwan

Microc hip Technolo gy Tai wan

11F-3, No. 207

Tung Hua North Road

Taipei, 105, Taiwan

Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

EUROPE

Denmark

Microchip Technology Nordic ApS

Regus Business Centre

Lautrup hoj 1-3

Ballerup DK-2750 Denmark

Tel: 45 4420 9895 Fax: 45 4420 9910

France

Microc hip Technolo gy SARL

Parc d’Activite du Moulin de Massy

43 Rue du Saule Trapu

Batiment A - ler Et age

91300 Massy, France

Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany

Microc hip Technolo gy GmbH

Gustav-Heinemann Ring 125

D-81739 Munich, Germany

Tel: 49-89-627-144 0 Fax: 49-89-627-144-44

Italy

Microc hip Technolo gy SRL

Centro Direzionale Colleoni

Palazzo Taurus 1 V. Le Colleoni 1

20041 Agrate Brianza

Milan, Italy

Tel: 39-039-65791-1 Fax: 39-039-6899883

United Kingdom

Arizona Microchip Technology Ltd.

505 Eskdale Road

Winnersh Triangle

Wokingham

Berksh ire, E ngla nd RG 41 5TU

Tel: 44 118 921 5869 Fax: 44-118 921-5820

01/18/02

WORLDWIDE SALES AND SERVICE