Semiconductor Components Industries, LLC, 2001
October, 2001 – Rev. 2 1Publication Order Number:
UC3844B/D
UC3844B, UC3845B,
UC2844B, UC2845B
High Performance
Current Mode Controllers
The UC3844B, UC3845B series are high performance fixed
frequency current mode controllers. They are specifically designed for
Off–Line and dc–to–dc converter applications offering the designer a
cost–effective solution with minimal external components. These
integrated circuits feature an oscillator, a temperature compensated
reference, high gain error amplifier, current sensing comparator , and a
high current totem pole output ideally suited for driving a power
MOSFET.
Also included are protective features consisting of input and
reference undervoltage lockouts each with hysteresis, cycle–by–cycle
current limiting, a latch for single pulse metering, and a flip–flop
which blanks the output off every other oscillator cycle, allowing
output deadtimes to be programmed from 50% to 70%.
These devices are available in an 8–pin dual–in–line and surface
mount (SO–8) plastic package as well as the 14–pin plastic surface
mount (SO–14). The SO–14 package has separate power and ground
pins for the totem pole output stage.
The UCX844B has UVLO thresholds of 16 V (on) and 10 V (off),
ideally suited for off–line converters. The UCX845B is tailored for
lower voltage applications having UVLO thresholds of 8.5 V (on) and
7.6 V (off).
•Trimmed Oscillator for Precise Frequency Control
•Oscillator Frequency Guaranteed at 250 kHz
•Current Mode Operation to 500 kHz Output Switching Frequency
•Output Deadtime Adjustable from 50% to 70%
•Automatic Feed Forward Compensation
•Latching PWM for Cycle–By–Cycle Current Limiting
•Internally Trimmed Reference with Undervoltage Lockout
•High Current Totem Pole Output
•Undervoltage Lockout with Hysteresis
•Low Startup and Operating Current
Pin numbers in parenthesis are for the D suffix SO-14 package.
Output
VC
RT/CT
Vref
VCC
Undervoltage
Lockout
Gnd
5.0V
Reference
Vref
Undervoltage
Lockout
Latching
PWM
Oscillator
Error
Amplifier
5(9)
3(5)
5(8)
6(10)
7(11)
Power
Ground
Current
Sense Input
1(1)
2(3)
4(7)
8(14)
Output/
Compensation
Voltage
Feedback
Input
VCC 7(12)
R
R
Figure 1. Simplified Block Diagram
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14 SO–14
D SUFFIX
CASE 751A
1
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
ORDERING INFORMATION
See general marking information in the device marking
section on page 17 of this data sheet.
DEVICE MARKING INFORMATION
1
8
PDIP–8
N SUFFIX
CASE 626
PIN CONNECTIONS
Compensation
NC
Voltage Feedback
NC
Current Sense
NC
RT/CT
Compensation
Voltage Feedback
Current Sense
RT/CT
Vref
Vref
NC
VCC
VC
Output
Gnd
Power Ground
VCC
Output
Gnd
(Top View)
8
7
6
5
1
2
3
4
1
2
3
4
14
13
12
11
5
6
7
10
9
8
(Top View)
SO–8
D1 SUFFIX
CASE 751
1
8
UC3844B, UC3845B, UC2844B, UC2845B
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MAXIMUM RATINGS
Rating Symbol Value Unit
Total Power Supply and Zener Current (ICC + IZ) 30 mA
Output Current, Source or Sink (Note 1) IO1.0 A
Output Energy (Capacitive Load per Cycle) W 5.0 µJ
Current Sense and Voltage Feedback Inputs Vin – 0.3 to + 5.5 V
Error Amp Output Sink Current IO10 mA
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package, SO–14 Case 751A
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction–to–Air
D1 Suffix, Plastic Package, SO–8 Case 751
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction–to–Air
N Suffix, Plastic Package, Case 626
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction–to–Air
PD
RθJA
PD
RθJA
PD
RθJA
862
145
702
178
1.25
100
mW
°C/W
mW
°C/W
W
°C/W
Operating Junction Temperature TJ+150 °C
Operating Ambient Temperature
UC3844B, UC3845B
UC2844B, UC2845B
TA0 to + 70
– 25 to + 85
°C
Storage Temperature Range Tstg – 65 to +150 °C
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 2], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 3], unless otherwise noted.)
UC284XB UC384XB, XBV
Characteristic Symbol Min Typ Max Min Typ Max Unit
REFERENCE SECTION
Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) Vref 4.95 5.0 5.05 4.9 5.0 5.1 V
Line Regulation (VCC = 12 V to 25 V) Regline – 2.0 20 – 2.0 20 mV
Load Regulation (IO = 1.0 mA to 20 mA) Regload – 3.0 25 – 3.0 25 mV
Temperature Stability TS– 0.2 – – 0.2 – mV/°C
Total Output Variation over Line, Load, and Temperature Vref 4.9 – 5.1 4.82 – 5.18 V
Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C) Vn– 50 – – 50 – µV
Long Term Stability (TA = 125°C for 1000 Hours) S – 5.0 – – 5.0 – mV
Output Short Circuit Current ISC –30 –85 –180 –30 –85 –180 mA
OSCILLATOR SECTION
Frequency
TJ = 25°C
TA = Tlow to Thigh
TJ = 25°C (RT = 6.2 k, CT = 1.0 nF)
fOSC 49
48
225
52
–
250
55
56
275
49
48
225
52
–
250
55
56
275
kHz
Frequency Change with Voltage (VCC = 12 V to 25 V) ∆fOSC/∆V – 0.2 1.0 – 0.2 1.0 %
Frequency Change with Temperature (TA = Tlow to Thigh)∆fOSC/∆T – 1.0 – – 0.5 – %
Oscillator Voltage Swing (Peak–to–Peak) VOSC – 1.6 – – 1.6 – V
Discharge Current (VOSC = 2.0 V)
TJ = 25°C
TA = Tlow to Thigh (UC284XB, UC384XB)
TA = Tlow to Thigh (UC384XBV)
Idischg 7.8
7.5
–
8.3
–
–
8.8
8.8
–
7.8
7.6
7.2
8.3
–
–
8.8
8.8
8.8
mA
1. Maximum package power dissipation limits must be observed.
2. Adjust VCC above the Startup threshold before setting to 15 V.
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow =0°C for UC3844B, UC3845B Thigh =+70°C for UC3844B, UC3845B
=–25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B
=–40°C for UC3844BV, UC3845BV = +105°C for UC3844BV, UC3845BV
UC3844B, UC3845B, UC2844B, UC2845B
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ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 4], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 5], unless otherwise noted.)
UC284XB UC384XB, XBV
Characteristic Symbol Min Typ Max Min Typ Max Unit
ERROR AMPLIFIER SECTION
Voltage Feedback Input (VO = 2.5 V) VFB 2.45 2.5 2.55 2.42 2.5 2.58 V
Input Bias Current (VFB = 5.0 V) IIB – – 0.1 –1.0 – – 0.1 – 2.0 µA
Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) AVOL 65 90 – 65 90 – dB
Unity Gain Bandwidth (TJ = 25°C) BW 0.7 1.0 – 0.7 1.0 – MHz
Power Supply Rejection Ratio (VCC = 12 V to 25 V) PSRR 60 70 – 60 70 – dB
Output Current
Sink (VO = 1.1 V, VFB = 2.7 V)
Source (VO = 5.0 V, VFB = 2.3 V) ISink
ISource 2.0
– 0.5 12
–1.0 –
–2.0
– 0.5 12
–1.0 –
–
mA
Output Voltage Swing
High State (RL = 15 k to ground, VFB = 2.3 V)
Low State (RL = 15 k to Vref, VFB = 2.7 V)
(UC284XB, UC384XB)
(UC384XBV)
VOH
VOL 5.0
–
–
6.2
0.8
–
–
1.1
–
5.0
–
–
6.2
0.8
0.8
–
1.1
1.2
V
CURRENT SENSE SECTION
Current Sense Input Voltage Gain (Notes 6 & 7)
(UC284XB, UC384XB)
(UC384XBV)
AV2.85
–3.0
–3.15
–2.85
2.85 3.0
3.0 3.15
3.25
V/V
Maximum Current Sense Input Threshold (Note 6)
(UC284XB, UC384XB)
(UC384XBV)
Vth 0.9
–1.0
–1.1
–0.9
0.85 1.0
1.0 1.1
1.1
V
Power Supply Rejection Ratio
(VCC = 12 V to 25 V) (Note 6) PSRR – 70 – – 70 – dB
Input Bias Current IIB – – 2.0 –10 – – 2.0 –10 µA
Propagation Delay (Current Sense Input to Output) tPLH(In/Out) – 150 300 – 150 300 ns
OUTPUT SECTION
Output Voltage
Low State (ISink = 20 mA)
(ISink = 200 mA, UC284XB, UC384XB)
(ISink = 200 mA, UC384XBV)
High State (ISource = 20 mA, UC284XB, UC384XB)
(ISource = 20 mA, UC384XBV)
(ISource = 200 mA)
VOL
VOH
–
–
–
13
–
12
0.1
1.6
–
13.5
–
13.4
0.4
2.2
–
–
–
–
–
–
–
13
12.9
12
0.1
1.6
1.6
13.5
–
13.4
0.4
2.2
2.3
–
–
–
V
Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA) VOL(UVLO) – 0.1 1.1 – 0.1 1.1 V
Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) tr– 50 150 – 50 150 ns
Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) tf– 50 150 – 50 150 ns
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold
UCX844B, BV
UCX845B, BV
Vth 15
7.8 16
8.4 17
9.0 14.5
7.8 16
8.4 17.5
9.0
V
Minimum Operating Voltage After Turn–On
UCX844B, BV
UCX845B, BV
VCC(min) 9.0
7.0 10
7.6 11
8.2 8.5
7.0 10
7.6 11.5
8.2
V
4. Adjust VCC above the Startup threshold before setting to 15 V.
5. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow =0°C for UC3844B, UC3845B Thigh =+70°C for UC3844B, UC3845B
=–25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B
=–40°C for UC3844BV, UC3845BV = +105°C for UC3844BV, UC3845BV
6. This parameter is measured at the latch trip point with VFB = 0 V.
7. Comparator gain is defined as: AV =∆V Output/Compensation
∆V Current Sense Input
UC3844B, UC3845B, UC2844B, UC2845B
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ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 8], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 9], unless otherwise noted.)
UC284XB UC384XB, XBV
Characteristic Symbol Min Typ Max Min Typ Max Unit
PWM SECTION
Duty Cycle
Maximum (UC284XB, UC384XB)
Maximum (UC384XBV)
Minimum
DC(max)
DC(min)
47
–
–
48
–
–
50
–
0
47
46
–
48
48
–
50
50
0
%
TOTAL DEVICE
Power Supply Current
Startup (VCC = 6.5 V for UCX845B,
Startup (VCC = 14 V for UCX844B, BV)
Operating (Note 8)
ICC –
–
0.3
12
0.5
17
–
–
0.3
12
0.5
17
mA
Power Supply Zener Voltage (ICC = 25 mA) VZ30 36 – 30 36 – V
8. Adjust VCC above the Startup threshold before setting to 15 V.
9. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow =0°C for UC3844B, UC3845B Thigh =+70°C for UC3844B, UC3845B
=–25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B
=–40°C for UC3844BV, UC3845BV = +105°C for UC3844BV, UC3845BV
0.8
2.0
5.0
8.0
20
50
80
RT, TIMING RESISTOR (k )
Ω
1.0 M500 k200 k100 k50 k20 k10 k
fOSC, OSCILLATOR FREQUENCY (kHz)
Figure 2. Timing Resistor
versus Oscillator Frequency Figure 3. Output Deadtime
versus Oscillator Frequency
1.0 M100 k10 k
fOSC, OSCILLATOR FREQUENCY (kHz)
50
% DT, PERCENT OUTPUT DEADTIME
ÄÄÄÄÄ
ÄÄÄÄÄ
ÄÄÄÄÄ
ÄÄÄÄÄ
ÄÄÄÄÄ
1.CT = 10 nF
2.CT = 5.0 nF
3.CT = 2.0 nF
4.CT = 1.0 nF
5.CT = 500 pF
6.CT = 200 pF
7.CT = 100 pF
55
60
65
70
75
20 k 50 k 200 k 500 k
2
3
7
5
6
NOTE: Output switches at
1/2 the oscillator frequency
VCC = 15 V
TA = 25°C
0.5 µs/DIV
20 mV/DIV
2.55 V
2.5 V
2.45 V
VCC = 15 V
AV = -1.0
TA = 25°C
VCC = 15 V
AV = -1.0
TA = 25°C
1.0 µs/DIV
200 mV/DIV
2.5 V
3.0 V
2.0 V
Figure 4. Error Amp Small Signal
Transient Response Figure 5. Error Amp Large Signal
Transient Response
1
4
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∆, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
O
V
-20
AVOL, OPEN LOOP VOLTAGE GAIN (dB)
10 M10
f, FREQUENCY (Hz)
Gain
Phase
0
30
60
90
120
150
180
100 1.0 k 10 k 100 k 1.0 M
0
20
40
60
80
100
, EXCESS PHASE (DEGREES)
φ
0
VO, ERROR AMP OUTPUT VOLTAGE (VO)
0
, CURRENT SENSE INPUT THRESHOLD (V
)
Vth
0.2
0.4
0.6
0.8
1.0
1.2
2.0 4.0 6.0 8.0
TA = -55°C
ÄÄÄÄ
ÄÄÄÄ
VCC = 15 V
RL ≤ 0.1 Ω
Figure 6. Error Amp Open Loop Gain and
Phase versus Frequency Figure 7. Current Sense Input Threshold
versus Error Amp Output Voltage
Figure 8. Reference Voltage Change
versus Source Current Figure 9. Reference Short Circuit Current
versus Temperature
, REFERENCE VOLTAGE CHANGE (mV)
-16
0
Iref, REFERENCE SOURCE CURRENT (mA)
20 40 60 80 100 120
ref
V
-12
-8.0
-4.0
0
, REFERENCE SHORT CIRCUIT CURRENT (mA)
SC
I
50
-55
TA, AMBIENT TEMPERATURE (°C)
-25 0 25 50 75 100 125
70
90
110
∆
-20
-24
TA = 125°C
VCC = 15 V
VO = 2.0 V to 4.0 V
RL = 100 k
TA = 25°C
VCC = 15 V
TA = 25°C
∆, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
O
2.0 ms/DIV
V
2.0 ms/DIV
VCC = 12 V to 25 V
TA = 25°C
VCC = 15 V
IO = 1.0 mA to 20 mA
TA = 25°C
Figure 10. Reference Load Regulation Figure 11. Reference Line Regulation
VCC = 15 V
TA = 125°C
TA = 25°C
TA = -55°C
UC3844B, UC3845B, UC2844B, UC2845B
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ÄÄÄÄÄ
ÄÄÄÄÄ
Sink Saturation
(Load to VCC)
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
RT = 10 k
CT = 3.3 nF
VFB = 0 V
ISense = 0 V
TA = 25°C
, SUPPLY CURRENT (mA)
CC
I
00
VCC, SUPPLY VOLTAGE (V)
10 20 30 40
5
10
15
20
25
UCX845B
UCX844B
Figure 12. Output Saturation Voltage
versus Load Current Figure 13. Output Waveform
ÄÄÄ
ÄÄÄ
TA = 25°C
ÄÄÄÄ
ÄÄÄÄ
TA = -55°C
ÄÄ
VCC
VCC = 15 V
80 µs Pulsed Load
120 Hz Rate
ÄÄÄÄ
ÄÄÄÄ
TA = -55°C
ÄÄÄÄ
ÄÄÄÄ
TA = 25°C
0
V
sat,
O
UTPUT
S
ATURATI
O
N V
O
LTA
G
E (V)
8000
IO, OUTPUT LOAD CURRENT (mA)
200 400 600
1.0
2.0
3.0
-2.0
-1.0
0
ÄÄÄÄÄ
ÄÄÄÄÄ
Source Saturation
(Load to Ground)
ÄÄÄ
Gnd
50 ns/DIV
90
%
10
%
VCC = 15 V
CL = 1.0 nF
TA = 25°C
100 ns/DIV
VCC = 30 V
CL = 15 pF
TA = 25°C
, SUPPLY CURRENT
100 mA/DIV 20 V/DIV
I, OUTPUT VOLTAGEV
CC O
Figure 14. Output Cross Conduction Figure 15. Supply Current versus Supply Voltage
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PIN FUNCTION DESCRIPTION
Pin
8–Pin 14–Pin Function Description
1 1 Compensation This pin is the Error Amplifier output and is made available for loop compensation.
2 3 V oltage
Feedback This is the inverting input of the Error Amplifier. It is normally connected to the switching
power supply output through a resistor divider.
3 5 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
4 7 RT/CTThe Oscillator frequency and maximum Output duty cycle are programmed by
connecting resistor RT to Vref and capacitor CT to ground. Oscillator operation to 1.0 kHz
is possible.
5 Gnd This pin is the combined control circuitry and power ground.
6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are
sourced and sunk by this pin. The output switches at one–half the oscillator frequency.
7 12 VCC This pin is the positive supply of the control IC.
8 14 Vref This is the reference output. It provides charging current for capacitor CT through
resistor RT.
8Power
Ground This pin is a separate power ground return that is connected back to the power source. It
is used to reduce the effects of switching transient noise on the control circuitry.
11 VCThe Output high state (VOH) is set by the voltage applied to this pin. With a separate
power source connection, it can reduce the effects of switching transient noise on the
control circuitry.
9 Gnd This pin is the control circuitry ground return and is connected back to the power
source ground.
2,4,6,13 NC No connection. These pins are not internally connected.
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OPERATING DESCRIPTION
The UC3844B, UC3845B series are high performance,
fixed frequency, current mode controllers. They are
specifically designed for Off–Line and dc–to–dc converter
applications offering the designer a cost–effective solution
with minimal external components. A representative block
diagram is shown in Figure 16.
Oscillator
The oscillator frequency is programmed by the values
selected for the timing components RT and C T. Capacitor CT
is charged from the 5.0 V reference through resistor RT to
approximately 2.8 V and discharged to 1.2 V by an internal
current sink. During the discharge of CT, the oscillator
generates an internal blanking pulse that holds the center
input of the NOR gate high. This causes the Output to be in
a low state, thus producing a controlled amount of output
deadtime. An internal flip–flop has been incorporated in the
UCX844/5B which blanks the output off every other clock
cycle b y holding one of the inputs of the NOR gate high. This
in combination with the CT discharge period yields output
deadtimes programmable from 50% to 70%. Figure 2 shows
RT versus Oscillator Frequency and Figure 3, Output
Deadtime versus Frequency, both for given values of CT.
Note that many values of RT and CT will give the same
oscillator frequency but only one combination will yield a
specific output deadtime at a given frequency. The oscillator
thresholds are temperature compensated to within ±6% at 50
kHz. Also, because of industry trends moving the UC384X
into higher and higher frequency applications, the
UC384XB is guaranteed to within ±10% at 250 kHz.
In many noise–sensitive applications it may be desirable
to frequency–lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the
circuit shown in Figure 18. For reliable locking, the
free–running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi–unit
synchronization is shown in Figure 19. By tailoring the
clock waveform, accurate Output duty cycle clamping can
be achieved to realize output deadtimes of greater than 70%.
Error Amplifier
A fully compensated Error Amplifier with access to the
inverting input and output is provided. It features a typical
dc voltage gain of 90 dB, and a unity gain bandwidth of
1.0 MHz with 57 degrees of phase margin (Figure 6). The
non–inverting input is internally biased at 2.5 V and is not
pinned out. The converter output voltage is typically divided
down and monitored by the inverting input. The maximum
input bias current is –2.0 µA which can cause an output
voltage error that is equal to the product of the input bias
current and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provided for external
loop compensation (Figure 29). The output voltage is offset
by two diode drops (≈1.4 V) and divided by three before it
connects to the inverting input of the Current Sense
Comparator. This guarantees that no drive pulses appear at
the Output (Pin 6) when Pin 1 is at its lowest state (VOL).
This occurs when the power supply is operating and the load
is removed, or at the beginning of a soft–start interval
(Figures 21, 22). The Error Amp minimum feedback
resistance is limited by the amplifier’s source current
(0.5 mA) and the required output voltage (VOH) to reach the
comparator’s 1.0 V clamp level:
Rf(min) ≈3.0 (1.0 V) + 1.4 V
0.5 mA = 8800 Ω
Current Sense Comparator and PWM Latch
The UC3844B, UC3845B operate as a current mode
controller, whereby output switch conduction is initiated by
the oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error
Amplifier Output/Compensation (Pin 1). Thus the error
signal controls the peak inductor current on a
cycle–by–cycle basis. The Current Sense Comparator PWM
Latch configuration used ensures that only a single pulse
appears at the Output during any given oscillator cycle. The
inductor current is converted to a voltage by inserting the
ground–referenced sense resistor RS in series with the
source of output switch Q1. This voltage is monitored by the
Current Sense Input (Pin 3) and compared to a level derived
from the Error Amp Output. The peak inductor current under
normal operating conditions is controlled by the voltage at
Pin 1 where:
Ipk = V(Pin 1) – 1.4 V
3 RS
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:
Ipk(max) = 1.0 V
RS
When designing a high power switching regulator it
becomes d esirable t o r educe t he i nternal c lamp v oltage i n o rder
to keep the power dissipation of RS to a reasonable level. A
simple method to adjust t his voltage is shown i n Figure 2 0. T he
two e xternal d iodes a re u sed t o c ompensate t he i nternal diodes,
yielding a constant clamp voltage over temperature. Erratic
operation d ue t o n oise pickup c an r esult i f t here i s a n e xcessive
reduction of the Ipk(max) clamp voltage.
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense Input with
a time constant that approximates the spike duration will
usually eliminate the instability (refer to Figure 24).
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Figure 16. Representative Block Diagram
Figure 17. Timing Diagram
Capacitor CT
Latch Set"
Input
Output/
Compensation
Current Sense
Input
Latch Reset"
Input
Output
Large RT/Small CTSmall RT/Large CT
+
-
Reference
Regulator
VCC
UVLO
+
-Vref
UVLO
3.6V
36V
S
R
Q
Internal
Bias
+1.0mA
Oscillator
2.5V
R
R
R
2R
Error
Amplifier
Voltage
Feedback
Input
Output/
Compensation Current Sense
Comparator
1.0V
VCC 7(12)
Gnd 5(9)
VC
7(11)
Output
6(10)
Power Ground
5(8)
Current Sense Input
3(5) RS
Q1
VCC Vin
1(1)
2(3)
4(7)
8(14)
RT
CT
Vref
= Sink Only Positive True Logic
Pin numbers adjacent to terminals are for the 8-pin dual-in-line package.
Pin numbers in parenthesis are for the D suffix SO-14 package.
PWM
Latch
(See
Text)
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Undervoltage Lockout
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional
before the output stage is enabled. The positive power
supply terminal (VCC) and the reference output (Vref) are
each monitored by separate comparators. Each has built–in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The VCC comparator
upper and lower thresholds are 16 V/10 V for the UCX844B,
and 8.4 V/7.6 V for the UCX845B. The Vref comparator
upper and lower thresholds are 3.6 V/3.4 V. The large
hysteresis and low startup current of the UCX844B makes
it ideally suited in off–line converter applications where
efficient bootstrap startup techniques are required
(Figure 30). The UCX845B is intended for lower voltage
dc–to–dc converter applications. A 36 V zener is connected
as a shunt regulator from VCC to ground. Its purpose is to
protect the IC from excessive voltage that can occur during
system startup. The minimum operating voltage for the
UCX844B is 11 V and 8.2 V for the UCX845B.
Output
These devices contain a single totem pole output stage that
was specifically designed for direct drive of power
MOSFETs. It is capable of up to ±1.0 A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pull–down resistor.
The SO–14 surface mount package provides separate pins
for VC (output supply) and Power Ground. Proper
implementation will significantly reduce the level of
switching transient noise imposed on the control circuitry.
This becomes particularly useful when reducing the Ipk(max)
clamp level. The separate VC supply input allows the
designer added flexibility in tailoring the drive voltage
independent of VCC. A zener clamp is typically connected
to this input when driving power MOSFETs in systems
where VCC is greater than 20 V. Figure 23 shows proper
power and control ground connections in a current–sensing
power MOSFET application.
Reference
The 5.0 V bandgap reference is trimmed to ±1.0%
tolerance at T J = 25°C on the UC284XB, and ±2.0% on the
UC384XB. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has
short–circuit protection and is capable of providing in
excess of 20 mA for powering additional control system
circuitry.
Design Considerations
Do not attempt to construct the converter on
wire–wrap or plug–in prototype boards. High frequency
circuit layout techniques are imperative to prevent
pulse–width jitter. This is usually caused by excessive noise
pick–up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances a t these points. The printed circuit layout should
contain a ground plane with low–current signal and
high–current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 µF) connected directly to VCC, VC,
and Vref may be required depending upon circuit layout.
This provides a low impedance path for filtering the high
frequency noise. All high current loops should be kept as
short as possible using heavy copper runs to minimize
radiated EMI. The Error Amp compensation circuitry and
the converter output voltage divider should be located close
to the IC and as far as possible from the power switch and
other noise–generating components.
Bias
+
Osc
R
R
R
2R
EA
5(9)
1(1)
2(3)
4(7)
8(14)
RT
CT
Vref
Figure 18. External Clock Synchronization Figure 19. External Duty Cycle Clamp and
Multi–Unit Synchronization
0.01
The diode clamp is required if the Sync amplitude is large enough to cause
the bottom side of CT to go more than 300 mV below ground.
External
Sync
Input
47
+
R
R
R
2R
Bias
Osc
EA
5(9)
1(1)
2(3)
4(7)
8(14)
To Additional
UCX84XBs
R
S
Q
8 4
6
5
2
1
C
3
7
RA
RB5.0k
5.0k
5.0k MC1455
f 1.44
(RA2R
B)C D(max)RA
RA2R
B
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If: SENSEFET = MTP10N10M
RS= 200
Figure 20. Adjustable Reduction of Clamp Level Figure 21. Soft–Start Circuit
Figure 22. Adjustable Buffered Reduction of
Clamp Level with Soft–Start
+
-
5.0V Ref
+
-
S
R
Q
Bias
+
Osc
R
R
R
2R
EA
1.0V
5(9)
7(11)
6(10)
5(8)
3(5) RS
Q1
VCC Vin
1(1)
2(3)
4(7)
8(14)
R1
VClamp
R2
Ipk(max)VClamp
RS
Where: 0 ≤ VClamp ≤ 1.0 V
5.0V Ref
+
-
S
R
Q
Bias
+
1.0mA
Osc
R
R
R
2R
EA
1.0V
5(9)
1(1)
2(3)
4(7)
8(14)
C
1.0M
tSoft-Start ≈ 3600C in µF
+
-
+
-
S
R
+
R
R
R
2R
Ipk(max)VClamp
RS
Figure 23. Current Sensing Power MOSFET
5.0V Ref
Q
Bias
Osc
EA
1.0V
5(9)
7(11)
6(10)
5(8)
3(5) RS
Q1
VCC Vin
1(1)
2(3)
4(7)
8(14)
R1
R2
Where: 0 ≤ VClamp ≤ 1.0 V
MPSA63
+
-
5.0V Ref
+
-
S
R
Q
(11)
(10)
(8)
Comp/Latch
(5) RS
1/4 W
VCC Vin
K
M
DSENSEFET
GS
Power Ground:
To Input Source
Return
Control Circuitry Ground:
To Pin (9)
Virtually lossless current sensing can be achieved with the implementation
of a SENSEFET power switch. For proper operation during over-current
conditions, a reduction of the Ipk(max) clamp level must be implemented.
Refer to Figures 20 and 22.
VPin5RSIpkrDS(on)
rDM(on)R
S
Then : VPin5 0.075Ipk
7(12)
7(12)
1.0 mA
Comp/Latch
Comp/Latch
1.0 mA
(12)
T
T
TT
VClamp
VClamp ≈1.67
R2
R11+ 0.33x10-3 R1R2
R1R2
VClamp ≈1.67
R2
R11
tSoftStart In1VC
3VClampC R1R2
R1R2
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Figure 24. Current Waveform Spike Suppression
+
-
5.0V Ref
+
-
S
R
Q
7(11)
6(10)
5(8)
3(5)
RS
Q1
VCC Vin
C
R
The addition of the RC filter will eliminate
instability caused by the leading edge spike
on the current waveform.
7(12)
Comp/Latch
T
Figure 25. MOSFET Parasitic Oscillations Figure 26. Bipolar Transistor Drive
+
-
S
R
5.0V Ref
Q
7(11)
6(10)
5(8)
3(5) RS
Q1
VCC Vin
Series gate resistor Rg will damp any high frequency
parasitic oscillations caused by the MOSFET input
capacitance and any series wiring inductance in the
gate-source circuit.
6(10)
5(8)
3(5) RS
Q1
Vin
C1
Base Charge
Removal
The totem pole output can furnish negative base current
for enhanced transistor turn-off, with the addition of
capacitor C1.
IB
+
-
0
7(12)
Rg
Comp/Latch
T
+
-
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+
R
2R
1.0mA
EA
2(3)
5(9)
2.5V
1(1)
Rf
Cf
Rd
Rp
From VO
Error Amp compensation circuit for stabilizing current mode boost
and flyback topologies operating with continuous inductor current.
Cp
Ri
Figure 27. Isolated MOSFET Drive
Figure 28. Latched Shutdown
Figure 29. Error Amplifier Compensation
+
-
S
R
5.0V Ref
Q
7(11)
6(10)
5(8)
3(5)
RS
Q1
VCC Vin
Isolation
Boundary
VGS Waveforms
+
-
0
50% DC 25% DC
NS
Np
Bias
+
Osc
R
R
R
2R
EA
5(9)
1(1)
2(3)
4(7)
8(14)
The MCR101 SCR must be selected for a holding of < 0.5 mA @ TA(min). The
simple two transistor circuit can be used in place of the SCR as shown. All
resistors are 10 k.
MCR
101
2N
3905
2N
3903
+
R
2R
1.0mA
EA
2(3)
5(9)
2.5V
1(1)
Rf
Cf
Rd
Ri
From VO
Error Amp compensation circuit for stabilizing any current mode topology except
for boost and flyback converters operating with continuous inductor current.
Rf ≥ 8.8k
Comp/Latch
7(12)
R
CNSNP
1.0 mA
T
+
-
0
+
-
Ipk = V(Pin1) - 1.4
3 RS
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14
MUR110
+
-
+
-
S
R
+
R
R
5.0V Ref
Q
Bias
EA
5(9)
7(11)
6(10)
5(8)
3(5) 0.5
MTP
4N50
1(1)
2(3)
4(7)
8(14)
33k
1.0nF
470pF
150k
100
pF
18k
4.7k
Figure 30. 7 W Off–Line Flyback Regulator
0.01
100
+
1.0k
115 Vac
4.7ΩMDA
202
250
56k
4.7k 3300
pF
1N4935 1N4935
++
68
47
1N4937
1N4937
680pF 2.7k
L3
L2
L1
++
++
++
1000
1000
2200
10
10
1000
5.0V/4.0A
5.0V RTN
12V/0.3A
±12V RTN
-12V/0.3A
Primary: 45 Turns #26 AWG
Secondary ±12 V: 9 Turns #30 AWG (2 Strands) Bifiliar Wound
Secondary 5.0 V: 4 Turns (six strands) #26 Hexfiliar Wound
Secondary Feedback: 10 Turns #30 AWG (2 strands) Bifiliar Wound
Core: Ferroxcube EC35-3C8
Bobbin: Ferroxcube EC35PCB1
Gap: ≈ 0.10" for a primary inductance of 1.0 mH
MUR110
MBR1635
T1
22
Osc
T1 -
7(12)
Comp/Latch
T
L1
L2, L3
- 15 µH at 5.0 A, Coilcraft Z7156
- 25 µH at 5.0 A, Coilcraft Z7157
1N5819
Test Conditions Results
Line Regulation: 5.0 V
±12 V Vin = 95 Vac to 130 Vac ∆ = 50 mV or ±0.5%
∆ = 24 mV or ±0.1%
Load Regulation: 5.0 V
±12 V Vin = 115 Vac, Iout = 1.0 A to 4.0 A
Vin = 115 Vac, Iout = 100 mA to 300 mA ∆ = 300 mV or ±3.0%
∆ = 60 mV or ±0.25%
Output Ripple: 5.0 V
±12 V Vin = 115 Vac 40 mVpp
80 mVpp
Efficiency Vin = 115 Vac 70%
All outputs are at nominal load currents unless otherwise noted.
UC3844B, UC3845B, UC2844B, UC2845B
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15
Osc
+
-
Reference
Regulator
+
-
34V
S
R
Q
Internal
Bias
+
0.5mA
Osc
R
R
R
2R
Error
Amplifier
1.0V
7(12)
7(11)
6(10)
5(8)
3(5)
R1
Vin = 15V
1(1)
2(3)
4(7)
8(14)
10k
1.0nF
The capacitor's equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor
may be required when using tantalum or other low ESR capacitors. The converter's output can provide excellent line
and load regulation by connecting the R2/R1 resistor divider as shown.
Figure 31. Step–Up Charge Pump Converter
5(9)
PWM
T
Latch
Current Sense
Comparator
2.5V
3.6V
VCC
UVLO
Vref
UVLO
UC3845B +47
1N5819
15 10 1N5819
+47
R2
Connect to
Pin 2 for
closed loop
operation.
R2
R1 1
VO ≈ 2 (Vin)
Output Load Regulation
(Open Loop Configuration)
IO (mA) VO (V)
0
2
9
18
36
29.9
28.8
28.3
27.4
24.4
+
-
+
-
S
R
+
R
R
R
2R
5(9)
PWM
T
Latch
Current Sense
Comparator
+47
15 10 1N5819
+47
Reference
Regulator
34V
Q
Internal
Bias
0.5mA
Error
Amplifier
1.0V
7(12)
7(11)
6(10)
5(8)
3(5)
Vin = 15V
1(1)
2(3)
4(7)
8(14)
10k
1.0nF
The capacitor's equivalent series resistance must limit the Drive Output current to 1.0 A.
An additional series resistor may be required when using tantalum or other low ESR capacitors.
Figure 32. Voltage–Inverting Charge Pump Converter
2.5V
3.6V
VCC
UVLO
Vref
UVLO
UC3845B
VO ≈ -Vin
Output Load Regulation
IO (mA) VO (V)
0
2
9
18
32
–14.4
–13.2
–12.5
–11.7
–10.6
1N5819
+
VO = 2.5
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16
ORDERING INFORMATION
Device Operating
Temperature Range Package Shipping
UC384XBD SO–14 55 Units/Rail
UC384XBDR2 SO–14 2500 Tape & Reel
UC384XBD1 TA = 0° to +70°CSO–8 98 Units/Rail
UC384XBD1R2
A
SO–8 2500 Tape & Reel
UC384XBN PDIP–8 50 Units/Rail
UC2845BD SO–14 55 Units/Rail
UC284XBDR2 SO–14 2500 Tape & Reel
UC2845BD1 TA = –25° to +85°CSO–8 98 Units/Rail
UC284XBD1R2
A
SO–8 2500 Tape & Reel
UC2844BN PDIP–8 50 Units/Rail
UC384XBVD SO–14 55 Units/Rail
UC3844BVDR2 SO–14 2500 Tape & Reel
UC384XBVD1 TA = –40° to +105°CSO–8 98 Units/Rail
UC384XBVD1R2
A
SO–8 2500 Tape & Reel
UC384XBVN PDIP–8 50 Units/Rail
X indicates either a 4 or 5 to define specific device part numbers.
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17
x = 4 or 5
F = Wafer Fab
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
SO–14
D SUFFIX
CASE 751A
MARKING DIAGRAMS
UC384xBD
AWLYWW
14
1
UC384xBN
AWL
YYWW
PDIP–8
N SUFFIX
CASE 626
1
8
384xB
ALYW
SO–8
D1 SUFFIX
CASE 751
1
8
UC384xBVD
AWLYWW
14
1
384xB
ALYWV
1
8
UC3844BVN
AWL
YYWW
1
8
UC284xBD
AWLYWW
14
1
284xB
ALYW
1
8
UC2844BN
FAWL
YYWW
1
8
UC3845BVN
FAWL
YYWW
1
8
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18
PACKAGE DIMENSIONS
PDIP–8
N SUFFIX
CASE 626–05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
58
F
NOTE 2 –A–
–B–
–T–
SEATING
PLANE
H
J
GDK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M--- 10 --- 10
N0.76 1.01 0.030 0.040

SO–8
D1 SUFFIX
CASE 751–07
ISSUE W
SEATING
PLANE
1
4
58
N
J
X 45
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
–X–
–Y–
G
M
Y
M
0.25 (0.010)
–Z–
Y
M
0.25 (0.010) Z SXS
M

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PACKAGE DIMENSIONS
SO–14
D SUFFIX
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
–B–
G
P7 PL
14 8
71 M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
–T–
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
 
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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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