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Old Company Name in Catalogs and Other Documents
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Renesas Electronics document. We appreciate your understanding.
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April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
User’s Manual
µ
PD789462
µ
PD789464
µ
PD789466
µ
PD789467
µ
PD78F9468
µ
PD789467 Subseries
8-Bit Single-Chip Microcontrollers
Printed in Japan
Document No. U15552EJ2V2UD00 (2nd edition)
Date Published August 2005 NS CP(K)
c
2 User’s Manual U15552EJ2V2UD
[MEMO]
User’s Manual U15552EJ2V2UD 3
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
4 User’s Manual U15552EJ2V2UD
FIP and EEPROM are trademarks of NEC Electronics Corporation.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
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PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
The information in this document is current as of August, 2005. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
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No part of this document may be copied or reproduced in any form or by any means without the prior
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appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
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or any other liability arising from the use of such products. No license, express, implied or otherwise, is
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Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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each NEC Electronics product before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
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determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
•
•
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
User’s Manual U15552EJ2V2UD 5
Regional Information
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-558-3737
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Shanghai, P.R. China
Tel: 021-5888-5400
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Taipei, Taiwan
Tel: 02-2719-2377
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Novena Square, Singapore
Tel: 6253-8311
J05.6
N
EC Electronics (Europe) GmbH
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• Sucursal en España
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Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
6 User’s Manual U15552EJ2V2UD
Major Revisions in This Edition
Page Description
Throughout Deletion of development status indication “under development” for
µ
PD789466 and 789467
p. 35 Addition of description on pin connections in 2.2.15 VPP (
µ
PD78F9468 only)
p. 55 Table 3-3 Special-Function Registers
• Change of attribute of port 8 (P8) to read-only and change of value after reset to undefined
• Modification of oscillation stabilization time selection register (OSTS) to allow use of 1-bit manipulation
instruction.
p. 74 Modification of Caution 2 in Figure 4-10 Format of Port Function Register 8
p. 79 Addition of Note on feedback resistor in Figure 5-3 Format of Suboscillation Mode Register
p. 91 6.2 Configuration of 8-Bit Timers 30 and 40
• Modification of Figure 6-3 Block Diagram of Output Controller (Timer 40)
• Addition of description to (2) 8-bit compare register 40 (CR40)
• Addition of description to (3) 8-bit H width compare register 40 (CRH40)
p. 96 Addition to Cautions in Figure 6-6 Format of Carrier Generator Output Control Register 40
p. 109 Addition to Cautions in 6.4.3 Operation as carrier generator
p. 115 Modification of description in 6.5 Notes on Using 8-Bit Timers 30 and 40
p. 137 Addition of (8) Input impedance of ANI0 pin to 9.5 Cautions Related to 8-Bit A/D Converter
pp. 141, 142 Addition to Notes and Cautions in Figure 10-2 Format of LCD Display Mode Register 0
p. 159 Addition to Cautions in Figure 12-2 Format of Interrupt Request Flag Register 0
p. 161 Addition to Cautions in Figure 12-6 Format of Key Return Mode Register 00
p. 169 Modification of oscillation stabilization time selection register (OSTS) to allow use of 1-bit manipulation
instruction in 13.1.2 Register controlling standby function
p. 183 Modification of Table 15-3 Communication Mode List
pp. 200, 202, 204,
205, 210
CHAPTER 18 ELECTRICAL SPECIFICATIONS
• Change from target values to formal specifications
• Addition of Note 1 to Absolute Maximum Ratings
• Addition of recommended oscillator constants for mask ROM versions
• Modification of Write and Erase Characteristics
p. 212 Addition of recommended conditions for
µ
PD789466 and 789467 in CHAPTER 20 RECOMMENDED
SOLDERING CONDITIONS
p. 218 Change of name “conversion connector” and “conversion socket” to “conversion adapter (TGB-052SBP)”
in A.5 Debugging Tools (Hardware)
p. 225 Addition of APPENDIX C REVISION HISTORY
Major revisions in modification version (U15552EJ2V2UD00)
pp. 22, 23 Addition of lead-free products in CHAPTER 1 GENERAL
p. 213 Addition of soldering conditions of lead-free products in Table 20-1 Surface Mounting Type Soldering
Conditions
The mark shows major revised points.
User’s Manual U15552EJ2V2UD 7
INTRODUCTION
Target Readers This manual is intended for users who wish to understand the functions of the
µ
PD789467 Subseries and to design and develop application systems and programs
using these microcontrollers.
Target products:
•
µ
PD789467 Subseries:
µ
PD789462, 789464, 789466, 789467, 78F9468
Purpose This manual is intended to give users an understanding of the functions described in
the organization below.
Organization The
µ
PD789467 Subseries User’s Manual is divided into two parts: this manual and
instructions (common to the 78K/0S Series).
µ
PD789467 Subseries
User’s Manual
78K/0S Series
Instructions
User’s Manual
• Pin functions
• Internal block functions
• Interrupt functions
• Other on-chip peripheral functions
• Electrical specifications
• CPU function
• Instruction set
• Explanation of each instruction
How to Use This Manual It is assumed that the reader of this manual has general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
• To understand the functions in general:
→ Read this manual in the order of the contents.
• How to interpret the register format:
→ For a bit whose number is enclosed in brackets, the bit name is defined as a
reserved word in the assembler, and already defined in the header file named
sfrbit.h in the C compiler.
• When you know a register name and want to confirm its details:
→ Read APPENDIX B REGISTER INDEX.
• To know the 78K/0S Series instruction functions in detail:
→ Read 78K/0S Series Instructions User’s Manual (U11047E).
• To know the electrical specifications of the
µ
PD789467 Subseries:
→ Read CHAPTER 18 ELECTRICAL SPECIFICATIONS.
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representation: xxx (overscore over pin or signal name)
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representation: Binary ... xxxx or xxxxB
Decimal ... xxxx
Hexadecimal ... xxxxH
8 User’s Manual U15552EJ2V2UD
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No.
µ
PD789467 Subseries User’s Manual This manual
78K/0S Series Instructions User’s Manual U11047E
Documents Related to Development Tools (Software) (User’s Manuals)
Document Name Document No.
Operation U14876E
Language U14877E
RA78K0S Assembler Package
Structured Assembly Language U11623E
Operation U14871E CC78K0S C Compiler
Language U14872E
Operation (WindowsTM Based) U15373E SM78K Series System Simulator Ver. 2.30 or Later
External Part User Open Interface Specifications U15802E
ID78K Series Integrated Debugger
Ver. 2.30 or Later
Operation (Windows Based) U15185E
Project Manager Ver. 3.12 or Later (Windows Based) U14610E
Documents Related to Development Tools (Hardware) (User’s Manuals)
Document Name Document No.
IE-78K0S-NS In-Circuit Emulator U13549E
IE-78K0S-NS-A In-Circuit Emulator U15207E
IE-789468-NS-EM1 Emulation Board To be prepared
Documents Related to Flash Memory Writing
Document Name Document No.
PG-FP3 Flash Memory Programmer User’s Manual U13502E
PG-FP4 Flash Memory Programmer User’s Manual U15260E
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
User’s Manual U15552EJ2V2UD 9
Other Related Documents
Document Name Document No.
SEMICONDUCTOR SELECTION GUIDE - Products and Packages - (CD-ROM) X13769X
Semiconductor Device Mount Manual Note
Quality Grades on NEC Semiconductor Devices C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html)
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
10 User’s Manual U15552EJ2V2UD
CONTENTS
CHAPTER 1 GENERAL...........................................................................................................................21
1.1 Features ......................................................................................................................................21
1.2 Applications................................................................................................................................21
1.3 Ordering Information .................................................................................................................22
1.4 Pin Configuration (Top View)....................................................................................................23
1.5 78K/0S Series Lineup.................................................................................................................25
1.6 Block Diagram ............................................................................................................................28
1.7 Overview of Functions...............................................................................................................29
CHAPTER 2 PIN FUNCTIONS ...............................................................................................................31
2.1 List of Pin Functions..................................................................................................................31
2.2 Description of Pin Functions ....................................................................................................33
2.2.1 P00 to P03 (Port 0) .......................................................................................................................33
2.2.2 P10, P11 (Port 1) ..........................................................................................................................33
2.2.3 P40 to P43 (Port 4) .......................................................................................................................33
2.2.4 P60, P61 (Port 6) ..........................................................................................................................33
2.2.5 P80 to P85 (Port 8) .......................................................................................................................34
2.2.6 S0 to S16 ......................................................................................................................................34
2.2.7 COM0 to COM3 ............................................................................................................................ 34
2.2.8 VLC0 to VLC2 ...................................................................................................................................34
2.2.9 CATH, CAPL................................................................................................................................. 34
2.2.10 RESET ..........................................................................................................................................34
2.2.11 X1, X2 ........................................................................................................................................... 34
2.2.12 XT1, XT2....................................................................................................................................... 34
2.2.13 VDD ................................................................................................................................................34
2.2.14 VSS ................................................................................................................................................34
2.2.15 VPP (
µ
PD78F9468 only) ................................................................................................................35
2.2.16 IC0 (mask ROM version only) .......................................................................................................35
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins.........................................36
CHAPTER 3 CPU ARCHITECTURE......................................................................................................38
3.1 Memory Space............................................................................................................................38
3.1.1 Internal program memory space ...................................................................................................43
3.1.2 Internal data memory (internal high-speed RAM) space ...............................................................44
3.1.3 Special-function register (SFR) area .............................................................................................44
3.1.4 Data memory addressing ..............................................................................................................45
3.2 Processor Registers ..................................................................................................................50
3.2.1 Control registers............................................................................................................................50
3.2.2 General-purpose registers............................................................................................................. 53
3.2.3 Special-function registers (SFRs).................................................................................................. 54
3.3 Instruction Address Addressing ..............................................................................................56
3.3.1 Relative addressing....................................................................................................................... 56
User’s Manual U15552EJ2V2UD 11
3.3.2 Immediate addressing................................................................................................................... 57
3.3.3 Table indirect addressing .............................................................................................................. 58
3.3.4 Register addressing ...................................................................................................................... 58
3.4 Operand Address Addressing..................................................................................................59
3.4.1 Direct addressing .......................................................................................................................... 59
3.4.2 Short direct addressing ................................................................................................................. 60
3.4.3 Special-function register (SFR) addressing................................................................................... 61
3.4.4 Register addressing ...................................................................................................................... 62
3.4.5 Register indirect addressing.......................................................................................................... 63
3.4.6 Based addressing ......................................................................................................................... 64
3.4.7 Stack addressing .......................................................................................................................... 64
CHAPTER 4 PORT FUNCTIONS........................................................................................................... 65
4.1 Port Functions............................................................................................................................65
4.2 Port Configuration .....................................................................................................................66
4.2.1 Port 0 ............................................................................................................................................ 66
4.2.2 Port 1 ............................................................................................................................................ 67
4.2.3 Port 4 ............................................................................................................................................ 68
4.2.4 Port 6 ............................................................................................................................................ 69
4.2.5 Port 8 ............................................................................................................................................ 71
4.3 Registers Controlling Port Function........................................................................................72
4.4 Port Function Operation............................................................................................................75
4.4.1 Writing to I/O port.......................................................................................................................... 75
4.4.2 Reading from I/O port ................................................................................................................... 75
4.4.3 Arithmetic operation of I/O port ..................................................................................................... 75
CHAPTER 5 CLOCK GENERATOR ......................................................................................................76
5.1 Clock Generator Functions....................................................................................................... 76
5.2 Clock Generator Configuration ................................................................................................76
5.3 Registers Controlling Clock Generator ................................................................................... 78
5.4 System Clock Oscillators..........................................................................................................80
5.4.1 Main system clock oscillator.......................................................................................................... 80
5.4.2 Subsystem clock oscillator ............................................................................................................ 81
5.4.3 Example of incorrect resonator connection ................................................................................... 82
5.4.4 Divider........................................................................................................................................... 83
5.4.5 When no subsystem clock is used ................................................................................................ 83
5.5 Clock Generator Operation.......................................................................................................84
5.6 Changing Setting of System Clock and CPU Clock ............................................................... 85
5.6.1 Time required for switching between system clock and CPU clock............................................... 85
5.6.2 Switching between system clock and CPU clock .......................................................................... 86
CHAPTER 6 8-BIT TIMERS 30 AND 40 .............................................................................................87
6.1 Functions of 8-Bit Timers 30 and 40 ........................................................................................ 87
6.2 Configuration of 8-Bit Timers 30 and 40..................................................................................88
12 User’s Manual U15552EJ2V2UD
6.3 Registers Controlling 8-Bit Timers 30 and 40 .........................................................................93
6.4 Operation of 8-Bit Timers 30 and 40 ........................................................................................98
6.4.1 Operation as 8-bit timer counter....................................................................................................98
6.4.2 Operation as 16-bit timer counter................................................................................................ 105
6.4.3 Operation as carrier generator .................................................................................................... 109
6.4.4 Operation as PWM output (timer 40 only) ................................................................................... 113
6.5 Notes on Using 8-Bit Timers 30 and 40 .................................................................................115
CHAPTER 7 WATCH TIMER ...............................................................................................................116
7.1 Watch Timer Functions ...........................................................................................................116
7.2 Watch Timer Configuration.....................................................................................................117
7.3 Register Controlling Watch Timer..........................................................................................118
7.4 Watch Timer Operation............................................................................................................119
7.4.1 Operation as watch timer ............................................................................................................ 119
7.4.2 Operation as interval timer .......................................................................................................... 119
CHAPTER 8 WATCHDOG TIMER .......................................................................................................121
8.1 Watchdog Timer Functions.....................................................................................................121
8.2 Watchdog Timer Configuration ..............................................................................................122
8.3 Registers Controlling Watchdog Timer .................................................................................123
8.4 Watchdog Timer Operation.....................................................................................................125
8.4.1 Operation as watchdog timer ...................................................................................................... 125
8.4.2 Operation as interval timer .......................................................................................................... 126
CHAPTER 9 8-BIT A/D CONVERTER ................................................................................................127
9.1 Functions of 8-Bit A/D Converter ...........................................................................................127
9.2 Configuration of 8-Bit A/D Converter.....................................................................................127
9.3 Registers Controlling 8-Bit A/D Converter ............................................................................130
9.4 8-Bit A/D Converter Operation................................................................................................132
9.4.1 Basic operation of 8-bit A/D converter......................................................................................... 132
9.4.2 Input voltage and conversion result............................................................................................. 133
9.4.3 Operation mode of 8-bit A/D converter........................................................................................ 134
9.5 Cautions Related to 8-Bit A/D Converter...............................................................................135
CHAPTER 10 LCD CONTROLLER/DRIVER.......................................................................................139
10.1 Functions of LCD Controller/Driver .......................................................................................139
10.2 Configuration of LCD Controller/Driver.................................................................................139
10.3 Registers Controlling LCD Controller/Driver ........................................................................141
10.4 Setting LCD Controller/Driver.................................................................................................145
10.4.1 Setting before starting display ..................................................................................................... 145
10.4.2 Setting until disabling display and stopping voltage boost........................................................... 145
10.5 LCD Display Data Memory ......................................................................................................146
10.6 Common and Segment Signals ..............................................................................................147
10.7 Display Modes ..........................................................................................................................149
10.7.1 Four-time-slice display example.................................................................................................. 149
User’s Manual U15552EJ2V2UD 13
10.8 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2 ............................................................152
CHAPTER 11 POWER-ON-CLEAR CIRCUIT .....................................................................................153
11.1 Functions of Power-on-Clear Circuit ..................................................................................... 153
11.2 Configuration of Power-on-Clear Circuit...............................................................................153
11.3 Power-on-Clear Circuit Operation..........................................................................................154
CHAPTER 12 INTERRUPT FUNCTION...............................................................................................155
12.1 Interrupt Types.........................................................................................................................155
12.2 Interrupt Sources and Configuration.....................................................................................155
12.3 Registers Controlling Interrupt Function ..............................................................................158
12.4 Interrupt Servicing Operation.................................................................................................162
12.4.1 Non-maskable interrupt request acknowledgment operation ...................................................... 162
12.4.2 Maskable interrupt request acknowledgment operation .............................................................. 164
12.4.3 Multiple interrupt servicing .......................................................................................................... 165
12.4.4 Putting interrupt requests on hold ............................................................................................... 167
CHAPTER 13 STANDBY FUNCTION..................................................................................................168
13.1 Standby Function and Configuration ....................................................................................168
13.1.1 Standby function ......................................................................................................................... 168
13.1.2 Register controlling standby function .......................................................................................... 169
13.2 Standby Function Operation ..................................................................................................170
13.2.1 HALT mode................................................................................................................................. 170
13.2.2 STOP mode ................................................................................................................................ 173
CHAPTER 14 RESET FUNCTION .......................................................................................................176
CHAPTER 15
µ
PD78F9468...................................................................................................................180
15.1 Flash Memory Characteristics................................................................................................182
15.1.1 Programming environment.......................................................................................................... 182
15.1.2 Communication mode ................................................................................................................. 183
15.1.3 On-board pin processing............................................................................................................. 185
15.1.4 Connection on flash memory writing adapter .............................................................................. 188
CHAPTER 16 MASK OPTION .............................................................................................................189
CHAPTER 17 INSTRUCTION SET ......................................................................................................190
17.1 Operation ..................................................................................................................................190
17.1.1 Operand identifiers and description methods.............................................................................. 190
17.1.2 Description of “Operation” column............................................................................................... 191
17.1.3 Description of “Flag” column ....................................................................................................... 191
17.2 Operation List...........................................................................................................................192
17.3 Instructions Listed by Addressing Type ...............................................................................197
14 User’s Manual U15552EJ2V2UD
CHAPTER 18 ELECTRICAL SPECIFICATIONS.................................................................................200
CHAPTER 19 PACKAGE DRAWING ..................................................................................................211
CHAPTER 20 RECOMMENDED SOLDERING CONDITIONS...........................................................212
APPENDIX A DEVELOPMENT TOOLS...............................................................................................214
A.1 Software Package ....................................................................................................................216
A.2 Language Processing Software .............................................................................................216
A.3 Control Software ......................................................................................................................217
A.4 Flash Memory Writing Tools...................................................................................................218
A.5 Debugging Tools (Hardware)..................................................................................................218
A.6 Debugging Tools (Software) ...................................................................................................219
A.7 Cautions When Designing Target System ............................................................................220
APPENDIX B REGISTER INDEX .........................................................................................................221
B.1 Register Index (Alphabetic Order of Register Name)...........................................................221
B.2 Register Index (Alphabetic Order of Register Symbol) .......................................................223
APPENDIX C REVISION HISTORY ........................................................................................................225
User’s Manual U15552EJ2V2UD 15
LIST OF FIGURES (1/4)
Figure No. Title Page
2-1 I/O Circuit Types............................................................................................................................................ 36
3-1 Memory Map (
µ
PD789462) ........................................................................................................................... 38
3-2 Memory Map (
µ
PD789464) ........................................................................................................................... 39
3-3 Memory Map (
µ
PD789466) ........................................................................................................................... 40
3-4 Memory Map (
µ
PD789467) ........................................................................................................................... 41
3-5 Memory Map (
µ
PD78F9468) ......................................................................................................................... 42
3-6 Data Memory Addressing (
µ
PD789462) ........................................................................................................ 45
3-7 Data Memory Addressing (
µ
PD789464) ........................................................................................................ 46
3-8 Data Memory Addressing (
µ
PD789466) ........................................................................................................ 47
3-9 Data Memory Addressing (
µ
PD789467) ........................................................................................................ 48
3-10 Data Memory Addressing (
µ
PD78F9468)...................................................................................................... 49
3-11 Program Counter Configuration..................................................................................................................... 50
3-12 Program Status Word Configuration .............................................................................................................. 50
3-13 Stack Pointer Configuration ........................................................................................................................... 52
3-14 Data to Be Saved to Stack Memory............................................................................................................... 52
3-15 Data to Be Restored from Stack Memory ...................................................................................................... 52
3-16 General-Purpose Register Configuration....................................................................................................... 53
4-1 Port Types ..................................................................................................................................................... 65
4-2 Block Diagram of P00 to P03......................................................................................................................... 66
4-3 Block Diagram of P10 and P11...................................................................................................................... 67
4-4 Block Diagram of P40 to P43......................................................................................................................... 68
4-5 Block Diagram of P60 .................................................................................................................................... 69
4-6 Block Diagram of P61 .................................................................................................................................... 70
4-7 Block Diagram of P80 to P85......................................................................................................................... 71
4-8 Format of Port Mode Register ....................................................................................................................... 72
4-9 Format of Pull-up Resistor Option Register 0 ................................................................................................ 73
4-10 Format of Port Function Register 8................................................................................................................ 74
5-1 Block Diagram of Clock Generator ................................................................................................................ 77
5-2 Format of Processor Clock Control Register ................................................................................................. 78
5-3 Format of Suboscillation Mode Register ........................................................................................................ 79
5-4 Format of Subclock Control Register ............................................................................................................. 79
5-5 External Circuit of Main System Clock Oscillator........................................................................................... 80
5-6 External Circuit of Subsystem Clock Oscillator.............................................................................................. 81
5-7 Examples of Incorrect Resonator Connection................................................................................................ 82
5-8 Example of Switching Between System Clock and CPU Clock .....................................................................86
16 User’s Manual U15552EJ2V2UD
LIST OF FIGURES (2/4)
Figure No. Title Page
6-1 Block Diagram of Timer 30 ............................................................................................................................89
6-2 Block Diagram of Timer 40 ............................................................................................................................90
6-3 Block Diagram of Output Controller (Timer 40)..............................................................................................91
6-4 Format of 8-Bit Timer Mode Control Register 30 ........................................................................................... 94
6-5 Format of 8-Bit Timer Mode Control Register 40 ........................................................................................... 95
6-6 Format of Carrier Generator Output Control Register 40 ............................................................................... 96
6-7 Format of Port Mode Register 6..................................................................................................................... 97
6-8 Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation) ..................................................99
6-9 Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to 00H).................................100
6-10 Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH) ................................100
6-11 Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N < M)) ......101
6-12 Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N > M)) ......101
6-13 iming of Interval Timer Operation with 8-Bit Resolution (When Timer 40 Match Signal Is Selected for
Timer 30 Count Clock).................................................................................................................................102
6-14 Timing of Square-Wave Output with 8-Bit Resolution.................................................................................. 104
6-15 Timing of Interval Timer Operation with 16-Bit Resolution ...........................................................................106
6-16 Timing of Square-Wave Output with 16-Bit Resolution ................................................................................108
6-17 Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M > N)) ......................................... 110
6-18 Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M < N)) ......................................... 111
6-19 Timing of Carrier Generator Operation (When CR40 = CRH40 = N) ...........................................................112
6-20 PWM Output Mode Timing (Basic Operation).............................................................................................. 114
6-21 PWM Output Mode Timing (When CR40 and CRH40 Are Overwritten) ...................................................... 114
6-22 Case in Which Error of 1.5 Clocks (Max.) Occurs........................................................................................115
7-1 Block Diagram of Watch Timer ....................................................................................................................116
7-2 Format of Watch Timer Mode Control Register ........................................................................................... 118
7-3 Watch Timer/Interval Timer Operation Timing ............................................................................................. 120
8-1 Block Diagram of Watchdog Timer ..............................................................................................................122
8-2 Format of Watchdog Timer Clock Selection Register .................................................................................. 123
8-3 Format of Watchdog Timer Mode Register .................................................................................................. 124
9-1 Block Diagram of 8-Bit A/D Converter.......................................................................................................... 128
9-2 Format of A/D Converter Mode Register 0...................................................................................................130
9-3 Format of A/D Input Selection Register 0..................................................................................................... 131
9-4 Basic Operation of 8-Bit A/D Converter ....................................................................................................... 132
9-5 Relationship Between Analog Input Voltage and A/D Conversion Result .................................................... 133
9-6 Software-Started A/D Conversion................................................................................................................134
9-7 How to Reduce Current Consumption in Standby Mode.............................................................................. 135
User’s Manual U15552EJ2V2UD 17
LIST OF FIGURES (3/4)
Figure No. Title Page
9-8 Conversion Result Readout Timing (When Conversion Result Is Undefined Value) ................................... 136
9-9 Conversion Result Readout Timing (When Conversion Result Is Normal Value) ........................................ 136
9-10 Analog Input Pin Handling ........................................................................................................................... 137
9-11 A/D Conversion End Interrupt Request Generation Timing ......................................................................... 138
10-1 Block Diagram of LCD Controller/Driver ...................................................................................................... 140
10-2 Format of LCD Display Mode Register 0 ..................................................................................................... 141
10-3 Format of LCD Clock Control Register 0 ..................................................................................................... 143
10-4 Format of LCD Voltage Boost Control Register 0 ........................................................................................ 144
10-5 Format of Port Function Register 8.............................................................................................................. 144
10-6 Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs .................... 146
10-7 Common Signal Waveforms ........................................................................................................................ 148
10-8 Voltages and Phases of Common and Segment Signals............................................................................. 148
10-9 Four-Time-Slice LCD Display Pattern and Electrode Connections .............................................................. 149
10-10 Example of Connecting Four-Time-Slice LCD Panel ................................................................................... 150
10-11 Examples of Four-Time-Slice LCD Drive Waveform.................................................................................... 151
10-12 Example of Pin Connection for LCD Driver.................................................................................................. 152
11-1 Block Diagram of Power-on-Clear Circuit .................................................................................................... 153
11-2 Timing of Internal Reset Signal Generation of POC Circuit ......................................................................... 154
12-1 Basic Configuration of Interrupt Function..................................................................................................... 157
12-2 Format of Interrupt Request Flag Register 0 ............................................................................................... 159
12-3 Format of Interrupt Mask Flag Register 0 .................................................................................................... 159
12-4 Format of External Interrupt Mode Register 0.............................................................................................. 160
12-5 Configuration of Program Status Word ........................................................................................................ 160
12-6 Format of Key Return Mode Register 00 ..................................................................................................... 161
12-7 Block Diagram of Falling Edge Detector ...................................................................................................... 161
12-8 Flow from Generation of Non-Maskable Interrupt Request to Acknowledgment.......................................... 163
12-9 Timing of Non-Maskable Interrupt Request Acknowledgment ..................................................................... 163
12-10 Non-Maskable Interrupt Request Acknowledgment..................................................................................... 163
12-11 Interrupt Request Acknowledgment Program Algorithm .............................................................................. 164
12-12 Interrupt Request Acknowledgment Timing (Example: MOV A, r) ............................................................... 165
12-13 Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Generated in Final Clock
Under Execution)......................................................................................................................................... 165
12-14 Example of Multiple Interrupt Servicing ....................................................................................................... 166
13-1 Format of Oscillation Stabilization Time Selection Register......................................................................... 169
13-2 Releasing HALT Mode by Interrupt.............................................................................................................. 171
18 User’s Manual U15552EJ2V2UD
LIST OF FIGURES (4/4)
Figure No. Title Page
13-3 Releasing HALT Mode by RESET Input ......................................................................................................172
13-4 Releasing STOP Mode by Interrupt .............................................................................................................174
13-5 Releasing STOP Mode by RESET Input...................................................................................................... 175
14-1 Block Diagram of Reset Function ................................................................................................................176
14-2 Reset Timing by RESET Input ..................................................................................................................... 177
14-3 Reset Timing by Overflow in Watchdog Timer.............................................................................................177
14-4 Reset Timing by RESET Input in STOP Mode............................................................................................. 177
14-5 Reset Timing by Power-on Clear .................................................................................................................178
15-1 Environment for Writing Program to Flash Memory .....................................................................................182
15-2 Communication Mode Selection Format ...................................................................................................... 183
15-3 Example of Connection with Dedicated Flash Programmer.........................................................................184
15-4 VPP Pin Connection Example .......................................................................................................................185
15-5 Signal Conflict (Input Pin of Serial Interface) ...............................................................................................186
15-6 Abnormal Operation of Other Device...........................................................................................................186
15-7 Signal Conflict (Reset Pin) ........................................................................................................................... 187
15-8 Wiring Example of Flash Memory Writing Adapter Using 3-Wire Serial I/O Mode .......................................188
A-1 Development Tools......................................................................................................................................215
A-2 Condition Diagram of Connection to Target System ....................................................................................220
User’s Manual U15552EJ2V2UD 19
LIST OF TABLES (1/2)
Table No. Title Page
2-1 Types of Pin I/O Circuits and Recommended Connection of Unused Pins.................................................... 36
3-1 Internal ROM Capacity .................................................................................................................................. 43
3-2 Vector Table .................................................................................................................................................. 43
3-3 Special-Function Registers............................................................................................................................ 55
4-1 Port Functions ............................................................................................................................................... 65
4-2 Configuration of Port...................................................................................................................................... 66
4-3 Port Mode Registers and Output Latch Settings When Using Alternate Functions........................................ 73
5-1 Configuration of Clock Generator .................................................................................................................. 76
5-2 Maximum Time Required for Switching CPU Clock....................................................................................... 85
6-1 Operation Modes ........................................................................................................................................... 87
6-2 Configuration of 8-Bit Timers 30 and 40 ........................................................................................................ 88
6-3 Interval Time of Timer 30 (at fX = 5.0 MHz Operation)................................................................................... 99
6-4 Interval Time of Timer 40 (at fX = 5.0 MHz Operation)................................................................................... 99
6-5 Square-Wave Output Range of Timer 40 (at fX = 5.0 MHz Operation) ........................................................ 103
6-6 Interval Time with 16-Bit Resolution (at fX = 5.0 MHz Operation) ................................................................ 105
6-7 Square-Wave Output Range with 16-Bit Resolution (at fX = 5.0 MHz Operation) ........................................ 107
7-1 Interval Time of Interval Timer ..................................................................................................................... 117
7-2 Configuration of Watch Timer ...................................................................................................................... 117
7-3 Interval Time of Interval Timer ..................................................................................................................... 119
8-1 Program Loop Detection Time of Watchdog Timer...................................................................................... 121
8-2 Interval Time of Watchdog Timer................................................................................................................. 121
8-3 Configuration of Watchdog Timer ................................................................................................................ 122
8-4 Program Loop Detection Time of Watchdog Timer...................................................................................... 125
8-5 Interval Time of Watchdog Timer................................................................................................................. 126
9-1 Configuration of 8-Bit A/D Converter ........................................................................................................... 127
10-1 Maximum Number of Pixels......................................................................................................................... 139
10-2 Configuration of LCD Controller/Driver ........................................................................................................ 139
10-3 Frame Frequencies (Hz).............................................................................................................................. 143
10-4 COM Signals ............................................................................................................................................... 147
10-5 Select and Deselect Voltages (COM0 to COM3)......................................................................................... 149
10-6 Output Voltages of VLC0 to VLC2 Pins ........................................................................................................... 152
20 User’s Manual U15552EJ2V2UD
LIST OF TABLES (2/2)
Table No. Title Page
12-1 Interrupt Source List ....................................................................................................................................156
12-2 Flags Corresponding to Interrupt Request Signal Names............................................................................158
12-3 Time from Generation of Maskable Interrupt Request to Servicing..............................................................164
13-1 Operation Statuses in HALT Mode .............................................................................................................. 170
13-2 Operation After Releasing HALT Mode........................................................................................................ 172
13-3 Operation Statuses in STOP Mode.............................................................................................................. 173
13-4 Operation After Releasing STOP Mode ....................................................................................................... 175
14-1 Hardware Status After Reset ....................................................................................................................... 179
15-1 Differences Between
µ
PD78F9468 and Mask ROM Versions ..................................................................... 180
15-2 Differences in LCD Controller/Driver of
µ
PD78F9468 and Mask ROM Version........................................... 181
15-3 Communication Mode List ...........................................................................................................................183
15-4 Pin Connection List......................................................................................................................................184
17-1 Operand Identifiers and Description Methods.............................................................................................. 190
20-1 Surface Mounting Type Soldering Conditions..............................................................................................212
User’s Manual U15552EJ2V2UD 21
CHAPTER 1 GENERAL
1.1 Features
• ROM and RAM capacities
Item Data Memory
Part Number
Program Memory
(ROM) Internal High-Speed
RAM
LCD Display RAM
µ
PD789462 4 KB
µ
PD789464 8 KB
256 bytes
µ
PD789466 16 KB
µ
PD789467
Mask ROM
24 KB
µ
PD78F9468 Flash memory 32 KB
512 bytes
23 × 4 bits
• Minimum instruction execution time can be changed from high-speed (0.4
µ
s: @ 5.0 MHz operation with main
system clock) to ultra-low-speed (122
µ
s: @ 32.768 kHz operation with subsystem clock)
• I/O ports: 18
• 8-bit resolution A/D converter: 1 channel
• Timer: 4 channels
• 8-bit timer: 2 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel
• LCD controller/driver (on-chip voltage booster)
Segment signals: 23, common signals: 4
• Vectored interrupt sources: 9
• On-chip power-on clear circuit (mask option for mask ROM versions)
• Power supply voltage: VDD = 1.8 to 5.5 VNote
• Operating ambient temperature: TA = –40 to +85°C
Note For mask ROM versions when the use of the POC circuit is selected or for flash memory versions, the
minimum value of the operation power supply voltage is the POC detection voltage (1.9 ±0.1 V).
1.2 Applications
Remote controllers, healthcare equipment, etc.
CHAPTER 1 GENERAL
22 User’s Manual U15552EJ2V2UD
1.3 Ordering Information
Part Number Package Internal ROM
µ
PD789462GB-×××-8ET 52-pin plastic LQFP (10 × 10) Mask ROM
µ
PD789464GB-×××-8ET 52-pin plastic LQFP (10 × 10) Mask ROM
µ
PD789466GB-×××-8ET 52-pin plastic LQFP (10 × 10) Mask ROM
µ
PD789467GB-×××-8ET 52-pin plastic LQFP (10 × 10) Mask ROM
µ
PD78F9468GB-8ET 52-pin plastic LQFP (10 × 10) Flash memory
µ
PD789462GB-×××-8ET-A 52-pin plastic LQFP (10 × 10) Mask ROM
µ
PD789464GB-×××-8ET-A 52-pin plastic LQFP (10 × 10) Mask ROM
µ
PD789466GB-×××-8ET-A 52-pin plastic LQFP (10 × 10) Mask ROM
µ
PD789467GB-×××-8ET-A 52-pin plastic LQFP (10 × 10) Mask ROM
µ
PD78F9468GB-8ET-A 52-pin plastic LQFP (10 × 10) Flash memory
Remarks 1. Products that have the part numbers suffixed by "-A" are lead-free products.
2. ××× indicates ROM code suffix.
CHAPTER 1 GENERAL
User’s Manual U15552EJ2V2UD 23
1.4 Pin Configuration (Top View)
52-pin plastic LQFP (10 × 10)
µ
PD789462GB-×××-8ET
µ
PD789464GB-×××-8ET
µ
PD789466GB-×××-8ET
µ
PD789467GB-×××-8ET
µ
PD78F9468GB-8ET
µ
PD789462GB-×××-8ET-A
µ
PD789464GB-×××-8ET-A
µ
PD789466GB-×××-8ET-A
µ
PD789467GB-×××-8ET-A
µ
PD78F9468GB-8ET-A
RESET
P60/TO40
P43/KR03
P42/KR02
P41/KR01
P40/KR00
P03
P02
P01
P00
INTP0/ANI0/P61
X1
X2
V
DD
V
SS
XT2
XT1
IC0 (V
PP
)
V
LC2
CAPL
CAPH
V
LC1
52 51 50 49 48 47 46 45 44 43 42
14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
39
38
37
36
35
34
33
32
31
30
29
P11
P10
P81/S21
P82/S20
P83/S19
P84/S18
P85/S17
S16
S15
S14
S13
S12
S11
S10
S9
COM0
COM1
COM2
COM3
S0
S1
S2
S3
S4
S5
S6
S7
S8
V
LC0
P80/S22
12
13
28
27
41 40
25 26
Caution Connect the IC0 (Internally Connected) pin directly to VSS.
Remark The parenthesized values apply to the
µ
PD78F9468.
CHAPTER 1 GENERAL
24 User’s Manual U15552EJ2V2UD
ANI0: Analog input RESET: Reset
CAPH, CAPL: LCD power supply capacitance S0 to S22: Segment output
control TO40: Timer output
COM0 to COM3: Common output VDD: Power supply
IC0: Internally connected VLC0 to VLC2: Power supply for LCD
INTP0: External interrupt input VPP: Programming power supply
KR00 to KR03: Key return VSS: Ground
P00 to P03: Port 0 X1, X2: Crystal (main system clock)
P10, P11: Port 1 XT1, XT2: Crystal (subsystem clock)
P40 to P43: Port 4
P60, P61: Port 6
P80 to P85: Port 8
CHAPTER 1 GENERAL
User’s Manual U15552EJ2V2UD 25
1.5 78K/0S Series Lineup
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
52-pin SIO + resistance division method LCD (24 × 4)
8-bit A/D + internal voltage boosting method LCD (23 × 4)
PD789327
LCD drive
80-pin
80-pin
PD789436
PD789446
PD789426
PD789456
PD789417A
PD789407A
PD789316
PD789467
PD789306
PD789426 with 10-bit A/D
PD789860 with enhanced timer function, SIO, and expanded ROM and RAM
PD789446 with 10-bit A/D
SIO + 8-bit A/D + resistance division method LCD (28 × 4)
SIO + 8-bit A/D + internal voltage boosting method LCD (15 × 4)
PD789407A with 10-bit A/D
SIO + 8-bit A/D + internal voltage boosting method LCD (5 × 4)
RC oscillation version of PD789306
SIO + internal voltage boosting method LCD (24 × 4)
64-pin
64-pin
52-pin
64-pin
64-pin
64-pin
SIO + 10-bit A/D + internal voltage boosting method LCD (28 × 4)
80-pin
SIO + 8-bit A/D + resistance division method LCD (28 × 4)
80-pin PD789478
PD789488
64-pin
Products under
development
Products in mass
production
Small-scale package, general-purpose applications
78K/0S
Series
28-pin
PD789014 with enhanced timer function and expanded ROM and RAM
On-chip UART and capable of low-voltage (1.8 V) operation
PD789074 with subsystem clock added
Inverter control
44-pin PD789842 On-chip inverter controller and UART
PD789146
PD789156
44-pin
Small-scale package, general-purpose applications and A/D function
44-pin
30-pin
30-pin
30-pin
30-pin
PD789124A
PD789134A
PD789177
PD789167
30-pin
30-pin
PD789104A
PD789114A
PD789167 with 10-bit A/D
PD789104A with enhanced timer
PD789124A with 10-bit A/D
RC oscillation version of PD789104A
PD789104A with 10-bit A/D
PD789026 with 8-bit A/D and multiplier added
PD789104A with EEPROM
TM
added
PD789146 with 10-bit A/D
PD789177Y
PD789167Y
Y subseries supports SMB.
USB
88-pin PD789830
PD789835
144-pin
UART + dot LCD (40 × 16)
UART + 8-bit A/D + dot LCD (total display outputs: 96)
42-/44-pin
44-pin
30-pin
20-pin
20-pin
PD789026 with enhanced timer function
RC oscillation version of PD789052
VFD drive
52-pin
64-pin
PD789871 On-chip VFD controller (total display outputs: 25)
Meter control
PD789881 UART + resistance division method LCD (26 × 4)
30-pin PD789074 with enhanced timer function and expanded ROM and RAM
44-pin PD789800 For PC keyboard. On-chip USB function
Keyless entry
20-pin
20-pin
30-pin
30-pin
44-pin
On-chip POC and key return circuit
RC oscillation version of PD789860
On-chip bus controller
On-chip CAN controller
µµ
µ
µ
µ
µ
µ
µ
µ
µ
PD789074
PD789088
PD789062
PD789014
PD789046
PD789026
PD789052
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
PD789860
PD789861
PD789862
µ
µ
µ
PD789850A
PD789852
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
PD789850A with enhanced timer, A/D, etc.
µ
µ
µ
µ
µ
µ
PD789860 without EEPROM
TM
, POC, and LVI
µµ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
Remark VFD (Vacuum Fluorescent Display) is referred to as FIP™ (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
CHAPTER 1 GENERAL
26 User’s Manual U15552EJ2V2UD
The major functional differences among the subseries are listed below.
Series for General-Purpose Applications and LCD Drive
Timer VDD Function
Subseries
ROM
Capacity 8-Bit 16-Bit Watch WDT
8-Bit
A/D
10-Bit
A/D
Serial Interface I/O
MIN.Value
Remarks
µ
PD789046 16 KB 1 ch
µ
PD789026 4 KB to 16 KB
1 ch 34
µ
PD789088
16 KB to 32 KB
3 ch
µ
PD789074 2 KB to 8 KB 1 ch
1 ch
24
µ
PD789014 2 KB to 4 KB 2 ch −
−
1 ch − − 1 ch (UART: 1ch)
22
1.8 V −
Small-
scale
package,
general-
purpose
applica-
tions
µ
PD789062 4 KB − 14 RC-oscillation
version
µ
PD789052 −
µ
PD789177 − 8 ch
µ
PD789167
16 KB to 24 KB
3 ch 1 ch
8 ch −
31 −
µ
PD789156 − 4 ch
µ
PD789146
8 KB to 16 KB
4 ch −
On-chip
EEPROM
µ
PD789134A − 4 ch
µ
PD789124A 4 ch −
RC-oscillation
version
µ
PD789114A − 4 ch
Small-
scale
package,
general-
purpose
applica-
tions +
A/D
converter
µ
PD789104A
2 KB to 8 KB
1 ch
1 ch
−
1ch
4 ch −
1 ch (UART: 1ch)
20
1.8 V
−
µ
PD789835
24 KB to 60 KB
6 ch − 3 ch 37 1.8 VNote
µ
PD789830 24 KB 1 ch
− 1 ch (UART: 1ch)
30 2.7 V
Dot LCD
supported
µ
PD789488
32 KB to 48 KB
−
8 ch
µ
PD789478
24 KB to 48 KB
8 ch −
2 ch (UART: 1ch) 45
µ
PD789417A − 7 ch
LCD
drive
µ
PD789407A
12 KB to 24 KB
3 ch
1 ch
1 ch 1 ch
7 ch −
1 ch (UART: 1ch) 43
1.8 V −
µ
PD789456 − 6 ch
µ
PD789446 6 ch −
30
µ
PD789436 − 6 ch
µ
PD789426
12 KB to 16 KB
6 ch
40
µ
PD789316 RC-oscillation
version
µ
PD789306
8 KB to 16 KB
− 2 ch (UART: 1ch) 23
µ
PD789467 1 ch − 18
µ
PD789327
4 KB to 24 KB
2 ch
−
−
−
1 ch 21
−
Note Flash memory version: 3.0 V
CHAPTER 1 GENERAL
User’s Manual U15552EJ2V2UD 27
Series for ASSP
Timer VDD Function
Subseries
ROM
Capacity 8-Bit 16-Bit Watch WDT
8-Bit
A/D
10-Bit
A/D
Serial Interface I/O
MIN.Value
Remarks
USB
µ
PD789800 8 KB 2 ch − − 1 ch − − 2 ch (USB: 1ch) 31 4.0 V −
Inverter
control
µ
PD789842 8 KB to 16 KB 3 ch Note 1 1 ch 1 ch 8 ch − 1 ch (UART: 1ch) 30 4.0 V −
µ
PD789852 24 KB to 32KB 3 ch − 8 ch 3 ch (UART: 2 ch) 31
On-chip
bus
controller
µ
PD789850A 16 KB 1 ch
1 ch − 1 ch
4 ch − 2 ch (UART: 1ch) 18
4.0 V −
µ
PD789861 1.8 V RC-oscillation
version,
on-chip
EEPROM
µ
PD789860
4 KB 2 ch − − 1 ch − − − 14
Keyless
entry
µ
PD789862 16 KB 1 ch 2 ch 1 ch (UART: 1ch) 22
On-chip
EEPROM
VFD
drive
µ
PD789871 4 KB to 8 KB 3 ch − 1 ch 1 ch − − 1 ch 33 2.7 V −
Meter
control
µ
PD789881 16 KB
2 ch 1 ch − 1 ch − − 1 ch (UART: 1 ch) 28 2.7 VNote 2 −
Notes 1. 10-bit timer: 1 channel
2. Flash memory version: 3.0 V
CHAPTER 1 GENERAL
28 User’s Manual U15552EJ2V2UD
1.6 Block Diagram
V
DD
V
SS
IC0
(V
PP
)
78K/0S
CPU core
ROM
(Flash
memory)
8-bit
timer
30
P00 to P03
Port 0
P10, P11
Port 1
Port 4 P40 to P43
Port 6 P60, P61
Port 8
Watchdog
timer
S17/P85 to S22/P80
COM0 to COM3
RAM
RAM space
for LCD
data
8-bit
timer
40
Cascaded
16-bit
timer
A/D converter
ANI0/P61
Note
V
LC0
LCD
controller
driver
System
control
RESET
X1
X2
XT1
XT2
Interrupt
control KR00/P40 to
KR03/P43
INTP0/P61
P80 to P85
Watch
timer
TO40/P60
Power-on clear
V
LC1
V
LC2
CAPH
CAPL
S0 to S16
Note Only when use of the POC circuit is selected by a mask option in the case of the mask ROM version
(
µ
PD789462, 789464, 789466, and 789467).
Remarks 1. The internal ROM and RAM capacities vary depending on the product.
2. The parenthesized values apply to the
µ
PD78F9468.
CHAPTER 1 GENERAL
User’s Manual U15552EJ2V2UD 29
1.7 Overview of Functions
Part Number
Item
µ
PD789462
µ
PD789464
µ
PD789466
µ
PD789467
µ
PD78F9468
Mask ROM Flash memoryROM
4 KB 8 KB 16 KB 24 KB 32 KB
High-speed RAM 256 bytes 512 bytes
Internal memory
LCD display RAM 23 × 4 bits
Main system clock (oscillation frequency) Ceramic/crystal oscillation (1.0 to 5.0 MHz)
Subsystem clock (oscillation frequency) Crystal oscillation (32.768 kHz)
0.4
µ
s/1.6
µ
s (@ 5.0 MHz operation with main system clock) Minimum instruction execution time
122
µ
s (@ 32.768 kHz operation with subsystem clock)
General-purpose registers 8 bits × 8 registers
Instruction set • 16-bit operations
• Bit manipulations (such as set, reset, and test)
I/O ports Total: 18Note 1
CMOS I/O: 12
CMOS input: 6Note 1
Timers • 8-bit timer: 2 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel
Timer outputs 1
A/D converter 8-bit resolution × 1 channel
LCD controller/driver • Segment signal outputs: 23Note 1
• Common signal outputs: 4
Maskable Internal: 6, external: 2 Vectored interrupt
sources Non-maskable Internal: 1
Reset • Reset by RESET input
• Internal reset by watchdog timer
• Reset by power-on-clear circuitNote 2
Power supply voltage VDD = 1.8 to 5.5 V Note 3
Operating ambient temperature TA = −40 to +85°C
Package 52-pin plastic LQFP (10 × 10)
Notes 1. Six of these pins are used to select either the port function or LCD segment output via the port function
register.
2. For mask ROM versions (
µ
PD789462, 789464, 789466, 789467), this is available only when use of POC
circuit is selected by a mask option.
3. For mask ROM versions when use of the POC circuit is selected or for flash memory versions, the
minimum value of the operating power supply voltage is the POC detection voltage (1.9 ±0.1 V).
CHAPTER 1 GENERAL
30 User’s Manual U15552EJ2V2UD
An outline of the timers is shown below.
8-Bit Timer 30 8-Bit Timer 40 Watch Timer Watchdog Timer
Interval timer 1 channel 1 channel 1 channelNote 1 1 channelNote 2 Operation
mode External event counter – – – –
Timer output – 1 output – –
Square-wave output – 1 output – –
Capture – – – –
Function
Interrupt sources 1 1 2 2
Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.
2. The watchdog timer has watchdog timer and interval timer functions. However, use the watchdog timer
by selecting either the watchdog timer function or interval timer function.
User’s Manual U15552EJ2V2UD 31
CHAPTER 2 PIN FUNCTIONS
2.1 List of Pin Functions
(1) Port pins
Pin Name I/O Function After Reset Alternate Function
P00 to P03 I/O Port 0.
4-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, the use of on-chip pull-up
resistors can be specified in port units using pull-up resistor
option register 0 (PU0).
Input −
P10, P11 I/O Port 1.
2-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, the use of on-chip pull-up
resistors can be specified in port units using pull-up resistor
option register 0 (PU0).
Input −
P40 to P43 I/O Port 4.
4-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, the use of on-chip pull-up
resistors can be specified in port units using pull-up resistor
option register 0 (PU0), or key return mode register 00
(KRM00).
Input KR00 to KR03
P60 TO40
P61
I/O Port 6.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Input
INTP0/ANI0
P80 to P85 Input Port 8.
6-bit input port.
Input S22 to S17
CHAPTER 2 PIN FUNCTIONS
32 User’s Manual U15552EJ2V2UD
(2) Non-port pins
Pin Name I/O Function After Reset Alternate Function
INTP0 Input External interrupt input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified.
Input P61/ANI0
KR00 to KR03 Input Key return signal detection Input P40 to P43
TO40 Output 8-bit timer 40 output Input P60
ANI0 Input A/D converter analog input Input P61/INTP0
S0 to S16 Low-level
output
−
S17 to S22
Output LCD controller/driver segment signal outputs
Input P85 to P80
COM0 to COM2 Output LCD controller/driver common signal outputs Low-level
output
−
Mask ROM
version
Low-level
output
COM3 Output
Flash memory
version
High-level
output
−
CAPH, CAPL − Voltage boost capacitor for LCD drive connection pins − −
VLC0 to VLC2 − LCD drive voltage − −
X1 Input − −
X2 −
Connecting crystal resonator for main system clock oscillation
− −
XT1 Input − −
XT2 −
Connecting crystal resonator for subsystem clock oscillation
− −
RESET Input System reset input Input −
VDD − Positive power supply − −
VSS − Ground potential − −
IC0 − Internally connected. Connect directly to VSS. − −
VPP – Sets flash memory programming mode. Applies high voltage
when a program is written or verified.
− −
CHAPTER 2 PIN FUNCTIONS
User’s Manual U15552EJ2V2UD 33
2.2 Description of Pin Functions
2.2.1 P00 to P03 (Port 0)
These pins constitute a 4-bit I/O port and can be set to the input or output port mode in 1-bit units using port mode
register 0 (PM0). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor
option register 0 (PU0) in port units.
2.2.2 P10, P11 (Port 1)
These pins constitute a 2-bit I/O port and can be set to the input or output port mode in 1-bit units using port mode
register 1 (PM1). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor
option register 0 (PU0) in port units.
2.2.3 P40 to P43 (Port 4)
These pins constitute a 4-bit I/O port. In addition, they also function as key return signal detection pins.
P40 to P43 can be specified in the following operation modes in 1-bit units.
(1) Port mode
In this mode, P40 to P43 function as a 4-bit I/O port. These pins can be set to the input or output port mode
in 1-bit units using port mode register 4 (PM4). When used as an input port, use of an on-chip pull-up
resistor can be specified by pull-up resistor option register 0 (PU0) or key return mode register 00 (KRM00) in
port units.
(2) Control mode
In this mode, the pins function as key return signal detection pins (KR00 to KR03).
2.2.4 P60, P61 (Port 6)
These pins constitute a 2-bit I/O port. In addition, they also function as a timer output, external interrupt input, and
analog input.
P60 and P61 can be specified in the following operation modes in 1-bit units.
(1) Port mode
In this mode, P60 and P61 function as a 2-bit I/O port. These pins can be set to the input or output port
mode in 1-bit units using port mode register 6 (PM6).
(2) Control mode
In this mode, the pins function as a timer output, external interrupt input, and analog input.
(a) TO40
This is the timer output pin to timer 40.
(b) INTP0
This is the external interrupt input pin for which the valid edge (rising edge, falling edge, or both rising
and falling edges) can be specified.
(c) ANI0
This is the analog input pin of the A/D converter.
CHAPTER 2 PIN FUNCTIONS
34 User’s Manual U15552EJ2V2UD
2.2.5 P80 to P85 (Port 8)
These pins constitute a 6-bit input port. In addition, they also function as LCD controller/driver segment signal
outputs.
P80 to P85 can be specified in the following operation modes in 1-bit units by using port function register 8 (PF8).
(1) Port mode
In this mode, P80 to P85 function as a 6-bit input port.
(2) Control mode
In this mode, the pins function as LCD controller/driver segment signal outputs (S17 to S22).
2.2.6 S0 to S16
These pins are segment signal output pins for the LCD controller/driver.
2.2.7 COM0 to COM3
These pins are common signal output pins for the LCD controller/driver.
2.2.8 VLC0 to VLC2
These pins are the power supply voltage pins for driving the LCD.
2.2.9 CATH, CAPL
These pins are used to connect a voltage booster capacitor for driving the LCD.
2.2.10 RESET
This pin inputs an active-low system reset signal.
2.2.11 X1, X2
These pins are used to connect a crystal resonator for main system clock oscillation.
To supply an external clock, input the clock to X1 and input the inverted signal to X2.
2.2.12 XT1, XT2
These pins are used to connect a crystal resonator for subsystem clock oscillation.
To supply an external clock, input the clock to XT1 and input the inverted signal to XT2.
2.2.13 VDD
This is the positive power supply pin.
2.2.14 VSS
This is the ground pin.
CHAPTER 2 PIN FUNCTIONS
User’s Manual U15552EJ2V2UD 35
2.2.15 VPP (
µ
PD78F9468 only)
A high voltage should be applied to this pin when the flash memory programming mode is set and when the
program is written or verified.
Perform either of the following.
• Independently connect a 10 kΩ pull-down resistor to VPP.
• Use the jumper on the board to connect VPP to the dedicated flash programmer in programming mode or to VSS
in normal operation mode.
If the wiring between the VPP and VSS pins is long or external noise is superimposed on the VPP pin, the user
program may not run correctly.
2.2.16 IC0 (mask ROM version only)
The IC0 (Internally Connected) pin is used to set the
µ
PD789462, 789464, 789466, and 789467 in the test mode
before shipment. In the normal operation mode, directly connect this pin to the VSS pin with as short a wiring length as
possible.
If a potential difference is generated between the IC0 pin and VSS pin due to a long wiring length, or an external
noise superimposed on the IC0 pin, the user program may not run correctly.
• Directly connect the IC0 pin to the VSS pin.
V
SS
IC0
Keep short
CHAPTER 2 PIN FUNCTIONS
36 User’s Manual U15552EJ2V2UD
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 2-1.
For the I/O circuit configuration of each type, see Figure 2-1.
Table 2-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins
Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins
P00 to P03
P10, P11
5-A I/O Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P40/KR00 to P43/KR03 8-A
P60/TO40 5
P61/INTP0/ANI0 33 Input: Independently connect to VSS via a resistor.
Output: Leave open.
P80/S22 to P85/S17 17-O
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
S0 to S16 17-D
COM0 to COM3 18-B
Output
VLC0 to VLC2
CAPH, CAPL
−
Leave open.
XT1 Input Connect to VSS.
XT2
−
− Leave open.
RESET 2 Input −
IC0 (mask ROM version) Connect directly to VSS.
VPP (
µ
PD78F9468)
− −
Independently connect VPP to a 10 kΩ pull-down resistor or directly
connect to VSS.
Figure 2-1. I/O Circuit Types (1/2)
Type 2 Type 5
Schmitt-triggered input with hysteresis characteristics.
IN
P-ch
IN/OUT
Data
Output
disable
Input
enable
V
DD
N-ch
V
SS
CHAPTER 2 PIN FUNCTIONS
User’s Manual U15552EJ2V2UD 37
Figure 2-1. I/O Circuit Types (2/2)
Type 5-A Type 8-A
Pull-up
enable
V
DD
P-ch
P-ch
IN/OUT
Data
Output
disable
Input
enable
V
DD
N-ch
V
SS
Pull-up
enable
V
DD
P-ch
Data
V
DD
P-ch
Output
disable
IN/OUT
N-ch
V
SS
Type 17-D Type 17-O
P-ch
N-ch
P-ch
N-ch
N-ch
N-ch
data OUT
V
LC0
V
LC1
SEG
V
LC2
P-ch
P-ch
V
SS
P-ch
N-ch
P-ch
N-ch
N-ch
N-ch
data
V
LC0
V
LC1
SEG
V
LC2
P-ch
P-ch
V
SS
IN/OUT
Input
enable
V
DD
V
SS
Type 18-B Type 33
P-ch
N-ch
P-ch
N-ch
P-ch
N-ch P-ch
N-ch
data
P-ch N-ch
V
LC1
V
LC0
V
LC2
OUT
COM
V
SS
N-ch
P-ch
IN/OUT
V
DD
Data
Output
disable
+
–
P-ch
N-ch
Comparator
V
REF
Input
enable
V
SS
V
SS
Input
enable
(Threshold voltage)
38 User’s Manual U15552EJ2V2UD
CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
The
µ
PD78467 Subseries can access 64 KB of memory space. Figures 3-1 to 3-5 show the memory maps.
Figure 3-1. Memory Map (
µ
PD789462)
Special-function registers
256 × 8 bits
Internal high-speed RAM
256 × 8 bits
LCD display RAM
23 × 4 bits
Reserved
Reserved
Internal ROM
4096 × 8 bits
FFFFH
FF00H
FEFFH
FE00H
FDFFH
FA00H
F9FFH
0000H
Program
memory space
Data
memory space
0FFFH
0000H
Program area
0080H
007FH
Program area
0040H
003FH
CALLT table area
0014H
0013H
Vector table area
FA17H
FA16H
1000H
0FFFH
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15552EJ2V2UD 39
Figure 3-2. Memory Map (
µ
PD789464)
Special-function registers
256 × 8 bits
Internal high-speed RAM
256 × 8 bits
Internal ROM
8192 × 8 bits
FFFFH
FF00H
FEFFH
0000H
Program
memory space
Data
memory space
1FFFH
0000H
Program area
0080H
007FH
Program area
0040H
003FH
CALLT table area
0014H
0013H
Vector table area
LCD display RAM
23 × 4 bits
Reserved
Reserved
FE00H
FDFFH
FA00H
F9FFH
FA17H
FA16H
2000H
1FFFH
CHAPTER 3 CPU ARCHITECTURE
40 User’s Manual U15552EJ2V2UD
Figure 3-3. Memory Map (
µ
PD789466)
Special-function registers
256 × 8 bits
Internal high-speed RAM
512 × 8 bits
Internal ROM
16384 × 8 bits
FFFFH
FF00H
FEFFH
0000H
Program
memory space
Data
memory space
3FFFH
0000H
Program area
0080H
007FH
Program area
0040H
003FH
CALLT table area
0014H
0013H
Vector table area
LCD display RAM
23 × 4 bits
Reserved
Reserved
FD00H
FCFFH
FA00H
F9FFH
FA17H
FA16H
4000H
3FFFH
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15552EJ2V2UD 41
Figure 3-4. Memory Map (
µ
PD789467)
Special-function registers
256 × 8 bits
Internal high-speed RAM
512 × 8 bits
Internal ROM
24576 × 8 bits
FFFFH
FF00H
FEFFH
0000H
Program
memory space
Data
memory space
5FFFH
0000H
Program area
0080H
007FH
Program area
0040H
003FH
CALLT table area
0014H
0013H
Vector table area
LCD display RAM
23 × 4 bits
Reserved
Reserved
FD00H
FCFFH
FA00H
F9FFH
FA17H
FA16H
6000H
5FFFH
CHAPTER 3 CPU ARCHITECTURE
42 User’s Manual U15552EJ2V2UD
Figure 3-5. Memory Map (
µ
PD78F9468)
Special-function registers
256 × 8 bits
Internal high-speed RAM
512 × 8 bits
Flash memory
32768 × 8 bits
FFFFH
FF00H
FEFFH
0000H
Program
memory space
Data
memory space
7FFFH
0000H
Program area
0080H
007FH
Program area
0040H
003FH
CALLT table area
0014H
0013H
Vector table area
LCD display RAM
23 × 4 bits
Reserved
Reserved
FD00H
FCFFH
FA00H
F9FFH
FA17H
FA16H
8000H
7FFFH
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15552EJ2V2UD 43
3.1.1 Internal program memory space
The internal program memory space stores programs and table data. This space is usually addressed by the
program counter (PC).
The
µ
PD789467 Subseries provides internal ROM (or flash memory) with the following capacity for each product.
Table 3-1. Internal ROM Capacity
Part Number Internal ROM
Structure Capacity
µ
PD789462 4096 × 8 bits
µ
PD789464 8192 × 8 bits
µ
PD789466 16384 × 8 bits
µ
PD789467
Mask ROM
24576 × 8 bits
µ
PD78F9468 Flash memory 32768 × 8 bits
The following areas are allocated to the internal program memory space.
(1) Vector table area
The 20-byte area of addresses 0000H to 0013H is reserved as a vector table area. This area stores program
start addresses to be used when branching by RESET input or interrupt request generation. Of a 16-bit
program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd
address.
Table 3-2. Vector Table
Vector Table Address Interrupt Request Vector Table Address Interrupt Request
0000H RESET input 000CH INTTM30
0004H INTWDT 000EH INTTM40
0006H INTP0 0010H INTKR00
0008H INTAD 0012H INTWTI
000AH INTWT
(2) CALLT instruction table area
The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of
addresses 0040H to 007FH.
CHAPTER 3 CPU ARCHITECTURE
44 User’s Manual U15552EJ2V2UD
3.1.2 Internal data memory (internal high-speed RAM) space
µ
PD789467 Subseries products incorporate the following RAM.
(1) Internal high-speed RAM
Internal high-speed RAM is incorporated in the area between FE00H and FEFFH in the
µ
PD789462 and
789464, and in the area between FD00H and FEFFH in the
µ
PD789466, 789467, and 78F9468.
The internal high-speed RAM is also used as a stack.
(2) LCD display RAM
LCD display RAM is allocated in the area between FA00H and FA16H. The LCD display RAM can also be
used as ordinary RAM.
3.1.3 Special-function register (SFR) area
Special-function registers (SFRs) of on-chip peripheral hardware are allocated in the area between FF00H and
FFFFH (see Table 3-3).
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15552EJ2V2UD 45
3.1.4 Data memory addressing
The
µ
PD789467 Subseries is provided with a variety of addressing modes to make memory manipulation as
efficient as possible. At the addresses corresponding to data memory area especially, specific addressing modes that
correspond to the particular function an area, such as the special-function registers, are available. Figures 3-6 to 3-10
show the data memory addressing modes.
Figure 3-6. Data Memory Addressing (
µ
PD789462)
Special-function registers (SFRs)
256 × 8 bits
Internal high-speed RAM
256 × 8 bits
Internal ROM
4096 × 8 bits
FFFFH
0000H
Direct addressing
Register indirect
addressing
Based addressing
FF00H
FEFFH
FF20H
FF1FH
FE20H
FE1FH
SFR addressing
Short direct
addressing
LCD display RAM
23 × 4 bits
Reserved
Reserved
FE00H
FDFFH
FA00H
F9FFH
1000H
0FFFH
FA17H
FA16H
CHAPTER 3 CPU ARCHITECTURE
46 User’s Manual U15552EJ2V2UD
Figure 3-7. Data Memory Addressing (
µ
PD789464)
Special-function registers (SFRs)
256 × 8 bits
Internal high-speed RAM
256 × 8 bits
Internal ROM
8192 × 8 bits
FFFFH
0000H
Direct addressing
Register indirect
addressing
Based addressing
FF00H
FEFFH
FF20H
FF1FH
FE20H
FE1FH
SFR addressing
Short direct
addressing
LCD display RAM
23 × 4 bits
Reserved
Reserved
FE00H
FDFFH
FA00H
F9FFH
2000H
1FFFH
FA17H
FA16H
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15552EJ2V2UD 47
Figure 3-8. Data Memory Addressing (
µ
PD789466)
Special-function registers (SFRs)
256 × 8 bits
Internal high-speed RAM
512 × 8 bits
Internal ROM
16384 × 8 bits
FFFFH
0000H
Direct addressing
Register indirect
addressing
Based addressing
FF00H
FEFFH
FF20H
FF1FH
FE20H
FE1FH
SFR addressing
Short direct
addressing
LCD display RAM
23 × 4 bits
Reserved
Reserved
FD00H
FCFFH
FA00H
F9FFH
4000H
3FFFH
FA17H
FA16H
CHAPTER 3 CPU ARCHITECTURE
48 User’s Manual U15552EJ2V2UD
Figure 3-9. Data Memory Addressing (
µ
PD789467)
Special-function registers (SFRs)
256 × 8 bits
Internal high-speed RAM
512 × 8 bits
Internal ROM
24576 × 8 bits
FFFFH
0000H
Direct addressing
Register indirect
addressing
Based addressing
FF00H
FEFFH
FF20H
FF1FH
FE20H
FE1FH
SFR addressing
Short direct
addressing
LCD display RAM
23 × 4 bits
Reserved
Reserved
FD00H
FCFFH
FA00H
F9FFH
6000H
5FFFH
FA17H
FA16H
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15552EJ2V2UD 49
Figure 3-10. Data Memory Addressing (
µ
PD78F9468)
Special-function registers (SFRs)
256 × 8 bits
Internal high-speed RAM
512 × 8 bits
Flash memory
32768 × 8 bits
FFFFH
0000H
Direct addressing
Register indirect
addressing
Based addressing
FF00H
FEFFH
FF20H
FF1FH
FE20H
FE1FH
SFR addressing
Short direct
addressing
LCD display RAM
23 × 4 bits
Reserved
Reserved
FD00H
FCFFH
FA00H
F9FFH
8000H
7FFFH
FA17H
FA16H
CHAPTER 3 CPU ARCHITECTURE
50 User’s Manual U15552EJ2V2UD
3.2 Processor Registers
The
µ
PD789467 Subseries provides the following on-chip processor registers.
3.2.1 Control registers
The control registers contain special functions to control the program sequence statuses and stack memory. The
program counter, program status word, and stack pointer are control registers.
(1) Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be
executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction
to be fetched. When a branch instruction is executed, immediate data or register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-11. Program Counter Configuration
015
PC14PC15PC PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction
execution.
The program status word contents are automatically stacked upon interrupt request generation or PUSH
PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW
instructions.
RESET input sets PSW to 02H.
Figure 3-12. Program Status Word Configuration
70
IE Z 0 AC 0 0 1 CY
PSW
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15552EJ2V2UD 51
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledgment operations of the CPU.
When 0, IE is set to the interrupt disabled status (DI), and interrupt requests other than non-maskable
interrupt are all disabled.
When 1, IE is set to the interrupt enabled status (EI). Interrupt request acknowledgment enable is
controlled with an interrupt mask flag corresponding to each interrupt source.
IE is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all
other cases.
(d) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out
value upon rotate instruction execution and functions as a bit accumulator during bit manipulation
instruction execution.
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52 User’s Manual U15552EJ2V2UD
(3) Stack pointer (SP)
This is a 16-bit register used to hold the start address of the memory stack area. Only the internal high-
speed RAM area can be set as the stack area.
Figure 3-13. Stack Pointer Configuration
015
SP14SP15SP SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore)
from the stack memory.
Each stack operation saves/restores data as shown in Figures 3-14 and 3-15.
Caution Because RESET input makes the SP contents undefined, be sure to initialize the SP before
instruction execution.
Figure 3-14. Data to Be Saved to Stack Memory
Interrupt
PSW
PC15 to PC8
PC15 to PC8
PC7 to PC0
Lower
register pairs
SP SP _ 2
SP _ 2
CALL, CALLT
instructions
PUSH rp
instruction
SP _ 1
SP
SP SP _ 2
SP _ 2
SP _ 1
SP
PC7 to PC0
SP _ 3
SP _ 2
SP _ 1
SP
SP SP _ 3
Higher
register pairs
Figure 3-15. Data to Be Restored from Stack Memory
RETI instruction
PSW
PC15 to PC8
PC15 to PC8
PC7 to PC0
Lower
register pairs
RET instructionPOP rp
instruction
SP PC7 to PC0
Higher
register pairs
SP + 1
SP SP + 2
SP
SP + 1
SP SP + 2
SP
SP + 1
SP + 2
SP SP + 3
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15552EJ2V2UD 53
3.2.2 General-purpose registers
The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, or two 8-bit registers in pairs can be used as a 16-bit register (AX,
BC, DE, and HL).
General-purpose registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, or HL)
or absolute names (R0 to R7 and RP0 to RP3).
Figure 3-16. General-Purpose Register Configuration
(a) Absolute names
R0
15 0 7 0
16-bit processing 8-bit processing
RP3
RP2
RP1
RP0
R1
R2
R3
R4
R5
R6
R7
(b) Function names
X
15 0 7 0
16-bit processing 8-bit processing
HL
DE
BC
AX
A
C
B
E
D
L
H
CHAPTER 3 CPU ARCHITECTURE
54 User’s Manual U15552EJ2V2UD
3.2.3 Special-function registers (SFRs)
Unlike a general-purpose register, each special-function register has a special function.
The special-function registers are allocated in the 256-byte area of FF00H to FFFFH.
Special-function registers can be manipulated, like general-purpose registers, by operation, transfer, and bit
manipulation instructions. The manipulatable bit units (1, 8, and 16) differ depending on the special-function register
type.
The manipulatable bits can be specified as follows.
• 1-bit manipulation
Describe a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This
manipulation can also be specified with an address.
• 8-bit manipulation
Describe a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This
manipulation can also be specified with an address.
• 16-bit manipulation
Describe a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When addressing
an address, describe an even address.
Table 3-3 lists the special-function registers. The meanings of the symbols in this table are as follows.
• Symbol
Indicates the address of the on-chip special-function register. The symbols shown in this column are reserved
words in the assembler, and have been defined in the header file “sfrbit.h” in the C compiler. Therefore, these
symbols can be used as instruction operands if an assembler or integrated debugger is used.
• R/W
Indicates whether the special-function register in question can be read or written.
R/W: Read/write
R: Read only
W: Write only
• Bit unit for manipulation
Indicates the bit units (1, 8, 16) in which the special-function register in question can be manipulated.
• After reset
Indicates the status of the special-function register when the RESET signal is input.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15552EJ2V2UD 55
Table 3-3. Special-Function Registers
Bit Unit for Manipulation Address Special-Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
After
Reset
FF00H Port 0 P0 √ √ −
FF01H Port 1 P1 √ √ −
FF03H port 4 P4 √ √ −
FF05H Port 6 P6
R/W
√ √ −
00H
FF08H Port 8 P8 √ √ −
FF15H A/D conversion result register ADCR0
R
− √ −
Undefined
FF20H Port mode register 0 PM0 √ √ −
FF21H Port mode register 1 PM1 √ √ −
FF24H Port mode register 4 PM4 √ √ −
FF26H Port mode register 6 PM6 √ √ −
FFH
FF42H Watchdog timer clock selection resister TCL2 − √ −
FF4AH Watch timer mode control register WTM √ √ −
FF58H Port function register 8 PF8
R/W
√ √ −
00H
FF63H 8-bit compare register 30 CR30 W − √ − Undefined
FF64H 8-bit timer counter 30 TM30 R − √ −
FF65H 8-bit timer mode control register 30 TMC30 R/W √ √ −
00H
FF66H 8-bit compare register 40 CR40 − √ −
FF67H 8-bit H width compare register 40 CRH40
W
− √ −
Undefined
FF68H 8-bit timer counter 40 TM40 R − √ −
FF69H 8-bit timer mode control register 40 TMC40 R/W √ √ −
FF6AH Carrier generator output control register 40 TCA40 W − √ −
FF80H A/D converter mode register 0 ADM0 √ √ −
FF84H A/D input selection register 0 ADS0 √ √ −
00H
FFB0H LCD display mode register 0 LCDM0 √ √ − 00HNote
FFB2H LCD clock control register 0 LCDC0 √ √ −
FFB3H LCD voltage boost control register 0 LCDVA0 √ √ −
FFE0H Interrupt request flag register 0 IF0 √ √ −
00H
FFE4H Interrupt mask flag register 0 MK0 √ √ − FFH
FFECH External interrupt mode register 0 INTM0 − √ −
FFF0H Suboscillation mode register SCKM √ √ −
FFF2H Subclock control register CSS √ √ −
FFF5H Key return mode register 00 KRM00 √ √ −
FFF7H Pull-up resistor option register 0 PU0 √ √ −
FFF9H Watchdog timer mode register WDTM √ √ −
00H
FFFAH Oscillation stabilization time selection register OSTS √ √ − 04H
FFFBH Processor clock control register PCC
R/W
√ √ − 02H
Note Bit 2 (LCDM02) must be set to 1 after reset.
CHAPTER 3 CPU ARCHITECTURE
56 User’s Manual U15552EJ2V2UD
3.3 Instruction Address Addressing
An instruction address is determined by the program counter (PC) contents. The PC contents are normally
incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each
time another instruction is executed. When a branch instruction is executed, the branch destination information is set
to the PC and branched by the following addressing (for details of each instruction, refer to 78K/0S Series
Instructions User’s Manual (U11047E)).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched. The
displacement value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes a sign bit.
This means that information is relatively branched to a location between –128 and +127, from the start address
of the next instruction when relative addressing is used.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15 0
PC
15 0
S
15 0
PC
+
876
α
jdisp8
When S = 0, α indicates all bits 0.
... PC is the start address of
the next instruction of
a BR instruction.
When S = 1, α indicates all bits 1.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15552EJ2V2UD 57
3.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed.
The CALL !addr16 and BR !addr16 instructions can be branched to any location in the memory space.
[Illustration]
In case of CALL !addr16 and BR !addr16 instructions
15 0
PC
87
70
CALL or BR
Low Addr.
High Addr.
CHAPTER 3 CPU ARCHITECTURE
58 User’s Manual U15552EJ2V2UD
3.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by the lower 5-bit
immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and
branched.
This function is carried out when the CALLT [addr5] instruction is executed. The instruction enables a branch
to any location in the memory space by referring to the addresses stored in the memory table at 40H to 7FH.
[Illustration]
15 1
15 0
PC
70
Low Addr.
High Addr.
Memory (table)
Effective address + 1
Effective address 01
00000000
87
87
65 0
0
001
765 10
ta4–0
Instruction code
3.3.4 Register addressing
[Function]
The register pair (AX) contents to be specified with an instruction word are transferred to the program counter
(PC) and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
70
rp
07
AX
15 0
PC
87
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15552EJ2V2UD 59
3.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) to undergo manipulation
during instruction execution.
3.4.1 Direct addressing
[Function]
The memory indicated by immediate data in an instruction word is directly addressed.
[Operand format]
Identifier Description
addr16 Label or 16-bit immediate data
[Description example]
MOV A, !FE00H; When setting !addr16 to FE00H
Instruction code 00101001OP code
00000000
11111110
00H
FEH
[Illustration]
70
OP code
addr16 (Lower)
addr16 (Higher)
Memory
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60 User’s Manual U15552EJ2V2UD
3.4.2 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied. Internal high-speed
RAM and special-function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH,
respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the whole SFR area.
Ports that are frequently accessed in a program and the compare register of the timer counter are mapped in
this area, and these SFRs can be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,
bit 8 is set to 1. See [Illustration] below.
[Operand format]
Identifier Description
saddr Label or FE20H to FF1FH immediate data
saddrp Label or FE20H to FF1FH immediate data (even address only)
[Description example]
MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H
Instruction code 1 1110101
10010000
01010000
OP code
90H (saddr-offset)
50H (Immediate data)
[Illustration]
15 0
Short direct memory
Effective
address 1111111
8
07
OP code
saddr-offset
α
When 8-bit immediate data is 20H to FFH, α = 0.
When 8-bit immediate data is 00H to 1FH, α = 1.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15552EJ2V2UD 61
3.4.3 Special-function register (SFR) addressing
[Function]
The memory-mapped special-function registers (SFRs) are addressed with 8-bit immediate data in an
instruction word.
This addressing is applied to the 256-byte space FF00H to FFFFH. However, the SFRs mapped at FF00H to
FF1FH can also be accessed with short direct addressing.
[Operand format]
Identifier Description
sfr Special-function register name
[Description example]
MOV PM0, A; When selecting PM0 for sfr
Instruction code 11100111
00100000
[Illustration]
15 0
SFR
Effective
address 1111111
87
07
OP code
sfr-offset
1
CHAPTER 3 CPU ARCHITECTURE
62 User’s Manual U15552EJ2V2UD
3.4.4 Register addressing
[Function]
In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose
register to be accessed is specified by a register specification code or functional name in the instruction code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
[Operand format]
Identifier Description
r X, A, C, B, E, D, L, H
rp AX, BC, DE, HL
r and rp can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,
B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; When selecting the C register for r
Instruction code 0 0001010
00100101
Register specification code
INCW DE; When selecting the DE register pair for rp
Instruction code 10001000
Register specification code
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15552EJ2V2UD 63
3.4.5 Register indirect addressing
[Function]
In the register indirect addressing mode, memory is manipulated according to the contents of a register pair
specified as an operand. The register pair to be accessed is specified by the register pair specification code in
an instruction code. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier Description
− [DE], [HL]
[Description example]
MOV A, [DE]; When selecting register pair [DE]
Instruction code 00101011
[Illustration]
15 08
D
7
E
07
7 0
A
DE
Addressed memory
contents are
transferred.
Memory address
specified with
register pair DE.
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64 User’s Manual U15552EJ2V2UD
3.4.6 Based addressing
[Function]
8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is
used to address the memory. Addition is performed by expanding the offset data as a positive number to 16
bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier Description
− [HL+byte]
[Description example]
MOV A, [HL+10H]; When setting byte to 10H
Instruction code 00101101
00010000
3.4.7 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call, and return
instructions are executed or the register is saved/restored upon generation of an interrupt request.
Only the internal high-speed RAM area can be addressed using stack addressing.
[Description example]
In the case of PUSH DE
Instruction code 10101010
User’s Manual U15552EJ2V2UD 65
CHAPTER 4 PORT FUNCTIONS
4.1 Port Functions
The
µ
PD789467 Subseries provides the ports shown in Figure 4-1, enabling various methods of control.
Numerous other functions are provided that can be used in addition to the digital I/O port functions. For more
information on these additional functions, see CHAPTER 2 PIN FUNCTIONS.
Figure 4-1. Port Types
P40 P00
P03
Port 0
Port 1
P10
Port 4
P43
P11
Port 6 P60
P61
P80
Port 8
P85
Table 4-1. Port Functions
Port Name Pin Name Function
Port 0 P00 to P03 This is an I/O port for which input and output can be specified in 1-bit units.
When used as an input port, the use of on-chip pull-up resistors can be specified using
pull-up resistor option register 0 (PU0).
Port 1 P10, P11 This is an I/O port for which input and output can be specified in 1-bit units.
When used as an input port, the use of on-chip pull-up resistors can be specified using
pull-up resistor option register 0 (PU0).
Port 4 P40 to P43 This is an I/O port for which input and output can be specified in 1-bit units.
When used as an input port, the use of on-chip pull-up resistors can be specified using
pull-up resistor option register 0 (PU0), or key return mode register 00 (KRM00).
Port 6 P60, P61 This is an I/O port for which input and output can be specified in 1-bit units.
Port 8 P80 to P85 This is an input port.
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66 User’s Manual U15552EJ2V2UD
4.2 Port Configuration
The ports include the following hardware.
Table 4-2. Configuration of Port
Item Configuration
Control registers Port mode registers (PMm: m = 0, 1, 4, 6)
Pull-up resistor option register 0 (PU0)
Port function register 8 (PF8)
Ports Total: 18 (CMOS I/O: 12, CMOS input: 6 (including pins shared with LCD)
Pull-up resistors Total: 10 (software control: 10)
4.2.1 Port 0
This is a 4-bit I/O port with an output latch. Port 0 can be set to the input or output mode in 1-bit units using port
mode register 0 (PM0). When the P00 to P03 pins are used as input port pins, on-chip pull-up resistors can be
connected in 4-bit units using pull-up resistor option register 0 (PU0).
Port 0 is set in the input mode when the RESET signal is input.
Figure 4-2 shows a block diagram of port 0.
Figure 4-2. Block Diagram of P00 to P03
WR
PU0
RD
WR
PORT
WR
PM
PU00
PM00 to PM03
V
DD
P-ch
P00 to P03
Internal bus
Selector
Output latch
(P00 to P03)
PU0: Pull-up resistor option register 0
PM: Port mode register
RD: Port 0 read signal
WR: Port 0 write signal
CHAPTER 4 PORT FUNCTIONS
User’s Manual U15552EJ2V2UD 67
4.2.2 Port 1
This is a 2-bit I/O port with an output latch. Port 1 can be set to the input or output mode in 1-bit units using port
mode register 1 (PM1). When using the P10 and P11 pins as input port pins, on-chip pull-up resistors can be
connected in 2-bit units using pull-up resistor option register 0 (PU0).
This port is set in the input mode when the RESET signal is input.
Figure 4-3 shows a block diagram of port 1.
Figure 4-3. Block Diagram of P10 and P11
WR
PU0
RD
WR
PORT
WR
PM
PU01
PM10, PM11
V
DD
P-ch
P10, P11
Internal bus
Selector
Output latch
(P10, P11)
PU0: Pull-up resistor option register 0
PM: Port mode register
RD: Port 1 read signal
WR: Port 1 write signal
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68 User’s Manual U15552EJ2V2UD
4.2.3 Port 4
This is a 4-bit I/O port with an output latch. Port 4 can be set to the input or output mode in 1-bit units using port
mode register 4 (PM4). When using the P40 to P43 pins as input port pins, on-chip pull-up resistors can be connected
in 4-bit units using pull-up resistor option register 0 (PU0).
This port is also used as a key return input.
This port is set in the input mode when the RESET signal is input.
Figure 4-4 shows block diagram of port 4.
Figure 4-4. Block Diagram of P40 to P43
WRKRM00
VDD
P40/KR00 to
P43/KR03
WRPU0
RD
WRPORT
WRPM
PU04
PM40 to PM43
KRM000
P-ch
Internal bus
Selector
Output latch
(P40 to P43)
Alternate function
KRM00: Key return mode register 00
PU0: Pull-up resistor option register 0
PM: Port mode register
RD: Port 4 read signal
WR: Port 4 write signal
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User’s Manual U15552EJ2V2UD 69
4.2.4 Port 6
This is a 2-bit I/O port with an output latch. Port 6 can be set to the input or output mode in 1-bit units using port
mode register 6 (PM6).
This port is also used as a timer output, external interrupt input, and analog input.
This port is set in the input mode when the RESET signal is input.
Figures 4-5 and 4-6 show block diagrams of port 6.
Figure 4-5. Block Diagram of P60
P60/TO40
WR
PORT
WR
PM
PM60
RD
Internal bus
Selector
Output latch
(P60)
Alternate
function
PM: Port mode register
RD: Port 6 read signal
WR: Port 6 write signal
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70 User’s Manual U15552EJ2V2UD
Figure 4-6. Block Diagram of P61
RD
WR
PORT
WR
PM
Output latch
(P61)
PM61
P61/INTP0/ANI0
Selector
V
REF
A/D converter +
–
ADS00
External interrupt
WR
ADS0
Internal bus
ADS0: A/D input selection register 0
PM: Port mode register
RD: Port 6 read signal
WR: Port 6 write signal
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User’s Manual U15552EJ2V2UD 71
4.2.5 Port 8
This is a 6-bit input port.
This port is also used as a segment output, and can be switched to the port function or segment output function in
1-bit units using port function register 8 (PF8).
This port is set in the input mode when the RESET signal is input.
Figure 4-7 shows a block diagram of port 8.
Figure 4-7. Block Diagram of P80 to P85
Internal bus
RD
P80/S22 to P85/S17
Alternate
function
VDD
VSS
PF80 to PF85
WRPF
PF: Port function register
RD: Port 8 read signal
WR: Port 8 write signal
CHAPTER 4 PORT FUNCTIONS
72 User’s Manual U15552EJ2V2UD
4.3 Registers Controlling Port Function
The ports are controlled by the following three types of registers.
• Port mode registers (PM0, PM1, PM4, PM6)
• Pull-up resistor option register 0 (PU0)
• Port function register 8 (PF8)
(1) Port mode registers (PM0, PM1, PM4, PM6)
These registers are used to set port input/output in 1-bit units.
The port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the registers to FFH.
When port pins are used as alternate-function pins, set the port mode register and output latch according to
Table 4-3.
Caution As P61 has an alternate function as external interrupt input, when the port function output
mode is specified and the output level is changed, the interrupt request flag is set. When
the output mode is used, therefore, the interrupt mask flag (PMK0) should be preset to 1.
Figure 4-8. Format of Port Mode Register
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PM0 1 1 1 1 PM03 PM02 PM01 PM00 FF20H FFH R/W
PM1 1 1 1 1 1 1 PM11 PM10 FF21H FFH R/W
PM4 1 1 1 1 PM43 PM42 PM41 PM40 FF24H FFH R/W
PM6 1 1 1 1 1 1 PM61 PM60 FF26H FFH R/W
PMmn Pmn pin input/output mode selection
(m = 0, 1, 4, 6 n = 0 to 3)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
CHAPTER 4 PORT FUNCTIONS
User’s Manual U15552EJ2V2UD 73
Table 4-3. Port Mode Registers and Output Latch Settings When Using Alternate Functions
Alternate Function PM×× PM×× ADS00 Pin Name
Name I/O
P40 to P43 KR00 to KR03 Input 1 × ×
P60 TO40 Output 0 0
×
INTP0 Input 1
× 0 P61
ANI0 Input 1
× 1
Remark ×: Don’t care
PM××: Port mode register
P××: Port output latch
ADS00: Bit 0 of A/D input selection register 0 (ADS0)
(2) Pull-up resistor option register 0 (PU0)
Pull-up resistor option register 0 (PU0) sets whether the on-chip pull-up resistor at ports 0, 1, and 4 is used or
not in port units.
For the port specified to use an on-chip pull-up resistor by PU0, the pull-up resistor can be internally used
only for the bits set in the input mode. No on-chip pull-up resistors can be used for the bits set in the output
mode regardless of the setting of PU0. This also applies to cases when the pins are used for alternate
functions.
PU0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PU0 to 00H.
Figure 4-9. Format of Pull-up Resistor Option Register 0
Symbol 7 6 5 <4> 3 2 <1> <0> Address After reset R/W
PU0 0 0 0 PU04 0 0 PU01 PU00 FFF7H 00H R/W
PU0m Pm on-chip pull-up resistor selection
(m = 0, 1, 4)
0 On-chip pull-up resistor not used
1 On-chip pull-up resistor used
Caution Bits 2, 3, and 5 to 7 must be set to 0.
CHAPTER 4 PORT FUNCTIONS
74 User’s Manual U15552EJ2V2UD
(3) Port function register 8 (PF8)
Port function register 8 (PF8) sets the port function of port 8 in 1-bit units.
The pins of port 8 are selected as either LCD segment signal outputs or general-purpose port pins according
to the setting of PF8.
PF8 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PF8 to 00H.
Figure 4-10. Format of Port Function Register 8
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PF8 0 0 PF85 PF84 PF83 PF82 PF81 PF80 FF58H 00H R/W
PF8n P8n port function (n = 0 to 5)
0 Operates as a general-purpose port
1 Operates as an LCD segment signal output
Cautions 1. Bits 6 and 7 must be set to 0.
2. When any one of pins P80 to P85 is used as a general-purpose pin, observe the
following two restrictions (because an ESD protection circuit for the LCD pins is
connected to the VLC0 side).
• Enable operation of the booster (VAON0 = 1).
• In VLC0 = 3.0 V mode (GAIN = 1)... Use the microcontroller in the range of VDD = 1.8 to
3.0 V.
In VLC0 = 4.5 V mode (GAIN = 0)... Use the microcontroller in the range of VDD = 1.8 to
4.5 V.
When all of pins P80 to P85 are used as LCD segment pins, the microcontroller can be
used in the range of VDD = 1.8 to 5.5 V.
P8n/Sm
Segment buffer
If a voltage higher
than V
LC0
is input
to the P8n/Sm pin,
current flows this way.
V
DD
V
SS
PF8n
V
SS
V
LC0
RD
Sm output signal
P8n input signal
Remark Sm: LCD segment output (m = 22 to 17)
P8n: Bit n of port 8 (n = 0 to 5)
PF8n: Bit n of port function register 8 (n = 0 to 5)
RD: Read signal of port 8n
CHAPTER 4 PORT FUNCTIONS
User’s Manual U15552EJ2V2UD 75
4.4 Port Function Operation
The operation of a port differs depending on whether the port is set in the input or output mode, as described
below.
4.4.1 Writing to I/O port
(1) In output mode
A value can be written to the output latch of a port by using a transfer instruction. The contents of the output
latch can be output from the pins of the port.
Once data is written to the output latch, it is retained until new data is written to the output latch.
(2) In input mode
A value can be written to the output latch by using a transfer instruction. However, the status of the port pin
is not changed because the output buffer is OFF.
Once data once written to the output latch, it is retained until new data is written to the output latch.
Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However,
this instruction accesses the port in 8-bit units. When this instruction is executed to
manipulate a bit of an input/output port, therefore, the contents of the output latch of the
pin that is set to the input mode and not subject to manipulation become undefined.
4.4.2 Reading from I/O port
(1) In output mode
The status of an output latch can be read by using a transfer instruction. The contents of the output latch are
not changed.
(2) In input mode
The status of a pin can be read by using a transfer instruction. The contents of the output latch are not
changed.
4.4.3 Arithmetic operation of I/O port
(1) In output mode
An arithmetic operation can be performed on the contents of the output latch. The result of the operation is
written to the output latch. The contents of the output latch are output from the port pins.
Once data is written to the output latch, it is retained until new data is written to the output latch.
(2) In input mode
The contents of the output latch become undefined. However, the status of the pin is not changed because
the output buffer is off.
Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However,
this instruction accesses the port in 8-bit units. When this instruction is executed to
manipulate a bit of an input/output port, therefore, the contents of the output latch of the
pin that is set to the input mode and not subject to manipulation become undefined.
76 User’s Manual U15552EJ2V2UD
CHAPTER 5 CLOCK GENERATOR
5.1 Clock Generator Functions
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following two types of system clock oscillators are used.
• Main system clock (ceramic/crystal) oscillator
This circuit oscillates at 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting
the processor clock control register (PCC).
• Subsystem clock oscillator
This circuit oscillates at 32.768 kHz. Oscillation can be stopped by the suboscillation mode register (SCKM).
5.2 Clock Generator Configuration
The clock generator includes the following hardware.
Table 5-1. Configuration of Clock Generator
Item Configuration
Control registers Processor clock control register (PCC)
Suboscillation mode register (SCKM)
Subclock control register (CSS)
Oscillators Main system clock oscillator
Subsystem clock oscillator
CHAPTER 5 CLOCK GENERATOR
User’s Manual U15552EJ2V2UD 77
Figure 5-1. Block Diagram of Clock Generator
Subsystem
clock
oscillator
f
XT
X1
X2
XT1
XT2
Main system
clock
oscillator
f
X
f
X
2
2
f
XT
2
1/2
Prescaler
Watch timer
LCD controller/driver
Clock to peripheral
hardware
CPU clock
(f
CPU
)
Standby
controller
Wait
controller
STOP MCC PCC1 CLS CSS0
Internal bus
Suboscillation mode register
(SCKM)
FRC SCC
Internal bus
Subclock control
register (CSS)
Processor clock
control register
(PCC)
Selector
CHAPTER 5 CLOCK GENERATOR
78 User’s Manual U15552EJ2V2UD
5.3 Registers Controlling Clock Generator
The clock generator is controlled by the following three registers.
• Processor clock control register (PCC)
• Suboscillation mode register (SCKM)
• Subclock control register (CSS)
(1) Processor clock control register (PCC)
PCC sets CPU clock selection and the division ratio.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PCC to 02H.
Figure 5-2. Format of Processor Clock Control Register
Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W
PCC MCC 0 0 0 0 0 PCC1 0 FFFBH 02H R/W
MCC Control of main system clock oscillator operation
0 Operation enabled
1 Operation disabled
Maximum instruction execution time: 2/fCPU
CSS0 PCC1 CPU clock (fCPU) selectionNote
At fX = 5.0 MHz or fXT = 32.768 kHz Operation
0 0 fX 0.4
µ
s
0 1 fX/22 1.6
µ
s
1 × fXT/2 122
µ
s
Note The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control
register (PCC) and the CSS0 flag in the subclock control register (CSS) (refer to 5.3 (3) Subclock
control register (CSS)).
Cautions 1. Bits 0 and 2 to 6 must be set to 0.
2. The MCC can be set only when the subsystem clock has been selected as the CPU
clock.
Setting MCC to 1 while the main system clock is operating is invalid.
Remarks 1. fX: Main system clock oscillation frequency
2. f
XT: Subsystem clock oscillation frequency
3. ×: Don’t care
CHAPTER 5 CLOCK GENERATOR
User’s Manual U15552EJ2V2UD 79
(2) Suboscillation mode register (SCKM)
SCKM selects use of a feedback resistor for the subsystem clock, and controls the oscillation of the clock.
SCKM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SCKM to 00H.
Figure 5-3. Format of Suboscillation Mode Register
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
SCKM 0 0 0 0 0 0 FRC SCC FFF0H 00H R/W
FRC Feedback resistor selectionNote
0 On-chip feedback resistor used
1 On-chip feedback resistor not used
Control of subsystem clock oscillator operation
0 Operation enabled
1 Operation disabled
Note The feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the
mid point of the supply voltage. When the subclock is not used, the current consumption in STOP
mode can be further reduced by setting FRC = 1.
Caution Bits 2 to 7 must be set to 0.
(3) Subclock control register (CSS)
CSS specifies whether the main system or subsystem clock oscillator is selected. It also specifies the CPU
clock operation status.
CSS is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSS to 00H.
Figure 5-4. Format of Subclock Control Register
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
CSS 0 0 CLS CSS0 0 0 0 0 FFF2H 00H R/WNote
CLS CPU clock operation status
0 Operation based on the output of the divided main system clock
1 Operation based on the subsystem clock
CSS0 Selection of the main system or subsystem clock oscillator
0 Divided output from the main system clock oscillator
1 Output from the subsystem clock oscillator
Note Bit 5 is read-only.
Caution Bits 0 to 3, 6, and 7 must be set to 0.
CHAPTER 5 CLOCK GENERATOR
80 User’s Manual U15552EJ2V2UD
5.4 System Clock Oscillators
5.4.1 Main system clock oscillator
The main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected
across the X1 and X2 pins.
An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the
inverted signal to the X2 pin.
Figure 5-5 shows the external circuit of the main system clock oscillator.
Figure 5-5. External Circuit of Main System Clock Oscillator
(a) Crystal or ceramic oscillation (b) External clock
Crystal
or
ceramic resonator
V
SS
X2
X1
External
clock X1
X2
Caution When using the main system or subsystem clock oscillator, wire as follows in the area enclosed
by the broken lines in Figures 5-5 and 5-6 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
CHAPTER 5 CLOCK GENERATOR
User’s Manual U15552EJ2V2UD 81
5.4.2 Subsystem clock oscillator
The subsystem clock oscillator is oscillated by the crystal resonator (32.768 kHz TYP.) connected across the XT1
and XT2 pins.
An external clock can also be input to the circuit. In this case, input the clock signal to the XT1 pin, and input the
inverted signal to the XT2 pin.
Figure 5-6 shows the external circuit of the subsystem clock oscillator.
Figure 5-6. External Circuit of Subsystem Clock Oscillator
(a) Crystal oscillation (b) External clock
XT2
V
SS
XT1
32.768
kHz
Crystal resonator
External
clock XT1
XT2
Caution When using the main system or subsystem clock oscillator, wire as follows in the area enclosed
by the broken lines in Figures 5-5 and 5-6 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
When using the subsystem clock, particular care is required because the subsystem clock
oscillator is designed as a low-amplitude circuit for reducing current consumption.
CHAPTER 5 CLOCK GENERATOR
82 User’s Manual U15552EJ2V2UD
5.4.3 Example of incorrect resonator connection
Figure 5-7 shows examples of incorrect resonator connection.
Figure 5-7. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring (b) Crossed signal line
V
SS
X1 X2
V
SS
X1 X2
PORTn
(n = 0, 1, 4, 6, 8)
(c) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
V
SS
X1 X2
High current
V
SS
X1
AB C
P
mn
V
DD
High current
X2
Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor
to XT2 in series.
CHAPTER 5 CLOCK GENERATOR
User’s Manual U15552EJ2V2UD 83
Figure 5-7. Examples of Incorrect Resonator Connection (2/2)
(e) Signal is fetched (f) Parallel and near signal lines of main system clock
and subsystem clock
V
SS
X1 X2
V
SS
X2
XT2 is wired parallel to X1.
X1 XT2 XT1
Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor
to XT2 in series.
Caution If the X1 wire is in parallel with the XT2 wire, crosstalk noise may occur between X1 and XT2,
resulting in a malfunction.
To avoid this, do not lay the X1 and XT2 wires in parallel.
5.4.4 Divider
The divider divides the output of the main system clock oscillator (fX) to generate various clocks.
5.4.5 When no subsystem clock is used
If a subsystem clock is not necessary, for example, for low-power consumption operation or clock operation,
handle the XT1 and XT2 pins as follows.
XT1: Connect to VSS
XT2: Leave open
In this case, however, a small current leaks via the on-chip feedback resistor in the subsystem clock oscillator
when the main system clock is stopped. To avoid this, set bit 1 (FRC) of the suboscillation mode register (SCKM) so
that the on-chip feedback resistor will not be used. Also in this case, handle the XT1 and XT2 pins as stated above.
CHAPTER 5 CLOCK GENERATOR
84 User’s Manual U15552EJ2V2UD
5.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as the
standby mode.
• Main system clock fX
• Subsystem clock fXT
• CPU clock fCPU
• Clock to peripheral hardware
The operation and function of the clock generator is determined by the processor clock control register (PCC),
suboscillation mode register (SCKM), and subclock control register (CSS), as follows.
(a) The low-speed mode (1.6
µ
s at 5.0 MHz operation) of the main system clock is selected when the
RESET signal is generated (PCC = 02H). While a low level is being input to the RESET pin, oscillation
of the main system clock is stopped.
(b) Three types of minimum instruction execution time (0.4
µ
s and 1.6
µ
s: main system clock (at 5.0 MHz
operation), 122
µ
s: subsystem clock (at 32.768 kHz operation)) can be selected by the PCC, SCKM,
and CSS settings.
(c) Two standby modes, STOP and HALT, can be used with the main system clock selected. In a system
where no subsystem clock is used, setting bit 1 (FRC) of SCKM so that the on-chip feedback resistor
cannot be used reduces current consumption in STOP mode. In a system where a subsystem clock is
used, setting SCKM bit 0 to 1 can cause the subsystem clock to stop oscillation.
(d) CSS bit 4 (CSS0) can be used to select the subsystem clock so that low current consumption operation
is used (122
µ
s at 32.768 kHz operation).
(e) With the subsystem clock selected, it is possible to cause the main system clock to stop oscillating
using bit 7 (MCC) of PCC. The HALT mode can be used, but the STOP mode cannot.
(f) The clock pulse for the peripheral hardware is generated by dividing the frequency of the main system
clock, but the subsystem clock pulse is only supplied to the watch timer and LCD controller/driver. The
watch timer and LCD controller/driver can therefore keep running even during standby. The other
hardware stops when the main system clock stops because it runs based on the main system clock
(except for external input clock operations).
CHAPTER 5 CLOCK GENERATOR
User’s Manual U15552EJ2V2UD 85
5.6 Changing Setting of System Clock and CPU Clock
5.6.1 Time required for switching between system clock and CPU clock
The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4
(CSS0) of the subclock control register (CSS).
The maximum time indicated in Table 5-2 is required until the CPU clock actually switches (i.e. switching does not
occur immediately after the PCC register is rewritten). Until this time has elapsed, therefore, it is impossible to
ascertain whether the clock before or after the switch is operating
Table 5-2. Maximum Time Required for Switching CPU Clock
Set Value Before Switching Set Value After Switching
CSS0 PCC1 CSS0 PCC1 CSS0 PCC1 CSS0 PCC1
0 0 0 1 1 ×
0 0 4 clocks 2fX/fXT clocks
(306 clocks)
1 2 clocks fX/2fXT clocks
(76 clocks)
1 × 2 clocks 2 clocks
Remarks 1. Two clocks is the minimum instruction execution time of the CPU clock before switching.
2. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
3. ×: Don’t care
CHAPTER 5 CLOCK GENERATOR
86 User’s Manual U15552EJ2V2UD
5.6.2 Switching between system clock and CPU clock
The following figure illustrates how the CPU clock and system clock switch.
Figure 5-8. Example of Switching Between System Clock and CPU Clock
System clock
CPU clock
Input request signal
RESET
VDD
fXfXfXT fX
Low-speed
operation
High-speed
operation
Subsystem clock
operation
High-speed
operation
Oscillation stabilization time wait
(6.55 ms at 5.0 MHz operation)
Internal reset operation
PCC
rewrite
Several clocks
(For maximum
values, refer
to Table 5-2.)
CSS
rewrite
CSS
rewrite
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released
when the RESET pin is later made high, and the main system clock starts oscillating. At this time, the
oscillation stabilization time (215/fX) is automatically secured.
After that, the CPU starts instruction execution at the slow speed of the main system clock (1.6
µ
s at
5.0 MHz operation).
<2> After the time required for the VDD voltage to rise to the level at which the CPU can operate at high speed
has elapsed, bit 1 (PCC1) of the processor clock control register (PCC) is rewritten.
<3> After a few clocks have elapsed, the CPU clock is switched to high speed (0.4
µ
s at 5.0 MHz operation), and
the CPU starts high-speed operation.
<4> A drop of the VDD voltage is detected by an interrupt request signal. Bit 4 (CSS0) of the subclock control
register (CSS) is rewritten so that the clock is switched to the subsystem clock (at this moment, the
subsystem clock must be in the oscillation stabilized status).
<5> After a few clocks have elapsed, the CPU clock is switched to the subsystem clock operation (122
µ
s at
32.768 kHz operation). (At this time, bit 7 (MCC) of PCC can be set to 1 to stop the main system clock.)
<6> When recovery of the VDD voltage is detected by an interrupt request signal, CSS0 is written so that the CPU
clock is switched to the main system clock. (If the main system clock is stopped, set bit 7 (MCC) of PCC to 0
so that the main system clock starts oscillating. After the time required for the oscillation to stabilize has
elapsed, rewrite CSS0.)
<7> After a few clocks, the CPU clock is switched to high speed (0.4
µ
s at 5.0 MHz operation), and the CPU
returns to high-speed operation.
Caution When the main system clock is stopped and the device is operating on the subsystem
clock, wait until the oscillation stabilization time has been secured by the program before
switching back to the main system clock.
User’s Manual U15552EJ2V2UD 87
CHAPTER 6 8-BIT TIMERS 30 AND 40
6.1 Functions of 8-Bit Timers 30 and 40
The 8-bit timer in the
µ
PD789467 Subseries has 2 channels (timer 30 and timer 40). The operation modes listed
in the following table can be set via mode register settings.
Table 6-1. Operation Modes
Channel
Mode
Timer 30 Timer 40
8-bit timer counter mode
(Discrete mode)
Available Available
16-bit timer counter mode
(Cascade connection mode)
Available
Carrier generator mode Available
PWM output mode Not available Available
(1) 8-bit timer counter mode (discrete mode)
The following functions can be used in this mode.
• Interval timer with 8-bit resolution
• Square-wave output with 8-bit resolution (timer 40 only)
(2) 16-bit timer counter mode (cascade connection mode)
Operation as a 16-bit timer is enabled during cascade connection mode.
The following functions can be used in this mode.
• Interval timer with 16-bit resolution
• Square-wave output with 16-bit resolution
(3) Carrier generator mode
The carrier clock generated by timer 40 is output in cycles set by timer 30.
(4) PWM output mode (timer 40 only)
Pulses are output using any duty factor set by timer 40.
CHAPTER 6 8-BIT TIMERS 30 AND 40
88 User’s Manual U15552EJ2V2UD
6.2 Configuration of 8-Bit Timers 30 and 40
The 8-bit timers 30 and 40 include the following hardware.
Table 6-2. Configuration of 8-Bit Timers 30 and 40
Item Configuration
Timer counters 8 bits × 2 (TM30, TM40)
Registers Compare registers: 8 bits × 3 (CR30, CR40, CRH40)
Timer outputs 1 (TO40)
Control registers 8-bit timer mode control register 30 (TMC30)
8-bit timer mode control register 40 (TMC40)
Carrier generator output control register 40 (TCA40)
Port mode register 6 (PM6)
Port 6 (P6)
CHAPTER 6 8-BIT TIMERS 30 AND 40
User’s Manual U15552EJ2V2UD 89
Figure 6-1. Block Diagram of Timer 30
TCE30
TCL300
TMD300
TCL301
8-bit timer mode control register 30
(TMC30)
Selector
Decoder
Selector
Selector
8-bit compare register 30
(CR30)
8-bit timer counter 30
(TM30)
Selector
Internal reset signal
Timer 40 match signal
(in cascade connection mode)
Timer 30 match signal
(in cascade connection mode)
From Figure 6-2 (D)
Count operation start signal
(for cascade connection) INTTM30
f
X
/2
6
f
X
/2
8
Timer 40 interrupt request signal
(from Figure 6-2 (B))
Carrier clock
(from Figure 6-2 (C))
Clear
Cascade connection mode
Match
From Figure 6-2 (E)
To Figure 6-2 (F)
To Figure 6-2 (G)
Internal bus
OVF
Timer 30 match signal
(in carrier generator mode)
Bit 7 of TM40
(from Figure 6-2 (A))
(A) (G)
(B)
(C)
(D)
(E)
(F)
CHAPTER 6 8-BIT TIMERS 30 AND 40
90 User’s Manual U15552EJ2V2UD
Figure 6-2. Block Diagram of Timer 40
TCE40
TCL402 TCL401 TCL400
TMD401
TMD400
TOE40
8-bit timer mode control
register 40 (TMC40)
Decoder
8-bit timer counter 40
(TM40)
F/F
TM30 match signal
(in cascade connection mode)
Count operation start signal to timer 30
(in cascade connection mode)
TM40 timer counter match signal
(in cascade connection mode)
Clear
f
X
f
X
/2
2
8-bit compare
register 40 (CR40)
Selector
Output
controller
Note
RMC40
NRZB40
NRZ40
Carrier generator output
control register 40 (TCA40)
To Figure 6-1 (D)
count clock input
signal to TM30
Internal reset signal
INTTM40
Bit 7 of TM40
(in cascade connection mode)
To Figure 6-1 (A)
To Figure 6-1 (F)
To Figure 6-1 (E)
Match TO40/P60
(G)
(C)
(A)
(B)
(F)
(D)
(E)
To Figure 6-1 (C)
Carrier clock
Reset
Carrier generator mode
PWM mode
Cascade connection mode
Note Refer to Figure 6-3 for details.
8-bit H width compare
register 40 (CRH40)
Internal bus
Selector
OVF
Prescaler
f
X
/2 f
X
/2
2
f
X
/2
3
f
X
/2
4
Timer 40 interrupt request signal
To Figure 6-1 (B)
Timer counter match signal from
timer 30 (in carrier generator mode)
From Figure 6-1 (G)
CHAPTER 6 8-BIT TIMERS 30 AND 40
User’s Manual U15552EJ2V2UD 91
Figure 6-3. Block Diagram of Output Controller (Timer 40)
F/F
RMC40 NRZ40
TOE40
PM60
P60
output latch
Selector
TO40/P60
Carrier generator mode
Carrier clock
(1) 8-bit compare register 30 (CR30)
This 8-bit register is used to continually compare the value set to CR30 with the count value in 8-bit timer
counter 30 (TM30) and to generate an interrupt request (INTTM30) when a match occurs.
CR30 is set with an 8-bit memory manipulation instruction.
RESET input makes CR30 undefined.
Caution CR30 cannot be used in PWM output mode.
(2) 8-bit compare register 40 (CR40)
This 8-bit register is used to continually compare the value set to CR40 with the count value in 8-bit timer
counter 40 (TM40) and to generate an interrupt request (INTTM40) when a match occurs. When connected
to TM30 via a cascade connection and used as a 16-bit timer, the interrupt request (INTTM40) occurs only
when matches occur simultaneously between CR30 and TM30 and between CR40 and TM40 (INTTM30 does
not occur).
In carrier generator mode or PWM output mode, CR40 sets the timer output low-level width.
CR40 is set with an 8-bit memory manipulation instruction.
RESET input makes CR40 undefined.
(3) 8-bit H width compare register 40 (CRH40)
In carrier generator mode or PWM output mode, the high-level width of timer output is set by writing a value to
CRH40.
The set value of CRH40 is always compared with the TM40 count value, and when they match, an interrupt
request (INTTM40) is generated.
CRH40 is set with an 8-bit memory manipulation instruction.
RESET input makes CRH40 undefined.
CHAPTER 6 8-BIT TIMERS 30 AND 40
92 User’s Manual U15552EJ2V2UD
(4) 8-bit timer counters 30 and 40 (TM30 and TM40)
These are 8-bit registers that are used to count the count pulse.
TM30 and TM40 are read with an 8-bit memory manipulation instruction.
RESET input sets TM30 and TM40 to 00H.
TM30 and TM40 are cleared to 00H under the following conditions.
(a) Discrete mode
(i) TM30
• After reset
• When TCE30 (bit 7 of 8-bit timer mode control register 30 (TMC30)) is cleared to 0
• When a match occurs between TM30 and CR30
• When the TM30 count value overflows
(ii) TM40
• After reset
• When TCE40 (bit 7 of 8-bit timer mode control register 40 (TMC40)) is cleared to 0
• When a match occurs between TM40 and CR40
• When the TM40 count value overflows
(b) Cascade connection mode (TM30 and TM40 are simultaneously cleared to 00H)
• After reset
• When the TCE40 flag is cleared to 0
• When matches occur simultaneously between TM30 and CR30 and between TM40 and CR40
• When the TM30 and TM40 count values overflow simultaneously
(c) Carrier generator mode/PWM output mode (TM40 only)
• After reset
• When the TCE40 flag is cleared to 0
• When a match occurs between TM40 and CR40
• When a match occurs between TM40 and CRH40
• When the TM40 count value overflows
CHAPTER 6 8-BIT TIMERS 30 AND 40
User’s Manual U15552EJ2V2UD 93
6.3 Registers Controlling 8-Bit Timers 30 and 40
8-bit timer 30 and 40 are controlled by the following five registers.
• 8-bit timer mode control register 30 (TMC30)
• 8-bit timer mode control register 40 (TMC40)
• Carrier generator output control register 40 (TCA40)
• Port mode register 6 (PM6)
• Port 6 (P6)
CHAPTER 6 8-BIT TIMERS 30 AND 40
94 User’s Manual U15552EJ2V2UD
(1) 8-bit timer mode control register 30 (TMC30)
8-bit timer mode control register 30 (TMC30) is used to control the timer 30 count clock setting and the
operation mode setting.
TMC30 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TMC30 to 00H.
Figure 6-4. Format of 8-Bit Timer Mode Control Register 30
Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W
TMC30 TCE30 0 0 TCL301 TCL300 0 TMD300 0 FF65H 00H R/W
TCE30 Control of TM30 count operationNote 1
0 Clear TM30 count value and stop operation
1 Start count operation
TCL301 TCL300 Selection of timer 30 count clock
0 0
fX/26 (78.1 kHz)
0 1
fX/28 (19.5 kHz)
1 0 Timer 40 match signal
1 1 Carrier clock created for timer 40
TMD300 TMD401 TMD400 Selection of operation mode for timer 30 and timer 40Note 2
0 0 0 8-bit timer counter mode (discrete mode)
1 0 1 16-bit timer counter mode (cascade connection mode)
0 1 1 Carrier generator mode
0 1 0 Timer 40: PWM output mode
Timer 30: 8-bit timer counter mode
Other than above Setting prohibited
Notes 1. Since the count operation is controlled by TCE40 (bit 7 of TMC40) in cascade connection mode,
any setting for TCE30 is ignored.
2. The operation mode selection is set to both the TMC30 register and TMC40 register.
Cautions 1. In cascade connection mode, the timer 40 output signal is forcibly selected for the
count clock.
2. Be sure to clear bits 0, 2, 5, and 6 to 0.
Remarks 1. f
X: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
CHAPTER 6 8-BIT TIMERS 30 AND 40
User’s Manual U15552EJ2V2UD 95
(2) 8-bit timer mode control register 40 (TMC40)
8-bit timer mode control register 40 (TMC40) is used to control the timer 40 count clock setting and the
operation mode setting.
TMC40 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TMC40 to 00H.
Figure 6-5. Format of 8-Bit Timer Mode Control Register 40
Symbol <7> 6 5 4 3 2 1 <0> Address After reset R/W
TMC40 TCE40 0 TCL402 TCL401 TCL400 TMD401 TMD400 TOE40 FF69H 00H R/W
TCE40 Control of TM40 count operationNote 1
0 Clear TM40 count value and stop operation (the count value is also cleared for TM30 during cascade
connection mode)
1 Start count operation (the count operation is also started for TM30 during cascade connection mode)
TCL402 TCL401 TCL400 Selection of timer 40 count clock
0 0 0 fX (5 MHz)
0 0 1
fX/22 (1.25 MHz)
0 1 0 fX/2 (2.5 MHz)
0 1 1
fX/22 (1.25 MHz)
1 0 0
fX/23 (625 kHz)
1 0 1
fX/24 (313 kHz)
Other than above Setting prohibited
TMD300 TMD401 TMD400 Selection of operation mode for timer 30 and timer 40Note 2
0 0 0 8-bit timer counter mode (discrete mode)
1 0 1 16-bit timer counter mode (cascade connection mode)
0 1 1 Carrier generator mode
0 1 0 Timer 40: PWM output mode
Timer 30: 8-bit timer counter mode
Other than above Setting prohibited
TOE40 Control of timer output
0 Output disabled (port mode)
1 Output enabled
Notes 1. Since the count operation is controlled by TCE40 in cascade connection mode, any setting for
TCE30 (bit 7 of TMC30) is ignored.
2. The operation mode selection is set to both the TMC30 register and TMC40 register.
Caution Be sure to clear bit 6 to 0.
Remarks 1. f
X: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
CHAPTER 6 8-BIT TIMERS 30 AND 40
96 User’s Manual U15552EJ2V2UD
(3) Carrier generator output control register 40 (TCA40)
This register is used to set the timer output data in carrier generator mode.
TCA40 is set with an 8-bit memory manipulation instruction.
RESET input sets TCA40 to 00H.
Figure 6-6. Format of Carrier Generator Output Control Register 40
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
TCA40 0 0 0 0 0 RMC40 NRZB40 NRZ40 FF6AH 00H R/W
RMC40 Control of remote control output
0 When NRZ40 = 1, carrier pulse is output to TO40/P60 pin
1 When NRZ40 = 1, high-level signal is output to TO40/P60 pin
NRZB40 This is the bit that stores the next data to be output to NRZ40. Data is transferred to NRZ40 at the rising edge
of the timer 30 match signal. Input the necessary value in NRZB40 in advance by program.
NRZ40 No return zero data
0 Output low-level signal (carrier clock is stopped)
1 Output carrier pulse or high-level signal
Cautions 1. Bits 3 to 7 must be set to 0.
2. TCA40 cannot be set with a 1-bit memory manipulation instruction. Be sure to use an 8-
bit memory manipulation instruction to set TCA40.
3. The NRZ40 flag can be written only when carrier generator output is stopped (TOE40 =
0). The data cannot be overwritten when TOE40 = 1.
4. When the carrier generator is stopped once and then started again, NRZB40 does not
hold the previous data. Re-set data to NRZB40. At this time, a 1-bit memory
manipulation instruction must not be used. Be sure to use an 8-bit memory
manipulation instruction.
5. To enable operation in the carrier generator mode, set a value to the compare registers
(CR30, CR40, and CRH40), and input the necessary value to the NRZB40 and NRZ40
flags in advance. Otherwise, the signal of the timer match circuit will become unstable
and the NRZ40 flag will be undefined.
CHAPTER 6 8-BIT TIMERS 30 AND 40
User’s Manual U15552EJ2V2UD 97
(4) Port mode register 6 (PM6)
This register is used to set the I/O mode of port 6 in 1-bit units.
When using the P60/TO40 pin as a timer output, set the PM60 and P60 output latch to 0.
PM6 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM6 to FFH.
Figure 6-7. Format of Port Mode Register 6
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PM6 1 1 1 1 1 1 PM61 PM60 FF26H FFH R/W
PM6n I/O mode of P6n pin
(n = 0, 1)
0 Output mode (output buffer is on)
1 Input mode (output buffer is off)
CHAPTER 6 8-BIT TIMERS 30 AND 40
98 User’s Manual U15552EJ2V2UD
6.4 Operation of 8-Bit Timers 30 and 40
6.4.1 Operation as 8-bit timer counter
Timers 30 and 40 can be independently used as 8-bit timer counters.
The following modes can be used for the 8-bit timer counters.
• Interval timer with 8-bit resolution
• Square-wave output with 8-bit resolution (timer 40 only)
(1) Operation as interval timer with 8-bit resolution
The interval timer with 8-bit resolution repeatedly generates an interrupt at a time interval specified by the
count value preset in 8-bit compare register n0 (CRn0).
To operate 8-bit timer n0 as an interval timer, settings must be made in the following sequence.
<1> Disable operation of 8-bit timer counter n0 (TMn0) (TCEn0 = 0).
<2> Disable timer output of TOn0 (TOEn0 = 0).
<3> Set a count value in CRn0.
<4> Set the operation mode of timer n0 to 8-bit timer counter mode (see Figures 6-4 and 6-5).
<5> Set the count clock for timer n0 (see Tables 6-3 and 6-4).
<6> Enable the operation of TMn0 (TCEn0 = 1).
When the count value of 8-bit timer counter n0 (TMn0) matches the value set in CRn0, TMn0 is cleared to
00H and continues counting. At the same time, an interrupt request signal (INTTMn0) is generated.
Tables 6-3 and 6-4 show the interval time, and Figures 6-8 to 6-12 show the timing of the interval timer
operation.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
Remark n = 3, 4
CHAPTER 6 8-BIT TIMERS 30 AND 40
User’s Manual U15552EJ2V2UD 99
Table 6-3. Interval Time of Timer 30 (at fX = 5.0 MHz Operation)
TCL301 TCL300 Minimum Interval Time Maximum Interval Time Resolution
0 0 26/fX (12.8
µ
s) 214/fX (3.28 ms) 24/fX (12.8
µ
s)
0 1 28/fX (51.2
µ
s) 216/fX (13.1 ms) 28/fX (51.2
µ
s)
1 0 Input cycle of timer 40 match
signal
Input cycle of timer 40 match
signal × 28
Input cycle of timer 40 match
signal
1 1 Carrier clock cycle created
with timer 40
Carrier clock cycle created
with timer 40 × 28
Carrier clock cycle created
with timer 40
Remark fX: Main system clock oscillation frequency
Table 6-4. Interval Time of Timer 40 (at fX = 5.0 MHz Operation)
TCL402 TCL401 TCL400 Minimum Interval Time Maximum Interval Time Resolution
0 0 0 1/fX (0.2
µ
s) 28/fX (51
µ
s) 1/fX (0.2
µ
s)
0 0 1 22/fX (0.8
µ
s) 210/fX (205
µ
s) 22/fX (0.8
µ
s)
0 1 0 2/fX (0.4
µ
s) 29/fX (102
µ
s) 2/fX (0.4
µ
s)
0 1 1 22/fX (0.8
µ
s) 210/fX (205
µ
s) 22/fX (0.8
µ
s)
1 0 0 23/fX (1.6
µ
s) 211/fX (410
µ
s) 23/fX (1.6
µ
s)
1 0 1 24/fX (3.2
µ
s) 212/fX (819
µ
s) 24/fX (3.2
µ
s)
Remark fX: Main system clock oscillation frequency
Figure 6-8. Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation)
Count stop
Count clock
CRn0
TCEn0
INTTMn0
TOn0
N
t
TMn0 N00H 01H N00H 01H N00H 00H
01H
00H 01H
Clear Clear Clear
Count start
Interrupt acknowledgment Interrupt acknowledgment
Interrupt acknowledgment
Interval time Interval time
Remarks 1. Interval time = (N + 1) × t: N = 00H to FFH
2. n = 3, 4
CHAPTER 6 8-BIT TIMERS 30 AND 40
100 User’s Manual U15552EJ2V2UD
Figure 6-9. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to 00H)
Count clock
CRn0
TCEn0
INTTMn0
TOn0
00H
TMn0 00H
Count start
Remark n = 3, 4
Figure 6-10. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH)
Count clock
CRn0
TCEn0
INTTMn0
TOn0
FFH
TMn0 FFH 00H 01H 00H 01H 00H 00H
00H 01H FFH FFH FFH
Clear Clear Clear
Count start
Remark n = 3, 4
CHAPTER 6 8-BIT TIMERS 30 AND 40
User’s Manual U15552EJ2V2UD 101
Figure 6-11. Timing of Interval Timer Operation with 8-Bit Resolution
(When CRn0 Changes from N to M (N < M))
Count clock
CRn0
TCEn0
INTTMn0
TOn0
TMn0 N00H 00H N00H 01H
00H 01H MNM
NM
Clear Clear Clear
Count start
Interrupt acknowledgment Interrupt acknowledgment
CRn0 overwritten
Remark n = 3, 4
Figure 6-12. Timing of Interval Timer Operation with 8-Bit Resolution
(When CRn0 Changes from N to M (N > M))
Count clock
CRn0
TCEn0
INTTMn0
TOn0
TMn0 00H 00H 00H
N − 1 NMN M
NM
00H FFH M
H
Clear Clear Clear
TMn0 overflows
because M < N
CRn0 overwritten
Remark n = 3, 4
CHAPTER 6 8-BIT TIMERS 30 AND 40
102 User’s Manual U15552EJ2V2UD
Figure 6-13. Timing of Interval Timer Operation with 8-Bit Resolution
(When Timer 40 Match Signal Is Selected for Timer 30 Count Clock)
Timer 40
count clock
CR40
TCE40
INTTM40
TO40
TM40 N00H M00H
00H 01H M
NM
00H M00H
00H 01H Y − 1 Y00H Y00H
Y
Input clock to timer 30
(timer 40 match signal)
TO30
INTTM30
TCE30
CR30
TM30
Clear Clear Clear Clear
Count start
Count start
Remark n = 3, 4
CHAPTER 6 8-BIT TIMERS 30 AND 40
User’s Manual U15552EJ2V2UD 103
(2) Operation as square-wave output with 8-bit resolution (timer 40 only)
Square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare
register 40 (CR40).
To operate timer 40 for square-wave output, settings must be made in the following sequence.
<1> Set P60 to output mode (PM60 = 0).
<2> Set the output latch of P60 to 0.
<3> Disable operation of timer counter 40 (TM40) (TCE40 = 0).
<4> Set a count clock for timer 40 and enable output of TO40 (TOE40 = 1).
<5> Set a count value in CR40.
<6> Enable the operation of TM40 (TCE40 = 1).
When the count value of TM40 matches the value set in CR40, the TO40 pin output will be inverted. Through
application of this mechanism, square waves of any frequency can be output. As soon as a match occurs,
TM40 is cleared to 00H and continues counting. At the same time, an interrupt request signal (INTTM40) is
generated.
The square-wave output is cleared to 0 by setting TCE40 to 0.
Table 6-5 shows the square-wave output range, and Figure 6-14 shows the timing of square-wave output.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
Table 6-5. Square-Wave Output Range of Timer 40 (at fX = 5.0 MHz Operation)
TCL402 TCL401 TCL400 Minimum Pulse Width Maximum Pulse Width Resolution
0 0 0 1/fX (0.2
µ
s) 28/fX (51
µ
s) 1/fX (0.2
µ
s)
0 0 1 22/fX (0.8
µ
s) 210/fX (205
µ
s) 22/fX (0.8
µ
s)
0 1 0 2/fX (0.4
µ
s) 29/fX (102
µ
s) 2/fX (0.4
µ
s)
0 1 1 22/fX (0.8
µ
s) 210/fX (205
µ
s) 22/fX (0.8
µ
s)
1 0 0 23/fX (1.6
µ
s) 211/fX (410
µ
s) 23/fX (1.6
µ
s)
1 0 1 24/fX (3.2
µ
s) 212/fX (819
µ
s) 24/fX (3.2
µ
s)
Remark fX: Main system clock oscillation frequency
CHAPTER 6 8-BIT TIMERS 30 AND 40
104 User’s Manual U15552EJ2V2UD
Figure 6-14. Timing of Square-Wave Output with 8-Bit Resolution
Count clock
CR40
TCE40
INTTM40
TO40
Note
N
TM40 N00H 01H N00H 01H N00H 01H
00H 01H
Clear Clear Clear
Count start
Interrupt acknowledgment Interrupt acknowledgment
Interrupt acknowldgement
Square-wave output cycle
t
Note The initial value of TO40 is low level when output is enabled (TOE40 = 1).
Remark Square-wave output cycle = 2 (N + 1) × t: N = 00H to FFH
CHAPTER 6 8-BIT TIMERS 30 AND 40
User’s Manual U15552EJ2V2UD 105
6.4.2 Operation as 16-bit timer counter
Timers 30 and 40 can be used as 16-bit timer counters via a cascade connection. In this case, 8-bit timer counter
30 (TM30) is the higher 8 bits and 8-bit timer counter 40 (TM40) is the lower 8 bits. 8-bit timer 40 controls reset and
clear.
The following modes can be used for the 16-bit timer counter.
• Interval timer with 16-bit resolution
• Square-wave output with 16-bit resolution
(1) Operation as interval timer with 16-bit resolution
The interval timer with 16-bit resolution repeatedly generates an interrupt at a time interval specified by the
count value preset in 8-bit compare register 30 (CR30) and 8-bit compare register 40 (CR40).
To operate as an interval timer with 16-bit resolution, settings must be made in the following sequence.
<1> Disable operation of 8-bit timer counter 30 (TM30) and 8-bit timer counter 40 (TM40) (TCE30 = 0,
TCE40 = 0).
<2> Disable timer output of TO40 (TOE40 = 0).
<3> Set the count clock for timer 40 (see Table 6-4).
<4> Set the operation mode of timer 30 and timer 40 to 16-bit timer counter mode (see Figures 6-4 and 6-
5).
<5> Set a count value in CR30 and CR40.
<6> Enable the operation of TM30 and TM40 (TCE40 = 1Note).
Note Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE40 (the value of
TCE30 is invalid).
When the count values of TM30 and TM40 match the values set in CR30 and CR40 respectively, both TM30 and
TM40 are simultaneously cleared to 00H and counting continues. At the same time, an interrupt request signal
(INTTM40) is generated (INTTM30 is not generated).
Table 6-6 shows interval time, and Figure 6-15 shows the timing of the interval timer operation.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
Table 6-6. Interval Time with 16-Bit Resolution (at fX = 5.0 MHz Operation)
TCL402 TCL401 TCL400 Minimum Interval Time Maximum Interval Time Resolution
0 0 0 1/fX (0.2
µ
s) 216/fX (13.1 ms) 1/fX (0.2
µ
s)
0 0 1 22/fX (0.8
µ
s) 218/fX (52.4 ms) 22/fX (0.8
µ
s)
0 1 0 2/fX (0.4
µ
s) 217/fX (26.2 ms) 2/fX (0.4
µ
s)
0 1 1 22/fX (0.8
µ
s) 218/fX (52.4 ms) 22/fX (0.8
µ
s)
1 0 0 23/fX (1.6
µ
s) 219/fX (105 ms) 23/fX (1.6
µ
s)
1 0 1 24/fX (3.2
µ
s) 220/fX (210 ms) 24/fX (3.2
µ
s)
Remark fX: Main system clock oscillation frequency
CHAPTER 6 8-BIT TIMERS 30 AND 40
106 User’s Manual U15552EJ2V2UD
Figure 6-15. Timing of Interval Timer Operation with 16-Bit Resolution
Interval time
TM40 count clock
TM40 count value
CR40
TCE40
INTTM40
TO40
FFH 00H7FH
00H
N00H
NN N N
80H 7FH 80H FFH 00H N00H
NNN
TM30 count clock
TM30 00H X
X − 1
01H
CR30 XXX
7FH 80H FFH 00H N00H
NNN
X
X − 1 00H
t
Not cleared because TM30 does not match Cleared because TM30 and TM40 match simultaneously
Count start
Interrupt not generated because
TM30 does not match Interrupt acknowledgment Interrupt acknowledgment
Remark Interval time = (256X + N + 1) × t: X = 00H to FFH, N = 00H to FFH
CHAPTER 6 8-BIT TIMERS 30 AND 40
User’s Manual U15552EJ2V2UD 107
(2) Operation as square-wave output with 16-bit resolution
Square waves of any frequency can be output at an interval specified by the count value preset in CR30 and
CR40.
To operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence.
<1> Disable operation of TM30 and TM40 (TCE30 = 0, TCE40 = 0).
<2> Disable output of TO40 (TOE40 = 0).
<3> Set a count clock for timer 40.
<4> Set P60 to output mode (PM60 = 0) and P60 output latch to 0 and enable TO40 output (TOE40 = 1).
<5> Set count values in CR30 and CR40.
<6> Enable the operation of TM40 (TCE40 = 1Note).
Note Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE40 (the value of
TCE30 is invalid).
When the count values of TM30 and TM40 simultaneously match the values set in CR30 and CR40
respectively, the TO40 pin output will be inverted. Through application of this mechanism, square waves of
any frequency can be output. As soon as a match occurs, TM30 and TM40 are cleared to 00H and counting
continues. At the same time, an interrupt request signal (INTTM40) is generated (INTTM30 is not generated).
The square-wave output is cleared to 0 by setting TCE40 to 0.
Table 6-7 shows the square wave-output range, and Figure 6-16 shows timing of square-wave output.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
Table 6-7. Square-Wave Output Range with 16-Bit Resolution (at fX = 5.0 MHz Operation)
TCL402 TCL401 TCL400 Minimum Pulse Width Maximum Pulse Width Resolution
0 0 0 1/fX (0.2
µ
s) 216/fX (13.1 ms) 1/fX (0.2
µ
s)
0 0 1 22/fX (0.8
µ
s) 218/fX (52.4 ms) 22/fX (0.8
µ
s)
0 1 0 2/fX (0.4
µ
s) 217/fX (26.2 ms) 2/fX (0.4
µ
s)
0 1 1 22/fX (0.8
µ
s) 218/fX (52.4 ms) 22/fX (0.8
µ
s)
1 0 0 23/fX (1.6
µ
s) 219/fX (105 ms) 23/fX (1.6
µ
s)
1 0 1 24/fX (3.2
µ
s) 220/fX (210 ms) 24/fX (3.2
µ
s)
Remark fX: Main system clock oscillation frequency
CHAPTER 6 8-BIT TIMERS 30 AND 40
108 User’s Manual U15552EJ2V2UD
Figure 6-16. Timing of Square-Wave Output with 16-Bit Resolution
TM40 count clock
TM40 count clock
CR40
TCE40
INTTM40
TO40
Note
FFH 00H7FH
00H
N00H
NN N N
80H 7FH 80H FFH 00H N00H
NNN
TM30 count clock
TM30 00H X
X − 1
01H
CR30 XXX
7FH 80H FFH 00H N00H
NNN
X
X − 1 00H
Not cleared because TM30 does not match Cleared because TM30 and TM40 match simultaneously
Count start
Interrupt not generated because
TM30 does not match Interrupt acknowledgment
Interrupt acknowledgment
Square-wave output cycle/2
t
Note The initial value of TO40 is low level when output is enabled (TOE40 = 1).
Remark Square-wave output cycle = 2 (256X + N + 1) × t: X = 00H to FFH, N = 00H to FFH
CHAPTER 6 8-BIT TIMERS 30 AND 40
User’s Manual U15552EJ2V2UD 109
6.4.3 Operation as carrier generator
An arbitrary carrier clock generated by TM40 can be output in the cycle set in TM30.
To operate timers 30 and 40 as carrier generators, settings must be made in the following sequence.
<1> Disable operation of TM30 and TM40 (TCE30 = 0, TCE40 = 0).
<2> Disable timer output of TO40 (TOE40 = 0).
<3> Set count values in CR30, CR40, and CRH40.
<4> Set the operation mode of timer 30 and timer 40 to carrier generator mode (see Figures 6-4 and 6-5).
<5> Set the count clock for timer 30 and timer 40.
<6> Set remote control output to carrier pulse (RMC40 (bit 2 of carrier generator output control register 40
(TCA40)) = 0).
Input the required value to NRZB40 (bit 1 of TCA40) by program.
Input a value to NRZ40 (bit 0 of TCA40) before it is reloaded from NRZB40.
<7> Set P60 to output mode (PM60 = 0) and the P60 output latch to 0 and enable TO40 output by setting TOE40
to 1.
<8> Enable the operation of TM30 and TM40 (TCE30 = 1, TCE40 = 1).
<9> Save the NRZB40 value to a general-purpose register.
<10> When INTTM30 rises, the NRZB40 value is transferred to NRZ40. After that, rewrite TCA40 using an 8-bit
memory manipulation instruction. Input the value to be transferred next to NRZ40 to NRZB40, and input the
value saved in step <9> to NRZ40.
<11> Generate the desired carrier signal by repeating steps <9> and <10>.
The operation of the carrier generator is as follows.
<1> When the count the value of TM40 matches the value set in CR40, an interrupt request signal (INTTM40) is
generated and the output of timer 40 is inverted, which makes the compare register switch from CR40 to
CRH40.
<2> After that, when the count the value of TM40 matches the value set in CRH40, an interrupt request signal
(INTTM40) is generated and the output of timer 40 is inverted again, which makes the compare register
switch from CRH40 to CR40.
<3> The carrier clock is generated by repeating <1> and <2> above.
<4> When the count value of TM30 matches the value set in CR30, an interrupt request signal (INTTM30) is
generated. The rising edge of INTTM30 is the data reload signal of NRZB40 and is transferred to NRZ40.
<5> When NRZ40 is 1, a carrier clock is output from TO40 pin.
Cautions 1. TCA40 cannot be set with a 1-bit memory manipulation instruction. Be sure to use an 8-bit
memory manipulation instruction.
2. The NRZ40 flag can be rewritten only when the carrier generator output is stopped (TOE40
= 0). The data of the flag is not changed even if a write instruction is executed while TOE40
= 1.
3. When the carrier generator is stopped once and then started again, NRZB40 does not hold
the previous data. Re-set data to NRZB40. At this time, a 1-bit memory manipulation
instruction must not be used. Be sure to use an 8-bit memory manipulation instruction.
4. To enable operation in the carrier generator mode, set a value to the compare registers
(CR30, CR40, and CRH40), and input the necessary value to the NRZB40 and NRZ40 flags in
advance. Otherwise, the signal of the timer match circuit will become unstable and the
NRZ40 flag will be undefined.
CHAPTER 6 8-BIT TIMERS 30 AND 40
110 User’s Manual U15552EJ2V2UD
Figures 6-17 to 6-19 show the operation timing of the carrier generator.
Figure 6-17. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M > N))
TM40 count clock
TM40
count value
CR40
TCE40
INTTM40
M
00HN00H 01H
N
CRH40 M
N00H
Carrier clock
N00H 00H N M
00H 01H X 00H 01H X 00H 01H X 00H X 00H 01H
TM30
CR30
TCE30
INTTM30
TM30 count clock
01010
0101
0
NRZB40
NRZ40
TO40
Carrier clock
Clear Clear Clear Clear
Count start
X
CHAPTER 6 8-BIT TIMERS 30 AND 40
User’s Manual U15552EJ2V2UD 111
Figure 6-18. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M < N))
TM40 count clock
TM40
count value
CR40
TCE40
INTTM40
N
00H
N
CRH40 M
Carrier clock
N
00H
00H 01H X00H 01H X 00H 01H X00H X 00H 01H
TM30
CR30
TCE30
INTTM30
TM30 count clock
01010
0101
0
NRZB40
NRZ40
TO40
Carrier clock
M00H MM00H M00H
Clear Clear Clear Clear
Count start
X
Remark This figure shows an example of when the NRZ40 value is changed while the carrier clock is high level.
CHAPTER 6 8-BIT TIMERS 30 AND 40
112 User’s Manual U15552EJ2V2UD
Figure 6-19. Timing of Carrier Generator Operation (When CR40 = CRH40 = N)
TM40 count clock
TM40
count value
CR40
TCE40
INTTM40
N
00H00H 00H
N
CRH40 N
N
Carrier clock
00H 00H N N
00H 01H X
X
00H 01H X 00H 01H X 00H X 00H 01H
TM30
CR30
TCE30
INTTM30
TM30 count clock
01010
0101
0
NRZB40
NRZ40
TO40
Carrier clock
NN00H
Clear Clear Clear Clear Clear
Count start
CHAPTER 6 8-BIT TIMERS 30 AND 40
User’s Manual U15552EJ2V2UD 113
6.4.4 Operation as PWM output (timer 40 only)
In the PWM output mode, a pulse of any duty ratio can be output by setting a low-level width using CR40 and a
high-level width using CRH40.
To operate timer 40 in PWM output mode, settings must be made in the following sequence.
<1> Disable operation of TM40 (TCE40 = 0).
<2> Disable timer output of TO40 (TOE40 = 0).
<3> Set count values in CR40 and CRH40.
<4> Set the operation mode of timer 40 to carrier generator mode (see Figure 6-5).
<5> Set the count clock for timer 40.
<6> Set P60 to output mode (PM60 = 0) and the P60 output latch to 0 and enable timer output of TO40 (TOE40 =
1).
<7> Enable the operation of TM40 (TCE40 = 1).
The operation in the PWM output mode is as follows.
<1> When the count value of TM40 matches the value set in CR40, an interrupt request signal (INTTM40) is
generated and the output of timer 40 is inverted, which makes the compare register switch from CR40 to
CRH40.
<2> A match between TM40 and CR40 clears the TM40 value to 00H and then counting starts again.
<3> After that, when the count value of TM40 matches the value set in CRH40, an interrupt request signal
(INTTM40) is generated and the output of timer 40 is inverted again, which makes the compare register
switch from CRH40 to CR40.
<4> A match between TM40 and CRH40 clears the TM40 value to 00H and then counting starts again.
A pulse of any duty ratio is output by repeating <1> to <4> above. Figures 6-20 and 6-21 show the operation timing
in the PWM output mode.
CHAPTER 6 8-BIT TIMERS 30 AND 40
114 User’s Manual U15552EJ2V2UD
Figure 6-20. PWM Output Mode Timing (Basic Operation)
TM40 count clock
TM40
count value
CR40
TCE40
INTTM40
00H
N
00H 01H
N
CRH40 M
N
TO40
Note
00H 00H
01H M01H 01H M00H
Clear Clear Clear Clear
Count start
Note The initial value of TO40 is low level when output is enabled (TOE40 = 1).
Figure 6-21. PWM Output Mode Timing (When CR40 and CRH40 Are Overwritten)
TM40 count clock
TM40
count value
CR40
TCE40
INTTM40
00H
N
00H 01H
N
CRH40 M
N
TO40
Note
M
X
Y00H 00H X
00H
X
YM
Clear Clear Clear Clear
Count start
Note The initial value of TO40 is low level when output is enabled (TOE40 = 1).
CHAPTER 6 8-BIT TIMERS 30 AND 40
User’s Manual U15552EJ2V2UD 115
6.5 Notes on Using 8-Bit Timers 30 and 40
(1) Error on starting timer
An error of up to 1.5 clocks is included in the time between when the timer is started and a match signal is
generated. This is because the counter may be incremented by detecting a rising edge at the timing at which
the timer starts while the count clock is high level (see Figure 6-22).
Figure 6-22. Case in Which Error of 1.5 Clocks (Max.) Occurs
TCEn0
TCEn0
00H 01H 02H 03H
If delay A > delay B when the timer starts while the selected
clock is high level, an error of 1.5 clocks (max.) occurs.
TMn0 count value
Count pulse
Clear signal
Selected clock
Clear signal
8-bit timer counter n0
(TMn0)
Count
pulse
Delay A
Delay A
Delay B
Delay B
Selected clock
Remark n = 3, 4
116 User’s Manual U15552EJ2V2UD
CHAPTER 7 WATCH TIMER
7.1 Watch Timer Functions
The watch timer has the following functions.
• Watch timer
• Interval timer
The watch and interval timers can be used at the same time.
Figure 7-1 shows a block diagram of the watch timer.
Figure 7-1. Block Diagram of Watch Timer
f
X
/2
7
f
XT
f
W
f
W
2
4
f
W
2
5
f
W
2
6
f
W
2
7
f
W
2
8
f
W
2
9
Clear
9-bit prescaler
Selector
Clear
5-bit counter INTWT
INTWTI
WTM7 WTM6 WTM5 WTM4 WTM1 WTM0
Watch timer mode
control register (WTM)
Internal bus
Selector
CHAPTER 7 WATCH TIMER
User’s Manual U15552EJ2V2UD 117
(1) Watch timer
The 4.19 MHz main system clock or 32.768 kHz subsystem clock is used to generate an interrupt request
(INTWT) at 0.5-second intervals.
Caution When the main system clock is operating at 5.0 MHz, it cannot be used to generate a 0.5-
second interval. In this case, the subsystem clock, which operates at 32.768 kHz, should
be used instead.
(2) Interval timer
The interval timer is used to generate an interrupt request (INTWT) at specified intervals.
Table 7-1. Interval Time of Interval Timer
Interval At fX = 5.0 MHz Operation At fX = 4.19 MHz Operation At fXT = 32.768 kHz Operation
24 × 1/fW 409.6
µ
s 488
µ
s 488
µ
s
25 × 1/fW 819.2
µ
s 977
µ
s 977
µ
s
26 × 1/fW 1.64 ms 1.95 ms 1.95 ms
27 × 1/fW 3.28 ms 3.91 ms 3.91 ms
28 × 1/fW 6.55 ms 7.81 ms 7.81 ms
29 × 1/fW 13.1 ms 15.6 ms 15.6 ms
Remarks 1. f
W: Watch timer clock frequency (fX/27 or fXT)
2. f
X: Main system clock oscillation frequency
3. f
XT: Subsystem clock oscillation frequency
7.2 Watch Timer Configuration
The watch timer includes the following hardware.
Table 7-2. Configuration of Watch Timer
Item Configuration
Counter 5 bits × 1
Prescaler 9 bits × 1
Control register Watch timer mode control register (WTM)
CHAPTER 7 WATCH TIMER
118 User’s Manual U15552EJ2V2UD
7.3 Register Controlling Watch Timer
The watch timer mode control register (WTM) is used to control the watch timer.
• Watch timer mode control register (WTM)
WTM selects the count clock for the watch timer and specifies whether to enable operation of the timer. It also
specifies the prescaler interval and how the 5-bit counter is controlled.
WTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets WTM to 00H.
Figure 7-2. Format of Watch Timer Mode Control Register
Symbol 7 6 5 4 3 2 <1> <0> Address After reset R/W
WTM WTM7 WTM6 WTM5 WTM4 0 0 WTM1 WTM0 FF4AH 00H R/W
WTM7 Watch timer count clock (fW) selection
0 fX/27 (39.1 kHz)
1 fXT (32.768 kHz)
WTM6 WTM5 WTM4 Prescaler interval selection
0 0 0 24/fW
0 0 1 25/fW
0 1 0 26/fW
0 1 1 27/fW
1 0 0 28/fW
1 0 1 29/fW
Other than above Setting prohibited
WTM1 Control of 5-bit counter operation
0 Cleared after stop
1 Started
WTM0 Watch timer operation
0 Operation stopped (both prescaler and timer cleared)
1 Operation enabled
Caution Be sure to clear bits 2 and 3 to 0.
Remarks 1. f
W: Watch timer clock frequency (fX/27 or fXT)
2. f
X: Main system clock oscillation frequency
3. f
XT: Subsystem clock oscillation frequency
4. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
CHAPTER 7 WATCH TIMER
User’s Manual U15552EJ2V2UD 119
7.4 Watch Timer Operation
7.4.1 Operation as watch timer
The watch timer is used to generate an interrupt request at 0.5-second intervals using the main system clock (4.19
MHz) or subsystem clock (32.768 kHz).
By setting bits 0 and 1 (WTM0 and WTM1) of the watch timer mode control register (WTM) to 1, the watch timer
starts counting. By setting them to 0, the 5-bit counter is cleared and the watch timer stops counting.
When the interval timer also operates at the same time, the watch timer can be started from 0 seconds by setting
WTM1 to 0. However, an error of up to 29 × 1/fW seconds may occur for the first overflow of the watch timer (INTWT)
after a 0-second start because the 9-bit prescaler is not cleared in this case.
7.4.2 Operation as interval timer
The interval timer is used to repeatedly generate an interrupt request at the interval specified by a preset count
value.
The interval time can be selected by bits 4 to 6 (WTM4 to WTM6) of the watch timer mode control register (WTM).
Table 7-3. Interval Time of Interval Timer
Interval At fX = 5.0 MHz Operation At fX = 4.19 MHz Operation At fXT = 32.768 kHz Operation
24 × 1/fW 409.6
µ
s 488
µ
s 488
µ
s
25 × 1/fW 819.2
µ
s 977
µ
s 977
µ
s
26 × 1/fW 1.64 ms 1.95 ms 1.95 ms
27 × 1/fW 3.28 ms 3.91 ms 3.91 ms
28 × 1/fW 6.55 ms 7.81 ms 7.81 ms
29 × 1/fW 13.1 ms 15.6 ms 15.6 ms
Remarks 1. f
W: Watch timer clock frequency (fX/27 or fXT)
2. f
X: Main system clock oscillation frequency
3. f
XT: Subsystem clock oscillation frequency
CHAPTER 7 WATCH TIMER
120 User’s Manual U15552EJ2V2UD
Figure 7-3. Watch Timer/Interval Timer Operation Timing
0H
Start Overflow Overflow
5-bit counter
Count clock
f
W
/2
9
Watch timer
interrupt
INTWT
Interval timer
interrupt
INTWTI
Watch timer interrupt time (0.5 s) Watch timer interrupt time (0.5 s)
Interval
timer (T)
T
Caution When operation of the watch timer and 5-bit counter has been enabled by setting the watch
timer mode control register (WTM) (setting WTM0 (bit 0 of WTM) to 1), the time until the first
interrupt request after this setting will not be exactly the same as the watch timer interrupt time
(0.5 s) WTM). This is because the 5-bit counter starts counting one cycle after the output of the
9-bit prescaler. The INTWT signal will be generated at the set time from its second generation.
Remarks 1. f
W: Watch timer clock frequency
2. The parenthesized values apply to operation at fW = 32.768 kHz.
User’s Manual U15552EJ2V2UD 121
CHAPTER 8 WATCHDOG TIMER
8.1 Watchdog Timer Functions
The watchdog timer has the following functions.
• Watchdog timer
• Interval timer
Caution Select either the watchdog timer mode or interval timer mode using the watchdog timer mode
register (WDTM).
(1) Watchdog timer
The watchdog timer is used to detect an inadvertent program loop. When an inadvertent program loop is
detected, a non-maskable interrupt or the RESET signal can be generated.
Table 8-1. Program Loop Detection Time of Watchdog Timer
Program Loop Detection Time At fX = 5.0 MHz Operation
211 × 1/fX 410
µ
s
213 × 1/fX 1.64 ms
215 × 1/fX 6.55 ms
217 × 1/fX 26.2 ms
Remark f
X: Main system clock oscillation frequency
(2) Interval timer
The interval timer generates an interrupt at preset intervals.
Table 8-2. Interval Time of Watchdog Timer
Interval Time At fX = 5.0 MHz Operation
211 × 1/fX 410
µ
s
213 × 1/fX 1.64 ms
215 × 1/fX 6.55 ms
217 × 1/fX 26.2 ms
Remark f
X: Main system clock oscillation frequency
CHAPTER 8 WATCHDOG TIMER
122 User’s Manual U15552EJ2V2UD
8.2 Watchdog Timer Configuration
The watchdog timer includes the following hardware.
Table 8-3. Configuration of Watchdog Timer
Item Configuration
Control registers Watchdog timer clock selection register (TCL2)
Watchdog timer mode register (WDTM)
Figure 8-1. Block Diagram of Watchdog Timer
Internal bus
Internal bus
Prescaler
Selector
Controller
f
X
2
6
f
X
2
8
f
X
2
10
2
7-bit counter
Clear
WDTIF
WDTMK
TCL22 TCL21
Watchdog timer clock selection
register (TCL2)
Watchdog timer mode register
(WDTM)
WDTM4
RUN
WDTM3
INTWDT
Maskable
interrupt request
RESET
INTWDT
Non-maskable
interrupt request
f
X
2
4
CHAPTER 8 WATCHDOG TIMER
User’s Manual U15552EJ2V2UD 123
8.3 Registers Controlling Watchdog Timer
The watchdog timer is controlled by the following two registers.
• Watchdog timer clock selection register (TCL2)
• Watchdog timer mode register (WDTM)
(1) Watchdog timer clock selection register (TCL2)
This register sets the watchdog timer count clock.
TCL2 is set with an 8-bit memory manipulation instruction.
RESET input sets TCL2 to 00H.
Figure 8-2. Format of Watchdog Timer Clock Selection Register
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
TCL2 0 0 0 0 0 TCL22 TCL21 0 FF42H 00H R/W
TCL22 TCL21 Watchdog timer count clock selection Program loop detection or interval time
0 0 fX/24 (313 kHz) 211/fX (410
µ
s)
0 1 fX/26 (78.1 kHz) 213/fX (1.64 ms)
1 0 fX/28 (19.5 kHz) 215/fX (6.55 ms)
1 1 fX/210 (4.88 kHz) 217/fX (26.2 ms)
Caution Be sure to clear bits 0 and 3 to 7 to 0.
Remarks 1. f
X: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
CHAPTER 8 WATCHDOG TIMER
124 User’s Manual U15552EJ2V2UD
(2) Watchdog timer mode register (WDTM)
This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog
timer.
WDTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets WDTM to 00H.
Figure 8-3. Format of Watchdog Timer Mode Register
Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W
WDTM RUN 0 0 WDTM4 WDTM3 0 0 0 FFF9H 00H R/W
RUN Selection of operation of watchdog timerNote 1
0 Stop counting
1 Clear counter and start counting
WDTM4 WDTM3 Selection of operation mode of watchdog timerNote 2
0 0 Operation stopped
0 1 Interval timer mode (when overflow occurs, a maskable interrupt occur)Note 3
1 0 Watchdog timer mode 1 (when overflow occurs, a non-maskable interrupt occurs)
1 1 Watchdog timer mode 2 (when overflow occurs, a reset operation starts)
Notes 1. Once RUN has been set (1), it cannot be cleared (0) by software. Therefore, when counting is
started, it cannot be stopped by any means other than RESET input.
2. Once WDTM3 and WDTM4 have been set (1), they cannot be cleared (0) by software.
3. The watchdog timer starts operating as an interval timer when RUN is set to 1.
Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up
to 0.8% shorter than the time set by the watchdog timer clock selection register (TCL2).
2. In watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming that the WDTIF (bit 0 of
interrupt request flag register 0 (IF0)) is set to 0. While WDTIF is 1, a non-maskable
interrupt is generated upon write completion if watchdog timer mode 1 or 2 is selected.
CHAPTER 8 WATCHDOG TIMER
User’s Manual U15552EJ2V2UD 125
8.4 Watchdog Timer Operation
8.4.1 Operation as watchdog timer
The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode
register (WDTM) is set to 1.
The count clock (program loop detection time interval) of the watchdog timer can be selected by bits 1 and 2
(TCL21 and TCL22) of the watchdog timer clock selection register (TCL2). By setting bit 7 (RUN) of WDTM to 1, the
watchdog timer is started. Set RUN to 1 within the set program loop detection time interval after the watchdog timer
has been started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1,
and the program loop detection time is exceeded, the system is reset or a non-maskable interrupt is generated
according to the value of bit 3 (WDTM3) of WDTM.
The watchdog timer continues operating in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1
before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction.
Cautions 1. The actual program loop detection time may be up to 0.8% shorter than the set time.
2. When the subsystem clock is selected as the CPU clock, the watchdog timer stops counting.
In this case, therefore, the watchdog timer stops operating even though the main system
clock is oscillating.
Table 8-4. Program Loop Detection Time of Watchdog Timer
TCL22 TCL21 Program Loop Detection Time At fX = 5.0 MHz Operation
0 0 211 × 1/fX 410
µ
s
0 1 213 × 1/fX 1.64 ms
1 0 215 × 1/fX 6.55 ms
1 1 217 × 1/fX 26.2 ms
Remark f
X: Main system clock oscillation frequency
CHAPTER 8 WATCHDOG TIMER
126 User’s Manual U15552EJ2V2UD
8.4.2 Operation as interval timer
When bit 4 (WDTM4) and bit 3 (WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1,
respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at time intervals
specified by a preset count value.
Select a count clock (or interval time) by setting bits 1 and 2 (TCL21 and TCL22) of the watchdog timer clock
selection register (TCL2). The watchdog timer starts operating as an interval timer when the RUN bit (bit 7 of WDTM)
is set to 1.
In the interval timer mode, the interrupt mask flag (WDTMK) is valid, and a maskable interrupt (INTWDT) can be
generated. The priority of INTWDT is set as the highest of all the maskable interrupts.
The interval timer continues operating in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1
before entering the STOP mode to clear the interval timer, and then execute the STOP instruction.
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when the watchdog timer mode is selected), the
interval timer mode is not set unless the RESET signal is input.
2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than the
set time.
Table 8-5. Interval Time of Watchdog Timer
TCL22 TCL21 Interval Time At fX = 5.0 MHz Operation
0 0 211 × 1/fX 410
µ
s
0 1 213 × 1/fX 1.64 ms
1 0 215 × 1/fX 6.55 ms
1 1 217 × 1/fX 26.2 ms
Remark f
X: Main system clock oscillation frequency
User’s Manual U15552EJ2V2UD 127
CHAPTER 9 8-BIT A/D CONVERTER
9.1 Functions of 8-Bit A/D Converter
The 8-bit A/D converter is an 8-bit resolution converter that converts analog inputs to digital signals. This converter
can control one channel of analog inputs (ANI0).
A/D conversion can only be started by software.
A/D conversion is performed repeatedly, with an interrupt request (INTAD0) being issued each time an A/D
conversion operation is completed.
Caution The A/D converter stops operating in STOP mode.
9.2 Configuration of 8-Bit A/D Converter
The 8-bit A/D converter includes the following hardware.
Table 9-1. Configuration of 8-Bit A/D Converter
Item Configuration
Analog input 1 channel (ANI0)
Registers Successive approximation register (SAR)
A/D conversion result register 0 (ADCR0)
Control registers A/D converter mode register 0 (ADM0)
A/D input selection register 0 (ADS0)
CHAPTER 9 8-BIT A/D CONVERTER
128 User’s Manual U15552EJ2V2UD
Figure 9-1. Block Diagram of 8-Bit A/D Converter
Selector
Tap selector
Sample & hold circuit
Voltage comparator
Successive approximation
register (SAR)
Controller
A/D conversion result
register 0 (ADCR0)
A/D input selection
register 0 (ADS0)
A/D converter mode
register 0 (ADM0)
Internal bus
INTAD0
V
DD
V
SS
V
SS
P-ch
ADS00 ADCS0 FR02 FR01 FR00
ANI0/INTP0/P61
(1) Successive approximation register (SAR)
The SAR receives the result of comparing an analog input voltage and a voltage at the voltage tap
(comparison voltage) received from the series resistor string, starting from the most significant bit (MSB).
Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D
conversion, the SAR sends its contents to A/D conversion result register 0 (ADCR0).
(2) A/D conversion result register 0 (ADCR0)
ADCR0 holds the result of A/D conversion. Each time A/D conversion ends, the conversion result received
from the successive approximation register is loaded into ADCR0, which is an 8-bit register that holds the
result of A/D conversion.
ADCR0 can be read with an 8-bit memory manipulation instruction.
RESET input makes this register undefined.
(3) Sample & hold circuit
The sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends
them to the voltage comparator. The sampled analog input voltage is held during A/D conversion.
(4) Voltage comparator
The voltage comparator compares an analog input with the voltage output by the series resistor string.
CHAPTER 9 8-BIT A/D CONVERTER
User’s Manual U15552EJ2V2UD 129
(5) Series resistor string
The series resistor string is configured between VDD and VSS. It generates the reference voltages against
which analog inputs are compared.
(6) ANI0 pin
The ANI0 pin is the 1-channel analog input pin for the A/D converter. It is used to receive the analog signals
for A/D conversion.
Caution Do not supply the ANI0 pin with a voltage that falls outside the rated range. If a voltage
greater than or equal to VDD or less than or equal to VSS (even if within the absolute
maximum ratings) is supplied to this pin, the conversion value will be undefined.
CHAPTER 9 8-BIT A/D CONVERTER
130 User’s Manual U15552EJ2V2UD
9.3 Registers Controlling 8-Bit A/D Converter
The following two registers are used to control the 8-bit A/D converter.
• A/D converter mode register 0 (ADM0)
• A/D input selection register 0 (ADS0)
(1) A/D converter mode register 0 (ADM0)
ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion.
ADM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ADM0 to 00H.
Figure 9-2. Format of A/D Converter Mode Register 0
Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W
ADM0 ADCS0 0 FR02 FR01 FR00 0 0 0 FF80H 00H R/W
ADCS0 A/D conversion control
0 Conversion disabled
1 Conversion enabled
FR02 FR01 FR00 A/D conversion time selectionNote 1
0 0 0 72/fX (14.4
µ
s)
0 0 1 60/fX (setting prohibitedNote 2)
0 1 0 48/fX (setting prohibitedNote 2)
1 0 0 144/fX (28.8
µ
s)
1 0 1 120/fX (24
µ
s)
1 1 0 96/fX (19.2
µ
s)
Other than above Setting prohibited
Notes 1. The specifications of FR02, FR01, and FR00 must be such that the A/D conversion time is at least 14
µ
s.
2. These bit combinations must not be used when fX = 5.0 MHz, as the A/D conversion time will fall below
14
µ
s.
Cautions 1. The result of conversion performed immediately after bit 7 (ADCS0) is set is undefined. Use
the second or later result.
2. The result of conversion performed after ADCS0 is cleared may become undefined. When
reading the result of conversion, read it during A/D conversion. If reading the result of
conversion after stopping A/D conversion, stop A/D conversion and then read the result
between completion of A/D conversion and when the next A/D conversion starts.
3. Always set bits 0 to 2 and bit 6 to 0.
Remarks 1. f
X: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
CHAPTER 9 8-BIT A/D CONVERTER
User’s Manual U15552EJ2V2UD 131
(2) A/D input selection register 0 (ADS0)
The ADS0 register specifies the port used to input the analog voltage to be converted to a digital signal.
ADS0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ADS0 to 00H.
Figure 9-3. Format of A/D Input Selection Register 0
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
ADS0 0 0 0 0 0 0 0 ADS00 FF84H 00H R/W
ADS00 Port function of P61
0 Operates as P61 (general-purpose port pin) or INTP0 (external interrupt pin)
1 Operates as ANI0 (analog input pin). External interrupts are prohibited.
Caution Always set bits 1 to 7 to 0.
CHAPTER 9 8-BIT A/D CONVERTER
132 User’s Manual U15552EJ2V2UD
9.4 8-Bit A/D Converter Operation
9.4.1 Basic operation of 8-bit A/D converter
<1> Set bit 0 of A/D input selection register 0 (ADS0) so that the P61/INTP0/ANI0 pin can be used as an analog
input.
<2> The analog input voltage is sampled using the sample & hold circuit.
<3> After sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input
analog voltage until A/D conversion is completed.
<4> Bit 7 of the successive approximation register (SAR) is set. The series resistor string voltage tap at the tap
selector is set to half VDD.
<5> The series resistor string voltage tap is compared with the analog input voltage using the voltage comparator.
If the analog input voltage is higher than half VDD, the MSB of the SAR is left set. If it is lower than half VDD,
the MSB is reset.
<6> Bit 6 of the SAR is set automatically, and comparison shifts to the next stage. The next voltage tap of the
series resistor string is selected according to bit 7, which reflects the previous comparison result, as follows.
• Bit 7 = 1: Three quarters of VDD
• Bit 7 = 0: One quarter of VDD
The voltage tap is compared with the analog input voltage. Bit 6 is set or reset according to the result of
comparison.
• Analog input voltage ≥ voltage tap: Bit 6 = 1
• Analog input voltage < voltage tap: Bit 6 = 0
<7> Comparison is repeated until bit 0 of the SAR is reached.
<8> When comparison is completed for all of the 8 bits, a significant digital result is left in the SAR. This value is
sent to and latched in A/D conversion result register 0 (ADCR0). At the same time, it is possible to generate
an A/D conversion end interrupt request (INTAD0).
Figure 9-4. Basic Operation of 8-Bit A/D Converter
Conversion
time
Sampling
time
Sampling A/D conversion
Undefined 80H C0H
or 40H
Conversion
result
Conversion
result
A/D converter
operation
SAR
ADCR0
INTAD0
CHAPTER 9 8-BIT A/D CONVERTER
User’s Manual U15552EJ2V2UD 133
A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software.
If an attempt is made to write to ADM0 or A/D input selection register 0 (ADS0) during A/D conversion, the A/D
conversion in progress is canceled. In this case, if ADCS0 is set (1), A/D conversion is restarted from the beginning.
RESET input makes the A/D conversion result register 0 (ADCR0) undefined.
Cautions 1. The first A/D conversion value immediately after starting the A/D conversion operation is
undefined. Use the second or later conversion value.
2. When in standby mode, the A/D converter stops operation.
9.4.2 Input voltage and conversion result
The relationship between the analog input voltage at the analog input pin (ANI0) and the A/D conversion result
(A/D conversion result register 0 (ADCR0)) is represented by:
ADCR0 = INT ( × 256 + 0.5)
or
(ADCR0 − 0.5) × ≤ VIN < (ADCR0 + 0.5) ×
INT( ): Function that returns the integer part of the parenthesized value
VIN: Analog input voltage
VDD: Supply voltage
ADCR0: Value in the A/D conversion result register 0 (ADCR0)
Figure 9-5 shows the relationship between the analog input voltage and the A/D conversion result.
Figure 9-5. Relationship Between Analog Input Voltage and A/D Conversion Result
255
254
253
3
2
1
0
A/D conversion
result (ADCR0)
1
512
1
256
3
512
2
256
5
512
3
256
507
512
254
256
509
512
255
256
511
512
1
Input voltage/V
DD
VIN
VDD
VDD
256
VDD
256
CHAPTER 9 8-BIT A/D CONVERTER
134 User’s Manual U15552EJ2V2UD
9.4.3 Operation mode of 8-bit A/D converter
A/D input selection register 0 (ADS0) is used to select the function of the P61/INTP0/ANI0 pin to be used as an
analog input for A/D conversion.
A/D conversion can only be started by software, that is, by setting A/D converter mode register 0 (ADM0).
The A/D conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt
request signal (INTAD0) is generated.
• Software-started A/D conversion
Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) triggers A/D conversion for the voltage applied to
the analog input pin specified by A/D input selection register 0 (ADS0). Upon completion of A/D conversion, the
conversion result is saved to A/D conversion result register 0 (ADCR0). At the same, an interrupt request signal
(INTAD0) is generated. Once A/D conversion is started, and completed, another A/D conversion operation is
started. A/D conversion is repeated until new data is written to ADM0. If data in which ADCS0 is 1 is written to
ADM0 again during A/D conversion, the A/D conversion in progress is discontinued, and an A/D conversion
operation begins for the new data. If data in which ADCS0 is 0 is written to the ADM0 again during A/D
conversion, A/D conversion is completely stopped.
Figure 9-6. Software-Started A/D Conversion
Rewriting ADM0
ADCS0 = 1
Rewriting ADM0
ADCS0 = 1 ADCS0 = 0
A/D conversion
ADCR0
INTAD0
ANI0 ANI0 ANI0 ANI0 ANI0
Stop
ANI0 ANI0 ANI0
Conversion is
discontinued;
no conversion
result is preserved.
CHAPTER 9 8-BIT A/D CONVERTER
User’s Manual U15552EJ2V2UD 135
9.5 Cautions Related to 8-Bit A/D Converter
(1) Current consumption in standby mode
When the A/D converter enters a standby mode, it stops operating. Setting bit 7 (ADCS0) of A/D converter
mode register 0 (ADM0) to 0 can reduce the current consumption.
Figure 9-7 shows how to reduce the current consumption in standby mode.
Figure 9-7. How to Reduce Current Consumption in Standby Mode
V
DD
V
SS
P-ch
Series resistor string
ADCS0
(2) Input range for the ANI0 pin
Be sure to keep the input voltage at ANI0 within the rating. If a voltage greater than or equal to VDD or less
than or equal to VSS (even if within the absolute maximum ratings) is input to this channel, the conversion
output of the channel becomes undefined.
(3) Conflict
<1> Conflict between writing to A/D conversion result register 0 (ADCR0) at the end of conversion and
reading from ADCR0
Reading from ADCR0 takes precedence. After reading, the new conversion result is written to the
ADCR0.
<2> Conflict between writing to ADCR0 at the end of conversion and writing to A/D converter mode register
0 (ADM0) or A/D input selection register 0 (ADS0)
Writing to ADM0 or ADS0 takes precedence. A request to write to ADCR0 is ignored. No conversion
end interrupt request signal (INTAD0) is generated.
CHAPTER 9 8-BIT A/D CONVERTER
136 User’s Manual U15552EJ2V2UD
(4) Conversion results immediately following start of A/D conversion
The first A/D conversion value immediately following the start of A/D converter operation is undefined. Be
sure to poll the A/D conversion end interrupt request (INTAD0), discard the first conversion result and use the
second or later conversion result.
(5) Timing that makes the A/D conversion result undefined
If the timing of the end of A/D conversion and the timing of the stop of operation of the A/C converter conflict,
the A/D conversion value may be undefined. Because of this, be sure to read out the A/D conversion result
while the A/D converter is operating. Furthermore, when reading out an A/D conversion result after A/D
converter operation has stopped, be sure to have done so by the time the next conversion result is complete.
The conversion result readout timing is shown in Figures 9-8 and 9-9.
Figure 9-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value)
A/D conversion end A/D conversion end
Normal conversion result Undefined value
Normal conversion result read out Undefined value read out
A/D operation stopped
ADCR0
INTAD0
ADCS0
Figure 9-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value)
Normal conversion result
A/D conversion end
Normal conversion result read outA/D operation stopped
ADCR0
INTAD0
ADCS0
CHAPTER 9 8-BIT A/D CONVERTER
User’s Manual U15552EJ2V2UD 137
(6) Noise prevention
To maintain a resolution of 8 bits, watch for noise at the VDD and ANI0 pins. The higher the output
impedance of the analog input source, the larger the effect by noise. To reduce noise, attach an external
capacitor to the relevant pins as shown in Figure 9-8.
Figure 9-10. Analog Input Pin Handling
C = 100 to 1000 pF
If noise greater than or equal to VDD or less than or equal to
VSS is likely to come to the ANI0 pin, clamp the voltage at the
pin by attaching a diode with a small VF (0.3 V or lower).
VSS
VDD
ANI0
(7) ANI0
The analog input pin (ANI0) is an alternate-function pin. It is also used as a port pin (P60).
If ANI0 has been selected for A/D conversion, do not execute input instructions for the ports; otherwise the
conversion resolution may drop.
If a digital pulse is applied to a pin adjacent to the analog input pin being A/D converted, coupling noise may
occur which prevents an A/D conversion result from being attained as expected. Avoid applying a digital
pulse to pins adjacent to the analog input pin being A/D converted.
(8) Input impedance of ANI0 pin
This A/D converter executes sampling by charging the internal sampling capacitor for approximately 1/10 of
the conversion time.
Therefore, only the leakage current flows during other than sampling, and the current for charging the
capacitor flows during sampling. The input impedance therefore varies and has no meaning.
To achieve sufficient sampling, it is recommended that the output impedance of the analog input source be
10 kΩ or less, or attach a capacitor of around 100 pF to the ANI0 pin (see Figure 9-10).
CHAPTER 9 8-BIT A/D CONVERTER
138 User’s Manual U15552EJ2V2UD
(9) Interrupt request flag (ADIF0)
Changing the contents of A/D converter mode register 0 (ADM0) does not clear the interrupt request flag
(ADIF0).
If the analog input pin is changed during A/D conversion, therefore, the conversion result and the conversion
end interrupt request flag may reflect the previous analog input immediately before writing to ADM0 occurs.
In this case, ADIF0 may appear to be set if it is read-accessed immediately after ADM0 is write-accessed,
even when A/D conversion has not been completed for the new analog input.
In addition, ADIF0 must be cleared before A/D conversion is restarted.
Figure 9-11. A/D Conversion End Interrupt Request Generation Timing
Rewriting ADM0
(to begin conversion
of ANI0)
A/D conversion
ADCR0
INTAD0
ANI0 ANI0 ANI0
ANI0 ANI0 ANI0
ANI0
ANI0
Rewriting ADM0
(to begin conversion
of ANI0)
ADIF0 has been set, but conversion
of ANI0 has not been completed.
(10) Input impedance of VDD pin
A series resistor string of several 10 kΩ is connected across the VDD and VSS pins.
Therefore, if the output impedance of the reference voltage source is high, this high impedance is eventually
connected in series with the series resistor string across the VDD and VSS pins, leading to a higher reference
voltage error.
User’s Manual U15552EJ2V2UD 139
CHAPTER 10 LCD CONTROLLER/DRIVER
10.1 Functions of LCD Controller/Driver
The features of the LCD controller/driver of the
µ
PD789467 Subseries are as follows.
(1) Automatic output of segment and common signals based on automatic display data memory read
(2) Four different frame frequencies selectable
(3) Up to 23 segment signal outputs (S0 to S22) and four common signal outputs (COM0 to COM3)
(4) Operation with subsystem clock
(5) Voltage booster incorporated
Table 10-1 lists the maximum number of pixels that can be displayed in each display mode.
Table 10-1. Maximum Number of Pixels
Bias Mode Number of Time Slices Common Signals
Used
Maximum Number of Pixels
1/3 4 COM0 to COM3 92 (23 segments × 4 commons)Note
Note 11-digit LCD panel, each digit having a 2-segment configuration.
10.2 Configuration of LCD Controller/Driver
The LCD controller/driver includes the following hardware.
Table 10-2. Configuration of LCD Controller/Driver
Item Configuration
Display outputs Segment signals: 23
Common signals: 4
Control registers LCD display mode register 0 (LCDM0)
LCD clock control register 0 (LCDC0)
LCD voltage boost control register (LCDVA0)
Port function register 8 (PF8)
CHAPTER 10 LCD CONTROLLER/DRIVER
140 User’s Manual U15552EJ2V2UD
Internal bus
LCDC03 LCDC02
LCDC01
LCDC00
2
2
Prescaler
Selector
LCD
clock
selector
Selector
fLCD
26fLCD
27fLCD
28fLCD
29
LCD clock control
register 0
LCDON0
VAON0
LCD display mode
register 0
VLC0
Segment
driver
Common driver
COM0 COM1 COM2 COM3
3210
32106574
FA00H
Display data
memory
LCDON0
Selector
Segment
driver
3210
32106574
FA16H
LCDON0
S22/P80
fX/25
fX/26
fX/27
fXT
S0
fLCD
PF85 PF84 PF83 PF82 PF80
PF81
Port function
register 8 (PF8)
PF80
Selector
Segment
driver
3210
32106574
FA11H
LCDON0
S17/P85
PF85
LCDCL
LIPS0 GAIN
LCD voltage
boost control
register 0
(LCDVA0)
VLC2
CAPH CAPL VLC1
Voltage booster
Common voltage
controller
Clock generator
for voltage
boost
Timing
controller
VAON0
Segment voltage
controller
Figure 10-1. Block Diagram of LCD Controller/Driver
CHAPTER 10 LCD CONTROLLER/DRIVER
User’s Manual U15552EJ2V2UD 141
10.3 Registers Controlling LCD Controller/Driver
• LCD display mode register 0 (LCDM0)
• LCD clock control register 0 (LCDC0)
• LCD voltage boost control register 0 (LCDVA0)
• Port function register 8 (PF8)
(1) LCD display mode register 0 (LCDM0)
This register is used to enable/disable display operation, enable/disable voltage boost, and specify
segment/common pin output and display mode.
LCDM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets LCDM0 to 00H.
Figure 10-2. Format of LCD Display Mode Register 0
Symbol <7> <6> 5 4 3 2 1 0 Address After reset R/W
LCDM0 LCDON0 VAON0 0 LIPS0 0 LCDM02 0 0 FFB0H 00H R/W
LCDON0 LCD display enable/disable
0 Display off (all segment outputs are unselected for signal output)
1 Display on
VAON0 Voltage booster enable/disableNote 1
0 Voltage boost disabled
1 Voltage boost enabled
LIPS0 Segment/common pin output controlNotes 1,2
0 Ground level is output to segment/common pins
1 Unselected level and LCD waveform are output to segment and common pins, respectively.
LCDM02 Display mode selectionNote 3
0 Four-time-slice, 1/3 bias mode
1 Static mode
Notes 1. When the LCD display panel is not used, set VAON0 and LIPS0 to 0 to reduce power
consumption. However, when any one of pins P80 to P85 is used as a general-purpose pin, set
VAON0 to 1.
2. LIPS0 is valid only in mask ROM versions. However, writing to LIPS0 in the
µ
PD78F9468 will not
cause an error.
3. Ordinarily use in four-time-slice, 1/3 bias mode.
In either of the following cases, however, switch to the static mode (LCDM02 =1).
• When changing to the STOP mode when the main system clock is selected as the LCD source
clock.
• Between reset and voltage boost start
• When disabling both display and voltage boost
CHAPTER 10 LCD CONTROLLER/DRIVER
142 User’s Manual U15552EJ2V2UD
Cautions 1. Bits 0, 1, 3, and 5 must be set to 0.
2. When the main system clock is selected as the LCD source clock, if the STOP mode is
selected, an abnormal display may occur. Before selecting the STOP mode, disable
display and select the static mode (LCDON0 = 0 and LCDM02 =1). If the subsystem
clock is selected as the LCD source clock, a normal operation is performed in the STOP
mode.
3. After reset, both display and voltage boost are disabled. Therefore, set LCDM02 to 1 to
select the static mode. Otherwise, an abnormal display may occur until voltage
boosting starts.
4. When operating VAON0, follow the procedure described below.
A. To stop voltage boost after switching display status from on to off:
1) Set to display off status by setting LCDON0 = 0.
2) Disable outputs of all the segment buffers and common buffers by setting LIPS0 = 0.
3) Select the static mode by setting LCDM02 = 1.
4) Stop voltage boost by setting VAON0= 0.
B. To stop voltage boost during display on status:
Setting prohibited. Be sure to stop voltage boost after setting display off.
C. To set display on from voltage boost stop status:
1) Start voltage boost by setting VAON0 = 1, then wait for about 500 ms.
2) Select the four-time-slice, 1/3 bias mode by setting LCDM02 = 0.
3) Set all the segment buffers and common buffers to the non-display output status
by setting LIPS0 = 1.
4) Set display on by setting LCDON0 = 1.
5. The combinations of settings of LCDON0, VAON0, and LIPS0 enabled/prohibited by the
device file are as follows.
LCDON0 VAON0 LIPS0 Combination enabled/prohibited
0 0 0
0 1 0
0 1 1
1 1 1
Enabled by device file
0 0 1
1 0 0
1 0 1
1 1 0
Prohibited by device file
(If this combination is set, an error occurs.)
CHAPTER 10 LCD CONTROLLER/DRIVER
User’s Manual U15552EJ2V2UD 143
(2) LCD clock control register 0 (LCDC0)
LCDC0 specifies the LCD source clock and LCD clock. The frame frequency is determined by the LCD clock
and the number of time slices.
LCDC0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets LCDC0 to 00H.
Figure 10-3. Format of LCD Clock Control Register 0
Symbol 7 6 5 4 3 2 1 <0> Address After reset R/W
LCDC0 0 0 0 0 LCDC03 LCDC02 LCDC01 LCDC00 FFB2H 00H R/W
LCDC03 LCDC02 LCD source clock (fLCD) selectionNote
0 0 fXT (32.768 kHz)
0 1 fX/25 (156.3 kHz)
1 0 fX/26 (78.1 kHz)
1 1 fX/27 (39.1 kHz)
LCDC01 LCDC00 LCD clock (LCDCL) selection
0 0 fLCD/26
0 1 fLCD/27
1 0 fLCD/28
1 1 fLCD/29
Note Specify an LCD source clock (fLCD) frequency of at least 32 kHz.
Remarks 1. f
X: Main system clock oscillation frequency
2. f
XT: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
Cautions 1. Bits 4 to 7 must be set to 0.
2. Be sure to turn the display off (LCDON0 = 0) and stop the voltage booster (VAON0 = 0)
before changing the LCDC0 settings.
An example of frame frequencies when fXT (32.768 kHz) is connected to the LCD source clock (fLCD) is shown
in Table 10-3.
Caution Set frame frequencies to 128 Hz or lower.
Table 10-3. Frame Frequencies (Hz)
LCD Clock (LCDCL)
Time Slices
fXT/29
(64 Hz)
fXT/28
(128 Hz)
fXT/27
(256 Hz)
fXT/26
(512 Hz)
4 16 32 64 128
CHAPTER 10 LCD CONTROLLER/DRIVER
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(3) LCD voltage boost control register 0 (LCDVA0)
LCDVA0 controls the voltage boost level during the voltage boost operation.
LCDVA0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets LCDVA0 to 00H.
Figure 10-4. Format of LCD Voltage Boost Control Register 0
0 GAINLCDVA0
Symbol Address After reset R/W
FFB3H 00H R/W
7654321<0>
GAIN
0
1
1.5 V (specification of the LCD panel used is 4.5 V.)
1.0 V (specification of the LCD panel used is 3 V.)
000000
Reference voltage (V
LC2
) level selection
Note
Note Select the settings according to the specifications of the LCD panel that is used.
Cautions 1. Bits 1 to 7 must be set to 0.
2. Before changing the LCDVA0 setting, be sure to stop voltage boost (VAON0 = 0).
Remark The TYP. value is indicated as the reference voltage (VLC2) value.
(4) Port function register 8 (PF8)
PF8 specifies whether S17/P85 to S22/P80 are used as LCD segment signal outputs or general-purpose
ports in 1-bit units.
PF8 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PF8 to 00H.
Figure 10-5. Format of Port Function Register 8
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PF8 0 0 PF85 PF84 PF83 PF82 PF81 PF80 FF58H 00H R/W
PF8n Port function of P8n (n = 0 to 5)
0 Operates as a general-purpose port
1 Operates as an LCD segment signal output
(For cautions on this register, refer to Figure 4-10.)
CHAPTER 10 LCD CONTROLLER/DRIVER
User’s Manual U15552EJ2V2UD 145
10.4 Setting LCD Controller/Driver
Set the LCD controller/driver using the following procedure.
Before changing the LCD clock or voltage boost level, disable display and voltage boost.
10.4.1 Setting before starting display
<1> With the default setting after reset, select the static mode by setting bit 2 (LCDM02 = 1) of LCDM0.
<2> Input the initial data to the LCD display data memory.
<3> Set the LCD clock, using LCD clock control register 0 (LCDC0).
<4> Set the voltage boost level, using LCD voltage boost control register 0 (LCDVA0).
GAIN = 0: VLC0 = 4.5 V, VLC1 = 3.0 V, VLC2 = 1.5 V
GAIN = 0: VLC0 = 3.0 V, VLC1 = 2.0 V, VLC2 = 1.0 V
<5> Set bit 6 (VAON0 = 1) of LCD display mode register 0 (LCDM0) to enable the voltage booster.
<6> Wait for 500 ms or more after setting VAON0.
<7> Clear bit 2 (LCDM02 = 0) of LCDM0 to select four-time-slice, 1/3 bias mode.
<8> Set bit 4 (LIPS0 = 1) of LCDM0 to output the deselect electric potential.
<9> Set bit 7 (LCDON0 = 1) of LCDM0 to start output corresponding to each data memory.
10.4.2 Setting until disabling display and stopping voltage boost
<1> Clear bit 7 (LCDON0 = 0) of LCDM0 to select the display off status.
<2> Clear bit 4 (LIPS0 =0) of LCDM0 to prohibit all segment buffers and common buffers from outputting.
<3> Set bit 2 (LCDM02 = 1) of LCDM0 to select the static mode.
<4> Clear bit 6 (VAON0 = 0) of LCDM0 to disable voltage boost.
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10.5 LCD Display Data Memory
The LCD display data memory is mapped at addresses FA00H to FA16H. Data in the LCD display data memory
can be displayed on the LCD panel using the LCD controller/driver.
Figure 10-6 shows the relationship between the contents of the LCD display data memory and the
segment/common outputs.
Parts of the display data memory not used for display can be used as ordinary RAM.
Figure 10-6. Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs
S22FA16H
S21FA15H
S20FA14H
FA13H S19
S2FA02H
S1FA01H
S0FA00H
COM3 COM2 COM1 COM0
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
Address
Caution No memory has been assigned as the higher 4 bits of the LCD display data memory. Be sure to
set these bits to 0.
CHAPTER 10 LCD CONTROLLER/DRIVER
User’s Manual U15552EJ2V2UD 147
10.6 Common and Segment Signals
Each pixel of the LCD panel turns on when the potential difference between the corresponding common and
segment signals becomes higher than a specific voltage (LCD drive voltage, VLCD). It turns off when the potential
difference becomes lower than VLCD.
Applying DC voltage to the common and segment signals for an LCD panel causes degradation. To avoid this
problem, this LCD panel is driven with AC voltage.
(1) Common signals
Each common signal is selected sequentially according to the specified number of time slices at the timing
listed in Table 10-4.
Table 10-4. COM Signals
COM Signal
Number of Time Slices
COM0 COM1 COM2 COM3
Four-time-slice mode
(2) Segment signals
The segment signals correspond to 23 bytes of LCD display data memory (FA00H to FA16H). Bits 0, 1, 2,
and 3 of each byte are read in synchronization with COM0, COM1, COM2, and COM3, respectively. If the
contents of each bit are 1, it is converted to the select voltage, and if 0, it is converted to the deselect voltage.
The conversion results are output to the segment pins (S0 to S22).
Check, using the information given above, what combination of the front-surface electrodes (corresponding to
the segment signals) and the rear-surface electrodes (corresponding to the common signals) forms display
patterns in the LCD display data memory, and write the bit data that corresponds to the desired display
pattern on a one-to-one basis.
LCD display data memory bits 4 to 7 are fixed to 0.
(3) Output waveforms of common and segment signals
When both common and segment signals are at the select voltage, a display-on voltage of ±VLCD is obtained.
The other combinations of the signals correspond to the display-off voltage.
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Figure 10-7 shows the common signal waveforms, and Figure 10-8 shows the voltages and phases of the common
and segment signals.
Figure 10-7. Common Signal Waveforms
TF = 4 × T
COMn
(Four-time-slice mode)
VLC0
VLCD
VLC1
VLC2
VSS
T: One LCD clock cycle TF: Frame frequency
Figure 10-8. Voltages and Phases of Common and Segment Signals
Select Deselect
Common signal
Segment signal
VLC0
VSS
VLCD
VLC0
VSS
VLCD
TT
VLC2
VLC2
VLC1
VLC1
T: One LCD clock cycle
CHAPTER 10 LCD CONTROLLER/DRIVER
User’s Manual U15552EJ2V2UD 149
10.7 Display Modes
10.7.1 Four-time-slice display example
Figure 10-10 shows how the 11-digit LCD panel having the display pattern shown in Figure 10-9 is connected to
the segment signals (S0 to S21) and the common signals (COM0 to COM3) of the
µ
PD789467 Subseries chip. This
example displays data “23456.789012” in the LCD panel. The contents of the display data memory (addresses
FA00H to FA15H) correspond to this display.
The following description focuses on numeral “6.” ( ) displayed in the seventh digit from the right. To display “6.”
in the LCD panel, it is necessary to apply the select or deselect voltage to the S12 and S13 pins according to Table
10-5 at the timing of the common signals COM0 to COM3.
Table 10-5. Select and Deselect Voltages (COM0 to COM3)
Segment
Common
S12 S13
COM0 Select Select
COM1 Deselect Select
COM2 Select Select
COM3 Select Select
According to Table 10-5, it is determined that the display data memory location (FA0CH) that corresponds to S12
must contain 1101.
Figure 10-11 shows examples of LCD drive waveforms between the S12 signal and each common signal. When
the select voltage is applied to S12 at the timing of COM0, an alternate rectangle waveform, +VLCD/–VLCD, is
generated to turn on the corresponding LCD segment.
Figure 10-9. Four-Time-Slice LCD Display Pattern and Electrode Connections
Remark n = 0 to 10
;;
;;
;;
;;
;
;
;;
;;
COM0
S
2n
COM1
S
2n+1
COM2
COM3
CHAPTER 10 LCD CONTROLLER/DRIVER
150 User’s Manual U15552EJ2V2UD
Figure 10-10. Example of Connecting Four-Time-Slice LCD Panel
0101101111111111110001
1111111010011111010111
1001010111011101110110
1010001011001000100010
Bit 0
Bit 1
Bit 2
Bit 3
Timing strobe
Data memory address
LCD panel
FA00H
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
FA10H
1
2
3
4
5
S 0
S 1
S 2
S 3
S 4
S 5
S 6
S 7
S 8
S 9
S 10
S 11
S 12
S 13
S 14
S 15
S 16
S 17
S 18
S 19
S 20
S 21
COM 3
COM 2
COM 1
COM 0
CHAPTER 10 LCD CONTROLLER/DRIVER
User’s Manual U15552EJ2V2UD 151
Figure 10-11. Examples of Four-Time-Slice LCD Drive Waveform
T
F
V
LC0
V
LC2
COM0
+V
LCD
0
COM0-S12
−V
LCD
V
LC1
+1/3V
LCD
−1/3V
LCD
V
SS
V
LC0
V
LC2
COM1 V
LC1
V
SS
V
LC0
V
LC2
COM2 V
LC1
V
SS
V
LC0
V
LC2
COM3 V
LC1
V
SS
+V
LCD
0
COM1-S12
−V
LCD
+1/3V
LCD
−1/3V
LCD
V
LC0
V
LC2
S12 V
LC1
V
SS
Remark The waveforms of COM2-S12 and COM3-S12 are not shown above.
CHAPTER 10 LCD CONTROLLER/DRIVER
152 User’s Manual U15552EJ2V2UD
10.8 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2
The
µ
PD789467 Subseries contains a booster circuit (×3 only) to generate a supply voltage to drive the LCD. The
internal LCD reference voltage is output from the VLC2 pin. A voltage two times higher than that on VLC2 is output from
the VLC1 pin and a voltage three times higher than that on VLC2 is output from the VLC0 pin.
The LCD reference voltage (VLC2) can be selected by setting LCD voltage boost control register 0 (LCDVA0).
The
µ
PD789467 Subseries requires an external capacitor (recommended value: 0.47
µ
F) because it employs a
capacitance division method to generate the supply voltage to drive the LCD.
Table 10-6. Output Voltages of VLC0 to VLC2 Pins
LCDVA0
LCD driving power supply pin
GAIN = 0 GAIN = 1
VLC0 4.5 V 3.0 V
VLC1 3.0 V 2.0 V
VLC2 (LCD reference voltage) 1.5 V 1.0 V
Cautions 1. When using the LCD function, do not leave the VLC0, VLC1, and VLC2 pins open. Refer to
Figure 10-12 for connection.
2. The power for the LCD drive is supplied separately from the
µ
PD789467 Subseries;
therefore, a constant voltage can be supplied regardless of the change of VDD.
Figure 10-12. Example of Pin Connection for LCD Driver
V
LC0
V
LC1
V
LC2
C2 C3 C4
CAPH
C1
External Pin
C1 = C2 = C3 = C4 = 0.47 F
CAPL
µ
Remark Use capacitors with as little leakage as possible. Use a non-polar capacitor for C1.
User’s Manual U15552EJ2V2UD 153
CHAPTER 11 POWER-ON-CLEAR CIRCUIT
The
µ
PD789467 Subseries provides a power-on-clear (POC) circuit. In the flash memory version (
µ
PD78F9468),
the POC circuit is always operating. However, it can only be used when selected by a mask option in mask ROM
versions (
µ
PD789462, 789464, 789466, and 789467) (see CHAPTER 16 MASK OPTION).
11.1 Functions of Power-on-Clear Circuit
The power-on-clear circuit includes the following functions.
• Compares the detection voltage (VPOC) with the power supply voltage (VDD) and generates an internal reset
signal if VDD < VPOC.
• Can operate even in STOP mode.
11.2 Configuration of Power-on-Clear Circuit
Figure 11-1 shows the block diagram of the power-on-clear circuit.
Figure 11-1. Block Diagram of Power-on-Clear Circuit
−
+
Detection
voltage
source (V
POC
)
V
DD
V
DD
Internal reset signal
CHAPTER 11 POWER-ON-CLEAR CIRCUITS
User’s Manual U15552EJ2V2UD
154
11.3 Power-on-Clear Circuit Operation
The POC circuit compares the detection voltage (VPOC) with the power supply voltage (VDD) and generates an
internal reset signal if VDD < VPOC.
Figure 11-2. Timing of Internal Reset Signal Generation of POC Circuit
Power supply voltage (V
DD
)
Detection voltage (V
POC
)
1.8 V Time
Internal reset
signal
User’s Manual U15552EJ2V2UD 155
CHAPTER 12 INTERRUPT FUNCTION
12.1 Interrupt Types
The following two types of interrupts are used.
(1) Non-maskable interrupt
This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top
priority over all other interrupt requests.
A standby release signal is generated.
One interrupt source from the watchdog timer is incorporated as a non-maskable interrupt.
(2) Maskable interrupt
This interrupt undergoes mask control. If two or more interrupts with the same priority are simultaneously
generated, each interrupt is serviced according to a predetermined priority as shown in Table 12-1.
A standby release signal is generated.
Two external and six internal interrupt sources are incorporated as maskable interrupts.
12.2 Interrupt Sources and Configuration
A total of nine non-maskable and maskable interrupts are incorporated as interrupt sources (see Table
12-1).
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156 User’s Manual U15552EJ2V2UD
Table 12-1. Interrupt Source List
Interrupt Source Interrupt Type PriorityNote 1
Name Trigger
Internal/
External
Vector Table
Address
Basic
Configuration
TypeNote 2
Non-maskable − INTWDT Watchdog timer overflow (with
watchdog timer mode 1 selected)
(A)
0 INTWDT Watchdog timer overflow (with
interval timer mode selected)
Internal 0004H
(B)
1 INTP0 Pin input edge detection External 0006H (C)
2 INTAD0 A/D conversion completion signal 0008H
3 INTWT Watch timer interrupt 000AH
4 INTTM30 Generation of 8-bit timer 30 match
signal
000CH
5 INTTM40 Generation of 8-bit timer 40 match
signal
Internal
000EH
(B)
6 INTKR00 Key return signal detection External 0010H (C)
Maskable
7 INTWTI Watch timer interval timer
interrupt
Internal 0012H (B)
Notes 1. “Priority” is the priority order when more than one maskable interrupt request is generated at the same
time. 0 is the highest priority and 7 is the lowest.
2. Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in Figure 12-1.
Remark There are two interrupt sources for the watchdog timer (INTWDT): non-maskable and maskable
interrupts (internal). Either one (but not both) should be selected for actual use.
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User’s Manual U15552EJ2V2UD 157
Figure 12-1. Basic Configuration of Interrupt Function
(A) Internal non-maskable interrupt
Internal bus
Interrupt request Vector table
address generator
Standby release signal
(B) Internal maskable interrupt
MK
IF
IE
Internal bus
Interrupt request
Vector table
address generator
Standby release signal
(C) External maskable interrupt
MK
IF
IE
Internal bus
INTM0, KRM00
Interrupt
request
Edge
detector
Vector table
address generator
Standby
release signal
INTP0: External interrupt mode register 0
KRM00: Key return mode register 00
IF: Interrupt request flag
IE: Interrupt enable flag
MK: Interrupt mask flag
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12.3 Registers Controlling Interrupt Function
The following five registers are used to control the interrupt function.
• Interrupt request flag register 0 (IF0)
• Interrupt mask flag register 0 (MK0)
• External interrupt mode register 0 (INTM0)
• Program status word (PSW)
• Key return mode register 00 (KRM00)
Table 12-2 gives a listing of interrupt request and interrupt mask flag names corresponding to interrupt requests.
Table 12-2. Flags Corresponding to Interrupt Request Signal Names
Interrupt Request Signal Name Interrupt Request Flag Interrupt Mask Flag
INTWDT
INTP0
INTAD0
INTWT
INTTM30
INTTM40
INTKR00
INTWTI
WDTIF
PIF0
ADIF0
WTIF
TMIF30
TMIF40
KRIF00
WTIIF
WDTMK
PMK0
ADMK0
WTMK
TMMK30
TMMK40
KRMK00
WTIMK
CHAPTER 12 INTERRUPT FUNCTION
User’s Manual U15552EJ2V2UD 159
(1) Interrupt request flag register 0 (IF0)
An interrupt request flag is set (1) when the corresponding interrupt request is generated, or when an
instruction is executed. It is cleared (0) when the interrupt request is acknowledged, when the RESET signal
is input, or when an instruction is executed.
IF0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets IF0 to 00H.
Figure 12-2. Format of Interrupt Request Flag Register 0
Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address After reset R/W
IF0 WTIIF KRIF00 TMIF40 TMIF30 WTIF ADIF0 PIF0 WDTIF FFE0H 00H R/W
××IF× Interrupt request flag
0 No interrupt request signal generated
1 An interrupt request signal is generated and an interrupt request made
Cautions 1. The WDTIF flag can be read/written only when the watchdog timer is being used as an
interval timer. It must be cleared to 0 if the watchdog timer is used in watchdog timer
mode 1 or 2.
2. Because P61 functions alternately as an external interrupt input, when the output level
changes after the output mode of the port function is specified, the interrupt request
flag will be inadvertently set. Therefore, be sure to preset the interrupt mask flag
(PMK0) to 1 before using the port in output mode.
3. When an interrupt is acknowledged, the interrupt request flag is automatically cleared
and then the interrupt routine is started.
(2) Interrupt mask flag register 0 (MK0)
Interrupt mask flags are used to enable and disable the corresponding maskable interrupts.
MK0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets MK0 to FFH.
Figure 12-3. Format of Interrupt Mask Flag Register 0
Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address After reset R/W
MK0 WTIMK KRMK00 TMMK40 TMMK30 WTMK ADMK0 PMK0 WDTMK FFE4H FFH R/W
××MK Interrupt servicing control
0 Interrupt servicing enabled
1 Interrupt servicing disabled
Cautions 1. When the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to
read the WDTMK flag results in an undefined value being detected.
2. Because P61 functions alternately as an external interrupt input, when the output level
changes after the output mode of the port function is specified, the interrupt request
flag will be inadvertently set. Therefore, be sure to preset the interrupt mask flag
(PMK0) to 1 before using the port in output mode.
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(3) External interrupt mode register 0 (INTM0)
INTM0 is used to specify the valid edge for INTP0.
INTM0 is set with an 8-bit memory manipulation instruction.
RESET input sets INTM0 to 00H.
Figure 12-4. Format of External Interrupt Mode Register 0
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
INTM0 0 0 0 0 ES01 ES00 0 0 FFECH 00H R/W
ES01 ES00 INTP0 valid edge selection
0 0 Falling edge
0 1 Rising edge
1 0 Setting prohibited
1 1 Both rising and falling edges
Cautions 1. Bits 0, 1, and 4 to 7 must be set to 0.
2. Before setting INTM0, set (1) the interrupt mask flag (PMK0) to disable interrupts.
To enable interrupts, clear (0) the interrupt request flag (PIF0), then clear (0) the
interrupt mask flag (PMK0).
(4) Program status word (PSW)
The program status word is a register used to hold the instruction execution result and the current status for
interrupt requests. The IE flag, used to set maskable interrupt enable/disable, is mapped to the PSW.
Besides 8-bit unit read/write, this register can carry out operations via bit manipulation instructions and
dedicated instructions (EI, DI). When a vectored interrupt is acknowledged, the PSW is automatically saved
into a stack, and the IE flag is reset to 0.
RESET input sets the PSW to 02H.
Figure 12-5. Configuration of Program Status Word
IE Z 0 AC 0 0 1 CYPSW
76543210
IE
0
1
02H
Symbol After reset
Used when normal instruction is executed
Interrupt acknowledgment enable/disable
Disabled
Enabled
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User’s Manual U15552EJ2V2UD 161
(5) Key return mode register 00 (KRM00)
KRM00 sets the pin that detects a key return signal (falling edge of port 4).
KRM00 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets KRM00 to 00H.
Figure 12-6. Format of Key Return Mode Register 00
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
KRM00 0 0 0 0 0 0 0 KRM000 FFF5H 00H R/W
KRM000 Key return signal detection control
0 No detection
1 Detection (detecting falling edge of port 4)
Cautions 1. Bits 1 to 7 must be set to 0.
2. Before setting KRM00, always set bit 6 of MK0 (KRMK00 = 1) to disable interrupts. After
setting KRM00, clear KRMK00 after clearing bit 6 of IF0 (KRIF00 = 0) to enable interrupts.
3. On-chip pull-up resistors are automatically connected in input mode to the pins
specified for key return signal detection (P40 to P43). Although these resistors are
disconnected when the mode changes to output, rising edge detection continues
unchanged. Therefore, when the output data of the pin falls, an interrupt (INTKR00)
occurs.
4. The key return signal can be detected while all of P40 to P43 are high level. The key
return signal cannot be detected while even one of P40 to P43 is low, even if the falling
edge of another key return pin is detected.
Figure 12-7. Block Diagram of Falling Edge Detector
P40/KR00
P41/KR01
P42/KR02
P43/KR03
Falling edge detector
KRMK00
INTKR00
Standby release
signal
Key return mode register 00 (KRM00)
Note
Selector
Note Selector that selects the pin used for falling edge input
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12.4 Interrupt Servicing Operation
12.4.1 Non-maskable interrupt request acknowledgment operation
A non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not
subject to interrupt priority control and takes precedence over all other interrupts.
When a non-maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order,
the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.
Figure 12-8 shows the flow from non-maskable interrupt request generation to acknowledgment, Figure 12-9
shows the timing of non-maskable interrupt acknowledgment, and Figure 12-10 shows the acknowledgment operation
when a number of non-maskable interrupts are generated.
Caution During non-maskable interrupt service program execution, do not input another non-maskable
interrupt request; if it is input, the service program will be interrupted and the new non-
maskable interrupt request will be acknowledged.
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User’s Manual U15552EJ2V2UD 163
Figure 12-8. Flow from Generation of Non-Maskable Interrupt Request to Acknowledgment
Start
WDTM4 = 1
(watchdog timer mode
is selected)
Interval timer
No
WDT
overflows
No
Yes
Reset processing
No
Yes
Yes
Interrupt request is generated
Interrupt servicing starts
WDTM3 = 0
(non-maskable interrupt
is selected)
WDTM: Watchdog timer mode register
WDT: Watchdog timer
Figure 12-9. Timing of Non-Maskable Interrupt Request Acknowledgment
Instruction Instruction
Save PSW and PC, and
jump to interrupt servicing Interrupt servicing program
CPU processing
WDTIF
Figure 12-10. Non-Maskable Interrupt Request Acknowledgment
Second interrupt servicing
First interrupt servicing
NMI request
(second)
NMI request
(first)
Main routine
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12.4.2 Maskable interrupt request acknowledgment operation
A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the
corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt
enabled status (when the IE flag is set to 1).
The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown in
Table 12-3.
Refer to Figures 12-12 and 12-13 for the timing of interrupt request acknowledgment.
Table 12-3. Time from Generation of Maskable Interrupt Request to Servicing
Minimum Time Maximum TimeNote
9 clocks 19 clocks
Note The wait time is maximum when an interrupt request is generated immediately before
the BT or BF instruction.
Remark 1 clock: (fCPU: CPU clock)
When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting
from the one assigned the highest priority by the priority specification flag.
A pending interrupt is acknowledged when the status in which it can be acknowledged is set.
Figure 12-11 shows the algorithm of interrupt request acknowledgment.
When a maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order, the IE
flag is reset to 0, the data in the vector table determined for each interrupt request is loaded to the PC, and execution
branches.
To return from interrupt servicing, use the RETI instruction.
Figure 12-11. Interrupt Request Acknowledgment Program Algorithm
Start
xxIF = 1 ?
xxMK = 0 ?
IE = 1 ?
Vectored interrupt
servicing
Yes (Interrupt request generated)
Yes
Yes
No
No
No
Interrupt request pending
Interrupt request pending
xxIF: Interrupt request flag
xxMK: Interrupt mask flag
IE: Flag to control maskable interrupt request acknowledgment (1 = Enabled, 0 = Disabled)
1
fCPU
CHAPTER 12 INTERRUPT FUNCTION
User’s Manual U15552EJ2V2UD 165
Figure 12-12. Interrupt Request Acknowledgment Timing (Example: MOV A, r)
Clock
CPU MOV A, r
Save PSW and PC, and
jump to interrupt servicing
8 clocks
Interrupt servicing program
Interrupt
If the interrupt request has generated an interrupt request flag (XXIF) by the time the instruction clocks under
execution, n clocks (n = 4 to 10), are n − 1, interrupt request acknowledgment processing will start following the
completion of the instruction under execution. Figure 12-12 shows an example using the 8-bit data transfer instruction
MOV A, r. Because this instruction is executed in 4 clocks, if an interrupt request is generated between the start of
execution and the 3rd clock, interrupt request acknowledgment processing will take place following the completion of
MOV A, r.
Figure 12-13. Interrupt Request Acknowledgment Timing
(When Interrupt Request Flag Is Generated in Final Clock Under Execution)
Clock
CPU NOP MOV A, r Save PSW and PC, and
jump to interrupt servicing
Interrupt servicing
program
Interrupt
8 clocks
If the interrupt request flag (XXIF) is generated in the final clock of the instruction, interrupt request
acknowledgment processing will begin after execution of the next instruction is complete.
Figure 12-13 shows an example whereby an interrupt request was generated in the 2nd clock of NOP (a 2-clock
instruction). In this case, the interrupt request will be serviced after execution of MOV A, r, which follows NOP, is
complete.
Caution When interrupt request flag register 0 (IF0) or interrupt mask flag register 0 (MK0) is being
accessed, interrupt requests will be held pending.
12.4.3 Multiple interrupt servicing
Multiple interrupt servicing, in which another interrupt request is acknowledged while an interrupt request being
serviced, can be executed using the priority order. If multiple interrupts are generated at the same time, they are
serviced in the order according to the priority assigned to each interrupt request in advance (refer to Table 12-1).
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166 User’s Manual U15552EJ2V2UD
Figure 12-14. Example of Multiple Interrupt Servicing
Example 1. Acknowledging multiple interrupts
INTyy
EI
Main servicing
EI
INTyy servicingINTxx servicing
RETI
IE = 0
INTxx
RETI
IE = 0
The interrupt request INTyy is acknowledged during the servicing of interrupt INTxx and multiple interrupt servicing
is performed. Before each interrupt request is acknowledged, the EI instruction is issued and interrupt requests are
enabled.
Example 2. Multiple interrupt servicing is not performed because interrupts are disabled
INTyy
EI
Main servicing
RETI
INTyy servicingINTxx servicing
IE = 0
INTxx
RETI
INTyy is held pending
IE = 0
Because interrupt requests are disabled (the EI instruction has not been issued) in the interrupt INTxx servicing,
the interrupt request INTyy is not acknowledged and multiple interrupt servicing is not performed. INTyy is held
pending and is acknowledged after INTxx servicing is completed.
IE = 0: Interrupt requests disabled
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12.4.4 Putting interrupt requests on hold
If an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type
of instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed. Such
instructions (interrupt request pending instructions) are as follows.
• Instructions that manipulate interrupt request flag register 0 (IF0)
• Instructions that manipulate interrupt mask flag register 0 (MK0)
168 User’s Manual U15552EJ2V2UD
CHAPTER 13 STANDBY FUNCTION
13.1 Standby Function and Configuration
13.1.1 Standby function
The standby function is used to reduce the power consumption of the system and can be effected in the following
two modes.
(1) HALT mode
This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the
CPU. The system clock oscillator continues oscillating. This mode does not reduce the power consumption
as much as the STOP mode, but is useful for resuming processing immediately when an interrupt request is
generated, or for intermittent operations.
(2) STOP mode
This mode is set when the STOP instruction is executed. The STOP mode stops the main system clock
oscillator and stops the entire system. The power consumption of the CPU can be substantially reduced in
this mode.
The data memory can be retained at a low voltage (VDD = 1.8 V). Therefore, this mode is useful for retaining
the contents of the data memory at an extremely low current.
The STOP mode can be released by an interrupt request, so this mode can be used for intermittent operation.
However, some time is required until the system clock oscillator stabilizes after the STOP mode has been
released. If processing must be resumed immediately by using an interrupt request, therefore, use the HALT
mode.
In both modes, the previous contents of the registers, flags, and data memory before setting the standby mode are
all retained. In addition, the statuses of the output latch of the I/O ports and output buffer are also retained.
Caution Be sure to stop the operations of the peripheral hardware before executing the STOP instruction.
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User’s Manual U15552EJ2V2UD 169
13.1.2 Register controlling standby function
The wait time after the STOP mode is released upon interrupt request until oscillation stabilizes is controlled with
the oscillation stabilization time selection register (OSTS).
OSTS is set with an 8-bit or 1-bit memory manipulation instruction.
RESET input sets OSTS to 04H. Note that the time required for oscillation to stabilize after RESET input is 215/fX,
independent of OSTS.
Figure 13-1. Format of Oscillation Stabilization Time Selection Register
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 FFFAH 04H R/W
OSTS2 OSTS1 OSTS0
0 0 0 212/fX (819
µ
s)
0 1 0 215/fX (6.55 ms)
1 0 0 217/fX (26.2 ms)
Other than above Setting prohibited
Caution The wait time after the STOP mode is released does not include the time from STOP mode
release to clock oscillation start (“a” in the figure below), regardless of whether STOP
mode is released by RESET input or by interrupt generation.
a
STOP mode release
X1 pin voltage
waveform
Remarks 1. f
X: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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13.2 Standby Function Operation
13.2.1 HALT mode
(1) HALT mode
The HALT mode is set by executing the HALT instruction.
The operation statuses in the HALT mode are shown in the following table.
Table 13-1. Operation Statuses in HALT Mode
HALT Mode Operation Status During Main
System Clock Operation
HALT Mode Operation Status During Subsystem
Clock Operation
Item
Subsystem Clock
Operating
Subsystem Clock
Stopped
Main System Clock
Operating
Main System Clock
Stopped
Main system clock Can be oscillated Oscillation stopped
CPU Operation stopped
Ports (output latches) Status before HALT mode setting retained
8-bit timer 30, 40 Operable Operation stopped
Watch timer Operable OperableNote 1 Operable OperableNote 2
Watchdog timer Operable Operation stopped
Power-on-clear circuit Operable
Key return circuit OperableNote 3
A/D converter Operable Operation stopped
LCD controller/driver OperableNote 4 OperableNotes 1, 4 OperableNote 4 OperableNotes 2, 4
External interrupts OperableNote 3
Notes 1. Operation is enabled when the main system clock is selected
2. Operation is enabled when the subsystem clock is selected
3. Operation is enabled only for a maskable interrupt that is not masked
4. The HALT instruction can be set after display instruction execution
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(2) Releasing HALT mode
The HALT mode can be released by the following three sources.
(a) Releasing by unmasked interrupt request
The HALT mode is released by an unmasked interrupt request. In this case, if interrupts are enabled to
be acknowledged, vectored interrupt servicing is performed. If interrupts are disabled, the instruction at
the next address is executed.
Figure 13-2. Releasing HALT Mode by Interrupt
HALT
instruction
Standby
release signal
Wait
WaitHALT mode
Operation
mode Operation mode
Clock Oscillation
Remarks 1. The broken lines indicate the case where the interrupt request that has released the standby mode
is acknowledged.
2. The wait time is as follows:
• When vectored interrupt servicing is performed: 9 to 10 clocks
• When vectored interrupt servicing is not performed: 1 to 2 clocks
(b) Releasing by non-maskable interrupt request
The HALT mode is released regardless of whether interrupts are enabled or disabled, and vectored
interrupt servicing is performed.
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(c) Releasing by RESET input
When the HALT mode is released by the RESET signal, execution branches to the reset vector address
in the same manner as the ordinary reset operation, and program execution is started.
Figure 13-3. Releasing HALT Mode by RESET Input
HALT
instruction
RESET
signal
Wait
Note
Reset
period
HALT mode
Operation
mode
Oscillation
stabilization
wait status
Clock
Operation
mode
Oscillation
stops
Oscillation Oscillation
Note 2
15/fX: 6.55 ms (@ fX = 5.0 MHz operation)
Remark f
X: Main system clock oscillation frequency
Table 13-2. Operation After Releasing HALT Mode
Releasing Source MK×× IE Operation
0 0 Next address instruction is executed
0 1 Interrupt servicing is executed
Maskable interrupt request
1 × HALT mode is retained
Non-maskable interrupt request − × Interrupt servicing is executed
RESET input -−- − Reset processing is executed
×: Don’t care
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13.2.2 STOP mode
(1) STOP mode
The STOP mode is set by executing the STOP instruction.
Caution Because the standby mode can be released by an interrupt request signal, the standby
mode is released as soon as it is set if there is an interrupt source whose interrupt request
flag is set and interrupt mask flag is reset. When the STOP mode is set, therefore, the
HALT mode is set immediately after the STOP instruction has been executed, the wait time
set by the oscillation stabilization time selection register (OSTS) elapses, and then the
operation mode is set.
The operation statuses in the STOP mode are shown in the following table.
Table 13-3. Operation Statuses in STOP Mode
STOP Mode Operation Status During Main System Clock Operation Item
Subsystem Clock Operating Subsystem Clock Stopped
Main system clock Oscillation stopped
CPU Operation stopped
Ports (output latches) Status before STOP mode setting retained
8-bit timer 30, 40 Operation stopped
Watch timer OperableNote 1 Operation stopped
Watchdog timer Operation stopped
Power-on-clear circuit Operable
Key return circuit OperableNote 2
A/D converter Operation stopped
LCD controller/driver OperableNote 1 Operation stoppedNote 3
External interrupts OperableNote 2
Notes 1. Operation is enabled when the subsystem clock is selected.
2. Operation is enabled only for a maskable interrupt that is not masked
3. Before setting the STOP mode, disable display and select the static mode (refer to 10.3 (1) LCD display
mode register 0 (LCDM0)).
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(2) Releasing STOP mode
The STOP mode can be released by the following two sources.
(a) Releasing by unmasked interrupt request
The STOP mode can be released by an unmasked interrupt request. In this case, if interrupts are
enabled to be acknowledged, vectored interrupt servicing is performed, after the oscillation stabilization
time has elapsed. If interrupts are disabled, the instruction at the next address is executed.
Figure 13-4. Releasing STOP Mode by Interrupt
STOP
instruction
Standby
release signal
Wait
(set time by OSTS)
STOP mode
Operation
mode
Oscillation stabilization
wait status
Clock
Operation
mode
Oscillation
stops Oscillation
Oscillation
Remark The broken line indicates the case where the interrupt request that has released the standby mode is
acknowledged.
CHAPTER 13 STANDBY FUNCTION
User’s Manual U15552EJ2V2UD 175
(b) Releasing by RESET input
When the STOP mode is released by the RESET signal, the reset operation is performed after the
oscillation stabilization time has elapsed.
Figure 13-5. Releasing STOP Mode by RESET Input
STOP
instruction
RESET
signal
WaitNote
STOP mode
Operation
mode
Oscillation
stabilization
wait status
Clock
Operation
mode
Oscillation
stops Oscillation
Oscillation
Reset
period
Note 2
15/fX: 6.55 ms (@ fX = 5.0 MHz operation)
Remark f
X: Main system clock oscillation frequency
Table 13-4. Operation After Releasing STOP Mode
Releasing Source MK×× IE Operation
Maskable interrupt request 0 0 Next address instruction is executed
0 1 Interrupt servicing is executed
1
× STOP mode is retained
RESET input − -−- Reset processing is executed
×: Don’t care
176 User’s Manual U15552EJ2V2UD
CHAPTER 14 RESET FUNCTION
The following three operations are available to generate reset signals.
(1) External reset signal input via RESET pin
(2) Internal reset by detection of watchdog timer program loop time
(3) Internal reset using power-on-clear circuit (POC)
The external and internal reset signals are functionally equivalent. When RESET is input, program execution
begins from the addresses written at 0000H and 0001H.
If a low-level signal is applied to the RESET pin, or if the watchdog timer overflows, a reset occurs, causing each
item of the hardware to enter the states listed in Table 14-1. While a reset is being applied, or while the oscillation
frequency is stabilizing immediately after the end of a reset sequence, each pin remains in the high-impedance state.
If a high-level signal is applied to the RESET pin, the reset sequence is terminated, and program execution is
started after the oscillation stabilization time has elapsed. A reset sequence caused by a watchdog timer overflow is
terminated automatically and program execution is started after the oscillation stabilization time has elapsed.
Reset by power-on clear (POCNote) is cleared if the supply voltage rises beyond a specific level, and program
execution is started after the oscillation stabilization time has elapsed.
Note Enabled in mask ROM versions (
µ
PD789462, 789464, 789466, and 789467) only when POC circuit usage
is selected by a mask option.
Cautions 1. For an external reset, input a low level for 10
µ
s or more to the RESET pin.
2. When the STOP mode is cleared by reset, the STOP mode contents are held during reset
input. However, the port pins become high impedance.
Figure 14-1. Block Diagram of Reset Function
RESET
Interrupt function
Count clock
Reset controller
Watchdog timer
Power-on-clear circuitNote
Over-
flow
Reset signal
V
DD
Stop
Note Enabled in mask ROM versions (
µ
PD789462, 789464, 789466, and 789467) only when POC circuit usage
is selected by a mask option.
CHAPTER 14 RESET FUNCTION
User’s Manual U15552EJ2V2UD 177
Figure 14-2. Reset Timing by RESET Input
X1
RESET
Internal
reset signal
Port pin
During normal
operation
Delay Delay
Hi-Z
Reset period
(oscillation stops)
Normal operation
(reset processing)
Oscillation
stabilization
time wait
Figure 14-3. Reset Timing by Overflow in Watchdog Timer
X1
Overflow in
watchdog timer
Internal
reset signal
Port pin Hi-Z
During normal
operation
Reset period
(oscillation
continues)
Normal operation
(reset processing)
Oscillation
stabilization
time wait
Figure 14-4. Reset Timing by RESET Input in STOP Mode
X1
RESET
Internal
reset signal
Port pin
Delay Delay
Hi-Z
STOP instruction execution
During normal
operation
Reset period
(oscillation stops)
Stop status
(oscillation stops)
Normal operation
(reset processing)
Oscillation
stabilization
time wait
CHAPTER 14 RESET FUNCTION
178 User’s Manual U15552EJ2V2UD
Figure 14-5. Reset Timing by Power-on Clear
(a) At power application
Hi-Z
Port pin
Reset period
(oscillation stops)
Oscillation stabilization
time wait
Normal operation
(reset processing)
X1
V
DD
Internal reset
signal
Power-on-clear voltage (V
POC
)
(b) In STOP mode
Hi-Z
Normal operation
Port pin
Reset period
(oscillation stops)
Stop status
(oscillation stops)
Oscillation stabilization
time wait
Normal operation
(reset processing)
X1
VDD
Internal reset
signal
Power-on-clear voltage (V
POC
)
STOP instruction execution
(c) In normal operation mode (including HALT mode)
Hi-Z
Normal operation
Port pin
Reset period
(oscillation stops)
Oscillation stabilization
time wait
Normal operation
(reset processing)
X1
V
DD
Internal reset
signal
Power-on-clear voltage (V
POC
)
CHAPTER 14 RESET FUNCTION
User’s Manual U15552EJ2V2UD 179
Table 14-1. Hardware Status After Reset
Hardware Status After Reset
Program counter (PC)Note 1 Contents of reset
vector table (0000H,
0001H) set
Stack pointer (SP) Undefined
Program status word (PSW) 02H
Data memory UndefinedNote 2 RAM
General-purpose registers UndefinedNote 2
Ports (P0, P1, P4, P6) (output latches) 00H
Port mode registers (PM0, PM1, PM4, PM6) FFH
Port function register 8 (PF8) 00H
Pull-up resistor option register 0 (PU0) 00H
Processor clock control register (PCC) 02H
Suboscillation mode register (SCKM) 00H
Subclock control register (CSS) 00H
Oscillation stabilization time selection register (OSTS) 04H
Timer counters (TM30, TM40) 00H
Compare registers (CR30, CR40, CRH40) Undefined
Mode control registers (TMC30, TMC40) 00H
8-bit timer 30, 40
Carrier generator output control register (TCA40) 00H
Watch timer Mode control register (WTM) 00H
Mode register (WDTM) 00H Watchdog timer
Clock selection register (TCL2) 00H
Mode register 0 (ADM0) 00H
Input selection register 0 (ADS0) 00H
A/D converter
Conversion result register 0 (ADCR0) Undefined
Display mode register 0 (LCDM0) 00HNote 3
Clock control register 0 (LCDC0) 00H
LCD controller/driver
Voltage boost control register 0 (LCDVA0) 00H
Request flag register 0 (IF0) 00H
Mask flag register 0 (MK0) FFH
External interrupt mode register 0 (INTM0) 00H
Interrupts
Key return mode register 00 (KRM00) 00H
Notes 1. While a reset signal is being input, and during the oscillation stabilization time wait, only the contents of
the PC will be undefined; the remainder of the hardware will be the same state as after reset.
2. In standby mode, RAM enters the hold state after reset.
3. Bit 2 (LCDM02) must be set to 1 after reset.
180 User’s Manual U15552EJ2V2UD
CHAPTER 15
µ
PD78F9468
The
µ
PD78F9468 is available as the flash memory version of the
µ
PD789467 Subseries.
The
µ
PD78F9468 is a version with the internal ROM of the
µ
PD789462, 789464, 789466, 789467 replaced with
flash memory. The differences between the
µ
PD78F9468 and the mask ROM versions are shown in Table 15-1.
Table 15-1. Differences Between
µ
PD78F9468 and Mask ROM Versions
Flash Memory
Version
Mask ROM Version Part Number
Item
µ
PD78F9468
µ
PD789462
µ
PD789464
µ
PD789466
µ
PD789467
ROM 32 KB
(flash memory)
4 KB 8 KB 16 KB 24 KB
High-speed RAM 512 bytes 256 bytes 512 bytes
Internal
memory
LCD display RAM 23 × 4 bits
LCD controller/driver Refer to Table 15-2 Differences in LCD Controller/Driver of
µ
PD78F9468 and Mask ROM
Version.
Power-on-clear (POC)
circuit
Always
operating
Enable/disable is selected by a mask option.
IC0 pin Not provided Provided
VPP pin Provided Not provided
Electrical specifications Refer to CHAPTER 18 ELECTRICAL SPECIFICATIONS.
Caution There are differences in noise immunity and noise radiation between the flash memory and mask
ROM versions. When pre-producing an application set with the flash memory version and then
mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the
commercial samples (not engineering samples) of the mask ROM version.
CHAPTER 15
µ
PD78F9468
User’s Manual U15552EJ2V2UD 181
The
µ
PD78F9468 and mask ROM version differ in the on-chip LCD controller/driver macro. The differences in the
LCD controller/driver of
µ
PD78F9468 and mask ROM version is shown in Table 15-2.
Table 15-2. Differences in LCD Controller/Driver of
µ
PD78F9468 and Mask ROM Version
Item Flash Memory Version (
µ
PD78F9468) Mask ROM Version
Output of pins COM0 to COM3
after reset
Pins COM0 to COM2: GND level output
Pin COM3: VLC0 level output
Pins COM0 to COM3: GND level output
Bit 4 (LIPS0) of LCD display
mode register 0 (LCDM0)
Setting is possible, but invalid Valid
Set (LIPS0 = 1) to enable display and clear
(LIPS0 = 0) to disable display.
Output of segment/common pins
when display and voltage booster
disabled
Segment pin: GND level output
Common pin: Two values, VLC0 and GND,
output
Therefore, an abnormal display may occur
even though display is disabled. Select the
static mode (LCDM02 = 1).
Segment pin: GND level output
Common pin: GND level output
Therefore display is disabled.
Operation procedure If a program conforming to the instructions described in 10.4 Setting LCD Controller/Driver
is applied, the same program allows a successful operation both in flash memory and
mask ROM versions.
CHAPTER 15
µ
PD78F9468
182 User’s Manual U15552EJ2V2UD
15.1 Flash Memory Characteristics
Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL-
PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the flash memory mounted on the
target system (on-board write). A flash memory writing adapter (program adapter), which is a target board used
exclusively for programming, is also provided.
Remark FL-PR3, FL-PR4, and the program adapter are products of Naito Densei Machida Mfg. Co., Ltd. (TEL
+81-45-475-4191).
Programming using flash memory has the following advantages.
• Software can be modified after the microcontroller is solder-mounted on the target system.
• Distinguishing software facilities low-quantity, varied model production
• Easy data adjustment when starting mass production
15.1.1 Programming environment
The following shows the environment required for
µ
PD78F9468 flash memory programming.
When Flashpro III (part no. FL-PR3, PG-FP3) or Flashpro IV (Part no. FL-PR4, PG-FP4) is used as a dedicated
flash programmer, a host machine is required to control the dedicated flash programmer. Communication between
the host machine and flash programmer is performed via RS-232C/USB (Rev. 1.1).
For details, refer the manuals for Flashpro III/Flashpro IV.
Remark USB is supported by Flashpro IV only.
Figure 15-1. Environment for Writing Program to Flash Memory
Host machine
RS-232C
USB
Dedicated flash programmer PD78F9468
V
PP
V
DD
V
SS
RESET
3-wire serial I/O
µ
CHAPTER 15
µ
PD78F9468
User’s Manual U15552EJ2V2UD 183
15.1.2 Communication mode
Use the communication mode shown in Table 15-3 to perform communication between the dedicated flash
programmer and
µ
PD78F9468.
Table 15-3. Communication Mode List
TYPE SettingNote 1
CPU Clock
Communication
Mode COMM PORT SIO Clock
In Flashpro On Target
Board
Multiple Rate
Pins Used Number of VPP
Pulses
3-wire serial
I/O
SIO ch-0
(3-wire, sync)
100 Hz to 1.25
MHzNote2
1, 2, 4, or 5
MHzNotes 3, 4
1 to 5 MHzNote 3 1.0 P00, P01, P02 1
Notes 1. Selection items for TYPE settings on the dedicated flash programmer (Flashpro III (part no. FL-PR3,
PG-FP3)/Flashpro IV (Part no. FL-PR4, PG-FP4)).
2. When VDD = 2.7 to 5.5 V. 100 Hz to 312.5 kHz when VDD = 1.8 to 2.7 V.
3. The possible setting range differs depending on the voltage. For details, refer to CHAPTER 18
ELECTRICAL SPECIFICATIONS.
4. When using Flashpro III, only 2 MHz or 4 MHz can be selected.
Caution Be sure to select a communication mode according to the number of VPP pulses shown in Table
15-3.
Figure 15-2. Communication Mode Selection Format
10 V
V
SS
V
DD
V
PP
V
DD
V
SS
RESET
12 n
V
PP
pulses
CHAPTER 15
µ
PD78F9468
184 User’s Manual U15552EJ2V2UD
Figure 15-3. Example of Connection with Dedicated Flash Programmer
VPP1
VDD
RESET
SCK
SO
SI
CLK
Note
GND
V
PP
V
DD
RESET
P00
P02
P01
X1
V
SS
PD78F9468
Dedicated flash programmer
µ
Note Connect this pin when the system clock is supplied by the dedicated flash programmer. If an oscillator is
already connected to the X1 pin, do not connect X1 to the CLK pin.
Caution The VDD pin, if already connected to the power supply, must be connected to the VDD pin of the
dedicated flash programmer. Before using the power supply connected to the VDD pin, supply
voltage before starting programming.
If Flashpro III/Flashpro IV is used as the dedicated flash programmer, the following signals are generated for the
µ
PD78F9468. For details, refer to the manual of Flashpro III/Flashpro IV.
Table 15-4. Pin Connection List
Signal Name I/O Pin Function Pin Name 3-Wire Serial I/O
VPP1 Output Write voltage VPP
VPP2 − − − ×
VDD I/O VDD voltage generation/voltage monitoring VDD Note
GND − Ground VSS
CLK Output Clock output X1
RESET Output Reset signal RESET
SI Input Reception signal P01
SO Output Transmit signal P02
SCK Output Transfer clock P00
HS − − − ×
Note VDD voltage must be supplied before programming is started.
Remark : Pin must be connected.
: If the signal is supplied on the target board, pin does not need to be connected.
×: Pin does not need to be connected.
CHAPTER 15
µ
PD78F9468
User’s Manual U15552EJ2V2UD 185
15.1.3 On-board pin processing
When performing programming on the target system, provide a connector on the target system to connect the
dedicated flash programmer.
An on-board function that allows switching between normal operation mode and flash memory programming mode
may be required in some cases.
<VPP pin>
In normal operation mode, input 0 V to the VPP pin. In flash memory programming mode, a write voltage of 10.0
V (TYP.) is supplied to the VPP pin, so perform the following.
(1) Connect a pull-down resistor (RVPP = 10 kΩ) to the VPP pin.
(2) Use the jumper on the board to switch the VPP pin input to either the programmer or directly to GND.
A VPP pin connection example is shown below.
Figure 15-4. VPP Pin Connection Example
PD78F9468
V
PP
Connection pin of dedicated flash programmer
Pull-down resistor (RV
PP
)
µ
<Serial interface pin>
The following shows the pins used by the serial interface.
Serial Interface Pins Used
3-wire serial I/O P00, P01, P02
When connecting the dedicated flash programmer to a serial interface pin that is connected to another device
on-board, signal conflict or abnormal operation of the other device may occur. Care must therefore be taken
with such connections.
CHAPTER 15
µ
PD78F9468
186 User’s Manual U15552EJ2V2UD
(1) Signal conflict
If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to
another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device
or set the other device to the output high impedance status.
Figure 15-5. Signal Conflict (Input Pin of Serial Interface)
Input pin Signal conflict
Connection pin of
dedicated flash
programmer
Other device
Output pin
In the flash memory programming mode, the signal output by another
device and the signal sent by the dedicated flash programmer conflict;
therefore, isolate the signal of the other device.
PD78F9468
µ
(2) Abnormal operation of other device
If the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is
connected to another device (input), a signal is output to the device, and this may cause an abnormal
operation. To prevent this abnormal operation, isolate the connection with the other device or set so that the
signals input to the other device are ignored.
Figure 15-6. Abnormal Operation of Other Device
Pin
Connection pin of
dedicated flash
programmer
Other device
Input pin
If the signal output by the PD78F9468 affects another device in the flash
memory programming mode, isolate the signals of the other device.
Pin
Connection pin of
dedicated flash
programmer
Other device
Input pin
If the signal output by the dedicated flash programmer affects another
device in the flash memory programming mode, isolate the signals of the
other device.
PD78F9468
PD78F9468
µ
µ
µ
CHAPTER 15
µ
PD78F9468
User’s Manual U15552EJ2V2UD 187
<RESET pin>
If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset
signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal
generator.
If the reset signal is input from the user system in the flash memory programming mode, a normal programming
operation cannot be performed. Therefore, do not input reset signals from other than the dedicated flash
programmer.
Figure 15-7. Signal Conflict (Reset Pin)
RESET
Connection pin of
dedicated flash
programmer
Signal conflict
Output pin
The signal output by the reset signal generator and the signal output from
the dedicated flash programmer conflict in the flash memory programming
mode, so isolate the signal of the reset signal generator.
PD78F9468
µ
<Port pins>
When the
µ
PD78F9468 enters the flash memory programming mode, all the pins other than those that
communicate with the flash programmer are in the same status as immediately after reset.
If the external device does not recognize initial statuses such as the output high impedance status, therefore,
connect the external device to VDD or VSS via a resistor.
<Oscillator>
When using the on-board clock, connect X1 and X2 as required in the normal operation mode.
When using the clock output of the flash programmer, connect it directly to X1, disconnecting the main oscillator
on-board, and leave the X2 pin open.
<Power supply>
When using the power supply output of the flash programmer, connect the VDD and VSS pins to VDD and GND
of the flash programmer, respectively.
When using the on-board power supply, connect it as required in the normal operation mode. Because the flash
programmer monitors the voltage, however, VDD of the flash programmer must be connected.
CHAPTER 15
µ
PD78F9468
188 User’s Manual U15552EJ2V2UD
15.1.4 Connection on flash memory writing adapter
The following shows an example of the recommended connection when using the flash memory writing adapter.
Figure 15-8. Wiring Example of Flash Memory Writing Adapter Using 3-Wire Serial I/O Mode
52 51 50 49 48 47 46 45 44 43 42
14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
39
38
37
36
35
34
33
32
31
30
29
12
13
28
27
41 40
25 26
µ
GND
VDD
VDD2 (LVDD)
SI SO SCK CLKOUT RESET VPP RESERVE/HS
WRITER INTERFACE
V
DD
(2.7 to 5.5 V)
GND
PD78F9468
User’s Manual U15552EJ2V2UD 189
CHAPTER 16 MASK OPTION
The mask ROM versions (
µ
PD789462, 789464, 789466, and 789467) have the following mask option.
• Power-on-clear (POC) circuit
Use/non use of the POC circuit can be selected.
<1> POC circuit used
<2> POC circuit not used
Caution The POC circuit always operates in the flash memory version (
µ
PD78F9468).
190 User’s Manual U15552EJ2V2UD
CHAPTER 17 INSTRUCTION SET
This chapter lists the instruction set of the
µ
PD789467 Subseries. For details of the operation and machine
language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E).
17.1 Operation
17.1.1 Operand identifiers and description methods
Operands are described in the “Operands” column of each instruction in accordance with the description method of
the instruction operand identifier (refer to the assembler specifications for details). When there are two or more
description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are keywords and are
described as they are. Each symbol has the following meaning.
• #: Immediate data specification • $: Relative address specification
• !: Absolute address specification • [ ]: Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, $ and [ ] symbols.
For operand register identifiers r and rp, either functional names (X, A, C, etc.) or absolute names (names in
parentheses in the table below: R0, R1, R2, etc.) can be used for description.
Table 17-1. Operand Identifiers and Description Methods
Identifier Description Method
r
rp
sfr
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special-function register symbol
saddr
saddrp
FE20H to FF1FH Immediate data or labels
FE20H to FF1FH Immediate data or labels (even addresses only)
addr16
addr5
0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)
0040H to 007FH Immediate data or labels (even addresses only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
Remark See Table 3-3 Special-Function Registers for symbols of special-function registers.
CHAPTER 17 INSTRUCTION SET
User’s Manual U15552EJ2V2UD 191
17.1.2 Description of “Operation” column
A: A register; 8-bit accumulator
X: X register
B: B register
C: C register
D: D register
E: E register
H: H register
L: L register
AX: AX register pair; 16-bit accumulator
BC: BC register pair
DE: DE register pair
HL: HL register pair
PC: Program counter
SP: Stack pointer
PSW: Program status word
CY: Carry flag
AC: Auxiliary carry flag
Z: Zero flag
IE: Interrupt request enable flag
NMIS: Flag indicating non-maskable interrupt servicing in progress
( ): Memory contents indicated by address or register contents in parentheses
XH, XL: Higher 8 bits and lower 8 bits of 16-bit register
∧: Logical product (AND)
∨: Logical sum (OR)
V: Exclusive logical sum (exclusive OR)
: Inverted data
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)
17.1.3 Description of “Flag” column
(Blank): Unchanged
0: Cleared to 0
1: Set to 1
x: Set/cleared according to the result
R: Previously saved value is restored
CHAPTER 17 INSTRUCTION SET
192 User’s Manual U15552EJ2V2UD
17.2 Operation List
Mnemonic Operands Bytes Clocks Operation Flag
ZACCY
r, #byte 3 6 r ← byte
saddr, #byte 3 6 (saddr) ← byte
sfr, #byte 3 6 sfr ← byte
A, r Note 1 2 4 A ← r
r, A Note 1 2 4 r ← A
A, saddr 2 4 A ← (saddr)
saddr, A 2 4 (saddr) ← A
A, sfr 2 4 A ← sfr
sfr, A 2 4 sfr ← A
A, !addr16 3 8 A ← (addr16)
!addr16, A 3 8 (addr16) ← A
PSW, #byte 3 6 PSW ← byte x x x
A, PSW 2 4 A ← PSW
PSW, A 2 4 PSW ← A x x x
A, [DE] 1 6 A ← (DE)
[DE], A 1 6 (DE) ← A
A, [HL] 1 6 A ← (HL)
[HL], A 1 6 (HL) ← A
A, [HL+byte] 2 6 A ← (HL + byte)
MOV
[HL+byte], A 2 6 (HL + byte) ← A
A, X 1 4 A ↔ X
A, r Note 2 2 6 A ↔ r
A, saddr 2 6 A ↔ (saddr)
A, sfr 2 6 A ↔ sfr
A, [DE] 1 8 A ↔ (DE)
A, [HL] 1 8 A ↔ (HL)
XCH
A, [HL+byte] 2 8 A ↔ (HL + byte)
Notes 1. Except r = A.
2. Except r = A, X.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
CHAPTER 17 INSTRUCTION SET
User’s Manual U15552EJ2V2UD 193
Mnemonic Operands Bytes Clocks Operation Flag
ZACCY
MOVW rp, #word 3 6 rp ← word
AX, saddrp 2 6 AX ← (saddrp)
saddrp, AX 2 8 (saddrp) ← AX
AX, rp
Note 1 4 AX ← rp
rp, AX
Note 1 4 rp ← AX
XCHW AX, rp Note 1 8 AX ↔ rp
ADD A, #byte 2 4 A, CY ← A + byte x x x
saddr, #byte 3 6 (saddr), CY ← (saddr) + byte x x x
A, r 2 4 A, CY ← A + r x x x
A, saddr 2 4 A, CY ← A + (saddr) x x x
A, !addr16 3 8 A, CY ← A + (addr16) x x x
A, [HL] 1 6 A, CY ← A + (HL) x x x
A, [HL+byte] 2 6 A, CY ← A + (HL + byte) x x x
ADDC A, #byte 2 4 A, CY ← A + byte + CY x x x
saddr, #byte 3 6 (saddr), CY ← (saddr) + byte + CY x x x
A, r 2 4 A, CY ← A + r + CY x x x
A, saddr 2 4 A, CY ← A + (saddr) + CY x x x
A, !addr16 3 8 A, CY ← A + (addr16) + CY x x x
A, [HL] 1 6 A, CY ← A + (HL) + CY x x x
A, [HL+byte] 2 6 A, CY ← A + (HL + byte) + CY x x x
SUB A, #byte 2 4 A, CY ← A − byte x x x
saddr, #byte 3 6 (saddr), CY ← (saddr) − byte x x x
A, r 2 4 A, CY ← A − r x x x
A, saddr 2 4 A, CY ← A − (saddr) x x x
A, !addr16 3 8 A, CY ← A − (addr16) x x x
A, [HL] 1 6 A, CY ← A − (HL) x x x
A, [HL+byte] 2 6 A, CY ← A − (HL + byte) x x x
Note Only when rp = BC, DE, or HL.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
CHAPTER 17 INSTRUCTION SET
194 User’s Manual U15552EJ2V2UD
Mnemonic Operands Bytes Clocks Operation Flag
ZACCY
SUBC A, #byte 2 4 A, CY ← A − byte − CY x x x
saddr, #byte 3 6 (saddr), CY ← (saddr) − byte − CY x x x
A, r 2 4 A, CY ← A − r − CY x x x
A, saddr 2 4 A, CY ← A − (saddr) − CY x x x
A, !addr16 3 8 A, CY ← A − (addr16) − CY x x x
A, [HL] 1 6 A, CY ← A − (HL) − CY x x x
A, [HL+byte] 2 6 A, CY ← A − (HL + byte) − CY x x x
AND A, #byte 2 4 A ← A ∧ byte x
saddr, #byte 3 6 (saddr) ← (saddr) ∧ byte x
A, r 2 4 A ← A ∧ r x
A, saddr 2 4 A ← A ∧ (saddr) x
A, !addr16 3 8 A ← A ∧ (addr16) x
A, [HL] 1 6 A ← A ∧ (HL) x
A, [HL+byte] 2 6 A ← A ∧ (HL + byte) x
OR A, #byte 2 4 A ← A ∨ byte x
saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte x
A, r 2 4 A ← A ∨ r x
A, saddr 2 4 A ← A ∨ (saddr) x
A, !addr16 3 8 A ← A ∨ (addr16) x
A, [HL] 1 6 A ← A ∨ (HL) x
A, [HL+byte] 2 6 A ← A ∨ (HL + byte) x
XOR A, #byte 2 4 A ← A V byte x
saddr, #byte 3 6 (saddr) ← (saddr) V byte x
A, r 2 4 A ← A V r x
A, saddr 2 4 A ← A V (saddr) x
A, !addr16 3 8 A ← A V (addr16) x
A, [HL] 1 6 A ← A V (HL) x
A, [HL+byte] 2 6 A ← A V (HL + byte) x
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
CHAPTER 17 INSTRUCTION SET
User’s Manual U15552EJ2V2UD 195
Mnemonic Operands Bytes Clocks Operation Flag
ZACCY
CMP A, #byte 2 4 A − byte x x x
saddr, #byte 3 6 (saddr) − byte x x x
A, r 2 4 A − r x x x
A, saddr 2 4 A − (saddr) x x x
A, !addr16 3 8 A − (addr16) x x x
A, [HL] 1 6 A − (HL) x x x
A, [HL+byte] 2 6 A − (HL + byte) x x x
ADDW AX, #word 3 6 AX, CY ← AX + word x x x
SUBW AX, #word 3 6 AX, CY ← AX − word x x x
CMPW AX, #word 3 6 AX − word x x x
INC r 2 4 r ← r + 1 x x
saddr 2 4 (saddr) ← (saddr) + 1 x x
DEC r 2 4 r ← r − 1 x x
saddr 2 4 (saddr) ← (saddr) − 1 x x
INCW rp 1 4 rp ← rp + 1
DECW rp 1 4 rp ← rp − 1
ROR A, 1 1 2 (CY, A7 ← A0, Am−1 ← Am) × 1 x
ROL A, 1 1 2 (CY, A0 ← A7, Am+1 ← Am) × 1 x
RORC A, 1 1 2 (CY ← A0, A7 ← CY, Am−1 ← Am) × 1 x
ROLC A, 1 1 2 (CY ← A7, A0 ← CY, Am+1 ← Am) × 1 x
SET1 saddr.bit 3 6 (saddr.bit) ← 1
sfr.bit 3 6 sfr.bit ← 1
A.bit 2 4 A.bit ← 1
PSW.bit 3 6 PSW.bit ← 1 x x x
[HL].bit 2 10 (HL).bit ← 1
CLR1 saddr.bit 3 6 (saddr.bit) ← 0
sfr.bit 3 6 sfr.bit ← 0
A.bit 2 4 A.bit ← 0
PSW.bit 3 6 PSW.bit ← 0 x x x
[HL].bit 2 10 (HL).bit ← 0
SET1 CY 1 2 CY ← 1 1
CLR1 CY 1 2 CY ← 0 0
NOT1 CY 1 2 CY ← CY x
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
CHAPTER 17 INSTRUCTION SET
196 User’s Manual U15552EJ2V2UD
Mnemonic Operands Bytes Clocks Operation Flag
ZACCY
CALL !addr16 3 6 (SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
CALLT [addr5] 1 8 (SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5), SP ← SP − 2
RET 1 6 PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2
RETI 1 8 PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0
RRR
PUSH PSW 1 2 (SP − 1) ← PSW, SP ← SP − 1
rp 1 4 (SP − 1) ← rpH, (SP − 2) ← rpL, SP ← SP − 2
POP PSW 1 4 PSW ← (SP), SP ← SP + 1 R R R
rp 1 6 rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2
MOVW SP, AX 2 8 SP ← AX
AX, SP 2 6 AX ← SP
BR !addr16 3 6 PC ← addr16
$addr16 2 6 PC ← PC + 2 + jdisp8
AX 1 6 PCH ← A, PCL ← X
BC $saddr16 2 6 PC ← PC + 2 + jdisp8 if CY = 1
BNC $saddr16 2 6 PC ← PC + 2 + jdisp8 if CY = 0
BZ $saddr16 2 6 PC ← PC + 2 + jdisp8 if Z = 1
BNZ $saddr16 2 6 PC ← PC + 2 + jdisp8 if Z = 0
BT saddr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
sfr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A.bit = 1
PSW.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW.bit = 1
BF saddr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
sfr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A.bit = 0
PSW.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW.bit = 0
DBNZ B, $addr16 2 6 B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0
C, $addr16 2 6 C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0
saddr, $addr16 3 8 (saddr) ← (saddr) − 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
NOP 1 2 No Operation
EI 3 6 IE ← 1 (Enable interrupt)
DI 3 6 IE ← 0 (Disable interrupt)
HALT 1 2 Set HALT mode
STOP 1 2 Set STOP mode
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
CHAPTER 17 INSTRUCTION SET
User’s Manual U15552EJ2V2UD 197
17.3 Instructions Listed by Addressing Type
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,
POP, DBNZ
2nd Operand
1st Operand
#byte A r sfr saddr !addr16 PSW [DE] [HL]
[HL+byte]
$addr1
6
1 None
A ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOVNote
XCHNote
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
ROR
ROL
RORC
ROLC
r MOV
MOV INC
DEC
B, C DBNZ
sfr MOV MOV
saddr MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV DBNZ INC
DEC
!addr16 MOV
PSW MOV MOV PUSH
POP
[DE] MOV
[HL] MOV
[HL+byte] MOV
Note Except r = A.
CHAPTER 17 INSTRUCTION SET
198 User’s Manual U15552EJ2V2UD
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
1st Operand
#word AX rpNote saddrp SP None
AX ADDW
SUBW
CMPW
MOVW
XCHW
MOVW MOVW
rp MOVW MOVWNote INCW
DECW
PUSH
POP
saddrp MOVW
SP MOVW
Note Only when rp = BC, DE, or HL.
(3) Bit manipulation instructions
SET1, CLR1, NOT1, BT, BF
2nd Operand
1st Operand
$addr16 None
A.bit BT
BF
SET1
CLR1
sfr.bit BT
BF
SET1
CLR1
saddr.bit BT
BF
SET1
CLR1
PSW.bit BT
BF
SET1
CLR1
[HL].bit SET1
CLR1
CY SET1
CLR1
NOT1
CHAPTER 17 INSTRUCTION SET
User’s Manual U15552EJ2V2UD 199
(4) Call instructions/branch instructions
CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ
2nd Operand
1st Operand
AX !addr16 [addr5] $addr16
Basic Instructions BR CALL
BR
CALLT BR
BC
BNC
BZ
BNZ
Compound Instructions DBNZ
(5) Other instructions
RET, RETI, NOP, EI, DI, HALT, STOP
200 User’s Manual U15552EJ2V2UD
CHAPTER 18 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbol Conditions Ratings Unit
VDD −0.3 to +6.5 V Supply voltage
VPP
µ
PD78F9468 only, Note 1 −0.3 to +10.5 V
Input voltage VI −0.3 to VDD + 0.3Note 2 V
VO1 P00 to P03, P10, P11, P40 to P43,
P60, P61
−0.3 to VDD + 0.3Note 2 V
Output voltage
VO2 COM0 to COM3, S0 to S16,
P80/S22 to P85/S17
−0.3 to VLC0 + 0.3Note 2 V
Pin P60/TO40 −30 mA
Per pin (except P60/TO40) −10 mA
Output current, high IOH
Total for all pins (except P60/TO40) −30 mA
Per pin 30 mA Output current, low IOL
Total for all pins 80 mA
During normal operation −40 to +85 °C Operating ambient temperature TA
During flash memory programming 10 to 40 °C
Mask ROM version −65 to +150 °C Storage temperature Tstg
Flash memory version −40 to +125 °C
Notes 1. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
V
PP must exceed VDD 10
µ
s or more after VDD has reached the lower-limit value (1.8 V) of the
operating voltage range (a in the figure below).
• When supply voltage falls
V
DD must be lowered 10
µ
s or more after VPP falls below the lower-limit value (1.8 V) of the range of
VDD (b in the figure below).
1.8 V
VDD
0 V
0 V
VPP
1.8 V
a b
2. 6.5 V or less
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 18 ELECTRICAL SPECIFICATIONS
User’s Manual U15552EJ2V2UD 201
Main System Clock Oscillator Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillation frequency
(fX)Note 1
1.0 5.0 MHz
Ceramic
resonator
X1
X2
C1
C2
Oscillation
stabilization timeNote 2
After VDD has reached the
oscillation voltage range MIN.
4 ms
Oscillation
frequency Note 1
1.0 5.0 MHz
4.5 ≤ VDD ≤ 5.5 V 10 ms
Crystal
resonator
X1
X2
C1
C2
Oscillation
stabilization timeNote 2
1.8 ≤ VDD ≤ 5.5 V 30 ms
X1 input frequency
(fX)Note 1
1.0 5.0 MHz
External
clock
X1 X2
X1 input high-/low-
level width (tXH, tXL)
85 500 ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release. Use the resonator to stabilize
oscillation within the oscillation wait time.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
CHAPTER 18 ELECTRICAL SPECIFICATIONS
202 User’s Manual U15552EJ2V2UD
Recommended Oscillator Constants
Ceramic resonator (TA = −40 to +85°C) (mask ROM version)
Recommended Circuit
Constant (pF)
Oscillation Voltage
Range (VDD)
Manufacturer Part Number Frequency
(MHz)
C1 C2 MIN. MAX.
Remark
CSBLA1M00J58-B0Note 1.0 100 100 2.0 5.5 Rd = 3.3 kΩ
CSTCC2M00G53-R0 2.0
CSTCR4M00G53-R0
CSTLS4M00G53-B0
4.0
CSTCR4M19G53-R0
CSTLS4M19G53-B0
4.194
CSTCR4M91G53-R0
CSTLS4M91G53-B0
4.915
CSTCR5M00G53-R0
Murata Mfg.
CSTLS5M00G53-B0
5.0
− − 1.8 5.5 With internal
capacitor
PBRC4.00HR 4.0
PBRC4.19HR 4.19
PBRC4.91HR 4.91
Kyocera
PBRC5.00HR 5.0
− − 1.8 5.5 With internal
capacitor
FCR4.0MC5 4.0 TDK
FCR5.0MC5 5.0
− − 2.0 5.5 With internal
capacitor
Note When using the CSBLA1M00J58-B0 (1.0 MHz) of Murata Mfg. as the ceramic resonator, a limiting resistor
(Rd = 3.3 kΩ) is necessary (refer to the figure below). The limiting resistor is not necessary when other
recommended resonators are used.
X2X1
C2C1
CSBLA1M00J58-B0
Rd
Caution The oscillator constant is a reference value based on evaluation under a specific environment by
the resonator manufacturer. If optimization of oscillator characteristics is necessary in the
actual application, apply to the resonator manufacturer for evaluation on the implementation
circuit.
The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the
µ
PD78946x so that the internal operating conditions are within the specifications of the DC and
AC characteristics.
Remark For the resonator selection and oscillator constant of the
µ
PD78F9468, users are required to either
evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
CHAPTER 18 ELECTRICAL SPECIFICATIONS
User’s Manual U15552EJ2V2UD 203
Subsystem Clock Oscillator Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillation frequency
(fXT)Note 1
32 32.768 35 kHz
4.5 ≤ VDD ≤ 5.5 V 1.2 2 s
Crystal
resonator
Oscillation
stabilization timeNote 2
1.8 ≤ VDD ≤ 5.5 V 10 s
XT1 input frequency
(fXT)Note 1
32 35 kHz
External
clock
XT1 XT2
XT1 input high-/low-
level width (tXTH, tXTL)
14.3 15.6
µ
s
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. The time required for oscillation to stabilize after VDD reaches the MIN. oscillation voltage range. Use a
resonator to stabilize oscillation during the oscillation wait time.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.
XT2
XT1
C4
C3
R
CHAPTER 18 ELECTRICAL SPECIFICATIONS
204 User’s Manual U15552EJ2V2UD
DC Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Per pin 10 mA Output current, low IOL
Total for all pins 80 mA
Per pin (except P60/TO40) −1 mA
P60/TO40 VDD = 3.0 V, VOH = 2.0 V −7 −15 −24 mA
Output current, high IOH
Total for all pins (except P60/TO40) −15 mA
2.7 ≤ VDD ≤ 5.5 V 0.7VDD VDD V VIH1 P00 to P03, P10, P11, P60,
P80 to P85 1.8 ≤ VDD ≤ 5.5 V 0.9VDD VDD V
2.7 ≤ VDD ≤ 5.5 V 0.8VDD VDD V VIH2 RESET, P40 to P43, P61
1.8 ≤ VDD ≤ 5.5 V 0.9VDD VDD V
VIH3 X1, X2 VDD − 0.1 VDD V
Input voltage, high
VIH4 XT1, XT2 VDD − 0.1 VDD V
2.7 ≤ VDD ≤ 5.5 V 0 0.3VDD V VIL1 P00 to P03, P10, P11, P60,
P80 to P85 1.8 ≤ VDD ≤ 5.5 V 0 0.1VDD V
2.7 ≤ VDD ≤ 5.5 V 0 0.2VDD V VIL2 RESET, P40 to P43, P61
1.8 ≤ VDD ≤ 5.5 V 0 0.1VDD V
VIL3 X1, X2 0 0.1 V
Input voltage, low
VIL4 XT1, XT2 0 0.1 V
VOH11 1.8 ≤ VDD ≤ 5.5 V,
IOH = −100
µ
A
VDD − 0.5 V
VOH12
P00 to P03, P10, P11,
P40 to P43, P61
1.8 ≤ VDD ≤ 5.5 V,
IOH = −500
µ
A
VDD − 0.7 V
VOH21 1.8 ≤ VDD ≤ 5.5 V,
IOH = −400
µ
A
VDD − 0.5 V
Output voltage, high
VOH22
P60/TO40
1.8 ≤ VDD ≤ 5.5 V,
IOH = −2 mA
VDD − 0.7 V
VOL1 1.8 ≤ VDD ≤ 5.5 V,
IOL = 400
µ
A
0.5 V
Output voltage, low
VOL2
P00 to P03, P10, P11,
P40 to P43, P60, P61
1.8 ≤ VDD ≤ 5.5 V,
IOL = 2 mA
0.7 V
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 18 ELECTRICAL SPECIFICATIONS
User’s Manual U15552EJ2V2UD 205
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
ILIH1 P00 to P03, P10,
P11, P40 to P43,
P60, P61, P80 to
P85, RESET
3
µ
A Input leakage current,
high
ILIH2
VIN = VDD
X1, X2, XT1, XT2 20
µ
A
ILIL1 P00 to P03, P10,
P11, P40 to P43,
P60, P61, P80 to
P85, RESET
−3
µ
A Input leakage current,
low
ILIL2
VIN = 0 V
X1, X2, XT1, XT2 −20
µ
A
Output leakage current,
high
ILOH VOUT = VDD 3
µ
A
Output leakage current,
low
ILOL VOUT = 0 V −3
µ
A
Software pull-up
resistors
R1 VIN = 0 V P00 to P03, P10,
P11, P40 to P43
50 100 200 kΩ
VDD = 5.5 VNote 2 1.5 3.0 mA IDD1 5.0 MHz crystal oscillation
operating mode VDD = 3.3 VNote 3 0.6 1.2 mA
VDD = 5.5 V 0.8 2.0 mA IDD2 5.0 MHz crystal oscillation
HALT mode VDD = 3.3 V 0.4 0.8 mA
VDD = 5.5 V 50 100
µ
A IDD3 32,768 kHz crystal
oscillation operating
modeNote 4
VDD = 3.3 V 30 60
µ
A
VDD = 5.5 V 25 50
µ
A IDD4 32.768 kHz crystal
oscillation HALT modeNote 4
VDD = 3.3 V 7 25
µ
A
VDD = 5.5 V 0.1 10
µ
A IDD5 STOP mode
(POC not operating) VDD = 3.3 V 0.05 5
µ
A
VDD = 5.5 V 2 20
µ
A IDD6 STOP mode
(POC operating) VDD = 3.3 V 1 10
µ
A
VDD = 5.5 V 2.3 5.0 mA
Supply currentNote 1
(mask ROM version)
IDD7 5.0 MHz crystal oscillation
A/D operating mode VDD = 3.3 V 1.1 2.4 mA
VDD = 5.5 VNote 2 5.0 15.0 mA IDD1 5.0 MHz crystal oscillation
operating mode VDD = 3.3 VNote 3 2.0 5.0 mA
VDD = 5.5 V 1.2 3.6 mA IDD2 5.0 MHz crystal oscillation
HALT mode VDD = 3.3 V 0.5 1.5 mA
VDD = 5.5 V 25 70
µ
A IDD4 32.768 kHz crystal
oscillation HALT modeNote 4
VDD = 3.3 V 10 35
µ
A
VDD = 5.5 V 2 20
µ
A
Supply currentNote 1
(
µ
PD78F9468)
IDD5 STOP mode
VDD = 3.3 V 1 10
µ
A
Notes 1. Excludes current flowing through ports (including current flowing through on-chip pull-up resistors).
2. High-speed mode operation (when the processor clock control register (PCC) is set to 00H).
3. Low-speed mode operation (when PCC is set to 02H)
4. When the main system clock operation is stopped.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 18 ELECTRICAL SPECIFICATIONS
206 User’s Manual U15552EJ2V2UD
AC Characteristics
(1) Basic operation (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
2.7 ≤ VDD ≤ 5.5 V 0.4 8.0
µ
s Cycle time
(Min. instruction execution time)
TCY
1.8 ≤ VDD ≤ 5.5 V 1.6 8.0
µ
s
Interrupt input
high-/low-level width
tINTH,
tINTL
INTP0 10
µ
s
Key return pin
low-level width
tKRIL KR00 to KR03 10
µ
s
RESET low-level width tRSL 10
µ
s
TCY vs. VDD (Main System Clock)
Supply voltage V
DD
(V)
123456
0.1
0.4
0.5
1.0
2.0
10
20
60
Cycle time T
CY
[ s]
Guaranteed
operation
range
µ
CHAPTER 18 ELECTRICAL SPECIFICATIONS
User’s Manual U15552EJ2V2UD 207
AC Timing Measurement Points (Excluding X1, XT1 Input)
0.8V
DD
0.2V
DD
Point of measurement
0.8V
DD
0.2V
DD
Clock Timing
1/f
X
t
XL
t
XH
X1 input V
IH3
(MIN.)
V
IL3
(MAX.)
1/f
XT
t
XTL
t
XTH
XT1 input V
IH4
(MIN.)
V
IL4
(MAX.)
Interrupt Input Timing
INTP0
tINTL tINTH
Key Return Input Timing
KR00 to KR03
tKRIL
RESET Input Timing
RESET
t
RSL
CHAPTER 18 ELECTRICAL SPECIFICATIONS
208 User’s Manual U15552EJ2V2UD
8-Bit A/D Converter Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 8 8 8 bit
2.7 ≤ VDD ≤ 5.5 V ±0.6 %FSROverall errorNotes 1, 2
1.8 ≤ VDD ≤ 5.5 V ±1.2 %FSR
2.7 ≤ VDD ≤ 5.5 V 14 100
µ
s Conversion time tCONV
1.8 ≤ VDD ≤ 5.5 V 28 100
µ
s
Notes 1. Excludes quantization error (±0.2% FSR).
2. The overall error is indicated as a ratio to the full-scale value (%FSR).
Remark FSR: Full scale range
LCD Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VLC20 VLC2 pin 1.35 1.5 1.65 V
VLC10 VLC1 pin 3.0 V
VLC00
GAIN = 0
VLC0 pin 4.5 V
VLC21 VLC2 pin 0.9 1.0 1.1 V
VLC11 VLC1 pin 2.0 V
LCD boost output voltage
VLC01
GAIN = 1
VLC0 pin 3.0 V
LCD output voltage differentialNote
(common)
VODC IO = ±5
µ
A 0 ±0.2 V
LCD output voltage differentialNote
(segment)
VODS IO = ±1
µ
A 0 ±0.2 V
Note The voltage differential is the difference between the output voltage and the ideal value of the segment and
common signal outputs.
CHAPTER 18 ELECTRICAL SPECIFICATIONS
User’s Manual U15552EJ2V2UD 209
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply voltage VDDDR 1.8 5.5 V
Low voltage detection (POC) voltageNote 1 VPOC Response time: 2 msNote 2 1.8 1.9 2.0 V
Release signal set time tSREL STOP released by RESET 10
µ
s
Cancelled by RESET 215/fX s
Oscillation stabilization wait timeNote 3 tWAIT
Cancelled by interrupt request Note 4 s
Notes 1. In mask ROM versions, only when the POC circuit is selected by a mask option (refer to CHAPTER 16
MASK OPTION).
2. The response time is the time until the output is inverted following detection of voltage by POC, or the
time until operation stabilizes after the shift from the operation stopped state to the operating state.
3. The oscillation stabilization time is the amount of time the CPU operation is stopped in order to avoid
unstable operation at the start of oscillation. Program operation does not start until both the oscillation
stabilization time and the time until oscillation starts have elapsed.
4. Selection of 212/fX, 215/fX, and 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time selection register (OSTS) (refer to 13.1.2 Register controlling standby function).
Remark fX: Main system clock oscillation frequency
CHAPTER 18 ELECTRICAL SPECIFICATIONS
210 User’s Manual U15552EJ2V2UD
Data Retention Timing
V
DD
Data retention mode
STOP mode
HALT mode
Internal reset operation
Operating mode
t
SREL
t
WAIT
STOP instruction execution
V
DDDR
RESET
VDD
Data retention mode
STOP mode
HALT mode
Operating mode
tSREL
tWAIT
STOP instruction execution
VDDDR
Standby release signal
(interrupt request)
Write and Erase Characteristics (TA = 10 to 40°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 1.0 5 MHz Write operation frequency fX
VDD = 1.8 to 5.5 V 1.0 1.25 MHz
Write current (VDD pin)Note IDDW When VPP supply voltage = VPP1
(at 5.0 MHz operation)
7 mA
Write current (VPP pin)Note IPPW When VPP supply voltage = VPP1 13 mA
Erase current (VDD pin) Note IDDE When VPP supply voltage = VPP1
(at 5.0 MHz operation)
7 mA
Erase current (VPP pin)Note IPPE When VPP supply voltage = VPP1 100 mA
Unit erase time ter 0.5 1 1 s
Total erase time tera 20 s
Number of rewrites Erase and write is considered as 1
cycle
20 Times
VPP0 Normal operation 0 0.2VDD V VPP supply voltage
VPP1 Flash memory programming 9.7 10.0 10.3 V
Note Excludes current flowing through ports (including on-chip pull-up resistors)
User’s Manual U15552EJ2V2UD 211
CHAPTER 19 PACKAGE DRAWING
M
39
40 26
52
114
13
27
SN S
J
detail of lead end
R
K
M
I
S
L
T
P
Q
G
F
H
52-PIN PLASTIC LQFP (10x10)
ITEM MILLIMETERS
A
B
D
G
12.0±0.2
10.0±0.2
0.13
1.1
I
12.0±0.2
J
C 10.0±0.2
H 0.32±0.06
0.65 (T.P.)
1.0±0.2K
L0.5
F 1.1
N
P
Q
0.10
1.4
0.1±0.05
T 0.25
S 1.5±0.1
U 0.6±0.15
S52GB-65-8ET-2
M 0.17+0.03
−0.05
R3°+4°
−3°
A
B
CD
U
212 User’s Manual U15552EJ2V2UD
CHAPTER 20 RECOMMENDED SOLDERING CONDITIONS
The
µ
PD789467 Subseries should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 20-1. Surface Mounting Type Soldering Conditions (1/2)
µ
PD789462GB-×××-8ET: 52-pin plastic LQFP (10 × 10)
µ
PD789464GB-×××-8ET: 52-pin plastic LQFP (10 × 10)
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or
higher), Count: Twice or less
IR35-00-2
VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or
higher), Count: Twice or less
VP15-00-2
Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count:
Once, Preheating temperature: 120°C max. (package surface temperature)
WS60-00-1
Partial heating Pin temperature: 350°C max. Time: 3 seconds max. (per pin row) —
Caution Do not use different soldering methods together (except for partial heating).
µ
PD789466GB-×××-8ET: 52-pin plastic LQFP (10 × 10)
µ
PD789467GB-×××-8ET: 52-pin plastic LQFP (10 × 10)
µ
PD78F9468GB-8ET: 52-pin plastic LQFP (10 × 10)
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or
higher), Count: Twice or less, Exposure limit: 7 daysNote (after that, prebake at
125°C for 10 hours)
IR35-107-2
VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or
higher), Count: Twice or less, Exposure limit: 7 daysNote (after that, prebake at
125°C for 10 hours)
VP15-107-2
Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count:
Once, Preheating temperature: 120°C max. (package surface temperature),
Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours)
WS60-107-1
Partial heating Pin temperature: 350°C max. Time: 3 seconds max. (per pin row) —
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
CHAPTER 20 RECOMMENDED SOLDERING CONDITIONS
User’s Manual U15552EJ2V2UD 213
Table 20-1. Surface Mounting Type Soldering Conditions (2/2)
µ
PD789462GB-×××-8ET-A: 52-pin plastic LQFP (10 × 10)
µ
PD789464GB-×××-8ET-A: 52-pin plastic LQFP (10 × 10)
µ
PD789466GB-×××-8ET-A: 52-pin plastic LQFP (10 × 10)
µ
PD789467GB-×××-8ET-A: 52-pin plastic LQFP (10 × 10)
µ
PD78F9468GB-8ET-A: 52-pin plastic LQFP (10 × 10)
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or
higher), Count: Three times or less, Exposure limit: 7 daysNote (after that,
prebake at 125°C for 20 to 72 hours)
IR60-207-3
Wave soldering When the pin pitch of the package is 0.65 mm or more, wave soldering can
also be performed.
For details, contact an NEC Electronics sales representative.
—
Partial heating Pin temperature: 350°C max., Time: 3 seconds max. (per pin row) —
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
214 User’s Manual U15552EJ2V2UD
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for development of systems using the
µ
PD789467 Subseries.
Figure A-1 shows development tools.
• Support of PC98-NX series
Unless specified otherwise, the products supported by IBM PC/AT compatibles can be used in the PC98-NX
series. When using the PC98-NX Series, refer to the explanation of IBM PC/AT compatibles.
• Windows
Unless specified otherwise, "Windows" indicates the following operating systems.
• Windows 3.1
• Windows 95, 98, 2000
• Windows NT Ver.4.0
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U15552EJ2V2UD 215
Figure A-1. Development Tools
Language processing software
• Assembler package
• C compiler package
• Device file
• C library source file
Note 1
Software for debugging
• Integrated debugger
• System simulator
Host machine
(PC or EWS)
Interface adapter
In-circuit emulator
Emulation board
Emulation probe
Conversion socket or
conversion adapter
Target system
Flash programmer
Flash memory
writing adapter
Flash memory
Power supply unit
• Software package
Control software
• Project manager
(Windows version only)
Note 2
Software package
Flash memory writing tools
Notes 1. The C library source file is not included in the software package.
2. The project manager is included in the assembler package. The project manager is used only for
Windows.
APPENDIX A DEVELOPMENT TOOLS
216 User’s Manual U15552EJ2V2UD
A.1 Software Package
Various software tools for 78K/0S Series development are integrated into one package.
The following tools are included.
RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, various device files
SP78K0S Software package
Part number:
µ
S××××SP78K0S
Remark ×××× in the part number differs depending on the operating system to be used.
µ
S××××SP78K0S
×××× Host Machine OS Supply Medium
AB17 Japanese Windows
BB17
PC-9800 series, IBM PC/AT
compatibles English Windows
CD-ROM
A.2 Language Processing Software
Program that converts program written in mnemonic into object codes that can be executed
by microcontroller.
In addition, automatic functions to generate symbol tables and optimize branch instructions
are also provided.
Used in combination with a device file (DF789468) (sold separately).
<Caution when used in PC environment>
The assembler package is a DOS-based application but may be used in the Windows
environment by using the Project Manager of Windows (included in the assembler package).
RA78K0S
Assembler package
Part number:
µ
S××××RA78K0S
Program that converts program written in C language into object codes that can be executed
by microcontroller.
Used in combination with an assembler package (RA78K0S) and device file (DF789468)
(both sold separately).
<Caution when used in PC environment>
The C compiler package is a DOS-based application but may be used in the Windows
environment by using the Project Manager of Windows (included in the assembler package).
CC78K0S
C compiler package
Part number:
µ
S××××CC78K0S
File containing the information specific to the device.
Used in combination with the RA78K0S, CC78K0S, and SM78K0S (sold separately).
DF789468Note 1
Device file
Part number:
µ
S××××DF789468
Source file of functions for generating object library included in C compiler package.
Necessary for changing object library included in C compiler package according to
customer’s specifications. Since this is a source file, its working environment does not
depend on any particular operating system.
CC78K0S-LNote 2
C library source file
Part number:
µ
S××××CC78K0S-L
Notes 1. DF789468 is a common file that can be used with the RA78K0S, CC78K0S, ID78K0S-NS, and
SM78K0S.
2. CC78K0S-L is not included in the software package (SP78K0S).
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U15552EJ2V2UD 217
Remark ×××× in the part number differs depending on the host machine and operating system to be used.
µ
S××××RA78K0S
µ
S××××CC78K0S
×××× Host Machine OS Supply Medium
AB13 Japanese Windows
BB13 English Windows
3.5” 2HD FD
AB17 Japanese Windows
BB17
PC-9800 series, IBM PC/AT
compatibles
English Windows
3P17 HP9000 series 700™ HP-UX™ (Rel.10.10)
3K17 SPARCstation™ SunOS™ (Rel.4.1.4),
Solaris™ (Rel.2.5.1)
CD-ROM
µ
S××××DF789468
µ
S××××CC78K0S-L
×××× Host Machine OS Supply Medium
AB13 Japanese Windows
BB13
PC-9800 series, IBM PC/AT
compatibles English Windows
3.5” 2HD FD
3P16 HP9000 series 700 HP-UX (Rel.10.10) DAT
3K13 3.5” 2HD FD
3K15
SPARCstation SunOS (Rel.4.1.4),
Solaris (Rel.2.5.1) 1/4” CGMT
A.3 Control Software
Project manager Control software designed so that the user program can be efficiently developed in the
Windows environment. A series of jobs for user program development including starting the
editor, building, and starting the debugger, can be executed on the project manager.
<Caution>
The project manager is included in the assembler package (RA78K0S). It cannot be used in
an environment other than Windows.
APPENDIX A DEVELOPMENT TOOLS
218 User’s Manual U15552EJ2V2UD
A.4 Flash Memory Writing Tools
Flashpro III (FL-PR3, PG-FP3)
Flashpro IV (FL-PR4, PG-FP4)
Flash programmer
Dedicated flash programmer for microcontrollers incorporating flash memory
FA-52GB-8ET
Flash memory writing adapter
Adapter for writing to flash memory and connected to Flashpro III or Flashpro IV.
FA-52GB-8ET: for 52-pin plastic LQFP (GB-8ET type)
Remark The FL-PR3, FL-PR4, and FA-52GB-8ET are products of Naito Densei Machida Mfg. Co., Ltd. (TEL
+81-45-475-4191).
A.5 Debugging Tools (Hardware)
IE-78K0S-NS
In-circuit emulator
In-circuit emulator for debugging hardware and software of application system using 78K/0S
Series. Can be used with integrated debugger (ID78K0S-NS). Used in combination with AC
adapter, emulation probe, and interface adapter for connecting the host machine.
IE-78K0S-NS-A
In-circuit emulator
A coverage function has been added to the IE-78K0S-NS function and the debug function has
been further enhanced, enhancing the tracer and timer functions.
IE-70000-MC-PS-B
AC adapter
Adapter for supplying power from AC 100 to 240 V outlet.
IE-70000-98-IF-C
Interface adapter
Adapter necessary when using PC-9800 series PC (except notebook type) as host machine
(C bus supported)
IE-70000-CD-IF-A
PC card interface
PC card and interface cable necessary when using notebook PC as host machine (PCMCIA
socket supported)
IE-70000-PC-IF-C
Interface adapter
Interface adapter necessary when using IBM PC/AT compatible as host machine (ISA bus
supported)
IE-70000-PCI-IF-A
Interface adapter
Adapter necessary when using personal computer incorporating PCI bus as host machine
IE-789468-NS-EM1
Emulation board
Board for emulating peripheral hardware specific to device. Used in combination with in-circuit
emulator.
NP-H52GB-TQ
Emulation probe
Probe for connecting in-circuit emulator and target system.
Used in combination with TGB-052SBP.
TGB-052SBP
Conversion
adapter
Conversion adapter to connect NP-H52GB-TQ and target system board on which 52-pin plastic
LQFP (GB-8ET type) can be mounted
Remarks 1. The NP-H52GB-TQ is a product of Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191).
2. The TGB-052SBP is a product of TOKYO ELETECH CORPORATION.
For further information, contact: Daimaru Kogyo, Ltd.
Tokyo Electronics Department (TEL +81-3-3820-7112)
Osaka Electronics Department (TEL +81-6-6244-6672)
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U15552EJ2V2UD 219
A.6 Debugging Tools (Software)
A debugger supporting in-circuit emulators for the 78K/0S Series: IE-78K0S-NS and IE-
78K0S-NS-A. The ID78K0S-NS is Windows-based software.
This program enhances the debugging functions for C language. Therefore, it can display
the trace results corresponding to the source program by using the window integration
function that links the source program, disassembled display, and memory display with the
trace results.
Use this program in combination with a device file (DF789468) (sold separately).
ID78K0S-NS
Integrated debugger
Part number:
µ
S××××ID78K0S-NS
A system simulator for the 78K/0S Series. The SM78K0S is Windows-based software.
C-source-level or assembler level debugging is possible while simulating the operation of the
target system on the host machine. Using the SM78K0S enables logical and performance
verification of an application independently of the hardware development. This enhances
development efficiency and improves software quality.
Use this program in combination with a device file (DF789468) (sold separately).
SM78K0S
System simulator
Part number:
µ
S××××SM78K0S
File containing information specific to the device.
Use this file in combination with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S
(sold separately).
DF789468Note
Device file
Part number:
µ
S××××DF789468
Note DF789468 is a common file that can be used with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S.
Remark ×××× in the part number differs depending on the operating system to be used and the supply medium.
µ
S××××ID78K0S-NS
µ
S××××SM78K0S
×××× Host Machine OS Supply Medium
AB13 Japanese Windows
BB13 English Windows
3.5” 2HD FD
AB17 Japanese Windows
BB17
PC-9800 series, IBM PC/AT
compatibles
English Windows
CD-ROM
APPENDIX A DEVELOPMENT TOOLS
220 User’s Manual U15552EJ2V2UD
A.7 Cautions When Designing Target System
The following shows the conditions when connecting the emulation probe to the conversion connector and
conversion socket. Design the system considering shapes and other conditions of the components to be mounted on
the target system and be sure to follow the configuration below.
Figure A-2. Condition Diagram of Connection to Target System
In-circuit emulator
IE-78K0S-NS or IE-78K0S-NS-A
Emulation board
IE-789468-NS-EM1
Connect to CN2 if
PD789467 Subseries is used.
CN2
CN1
Emulation probe
NP-H52GB-TQ
When CN2 is connected: 350 mm
Target system
Conversion adapter: TGB-052SBP
Conversion adapter: TGB-052SBP
Emulation probe
NP-H52GB-TQ
Emulation board
IE-789468-NS-EM1 10 mm
43 mm
11 mm
45 mm
53 mm No.1pin
45 mm
23 mm
14.45 mm
14.45 mm
Target system
µ
User’s Manual U15552EJ2V2UD 221
APPENDIX B REGISTER INDEX
B.1 Register Index (Alphabetic Order of Register Name)
[A]
A/D conversion result register 0 (ADCR0)............................................................................................................ 128
A/D converter mode register 0 (ADM0) ................................................................................................................ 130
A/D input selection register 0 (ADS0)................................................................................................................... 131
[C]
Carrier generator output control register 40 (TCA40) ............................................................................................. 96
[E]
8-bit compare register 30 (CR30) ........................................................................................................................... 91
8-bit compare register 40 (CR40) ........................................................................................................................... 91
8-bit H width compare register 40 (CRH40)............................................................................................................ 91
8-bit timer counter 30 (TM30)................................................................................................................................. 92
8-bit timer counter 40 (TM40)................................................................................................................................. 92
8-bit timer mode control register 30 (TMC30).........................................................................................................94
8-bit timer mode control register 40 (TMC40).........................................................................................................95
External interrupt mode register 0 (INTM0) .......................................................................................................... 160
[ I ]
Interrupt mask flag register 0 (MK0) ..................................................................................................................... 159
Interrupt request flag register 0 (IF0).................................................................................................................... 159
[K]
Key return mode register 00 (KRM00).................................................................................................................. 161
[L]
LCD clock control register 0 (LCDC0) .................................................................................................................. 143
LCD display mode register 0 (LCDM0)................................................................................................................. 141
LCD voltage boost control register 0 (LCDVA0) ................................................................................................... 144
[O]
Oscillation stabilization time selection register (OSTS) ........................................................................................ 169
[P]
Port 0 (P0).............................................................................................................................................................. 66
Port 1 (P1).............................................................................................................................................................. 67
Port 4 (P4).............................................................................................................................................................. 68
Port 6 (P6).............................................................................................................................................................. 69
Port 8 (P8).............................................................................................................................................................. 71
Port function register 8 (PF8) ......................................................................................................................... 74, 144
Port mode register 0 (PM0) .................................................................................................................................... 72
Port mode register 1 (PM1) .................................................................................................................................... 72
APPENDIX B REGISTER INDEX
222 User’s Manual U15552EJ2V2UD
Port mode register 4 (PM4) ....................................................................................................................................72
Port mode register 6 (PM6) ..............................................................................................................................72, 97
Processor clock control register (PCC)...................................................................................................................78
Pull-up resistor option register 0 (PU0)...................................................................................................................73
[S]
Subclock control register (CSS)..............................................................................................................................79
Suboscillation mode register (SCKM).....................................................................................................................79
[W]
Watch timer mode control register (WTM)............................................................................................................118
Watchdog timer clock selection register (TCL2) ...................................................................................................123
Watchdog timer mode register (WDTM) ...............................................................................................................124
APPENDIX B REGISTER INDEX
User’s Manual U15552EJ2V2UD 223
B.2 Register Index (Alphabetic Order of Register Symbol)
[A]
ADCR0: A/D conversion result register 0........................................................................................................... 128
ADM0: A/D converter mode register 0.............................................................................................................130
ADS0: A/D input selection register 0............................................................................................................... 131
[C]
CR30: 8-bit compare register 30....................................................................................................................... 91
CR40: 8-bit compare register 40....................................................................................................................... 91
CRH40: 8-bit H width compare register 40..........................................................................................................91
CSS: Subclock control register .......................................................................................................................79
[ I ]
IF0: Interrupt request flag register 0 ...........................................................................................................159
INTM0: External interrupt mode register 0 ....................................................................................................... 160
[K]
KRM00: Key return mode register 00 ................................................................................................................ 161
[L]
LCDC0: LCD clock control register 0 ................................................................................................................ 143
LCDM0: LCD display mode register 0 ............................................................................................................... 141
LCDVA0: LCD voltage boost control register 0 ................................................................................................... 144
[M]
MK0: Interrupt mask flag register 0............................................................................................................... 159
[O]
OSTS: Oscillation stabilization time selection register..................................................................................... 169
[P]
P0: Port 0.....................................................................................................................................................66
P1: Port 1.....................................................................................................................................................67
P4: Port 4.....................................................................................................................................................68
P6: Port 6.....................................................................................................................................................69
P8: Port 8.....................................................................................................................................................71
PCC: Processor clock control register............................................................................................................. 78
PF8: Port function register 8 .................................................................................................................. 74, 144
PM0: Port mode register 0.............................................................................................................................. 72
PM1: Port mode register 1.............................................................................................................................. 72
PM4: Port mode register 4.............................................................................................................................. 72
PM6: Port mode register 6........................................................................................................................ 72, 97
PU0: Pull-up resistor option register 0 ............................................................................................................ 73
[S]
SCKM: Suboscillation mode register..................................................................................................................79
APPENDIX B REGISTER INDEX
224 User’s Manual U15552EJ2V2UD
[T]
TCA40: Carrier generator output control register 40...........................................................................................96
TCL2: Watchdog timer clock selection register ..............................................................................................123
TM30: 8-bit timer counter 30.............................................................................................................................92
TM40: 8-bit timer counter 40.............................................................................................................................92
TMC30: 8-bit timer mode control register 30 .......................................................................................................94
TMC40: 8-bit timer mode control register 40 .......................................................................................................95
[W]
WDTM: Watchdog timer mode register.............................................................................................................124
WTM: Watch timer mode control register.......................................................................................................118
User’s Manual U15552EJ2V2UD 225
APPENDIX C REVISION HISTORY
The revision history is described below. The “Applied to” column indicates the chapters in each edition.)
(1/2)
Edition Major Revisions from Previous Edition Applied to
Deletion of development status indication “under development” for
µ
PD789466 and
789467
Throughout
Addition of description on pin connections in 2.2.15 VPP (
µ
PD78F9468 only) CHAPTER 2 PIN
FUNCTIONS
Table 3-3 Special-Function Registers
• Change of attribute of port 8 (P8) to read-only and change of value after reset to
undefined
• Modification of oscillation stabilization time selection register (OSTS) to allow
use of 1-bit manipulation instruction.
CHAPTER 3 CPU
ARCHITECTURE
Modification of Caution 2 in Figure 4-10 Format of Port Function Register 8 CHAPTER 4 PORT
FUNCTIONS
Addition of Note on feedback resistor in Figure 5-3 Format of Suboscillation
Mode Register
CHAPTER 5 CLOCK
GENERATOR
6.2 Configuration of 8-Bit Timers 30 and 40
• Modification of Figure 6-3 Block Diagram of Output Controller (Timer 40)
• Addition of description to (2) 8-bit compare register 40 (CR40)
• Addition of description to (3) 8-bit H width compare register 40 (CRH40)
Addition to Cautions in Figure 6-6 Format of Carrier Generator Output Control
Register 40
Addition to Cautions in 6.4.3 Operation as carrier generator
Modification of description in 6.5 Notes on Using 8-Bit Timers 30 and 40
CHAPTER 6 8-BIT
TIMERS 30 AND 40
Addition of (8) Input impedance of ANI0 pin to 9.5 Cautions Related to 8-Bit
A/D Converter
CHAPTER 9 8-BIT A/D
CONVERTER
Addition to Notes and Cautions in Figure 10-2 Format of LCD Display Mode
Register 0
CHAPTER 10 LCD
CONTROLLER/DRIVER
Addition to Cautions in Figure 12-2 Format of Interrupt Request Flag Register
0
Addition to Cautions in Figure 12-6 Format of Key Return Mode Register 00
CHAPTER 12
INTERRUPT
FUNCTION
Modification of oscillation stabilization time selection register (OSTS) to allow use
of 1-bit manipulation instruction in 13.1.2 Register controlling standby function
CHAPTER 13
STANDBY FUNCTION
Modification of Table 15-3 Communication Mode List CHAPTER 15
µ
PD78F9468
CHAPTER 18 ELECTRICAL SPECIFICATIONS
• Change from target values to formal specifications
• Addition of Note 1 to Absolute Maximum Ratings
• Addition of recommended oscillator constants for mask ROM versions
• Modification of Write and Erase Characteristics
CHAPTER 18
ELECTRICAL
SPECIFICATIONS
Addition of recommended conditions for
µ
PD789466 and 789467 in CHAPTER 20
RECOMMENDED SOLDERING CONDITIONS
CHAPTER 20
RECOMMENDED
SOLDERING
CONDITIONS
Change of name “conversion connector” and “conversion socket” to “conversion
adapter (TGB-052SBP)” in A.5 Debugging Tools (Hardware)
APPENDIX A
DEVELOPMENT
TOOLS
2nd edition
Addition of APPENDIX C REVISION HISTORY APPENDIX C
REVISION HISTORY
APPENDIX C REVISION HISTORY
User’s Manual U15552EJ2V2UD
226
(2/2)
Edition Major Revisions from Previous Edition Applied to
Addition of lead-free products CHAPTER 1
GENERAL
2nd edition
(modification
ver.2) Addition of soldering conditions of lead-free products in Table 20-1 Surface
Mounting Type Soldering Conditions
CHAPTER 20
RECOMMENDED
SOLDERING
CONDITIONS
