ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com 12-Bit, 1MSPS, 4-/8-Channel, Bipolar-Input, SAR Analog-to-Digital Converter with Software-Selectable Ranges Check for Samples: ADS8634, ADS8638 FEATURES DESCRIPTION * The ADS8634 and ADS8638 (ADS8634/8) are 12-bit analog-to-digital converters (ADCs) capable of measuring inputs up to 10V at 1MSPS. Using a successive approximation register (SAR) core, these ADCs provide a sample-and-hold front-end with no latency in conversions. The ADS8634 includes an input multiplexer (mux) for measuring up to four inputs. The ADS8638 can measure up to eight inputs. 1 23 * * * * * * * Selectable Input Range: 10V, 5V, 2.5V, 0V to 10V, or 0V to 5V Up to 12V with External Reference No Latent Conversions Up to 1MSPS Outstanding Performance: 12 Bits No Missing Codes INL: 0.9LSB SNR: 71.8dB Highly Integrated: 4- or 8-Channel Input Mux Temperature Sensor Internal Voltage Reference Alarm Thresholds for Each Channel Low Power: 14.45mW at 1MSPS 5.85mW at 0.1MSPS Flexible Power-Down Mode SPITM-Compatible Serial Interface Extended Temperature Range: -40C to +125C Small Footprint: 4mm x 4mm QFN Package In addition to the input multiplexer, the ADS8634/8 feature an internal temperature sensor, voltage reference, and a digital comparator for setting alarm thresholds on each input; therefore, a minimal amount of external components are required. A simple SPI-compatible interface provides for communication and control. The digital supply operates from 5V all the way down to 1.8V for direct connection to a wide range of processors and controllers. Ideal for demanding industrial measurement applications, the ADS8634/8 are fully specified over the extended industrial temperature range of -40C to +125C and are available in a small form-factor QFN-24 package. APPLICATIONS * * * * Industrial Process Controls (PLC) Data Acquisition Systems High-Speed, Closed-Loop Systems Digital Power Supplies HVDD AVDD REF DVDD HVDD Alarm Threshold REF AIN0 AVDD REF REF AIN0 DVDD Alarm Threshold AIN1 Comparator AIN1 AL_PD Comparator AIN2 AL_PD AIN3 MUX AIN2 MUX AIN4 ADC SPI AIN3 CS, SCLK, DIN, DOUT ADC AIN5 SPI AIN6 CS, SCLK, DIN, DOUT AIN7 ADS8634 Temp Sensor ADS8638 Temp Sensor AINGND AINGND HVSS AGND REFGND DGND HVSS AGND REFGND DGND 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011, Texas Instruments Incorporated ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DEVICE COMPARISON (1) PRODUCT RESOLUTION ADS8634 12-Bit ADS8638 (1) CHANNELS SAMPLE RATE 4 1MSPS 8 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range, unless otherwise noted. (1) VALUE UNIT AINn to AGND or AINGND to AGND HVSS - 0.3 to HVDD + 0.3 V AVDD to AGND or DVDD to DGND -0.3 to 7 V HVDD to AGND -0.3 to 18 V HVSS to AGND -18 to 0.3 V HVDD to HVSS -0.3 to 33 V Digital input voltage to DGND -0.3 to DVDD + 0.3 V Digital output to DGND -0.3 to DVDD + 0.3 V Operating temperature range -40 to +125 C Storage temperature range -65 to +150 C Human body model (HBM) 2000 V Charged device model (CDM) 500 V ESD ratings, all pins (1) 2 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond those specified in the Electrical Characteristics table is not implied. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS: ADS8634, ADS8638 Minimum/maximum specifications at TA = -40C to +125C, fSAMPLE = 1MSPS, HVDD = 10V to 15V, HVSS = -10V to -15V, AVDD = 4.75V to 5.25V, DVDD = 2.7V to 3.6V, and VREF = 2.5V, unless otherwise noted. Typical specifications at +25C, fSAMPLE = 1MHz, HVDD = 10V, HVSS = -10V, AVDD = 3.3V, DVDD = 3.3V, and VREF = 2.5V, unless otherwise noted. ADS8634, ADS8638 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Bipolar ranges, VREF = 2.5V Full-scale input span (1) Unipolar ranges, VREF = 2.5V AINx absolute input range AINGND absolute input range V 5 V 10 V 0 to 5 V 0 to 10 V HVSS HVDD -0.2 0.2 Input capacitance Input leakage current 2.5 At +125C V V 8 pF 200 nA 12 Bits SYSTEM PERFORMANCE Resolution No missing codes 12 Bits Integral linearity -1.5 +0.9/-0.9 1.5 LSB (2) Differential linearity -1.0 +0.9/-0.5 1.6 LSB -3 0.8 3 Offset error (3) Offset error drift 0.75 Gain error (5) -8 Gain error drift Noise At FFCh output code with 250mVPP and 480Hz ripple on AVDD Power-supply rejection Isolation crosstalk Crosstalk Crosstalk on channel 0 with channel 0 permanently selected, 2kHz full-scale sine wave on channel 1, all other channels grounded Crosstalk on channel 0, 2kHz full-scale sine wave on channel 1, Memory crosstalk all other channels grounded, device scans channel 0 and channel 1 alternately 2 LSB ppmFS/C ( 4) 8 LSB 1.2 ppm/C 0.33 LSB -87 dB -110 dB -81 dB SAMPLING DYNAMICS Conversion time At 20MHz SCLK, DVDD = 2.7V to 5.25V Acquisition time AVDD = 2.7V to 5.25V Maximum throughput rate At 20MHz SCLK, DVDD = 2.7V to 5.25V 750 ns 250 ns 1 1 MSPS Aperture delay 13 ns Step response 250 ns (1) (2) (3) (4) (5) Ideal input span; does not include gain or offset error. LSB means least significant bit. Measured relative to an ideal full-scale input. ppmFS/C is drift measured in parts per million of full-scale range per degree centigrade. Does not include reference drift. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 3 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS: ADS8634, ADS8638 (continued) Minimum/maximum specifications at TA = -40C to +125C, fSAMPLE = 1MSPS, HVDD = 10V to 15V, HVSS = -10V to -15V, AVDD = 4.75V to 5.25V, DVDD = 2.7V to 3.6V, and VREF = 2.5V, unless otherwise noted. Typical specifications at +25C, fSAMPLE = 1MHz, HVDD = 10V, HVSS = -10V, AVDD = 3.3V, DVDD = 3.3V, and VREF = 2.5V, unless otherwise noted. ADS8634, ADS8638 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC CHARACTERISTICS Total harmonic distortion (6) (THD) Signal-to-noise ratio (SNR) Signal-to-noise and distortion ratio (SINAD) Spurious-free dynamic range (SFDR) At 1kHz -81 dB At 100kHz -80 dB 71.8 dB 71.1 dB 71.3 dB At 100kHz 70.5 dB At 1kHz -83 dB At 100kHz -80 At 1kHz 71 At 100kHz At 1kHz 70.1 At -3dB Full-power bandwidth dB 1 MHz DIGITAL INPUT/OUTPUT Logic family CMOS VIH Logic level V 0.7 DVDD V VIL 0.3 DVDD VOH With 20pF load on SDO VOL With 20pF load on SDO 0.8 DVDD V V 0.2 DVDD V 3.0 or AVDD, whichever is less V 1.2 % EXTERNAL VOLTAGE REFERENCE Reference input voltage range VREF 2.0 INTERNAL VOLTAGE REFERENCE Reference output voltage 2.5 -1.2 Initial accuracy Temperature drift 20 Drive current, source (7) Drive current, sink Driver output impedance Turn-on settling time V With 10F decoupling capacitor from REF to REFGND ppm/C 750 A 20 A 1 9 ms 5 % of FSR INTERNAL TEMPERATURE SENSOR Absolute accuracy (6) (7) 4 Calculated on the first nine harmonics of the input frequency. Internal reference output is short-circuit protected. In case of short-circuit to ground, the drive current is limited to this value. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS: ADS8634, ADS8638 (continued) Minimum/maximum specifications at TA = -40C to +125C, fSAMPLE = 1MSPS, HVDD = 10V to 15V, HVSS = -10V to -15V, AVDD = 4.75V to 5.25V, DVDD = 2.7V to 3.6V, and VREF = 2.5V, unless otherwise noted. Typical specifications at +25C, fSAMPLE = 1MHz, HVDD = 10V, HVSS = -10V, AVDD = 3.3V, DVDD = 3.3V, and VREF = 2.5V, unless otherwise noted. ADS8634, ADS8638 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VAVDD 2.7 3.3 5.25 V VDVDD 1.65 3.3 5.25 V POWER-SUPPLY REQUIREMENTS Supply voltage VHVDD 10V < VHVDD - VHVSS < 30V 5 10 15 V VHVSS 10V < VHVDD - VHVSS < 30V -15 -10 0 V IAVDD(dynamic) AVDD supply current IAVDD(static) At VAVDD = 2.7V to 3.6V and 1MHz throughput, normal mode with internal reference and temperature sensor off 2.5 At VAVDD = 4.75V to 5.25V and 1MHz throughput, normal mode with internal reference and temperature sensor off 3.1 At VAVDD = 2.7V to 3.6V and SCLK off, normal mode with internal reference and temperature sensor off mA 3.6 mA 1.45 mA At VAVDD = 4.75V to 5.25V and SCLK off, normal mode with internal reference and temperature sensor off 1.5 IAVDD(ref) (8) At VAVDD = 2.7V to 5.25V, additional AVDD current with internal reference on and temperature sensor off 180 A IAVDD(temp) (9) At VAVDD = 2.7V to 5.25V, additional AVDD current with internal temperature sensor on and internal reference off 400 A HVDD supply current IHVDD(dynamic) HVDD = 15V and 1MSPS throughput 270 IHVDD(static) HVDD = 15V and device static with SCLK off HVSS supply current IHVSS(dynamic) HVSS = -15 V and 1MSPS throughput IHVSS(static) HVSS = -15V and device static with SCLK off IDVDD DVDD = 3.3V, fSAMPLE = 1MSPS, DOUT load = 20pF DVDD supply current (10) mA A 350 A 5 A 520 5 A 2.5 mA SCLK off, internal reference and temperature sensor off 10 A SCLK on, internal reference and temperature sensor off 160 A HVDD current 5 A HVSS current 5 A AVDD current Power-down state 1.9 TEMPERATURE RANGE -40 Specified performance C +125 (8) Add IAVDD(ref) to IAVDD(dynamic) or IAVDD(static)(as applicable), if internal reference is selected. (9) Add IAVDD(temp) to IAVDD(dynamic) or IAVDD(static)(as applicable), if internal temperature sensor is enabled. (10) IDVDD consumes only dynamic current. IDVDD = CLOAD x VDVDD x number of 0 1 transitions in DOUT x fSAMPLE. IDVDD is a load-dependent current; there is no current when the output is not toggling. THERMAL INFORMATION ADS8634/8RGE THERMAL METRIC (1) RGE UNITS 24 PINS JA Junction-to-ambient thermal resistance 32.6 JCtop Junction-to-case (top) thermal resistance 30.5 JB Junction-to-board thermal resistance 3.3 JT Junction-to-top characterization parameter 0.4 JB Junction-to-board characterization parameter 9.3 JCbot Junction-to-case (bottom) thermal resistance 2.6 (1) C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 5 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION TIMING DIAGRAM 1/fSAMPLE tsu(CS-SCLK) CS 1R 1F 2 3 4 5 12 13 14 15 16R 16F SCLK th(SCLK-DOUT) tw(SCLK_H) td(SCLK-DOUT) td(CS-DO) tw(SCLK_L) td(CS-DOHZ) DOUT tsu(DIN-SCLK) th(SCLK-DIN) DIN Acquisition (Internal) t(ACQ) tc Table 1. Timing Requirements (1) (2) (3) TEST CONDITIONS PARAMETER tc Conversion time t(ACQ) Acquisition time td(CS-DO) Delay time, CS low to first data (D0 to D15) out ADS8634, ADS8638 MIN MAX UNIT DVDD = 1.8V 15 SCLK DVDD = 3V 15 SCLK DVDD = 5V 15 SCLK DVDD = 1.8V 250 ns DVDD = 3V 250 ns DVDD = 5V 250 Setup time, CS low to first SCLK rising edge td(SCLK-DOUT) Delay time, SCLK falling to DOUT 52.5 ns DVDD = 3V 40.0 ns 30.5 ns DVDD = 1.8V 26.0 ns DVDD = 3V 18.5 ns DVDD = 5V 15.5 td(CS-DOHZ) (1) (2) (3) 6 Delay time CS high to DOUT high-z ns DVDD = 1.8V 51.5 ns DVDD = 3V 33.0 ns 25.3 ns DVDD = 5V th(SCLK-DOUT) Hold time, SCLK falling to DOUT valid ns DVDD = 1.8V DVDD = 5V tsu(CS-SCLK) TYP DVDD = 1.8V 5.5 ns DVDD = 3V 5.0 ns DVDD = 5V 4.7 ns DVDD = 1.8V 7.3 31.0 ns DVDD = 3V 6.4 22.0 ns DVDD = 5V 5.9 16.4 ns All specifications at -40C to +125C, unless otherwise noted. 1.8V specifications apply from 1.65V to 1.95V; 3V specifications apply from 2.7V to 3.6V; and 5V specifications apply from 4.75V to 5.25V. With 20pF load on DOUT. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Table 1. Timing Requirements(1)(2)(3) (continued) PARAMETER tsu(DIN-SCLK) th(SCLK-DIN) tW(SCLK_H) tW(SCLK_L) fSCLK Setup time, DIN valid to SCLK rising edge Hold time, SCLK rising to DIN valid Pulse duration, SCLK high Pulse duration, SCLK low SCLK frequency ADS8634, ADS8638 TEST CONDITIONS MIN DVDD = 1.8V 7.0 ns DVDD = 3V 6.0 ns TYP MAX DVDD = 5V 5.0 ns DVDD = 1.8V 9.0 ns DVDD = 3V 8.0 ns DVDD = 5V 7.0 ns DVDD = 1.8V 25 ns DVDD = 3V 20 ns DVDD = 5V 20 ns DVDD = 1.8V 25 ns DVDD = 3V 20 ns DVDD = 5V 20 ns DVDD = 1.8V 16 MHz DVDD = 3V 20 MHz DVDD = 5V 20 MHz DVDD = 1.8V fSAMPLE Sampling frequency UNIT 0.84 MSPS DVDD = 3V 1 MSPS DVDD = 5V 1 MSPS POWER-UP TIMING REQUIREMENTS CS 1 2 16 1 2 16 1 2 16 1 2 16 SCLK AL_PD Programmed as PD Power-Down State (Internal) DOUT Td(PWRUP) Power-Down Invalid Data Power-Up Delay Invalid Data Active Invalid Data Valid Data Valid Data Table 2. TIMING REQUIREMENTS (1) ADS8634, ADS8638 PARAMETER td(PWRUP) (2) (1) (2) MIN TYP MAX UNIT Power-up delay from first CS after power-up command 1 s Invalid conversions after device is active (powered up) 1 Conversion All specifications at -40C to +125C, unless otherwise noted. Power-up time excludes internal reference and temperature sensor. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 7 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com PIN CONFIGURATIONS REF REFGND AL_PD DVDD DGND DOUT 24 23 22 21 20 19 RGE PACKAGE 4mm x 4mm QFN-24 (TOP VIEW) AVDD 1 18 DIN AGND 2 17 SCLK AGND 3 16 CS NC 4 15 HVSS AINGND 5 14 HVDD NC 6 13 NC 7 8 9 10 11 12 NC AIN3 AIN2 AIN1 AIN0 NC Thermal Pad (Bottom Side) Figure 1. ADS8634 Pin Configuration ADS8634 PIN ASSIGNMENTS 8 PIN NUMBER NAME FUNCTION 1 AVDD Analog power supply Analog power supply DESCRIPTION 2, 3 AGND Analog power supply Analog ground 4, 6, 7, 12, 13 NC -- 5 AINGND Input 8 AIN3 Analog input Analog input channel 3 9 AIN2 Analog input Analog input channel 2 10 AIN1 Analog input Analog input channel 1 11 AIN0 Analog input Analog input channel 0 14 HVDD High-voltage power supply High-voltage positive supply for multiplexer channels 15 HVSS High-voltage power supply High-voltage negative supply for multiplexer channels 16 CS Digital input Chip select input 17 SCLK Digital input Serial clock input 18 DIN Digital input Serial data input 19 DOUT Digital output Serial data output 20 DGND Digital power supply Digital ground 21 DVDD Digital power supply Digital I/O supply These pins are not internally connected; do not float these pins. It is recommended to connect these pins to AGND. Common for all analog input channels; acts as ground sense terminal Digital output Active high, output indicates alarm (programmed as an output pin) Digital input Active low, asynchronous power-down. The device features an internal, weak pull-up resistor from the AL_PD pin to DVDD. The AL_PD pin can also be floated when programmed as a power-down input. (The default condition for this pin is programmed as a power-down input pin.) 22 AL_PD 23 REFGND Analog input Reference ground input to device when an external reference is selected. This pin acts as a reference decoupling ground terminal when an internal reference is selected. 24 REF Analog input Reference input to device when an external reference is selected. This pin acts as a reference decoupling terminal when an internal reference is selected. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com REF REFGND AL_PD DVDD DGND DOUT 24 23 22 21 20 19 RGE PACKAGE 4mm x 4mm QFN-24 (TOP VIEW) AVDD 1 18 DIN AGND 2 17 SCLK AGND 3 16 CS NC 4 15 HVSS AINGND 5 14 HVDD AIN7 6 13 AIN0 7 8 9 10 11 12 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 Thermal Pad (Bottom Side) Figure 2. ADS8638 Pin Configuration ADS8638 PIN ASSIGNMENTS PIN NUMBER NAME FUNCTION 1 AVDD Analog power supply Analog power supply DESCRIPTION 2, 3 AGND Analog power supply Analog ground 4 NC -- 5 AINGND Input 6 AIN7 Analog input Analog input channel 7 7 AIN6 Analog input Analog input channel 6 8 AIN5 Analog input Analog input channel 5 9 AIN4 Analog input Analog input channel 4 10 AIN3 Analog input Analog input channel 3 11 AIN2 Analog input Analog input channel 2 12 AIN1 Analog input Analog input channel 1 13 AIN0 Analog input Analog input channel 0 14 HVDD High-voltage power supply High-voltage positive supply for multiplexer channels 15 HVSS High-voltage power supply High-voltage negative supply for multiplexer channels 16 CS Digital input Chip select input 17 SCLK Digital input Serial clock input 18 DIN Digital input Serial data input 19 DOUT Digital output Serial data output 20 DGND Digital power supply Digital ground 21 DVDD Digital power supply Digital I/O supply This pin is not internally connected; do not float this pin. It is recommended to connect this pin to AGND. Common for all analog input channels; acts as ground sense terminal Digital output Active high, output indicating alarm (programmed as an output pin) Digital input Active low, asynchronous power-down (programmed as an input pin, default condition) 22 AL_PD 23 REFGND Analog input Reference ground input to device when an external reference is selected. This pin acts as reference decoupling ground terminal when an internal reference is selected. 24 REF Analog input Reference input to device when an external reference is selected. This pin acts as reference decoupling terminal when an internal reference is selected. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 9 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS At TA = +25C, internal reference = 2.5V, channel 0, range = 2.5V, AVDD = 2.7V, DVDD = 1.8V, HVDD = 10V, HVSS = -10V, and fSAMPLE = 1MSPS, unless otherwise noted. DNL vs SIGNAL RANGE Differential Nonlinearity (LSB) Differential Nonlinearity (LSB) DNL vs ANALOG SUPPLY VOLTAGE 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 2.7 Maximum DNL Minimum DNL 3.2 3.7 4.2 AVDD (V) 4.7 5.2 5.7 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 2.5V Maximum DNL Minimum DNL 5V G013 Figure 3. Differential Nonlinearity (LSB) Differential Nonlinearity (LSB) Minimum DNL 2.2 2.4 2.6 Reference Voltage (V) 2.8 3 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 Minimum DNL 0 1 G015 3 4 Channel Number 5 6 7 G016 DNL vs POSITIVE HIGH-VOLTAGE SUPPLY Differential Nonlinearity (LSB) Differential Nonlinearity (LSB) 2 Figure 6. DNL vs FREE-AIR TEMPERATURE Maximum DNL Minimum DNL 5 20 35 50 65 80 Free-Air Temperature (C) 95 110 125 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 2.5 G017 Figure 7. 10 G014 Maximum DNL Figure 5. 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -40 -25 -10 0-10V DNL vs CHANNEL NUMBER Maximum DNL 2 0-5V Figure 4. DNL vs REFERENCE VOLTAGE 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 10V Signal Range Maximum DNL Minimum DNL 5 7.5 10 12.5 HVDD, Positive High-Voltage Supply (V) 15 G018 Figure 8. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, internal reference = 2.5V, channel 0, range = 2.5V, AVDD = 2.7V, DVDD = 1.8V, HVDD = 10V, HVSS = -10V, and fSAMPLE = 1MSPS, unless otherwise noted. INL vs ANALOG SUPPLY VOLTAGE INL vs SIGNAL RANGE 1.5 1.5 1.2 Maximum INL Integral Nonlinearity (LSB) Integral Nonlinearity (LSB) 1.2 0.9 0.6 0.3 0 Minimum INL -0.3 -0.6 -0.9 -1.2 Maximum INL 0.9 0.6 0.3 0 Minimum INL -0.3 -0.6 -0.9 -1.2 -1.5 2.7 3.2 3.7 4.2 AVDD (V) 4.7 5.2 -1.5 2.5V 5.7 5V 10V Signal Range G019 Figure 9. INL vs REFERENCE VOLTAGE INL vs CHANNEL NUMBER 1.2 Maximum INL Integral Nonlinearity (LSB) Integral Nonlinearity (LSB) G020 1.5 1.2 0.9 0.6 0.3 0 Minimum INL -0.3 -0.6 -0.9 -1.2 Maximum INL 0.9 0.6 0.3 0 Minimum INL -0.3 -0.6 -0.9 -1.2 2 2.2 2.4 2.6 Reference Voltage (V) 2.8 -1.5 3 0 1 G021 Figure 11. INL vs FREE-AIR TEMPERATURE Maximum INL 1.2 0.6 0.3 0 Minimum INL -0.6 -0.9 -1.2 -1.5 -40 -25 -10 5 6 7 G022 INL vs POSITIVE HIGH-VOLTAGE SUPPLY 0.9 -0.3 3 4 Channel Number 1.5 Integral Nonlinearity (LSB) 1.2 2 Figure 12. 1.5 Integral Nonlinearity (LSB) 0-10V Figure 10. 1.5 -1.5 0-5V Maximum INL 0.9 0.6 0.3 0 -0.3 Minimum INL -0.6 -0.9 -1.2 5 20 35 50 65 80 Free-Air Temperature (C) 95 110 125 -1.5 2.5 G023 Figure 13. 5 7.5 10 12.5 HVDD, Positive High-Voltage Supply (V) 15 G024 Figure 14. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 11 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, internal reference = 2.5V, channel 0, range = 2.5V, AVDD = 2.7V, DVDD = 1.8V, HVDD = 10V, HVSS = -10V, and fSAMPLE = 1MSPS, unless otherwise noted. OFFSET ERROR vs ANALOG SUPPLY VOLTAGE OFFSET ERROR vs SIGNAL RANGE 2.5 2 2 1.5 1.5 Offset Error (LSB) Offset Error (LSB) 2.5 1 0.5 0 -0.5 -1 -1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2 -2.5 2.7 3.2 3.7 4.2 AVDD (V) 4.7 5.2 -2.5 2.5V 5.7 5V G025 Figure 15. OFFSET ERROR vs REFERENCE VOLTAGE G026 OFFSET ERROR vs CHANNEL NUMBER 2 2 1.5 1.5 Offset Error (LSB) Offset Error (LSB) 0-10V 2.5 1 0.5 0 -0.5 -1 -1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2 -2.5 -2.5 2 2.2 2.4 2.6 Reference Voltage (V) 2.8 3 0 1 G027 2 3 4 Channel Number 5 6 7 G028 Figure 17. Figure 18. OFFSET ERROR vs FREE-AIR TEMPERATURE OFFSET ERROR vs POSITIVE HIGH-VOLTAGE SUPPLY 2.5 2.5 2 2 1.5 1.5 Offset Error (LSB) Offset Error (LSB) 0-5V Figure 16. 2.5 1 0.5 0 -0.5 -1 -1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 -40 -25 -10 -2 5 20 35 50 65 80 Free-Air Temperature (C) 95 110 125 -2.5 2.5 G029 Figure 19. 12 10V Signal Range 5 7.5 10 12.5 HVDD, Positive High-Voltage Supply (V) 15 G030 Figure 20. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, internal reference = 2.5V, channel 0, range = 2.5V, AVDD = 2.7V, DVDD = 1.8V, HVDD = 10V, HVSS = -10V, and fSAMPLE = 1MSPS, unless otherwise noted. GAIN ERROR vs SIGNAL RANGE 8 6 6 4 4 Gain Error (LSB) Gain Error (LSB) GAIN ERROR vs ANALOG SUPPLY VOLTAGE 8 2 0 -2 2 0 -2 -4 -4 -6 -6 -8 2.7 3.2 3.7 4.2 AVDD (V) 4.7 5.2 -8 2.5V 5.7 5V 10V Signal Range G031 Figure 21. 6 4 4 Gain Error (LSB) Gain Error (LSB) 6 2 0 -2 2 0 -2 -4 -4 -6 -6 2.2 G032 GAIN ERROR vs CHANNEL NUMBER 8 2.4 2.6 Reference Voltage (V) 2.8 -8 3 0 1 G033 2 3 4 Channel Number 5 6 7 G034 Figure 23. Figure 24. GAIN ERROR vs FREE-AIR TEMPERATURE GAIN ERROR vs POSITIVE HIGH-VOLTAGE SUPPLY 8 8 6 6 4 4 Gain Error (LSB) Gain Error (LSB) GAIN ERROR vs REFERENCE VOLTAGE 2 0-10V Figure 22. 8 -8 0-5V 2 0 -2 2 0 -2 -4 -4 -6 -6 -8 -40 -25 -10 5 20 35 50 65 80 Free-Air Temperature (C) 95 110 125 -8 2.5 G035 Figure 25. 5 7.5 10 12.5 HVDD, Positive High-Voltage Supply (V) 15 G036 Figure 26. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 13 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, internal reference = 2.5V, channel 0, range = 2.5V, AVDD = 2.7V, DVDD = 1.8V, HVDD = 10V, HVSS = -10V, and fSAMPLE = 1MSPS, unless otherwise noted. SNR vs SIGNAL RANGE 72 71.8 71.8 Signal-to-Noise Ratio (dB) Signal-to-Noise Ratio (dB) SNR vs ANALOG SUPPLY VOLTAGE 72 71.6 71.4 71.2 71 70.8 70.6 70.4 70.2 71.6 71.4 71.2 71 70.8 70.6 70.4 70.2 70 2.7 3.2 3.7 4.2 AVDD (V) 4.7 5.2 70 2.5V 5.7 5V G037 Figure 27. 71.8 71.8 71.6 71.4 71.2 71 70.8 70.6 70.4 70.2 G038 71.6 71.4 71.2 71 70.8 70.6 70.4 70.2 2 2.2 2.4 2.6 Reference Voltage (V) 2.8 70 3 0 1 G039 Figure 29. 3 4 Channel Number 5 6 7 G040 SNR vs POSITIVE HIGH-VOLTAGE SUPPLY 72 71.8 71.8 Signal-to-Noise Ratio (dB) 72 71.6 71.4 71.2 71 70.8 70.6 70.4 70.2 70 -40 -25 -10 2 Figure 30. SNR vs FREE-AIR TEMPERATURE Signal-to-Noise Ratio (dB) 0-10V SNR vs CHANNEL NUMBER 72 Signal-to-Noise Ratio (dB) Signal-to-Noise Ratio (dB) SNR vs REFERENCE VOLTAGE 71.6 71.4 71.2 71 70.8 70.6 70.4 70.2 5 20 35 50 65 80 Free-Air Temperature (C) 95 110 125 70 2.5 G041 Figure 31. 14 0-5V Figure 28. 72 70 10V Signal Range 5 7.5 10 12.5 HVDD, Positive High-Voltage Supply (V) 15 G042 Figure 32. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, internal reference = 2.5V, channel 0, range = 2.5V, AVDD = 2.7V, DVDD = 1.8V, HVDD = 10V, HVSS = -10V, and fSAMPLE = 1MSPS, unless otherwise noted. SNR vs INPUT FREQUENCY SINAD vs ANALOG SUPPLY VOLTAGE 72 Signal-to-Noise and Distortion (dB) 72 Signal-to-Noise Ratio (dB) 71.8 71.6 71.4 71.2 71 70.8 70.6 70.4 70.2 70 0 15 30 45 60 75 fIN, Input Frequency (kHz) 90 71.8 71.6 71.4 71.2 71 70.8 70.6 70.4 70.2 70 2.7 105 3.2 G043 Figure 33. SINAD vs SIGNAL RANGE 5.2 5.7 G044 SINAD vs REFERENCE VOLTAGE Signal-to-Noise and Distortion (dB) Signal-to-Noise and Distortion (dB) 4.7 72 71.8 71.6 71.4 71.2 71 70.8 70.6 70.4 70.2 70 2.5V 5V 10V Signal Range 0-5V 71.5 71 70.5 70 69.5 69 68.5 68 0-10V 2 2.2 G045 Figure 35. 2.4 2.6 Reference Voltage (V) 2.8 3 G046 Figure 36. SINAD vs CHANNEL NUMBER SINAD vs FREE-AIR TEMPERATURE 72 Signal-to-Noise and Distortion (dB) 72 Signal-to-Noise and Distortion (dB) 4.2 AVDD (V) Figure 34. 72 71.5 71 70.5 70 69.5 69 68.5 68 3.7 0 1 2 3 4 Channel Number 5 6 7 71.5 71 70.5 70 69.5 69 68.5 68 -40 -25 -10 G047 Figure 37. 5 20 35 50 65 80 Free-Air Temperature (dB) 95 110 125 G048 Figure 38. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 15 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, internal reference = 2.5V, channel 0, range = 2.5V, AVDD = 2.7V, DVDD = 1.8V, HVDD = 10V, HVSS = -10V, and fSAMPLE = 1MSPS, unless otherwise noted. SINAD vs POSITIVE HIGH-VOLTAGE SUPPLY SINAD vs INPUT FREQUENCY 72 Signal-to-Noise and Distortion (dB) Signal-to-Noise and Distortion (dB) 72 71.5 71 70.5 70 69.5 69 68.5 68 2.5 5 7.5 10 12.5 HVDD, Positive High-Voltage Supply (V) 71.5 71 70.5 70 69.5 69 68.5 68 15 0 15 G049 30 45 60 75 fIN, Input Frequency (kHz) Figure 39. THD vs ANALOG SUPPLY VOLTAGE Total Harmonic Distortion (dB) Total Harmonic Distortion (dB) -83 -83.5 -84 -84.5 -85 -85.5 -86 -86.5 3.7 4.2 AVDD (V) 4.7 5.2 5.7 -75 -76 -77 -78 -79 -80 -81 -82 -83 -84 -85 -86 -87 2.5V 5V G051 Figure 41. 2.2 2.4 2.6 Reference Voltage (V) 2.8 3 Total Harmonic Distortion (dB) -75 -76 -77 -78 -79 -80 -81 -82 -83 -84 -85 -86 -87 0 1 G053 Figure 43. 16 0-5V 0-10V G052 THD vs CHANNEL NUMBER Total Harmonic Distortion (dB) 2 10V Signal Range Figure 42. THD vs REFERENCE VOLTAGE -75 -76 -77 -78 -79 -80 -81 -82 -83 -84 -85 -86 -87 G050 THD vs SIGNAL RANGE -82.5 3.2 105 Figure 40. -82 -87 2.7 90 2 3 4 Channel Number 5 6 7 G054 Figure 44. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, internal reference = 2.5V, channel 0, range = 2.5V, AVDD = 2.7V, DVDD = 1.8V, HVDD = 10V, HVSS = -10V, and fSAMPLE = 1MSPS, unless otherwise noted. THD vs POSITIVE HIGH-VOLTAGE SUPPLY -75 -83 -84 -85 -86 -87 -40 -25 -10 Total Harmonic Distortion (dB) Total Harmonic Distortion (dB) THD vs FREE-AIR TEMPERATURE -75 -76 -77 -78 -79 -80 -81 -82 5 20 35 50 65 80 Free-Air Temperature (C) 95 -77 -79 -81 -83 -85 -87 2.5 110 125 5 7.5 10 12.5 HVDD, Positive High-Voltage Supply (V) G055 Figure 45. SFDR vs ANALOG SUPPLY VOLTAGE 88 Spurious-Free Dynamic Range (dB) Total Harmonic Distortion (dB) THD vs INPUT FREQUENCY 0 15 30 45 60 75 fIN, Input Frequency (kHz) 90 87.5 87 86.5 86 85.5 85 84.5 84 2.7 105 3.2 G057 Figure 47. 5V 10V Signal Range 4.2 AVDD (V) 4.7 5.2 5.7 G058 SFDR vs REFERENCE VOLTAGE Spurious-Free Dynamic Range (dB) 88 87.5 87 86.5 86 85.5 85 84.5 84 83.5 83 82.5 82 2.5V 3.7 Figure 48. SFDR vs SIGNAL RANGE Spurious-Free Dynamic Range (dB) G056 Figure 46. -75 -76 -77 -78 -79 -80 -81 -82 -83 -84 -85 -86 -87 15 0-5V 0-10V 88 87.5 87 86.5 86 85.5 85 84.5 84 83.5 83 82.5 82 2 G059 Figure 49. 2.2 2.4 2.6 Reference Voltage (V) 2.8 3 G060 Figure 50. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 17 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, internal reference = 2.5V, channel 0, range = 2.5V, AVDD = 2.7V, DVDD = 1.8V, HVDD = 10V, HVSS = -10V, and fSAMPLE = 1MSPS, unless otherwise noted. SFDR vs CHANNEL NUMBER SFDR vs FREE-AIR TEMPERATURE 88 Spurious-Free Dynamic Range (dB) Spurious-Free Dynamic Range (dB) 88 87.5 87 86.5 86 85.5 85 84.5 84 0 1 2 3 4 Channel Number 5 6 87 86 85 84 83 82 -40 -25 -10 7 G061 5 20 35 50 65 80 Free-Air Temperature (C) Figure 51. SFDR vs POSITIVE HIGH-VOLTAGE SUPPLY SFDR vs INPUT FREQUENCY Spurious-Free Dynamic Range (dB) Spurious-Free Dynamic Range (dB) 87 86 85 84 83 5 7.5 10 12.5 HVDD, Positive High-Voltage Supply (V) 89 88 87 86 85 84 15 0 15 G063 30 45 60 75 fIN, Input Frequency (kHz) 90 105 G064 Figure 53. Figure 54. CROSSTALK vs INPUT FREQUENCY ANALOG SUPPLY CURRENT (Dynamic) vs ANALOG SUPPLY VOLTAGE 3.5 AVDD Dynamic Current (mA) -70 Memory Crosstalk -80 Crosstalk (dB) G062 90 82 2.5 -90 Isolation Crosstalk -100 -110 0 15 30 45 60 75 fIN, Input Frequency (kHz) 90 105 3 2.5 2 1.5 HVDD = 15V HVSS = -15V 1 2.7 3.2 G065 Figure 55. 18 110 125 Figure 52. 88 -120 95 3.7 4.2 AVDD (V) 4.7 5.2 5.7 G001 Figure 56. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, internal reference = 2.5V, channel 0, range = 2.5V, AVDD = 2.7V, DVDD = 1.8V, HVDD = 10V, HVSS = -10V, and fSAMPLE = 1MSPS, unless otherwise noted. ANALOG SUPPLY CURRENT (Dynamic) vs FREE-AIR TEMPERATURE ANALOG SUPPLY CURRENT (Dynamic) vs SAMPLE RATE 3.5 2.4 AVDD Dynamic Current (mA) AVDD Dynamic Current (mA) HVDD = 15V HVSS = -15V 2.35 2.3 2.25 2.2 -40 -25 -10 5 20 35 50 65 80 Free-Air Temperature (C) 95 1 0.5 0 0.2 0.4 0.6 0.8 fSAMPLE, Sample Rate (MSPS) 1 G003 Figure 58. ANALOG SUPPLY CURRENT (Static) vs ANALOG SUPPLY VOLTAGE POSITIVE HIGH-VOLTAGE SUPPLY CURRENT (Dynamic) vs ANALOG SUPPLY VOLTAGE 0.5 HVDD Dynamic Current (mA) AVDD Static Current (mA) 1.5 Figure 57. HVDD = 15V HVSS = -15V 1.6 1.4 1.2 3.2 3.7 4.2 AVDD (V) 4.7 5.2 0.45 0.4 0.35 0.3 0.25 0.2 2.7 5.7 3.2 G004 3.7 4.2 AVDD (V) 4.7 5.2 5.7 G005 Figure 59. Figure 60. POSITIVE HIGH-VOLTAGE SUPPLY CURRENT (Dynamic) vs FREE-AIR TEMPERATURE POSITIVE HIGH-VOLTAGE SUPPLY CURRENT (Dynamic) vs POSITIVE HIGH-VOLTAGE SUPPLY 0.5 0.45 1 HVDD = 15V HVSS = -15V HVDD Dynamic Current (mA) HVDD Dynamic Current (mA) 2 G002 1.8 1 2.7 2.5 0 110 125 HVDD = 15V HVSS = -15V 3 0.4 0.35 0.3 0.25 0.2 -40 -25 -10 5 20 35 50 65 80 Free-Air Temperature (C) 95 110 125 HVDD = 15V HVSS = -15V 0.8 0.6 0.4 0.2 0 5 G006 Figure 61. 7 9 11 13 HVDD, Positive High-Voltage Supply (V) 15 G007 Figure 62. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 19 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, internal reference = 2.5V, channel 0, range = 2.5V, AVDD = 2.7V, DVDD = 1.8V, HVDD = 10V, HVSS = -10V, and fSAMPLE = 1MSPS, unless otherwise noted. POSITIVE HIGH-VOLTAGE SUPPLY CURRENT (Dynamic) vs SAMPLE RATE NEGATIVE HIGH-VOLTAGE SUPPLY CURRENT (Dynamic) vs ANALOG SUPPLY VOLTAGE -0.2 HVDD = 15V HVSS = -15V HVSS Dynamic Current (mA) HVDD Dynamic Current (mA) 0.5 0.4 0.3 0.2 0.1 0 0 0.2 0.4 0.6 0.8 fSAMPLE, Sample Rate (MSPS) -0.25 -0.3 -0.35 -0.4 -0.45 -0.5 2.7 1 3.2 3.7 G008 4.2 AVDD (V) 4.7 5.2 5.7 G009 Figure 63. Figure 64. NEGATIVE HIGH-VOLTAGE SUPPLY CURRENT (Dynamic) vs FREE-AIR TEMPERATURE NEGATIVE HIGH-VOLTAGE SUPPLY CURRENT (Dynamic) vs NEGATIVE HIGH-VOLTAGE SUPPLY -0.3 0 -0.05 HVSS Dynamic Current (mA) HVSS Dynamic Current (mA) HVDD = 15V -0.35 -0.4 -0.45 -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 -0.4 -0.45 -0.5 -40 -25 -10 5 20 35 50 65 80 Free-Air Temperature (C) 95 -0.5 -15 110 125 -12 -9 -6 -3 HVSS, Negative High-Voltage Supply (V) G010 Figure 65. DNL HVDD = 15V HVSS = -15V Differential Nonlinearity (LSB) HVSS Dynamic Current (mA) 0 -0.1 -0.2 -0.3 -0.4 0 0.2 0.4 0.6 0.8 fSAMPLE, Sample Rate (MSPS) 1 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 512 G012 Figure 67. 20 G011 Figure 66. NEGATIVE HIGH-VOLTAGE SUPPLY CURRENT (Dynamic) vs SAMPLE RATE -0.5 0 1024 1536 2048 2560 3072 ADC Output Code (LSB) 3584 4095 G066 Figure 68. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, internal reference = 2.5V, channel 0, range = 2.5V, AVDD = 2.7V, DVDD = 1.8V, HVDD = 10V, HVSS = -10V, and fSAMPLE = 1MSPS, unless otherwise noted. INL SPECTRAL RESPONSE 1.5 0.9 0.6 Amplitude (dB) Integral Nonlinearity (LSB) 1.2 0.3 0 -0.3 -0.6 -0.9 -1.2 -1.5 0 512 1024 1536 2048 2560 3072 ADC Output Code (LSB) 3584 4095 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 50 G067 100 150 200 250 300 350 400 450 500 fIN, Input Frequency (kHz) G068 Figure 69. Figure 70. TEMPERATURE SENSOR OUTPUT vs FREE-AIR TEMPERATURE 3900 ADC, Output Code 3875 3850 3825 3800 3775 3750 3725 3700 -40 -25 -10 5 20 35 50 65 80 Free-Air Temperature (C) 95 110 125 G069 Figure 71. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 21 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com OVERVIEW The ADS8634 and ADS8638 are 12-bit, 4- and 8-channel devices, respectively. The ADS8634/8 feature software-selectable bipolar and unipolar ranges, an internal reference with an option to use an external reference, and an internal temperature sensor. Independent power-down control for the internal reference and temperature sensor blocks allows for optimal power based on application. The following sections describe the individual blocks and operation. MULTIPLEXER AND ANALOG INPUT The ADS8634/8 feature single ended inputs with ground sense and a 4-/8-channel, single-pole multiplexer, respectively. The ADC samples the difference voltage between analog input pins AINx and the ground sense pin AINGND. The ADS8634/8 can scan these analog inputs in either manual or auto-scan mode. In manual mode, the channel is selected for every sample via a register write; in auto-scan mode, the channel number is incremented automatically on every CS falling edge after the present channel is sampled. It is possible to select the analog inputs for an auto scan with register settings. The devices automatically scan only the selected analog inputs in ascending order. The ADS8634/8 offer multiple software-programmable ranges 10V, 5V, 2.5V, 0V to 5V, and 0V to 10V with a 2.5V reference. Any of these ranges can be assigned to any analog input (for instance, 10V can be assigned to AIN1, 2.5V to AIN2, 0V to 10V can be assigned to AIN3, and so on). During a scan (either auto or manual), the programmed signal range is assigned to the selected channel. The range selection, however, can be temporarily overridden using the DIN line for a particular scan. This feature is useful for zooming into a narrow range when needed. Refer to Table 11 for configuration register settings. 22 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com Figure 72 shows electrostatic discharge (ESD) diodes connected to the HVDD and HVSS supplies. Make sure these diodes do not turn on by keeping the analog inputs within the specified range. HVDD AIN0 HVSS HVDD Temperature Sensor AIN1 HVSS SAR ADC HVDD AIN3/7 HVSS HVDD AINGND HVSS Figure 72. Analog Inputs Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 23 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com The ADS8634/8 sample the voltage difference (VAINx - VAINGND) between the selected analog input channel and the AINGND pin. The ADS8634/8 allow a 0.2V range on AINGND. This feature is useful in modular systems where the sensor/signal conditioning block is removed from the ADC and when there could be a difference in the ground potential of the sensor/signal condioner from the ADC ground. In such cases, it is recommended to run separate wires from the AINGND terminal of the device to the sensor/signal conditioner ground. REFERENCE The ADS8634/8 measure the analog input signals relative to the voltage reference using either an internal precision 2.5V voltage reference (Figure 73) or an external voltage reference (Figure 74). Binary-weighted capacitors are switched onto the reference terminal during conversion. The switching frequency is the same as the SCLK frequency. Whether it is an internal or external reference, be sure to decouple the REF terminal to REFGND with a 10F capacitor. Place the capacitor close to the REFP and REFGND pins. AVDD AGND Internal Reference Configuration Register REF 10 F REFGND ADC Figure 73. Operation Using The Internal Reference (Refer to Table 11 for more details on the configuration register settings) AVDD AGND Internal Reference AVDD Plane Configiguration Register REF REF30/50xx 1 F REFGND AGND Plane ADC Figure 74. Operation Using an External Reference (Refer to Table 11 for more details on the configiguration register settings) 24 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com These devices allow the use of an external reference in the range of 2.0V to 3.0V. The nominal input ranges 10V, 5V, 2.5V, 0V to 5V, and 0V to 10V assume a 2.5V reference; a different reference voltage scales the full-scale ranges proportionately. For example, if a 3.0V reference is used and the 10V range is selected, the actual input range is scaled by (3.0/2.5) for a full-scale range of 12V. The internal reference can be enabled/disabled through the configuration register. The reference block is powered down when the internal reference is disabled. Ensure that the internal reference is disabled when the external reference is connected. The external reference is the default selection after power-on or reset. TEMPERATURE SENSOR The ADS8634/8 feature an on-chip temperature sensoras shown in Figure 75. The device temperature can be read at any time during a scan, either in auto or manual mode.There are three registers associated with the temperature sensor operation. The temperature sensor can be enabled/disabled through the Aux-Config configuration register. Disabling the temperature sensor powers down the temperature block. It is necessary to enable (power up) the temperature sensor at least one cycle before the device temperature sensor is selected with the channel sequencing control registers (manual/auto). This selection overrides the input channel scan sequence and range selection and connects the ADC input to an internal temperature sensor. The temperature sensor must be deselected with channel sequencing control registers (manual/auto) to resume normal scanning. In case of auto-sequencing, the device starts scanning from where it left off before the temperature measurement. The temperature sensor is disabled by default after power-on or reset. AVDD AGND Config Reg Ch Seq Control Reg Temp Sensor AIN0 AIN1 AIN2 ADC AIN3/7 AINGND Figure 75. Reading the ADS8634/8 Temperature (Refer to Table 11 for more details on configuration register settings) The temperature sensor transfer function follows a straight line, as shown in Equation 1: Output Code = mREFx Device Temperature in C + CREF (1) Equation 1 can be re-written as Equation 2: Device Temperature in C = (Output Code - CREF)/mREF where: mREF = the slope, and CREF = the offset (in ADC output code) of the temperature sensor transfer function (2) Both mREF and CREF change with the reference voltage. The initial values of mREF and CREF at a 2.5V reference are: mREF_2.5 = 0.47 and CREF_2.5 = 3777.2 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 25 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com Values of mREF and CREF for any reference voltage other than 2.5V can be calculated using Equation 3 and Equation 4: mREF = mREF_2.5 x 2.5/VREF CREF = (CREF_2.5 - 3584) x 2.5/VREF + 3584 (3) (4) For example, at a 2V reference: mREF_2 = 0.47 x 2.5/2 = 0.59 and CREF_2 = (3777.2 - 3584) x 2.5/2 + 3584 = 3825.5 For the reference voltage used, Equation 2 can be rewritted using mREF and CREF as calculated in Equation 3 and Equation 4. Table 3 can be used as quick reference for temperature sensor transfer function at typical reference values. Table 3. Temperature Sensor Transfer Function at Typical Reference Values REFERENCE VOLTAGE (V) TRANSFER FUNCTION 2 Device temperature in C = (output code - 3825.5)/0.59 2.5 Device temperature in C = (output code - 3777.2)/0.47 3 Device temperature in C = (output code - 3745.0)/0.39 DATA FORMAT The ADS8634/8 output 12-bits of ADC conversion results in binary format (MSB first) for all ranges, as shown in Table 4. Figure 76 shows the ADC transfer function for bipolar signal ranges. The unipolar range output is shown in Table 5 and Figure 77 shows the transfer function. Table 4. Bipolar Range Ideal Output Codes (1) INPUT SIGNAL (AINx - AINGND) 10V RANGE (V) 5V RANGE (V) 2.5V RANGE (V) 10 x (211- 1)/211 (2) 5 x (211- 1)/211 2.5 x (211- 1)/211 11 (1) (2) 11 IDEAL OUTPUT CODE FFFh 11 10/2 5/2 0 0 2.5/2 0 801h 800h -10 /211 -5/211 -2.5/211 7FFh -10 x (211- 1)/211 -5 x (211- 1)/211 -2.5 x (211- 1)/211 000h Excludes noise, offset and gain errors. LSB size for the bipolar ranges = positive (or negative) full-scale/211. The ADS8634/8 offer 12-bit resolution across the entire range from positive full-scale to negative full-scale; in other words, the resolution for half range from '0' to positive (or negative) full-scale is 11 bits. For example, a 1LSB for a 10V range is 10/211. Table 5. Unipolar Range Ideal Output Codes (1) INPUT SIGNAL (AINx - AINGND) 0V TO 10V RANGE (V) 12 12 10 x (2 - 1)/2 (1) 26 0V TO 5V RANGE (V) IDEAL OUTPUT CODE 12 FFFh 12 5 x (2 - 1)/2 10/212 5/212 001h < 10/212 < 5/212 000h Excludes noise, offset and gain errors. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com ADC Code FFFh 800h 001h Negative FSR + 1LSB Positive FSR 1LSB 0 Analog Input (AINx AINGND) Figure 76. Transfer Function for Bipolar Signal Ranges ADC Code FFFh 800h 001h 1LSB FSR/2 Analog Input (AINx FSR - 1LSB AINGND) Figure 77. Transfer Function for Unipolar Signal Ranges Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 27 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com AL_PD: USER-CONFIGURABLE PIN The ADS8634/8 feature a user-configurable AL_PD pin. This pin can either be configured as an alarm output (AL) or as a power-down control pin (PD). Refer to the Page 0, Register Descriptions for the ADS8638 and Page 0, Register Descriptions for the ADS8634 sections for details. When programmed as an alarm output, an active-high alarm is flagged on this pin if there is a high or low alarm on any channel. The Alarm Functionality section describes the pin details. When programmed as PD, the AL_PD pin functions as an active-low power-down input pin. Powering down through this pin is asynchronous. The devices power down immediately after the pin goes low. The Power-Down Functionality section describes the pin details. This pin is configured as a PD input by default after power-on or reset. Alarm Functionality The ADS8634/8 output an active-high alarm on the AL_PD pin when it is programmed as an AL. AL is synchronous and changes its state on the 16th SCLK rising edge. A high level on AL indicates there is an active alarm on one or more channels. This pin can be wired to interrupt the host input. When an alarm interrupt is received, the alarm flag registers are read to determine which channels have an alarm. The ADS8634/8 feature independently-programmable alarms for each channel. There are two alarms per channel (low and high alarm) and each alarm threshold has a separate hysteresis setting. The ADS8634/8 set a high alarm when the digital output for a particular channel exceeds the high alarm upper limit (high alarm threshold T + hysteresis H). The alarm resets when the digital output for the channel is less than or equal to the high alarm lower limit (high alarm T - H). This function is shown in Figure 78. Alarm H_ALARM On H_ALARM Off (T - H) (T + H + 1) ADC Output NOTE: T = alarm threshold and H = hysteresis. Figure 78. High-Alarm Hysteresis Similarly, the lower alarm is triggered when the digital output for a particular channel falls below the low alarm lower limit (low alarm threshold T - H). The alarm resets when the digital output for the channel is greater than or equal to the low alarm higher limit (low alarm T + H). This function is shown in Figure 79. Alarm L_ALARM On L_ALARM Off (T - H - 1) (T + H) ADC Output NOTE: T = alarm threshold and H = hysteresis. Figure 79. Low-Alarm Hysteresis 28 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com All Channel H/L Alarms Figure 80 shows a functional block diagram for a single-channel alarm. For each high and low alarm there are two flags: Active Alarm Flag and Tripped Alarm Flag; refer to the Alarm Flags for the ADS8638 (Read-Only) and Alarm Flags for the ADS8634 (Read-Only) sections for more details. The active alarm flag is triggered when an alarm condition is encountered for a particular channel; the active alarm flag resets when the alarm shuts off. A tripped alarm flag sets an alarm condition in the same manner as it does for an active alarm flag; however, it remains latched and resets only when the appropriate alarm flag register is read. Alarm Threshold Channel n +/Hysteresis Channel n AL_PD Programmed as Alarm Output Active Alarm Flag Channel n + ADC Output Channel n 16th SCLK S Q R Q Tripped Alarm Flag Channel n Alarm Flag Read SDO ADC Figure 80. Alarm Functionality Power-Down Functionality The ADS8634/8 feature a power-down/up control through the programmable AL_PD pin or the channel sequencing control registers; see the Channel Sequencing Control Registers for the ADS8638 and Channel Sequencing Control Registers for the ADS8634 sections for more details. This feature is extremely useful for saving power while running the ADS8634/8 at a slower speed, or for acquiring data at full-speed in bursts and then waiting in a power-down state for the next acquisition start event. Figure 81 through Figure 84 describe entry to and exit from the power-down state. The AL_PD pin can be programmed as a power-down control pin. The AL_PD pin, when programmed as PD, is shown in Figure 81. A low on AL_PD powers down the device immediately; this action is asynchronous operation. Data on DOUT are not valid when the device is in a power-down state. AL_PD Programmed as PD Power-Down State (Internal) Active Power-Down DOUT Valid data terminates on power down. Figure 81. Power-Down Using the AL_PD Pin Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 29 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com A high level on AL_PD acts as a power-up request and the power-up sequence begins on the next CS falling edge. The device is active after td(PWRUP). The first valid acquisition initiates in the first data frame (with a CS falling edge) after a power-up delay. The first valid data are presented in the second data frame after the device attains an active state, as shown in Figure 82. CS 1 2 16 1 2 16 1 2 16 1 2 16 SCLK AL_PD Programmed as PD Power-Down State (Internal) Td(PWRUP) Power-Down DOUT Power-Up Delay Invalid Data Active Invalid Data Invalid Data Valid Data Valid Data Figure 82. Power-Up Via the AL_PD Pin The power-down/up operation can also be controlled with register settings. See the Channel Sequencing Control Registers for the ADS8638 and Channel Sequencing Control Registers for the ADS8634 sections for details. Figure 83 illustrates power-down and power-up commands for quick reference. CS 1 2 15 16 SCLK DIN Power-Down Command Power-Down State (Internal) Power-Down Active DOUT Valid Data Figure 83. Power-Down Via Register Write After receiving a valid power-down command, the device enters a power-down state on 16th SCLK falling edge. An example of this command is given in Table 6. Table 6. Power-Down Command Example RD/ WR REGISTER ADDRESS PIN DIN Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 0 0 0 0 1 Auto/manual sequence 30 0 Bit 9 X DATA Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 X X X 1 1 1 X W 0 X X X Submit Documentation Feedback Power-down X Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com The serial interface is active even during a device power-down state. Commands can be issued via the DIN pin during a power-down state. A power-up command (through DIN) is acknowledged on the next CS falling edge and a power-up sequence initiates. An example of this command is given in Table 7. The device is in an active state after td(PWRUP) and initiates a valid acquisition in the first data frame (initiated with a CS falling edge) after a power-up delay. The first valid data are presented in the second data frame after the device attains an active state, as shown in Figure 84. Table 7. Power-Up Command Example RD/ WR REGISTER ADDRESS PIN DIN Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 0 0 0 0 1 0 DATA Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 X 0 0 X X X Any combination from 000 to 110, except 111 X W 0 X X X Power-up X 16 1 Auto/manual sequence Bit 3 Bit 2 Bit 1 Bit 0 CS 1 2 16 1 2 2 16 1 2 16 1 2 16 SCLK Operation Commands Except Power-Down Command DIN Power-Up Command Operation Command Operation Command Operation Command Operation Command td(PWRUP) Power-Down State (Internal) DOUT Power-Down Invalid Data Power-Up Delay Invalid Data Active Invalid Data Valid Data Valid Data Figure 84. Power-Up Via Register Write Use only one method (DIN pin or register settings) for power-down/up control. Do not combine these two methods or the results may be confusing. Do not issue a power-down command through DIN while using the AL_PD pin. Similarly, do not pull the AL_PD pin low while using the register write method for power-down/up control. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 31 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com DEVICE OPERATION The ADS8634/8 are 12-bit, 4-/8-channel devices. Each frame begins with a CS falling edge. The ADS8634/8 sample the input signal from the selected channel on the CS falling edge and initiate conversion. SCLK is used for conversion and data are output on the DOUT line while conversion is in process. The 16-bit data word contains a 4-bit channel address followed by the 12-bit conversion result in MSB-first format. The MSB of the 4-bit channel address is output on the CS falling edge; the remaining address bits are clocked out serially for three SCLK falling edges. The MSB of the 12-bit conversion result is output on the fourth SCLK falling edge. Afterwards, the next lower data bits are ouput serially on every subsequen SCLK falling edge. Each data bit can be read (latched) immediately on the next SCLK falling edge from the SCLK falling edge on which the respective data bits are output. For example, if the MSB of a 12-bit data word is output on the fourth SCLK falling edge then the same word can be latched on the fifth SCLK falling edge. Refer to the Hold time, SCLK falling to DOUT valid, and Delay time, SCLK falling to DOUT parameters in the Timing Requirements section. The 16-bit word is read on the DIN pin while the data are output on the DOUT pin. DIN data are latched on every SCLK rising edge, starting with the first clock, as shown in Figure 85. Sample n Sample n + 1 CS 1 4 8 12 15 16 SCLK DOUT A3 A0 D11 Ch Address DIN B15 ADC Phase (Internal) D0 A3 B0 B15 Conversion Result For Sample n Conversion n Acquisition n+1 Conversion n+1 AL_PD (Programmed as an alarm Figure 85. ADS8634/8 Operation Device configuration and operation mode are controlled through register settings. It is recommended to write to the configuration registers after powering on the device. The configuration information is retained until the devices are powered off or reset. Note that powering down the device with either the AL_PD pin or a register write does not erase the device configuration. The ADS8634/8 feature an AL_PD pin that functions as a alarm output/power-down pin. The pin can be programmed as an alarm output (AL) or it can be programmed as a power-down control pin (PD). When AL_PD is programmed as an alarm output, it is refreshed on every 16th SCLK rising edge. 32 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com CHANNEL SEQUENCING MODES The ADS8634/8 offer two channel sequencing modes: auto and manual. In auto-scan mode, the channel number automatically increments every frame. In manual mode, the channel is selected for every frame of a register write. The analog inputs can be selected for an automatic scan with a register setting. The device automatically scans only the selected analog inputs in ascending order. The auto-mode sequence can be reset at any time during an automatic scan (refer to the Auto register in the PAGE-0 Register Map for the ADS8638 section ). When the reset command has been received, the ongoing auto-mode sequence is reset and restarts it from the lowest selected channel in the sequence. Figure 86 shows the DIN command sequence for transitions from auto to manual mode. Figure 87 shows the DIN command sequence for transitions from manual to auto-scan mode. Note that each DIN command is executed on the next CS falling edge. Ch 5 Sample Ch 0 Sample Ch 5 Sample Ch 1 Sample Ch 0 Sample CS SCLK DOUT DIN Ch 5 Data Ch 0 Data Ch 5 Data Ch 1 Data Ch 0 Data Auto/0000h Man Ch 1 Man Ch 0 Man Ch 3 Man Ch 7 Ch 0 Ch 5 Ch 1 Ch 0 Ch 3 Selected Channel Auto Scan Manual Scan Figure 86. Transition from Auto to Manual Mode (Channels 0 and 5 are selected for auto sequence) Ch n 1 Sample Ch n Sample Ch 3 Sample Ch 2 Sample Ch 5 Sample CS SCLK DOUT DIN Selected Channel Ch n Data Ch 3 Data Ch 2 Data Ch 5 Data Man Ch3 Auto 0000h 0000h 0000h Ch n Ch 3 Ch 2 Ch 5 Ch 2 Ch n 1 Data Manual Scan Auto Scan Figure 87. Transition from Manual to auto-scan mode (Channels 2 and 5 are selected for auto sequence) Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 33 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com DEVICE TEMPARATURE READ The ADS8634/8 feature an internal temperature sensor. The device temperature can be read at any time during any scan. It is essential to enable (power-up) the internal temperature at least one cycle before selecting the temperature sensor for the device temperature measurement. The temperature sensor must be deselected after temperature measurement. The device resumes the channel sequence from where it left the scan after deselection of the temperature sensor. Do not disable (power-down) the temperature sensor before it is deselected. Figure 88 illustrates a typical command sequence for device temperature measurement during an auto scan. Ch 3 Sample Ch 0 Sample Ch 3 Sample Ch 0 Sample Temperature Sample CS SCLK DOUT Ch 3 Data Ch 0 Data Ch 3 Data DIN Auto/0000h Aux (TS Enable) Sel Temp Sensor Ch 0 Ch 3 Ch 0 Selected Channel Auto Scan Ch 0 Data Temp Data Deselect Temp Sensor Auto/0000h Temp Sensor Ch 3 Temp Sensor Auto Scan Figure 88. Reading Temperature During Auto Scan (Channels 0 and 3 are selected for auto sequence) SPI INTERFACE The ADS8634/8 employ a four-wire SPI-compatible interface. Apart from the interface, CS and SCLK also perform an ADC control function. The data frame is synchronized with the CS falling edge. A low level on CS releases the DOUT pin from three-state and the ADC conversion results are output on the DOUT line. Data bits are clocked out on the falling edges of SCLK. The ADS8634/8 sample the analog input signal on the falling edge of CS and conversion is performed using SCLK. DOUT is the serial data output line. Depending on register settings,the ADC conversion results are output along with the selected channel address or register data on the DOUT pin. The data output frame always consists of 16 bits. The SDO line goes to three-state after all the 16-bits of data frame are output or after CS goes high. DIN is a serial data input line. It is used to program various registers for either device configuration or for dynamic changes applicable on the next immediate CS falling edge. 34 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com DOUT DATA FORMAT The device outputs 16-bit data in every cycle. Table 8 shows the DOUT data format. Table 8. DOUT Data Format CHANNEL ADDRESS CONVERSION RESULT PIN Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DOUT ADDR 3 ADDR 2 ADDR 1 ADDR 0 D11 (MSB) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) Bit Description for the ADS8638 DOUT Data Bits[15:12] Channel/temperature sensor address These bits represent the adress of channel or temperature sensor. 0000 = Channel 0 0001 = Channel 1 0010 = Channel 2 0011 = Channel 3 0100 = Channel 4 0101 = Channel 5 0110 = Channel 6 0111 = Channel 7 1111 = Temperature sensor Bits[11:0] Conversion result for the channel/temperature sensor represented by bits[15:12], in MSB-first format Bit Description for the ADS8634 DOUT Data Bits[15:12] Channel/temperature sensor address These bits represent the adress of channel or temperature sensor. 000X = Channel 0 001X = Channel 1 010X = Channel 2 011X = Channel 3 1111 = Temperature sensor Bits[11:0] Conversion result for the channel/temperature sensor represented by bits[15:12], in MSB-first format Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 35 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com DIN DATA FORMAT (SPI COMMAND WORD) Device registers can be written to and read from. There must be a minimum of 16 SCLKs after the CS falling edge for any read or write operation. The device receives the command (as shown in Table 9 and Table 10) through DIN where the first seven bits (bits[15:9]) represent the register address and the eighth bit (bit 8) is the read/write instruction. For a write cycle, the next eight bits (bits[7:0]) in the DIN are the desired data for the addressed register (Table 9). For a read cycle, the next eight bits (bits[7:0]) in the DIN are don't care. DOUT outputs the 8-bit data from the addressed register (Table 10) during these eight clocks, corresponding to bits[7:0]. Table 9. Write Cycle Command Word RD/ WR REGISTER ADDRESS DATA PIN Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DIN ADDR 6 ADDR 5 ADDR 4 ADDR 3 ADDR 2 ADDR 1 ADDR 0 R/W DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 Table 10. Read Cycle Command Word RD/ WR REGISTER ADDRESS DATA PIN Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DIN ADDR 6 ADDR 5 ADDR 4 ADDR 3 ADDR 2 ADDR 1 ADDR 0 R/W X X X X X X X X DOUT X X X X X X X X DOUT 7 DOUT 6 DOUT 5 DOUT 4 DOUT 3 DOUT 2 DOUT 1 DOUT 0 36 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com SPI REGISTER WRITE CYCLE Figure 89 shows a timing diagram of the SPI write cycle. The device executes the command on the first CS falling edge after a command write cycle. The only exception to this command execution timing is the power-down command. The power-down command (through a register write) is executed on the 16th falling edge of SCLK. This falling edge occurs immediately after the last command bit is written to the device. CS SCLK DIN A6 A5 A0 W D7 D6 D1 D0 DOUT Figure 89. Write Cycle SPI REGISTER READ CYCLE Figure 90 shows a timing diagram of the SPI read cycle. CS SCLK DIN A6 A5 DOUT A0 R D7 D6 D1 D0 D7 D6 D1 D0 Figure 90. Read Cycle Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 37 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com REGISTER MAP: ADS8638 The ADS8638 internal registers are mapped in two pages: page 0 and page 1. Page 0 is selected by default at power-up and after reset. Any register read/write operation performed while on page 0 addresses the page 0 registers. Writing 01h to register address 7Fh selects page 1 for any further register operations. Page 0 registers are used to select the channel sequencing mode, program the configuration registers, and read the alarm flags. Page 1 resisters are used to program alarm thresholds for each channel and for the temperature sensor. Table 11 details page 0 and Table 12 details page 1. Table 11. ADS8638 Page 0 Register Map REGISTER REGISTER ADDRESS BITS[15:9] DEFAULT VALUE (1) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Channel Sequencing Control Registers Manual 04h 00h 0 Auto 05h 00h Reset-Seq Channel Select[2:0] 0 0 0 Range Select[2:0] Sel Temp Sensor Range Select[2:0] Sel Temp Sensor Holding the DIN line low continuously (equivalent to writing '0' to all 16 bits) during device operation as per Figure 85 continues device operation in the last selected mode (auto or manual). Configuration Registers Reset-Device 01h 00h 0 0 0 0 0 0 0 Reset-Dev Temp Sensor Enable 0 Sel Ch6 Sel Ch7 0 0 AL_PD Control Int VREF Enable Sel Ch2 Sel Ch3 Sel Ch4 Sel Ch5 Aux-Config 06h 08h 0 0 Auto-Md Ch-Sel 0Ch 00h Sel Ch0 Sel Ch1 Ch0-1 Range 10h 11h 0 Range Select Ch0[2:0] 0 Range Select Ch1[2:0] Ch2-3 Range 11h 11h 0 Range Select Ch2[2:0] 0 Range Select Ch3[2:0] Ch4-5 Range 12h 11h 0 Range Select Ch4[2:0] 0 Range Select Ch5[2:0] Ch6-7 Range 13h 11h 0 Range Select Ch6[2:0] 0 Range Select Ch7[2:0] Temp-Flag 20h 00h Tripped Alarm Flag Temperature Low Tripped Alarm Flag Temperature High Active Alarm Flag Temperature Low Active Alarm Flag Temperature High 0 0 0 0 Ch0-3 Tripped-Flag 21h 00h Tripped Alarm Flag Ch0 Low Tripped Alarm Flag Ch0 High Tripped Alarm Flag Ch1 Low Tripped Alarm Flag Ch1 High Tripped Alarm Flag Ch2 Low Tripped Alarm Flag Ch2 High Tripped Alarm Flag Ch3 Low Tripped Alarm Flag Ch3 High Ch0-3 Active-Flag 22h 00h Active Alarm Flag Ch0 Low Active Alarm Flag Ch0 High Active Alarm Flag Ch1 Low Active Alarm Flag Ch1 High Active Alarm Flag Ch2 Low Active Alarm Flag Ch2 High Active Alarm Flag Ch3 Low Active Alarm Flag Ch3 High Ch4-7 Tripped-Flag 23h 00h Tripped Alarm Flag Ch4 Low Tripped Alarm Flag Ch4 High Tripped Alarm Flag Ch5 Low Tripped Alarm Flag Ch5 High Tripped Alarm Flag Ch6 Low Tripped Alarm Flag Ch6 High Tripped Alarm Flag Ch7 Low Tripped Alarm Flag Ch7 High Ch4-7 Active-Flag 24h 00h Active Alarm Flag Ch4 Low Active Alarm Flag Ch4 High Active Alarm Flag Ch5 Low Active Alarm Flag Ch5 High Active Alarm Flag Ch6 Low Active Alarm Flag Ch6 High Active Alarm Flag Ch7 Low Active Alarm Flag Ch7 High 7Fh 00h 0 0 0 0 0 0 0 Page Addr Alarm Flag Registerss (Read-Only) Page Selection Register Page (1) 38 All registers are reset to the default values at power-on or at device reset using the register settings method. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com Table 12. ADS8638 Page 1 Register Map REGISTER REGISTER ADDRESS BITS[15:9] DEFAULT VALUE (1) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Alarm Threshold Registers TLA MSB 00h 00h TLA LSB 01h 00h THA MSB 02h 00h THA LSB 03h 00h Ch0LA MSB 04h 00h Ch0LA LSB 05h 00h Ch0HA MSB 06h 00h Ch0HA LSB 07h 00h Ch1LA MSB 08h 00h Ch1LA LSB 09h 00h Ch1 HA MSB 0Ah 00h Ch1 HA LSB 0Bh 00h Ch2 LA MSB 0Ch 00h Ch2 LA LSB 0Dh 00h Ch2 HA MSB 0Eh 00h Ch2 HA LSB 0Fh 00h Ch3 LA MSB 10h 00h Ch3 LA LSB 11h 00h Ch3 HA MSB 12h 00h Ch3 HA LSB 13h 00h Ch4 LA MSB 14h 00h Ch4 LA LSB 15h 00h Ch4 HA MSB 16h 00h Ch4 HA LSB 17h 00h Ch5 LA MSB 18h 00h Ch5 LA LSB 19h 00h Ch5 HA MSB 1Ah 00h Ch5 HA LSB 1Bh 00h Ch6 LA MSB 1Ch 00h Ch6 LA LSB 1Dh 00h Ch6 HA MSB 1Eh 00h Ch6 HA LSB 1Fh 00h Ch7 LA MSB 20h 00h Ch7 LA LSB 21h 00h Ch7 HA MSB 22h 00h Ch7 HA LSB 23h 00h 7Fh 00h TLA Hysteresis[3:0] TLA[11:8] TLA[7:0] THA Hysteresis[3:0] THA[11:8] THA[7:0] Ch0-LA Hysteresis[3:0] Ch0-LA[11:8] Ch0-LA[7:0] Ch0-HA Hysteresis[3:0] Ch0-HA[11:8] Ch0-HA[7:0] Ch1-LA Hysteresis[3:0] Ch1-LA[11:8] Ch1-LA[7:0] Ch1-HA Hysteresis[3:0] Ch1-HA[11:8] Ch1-HA[7:0] Ch2-LA Hysteresis[3:0] Ch2-LA[11:8] Ch2-LA[7:0] Ch2-HA Hysteresis[3:0] Ch2-HA[11:8] Ch2-HA[7:0] Ch3-LA Hysteresis[3:0] Ch3-LA[11:8] Ch3-LA[7:0] Ch3-HA Hysteresis[3:0] Ch3-HA[11:8] Ch3-HA[7:0] Ch4-LA Hysteresis[3:0] Ch4-LA[11:8] Ch4-LA[7:0] Ch4-HA Hysteresis[3:0] Ch4-HA[11:8] Ch4-HA[7:0] Ch5-LA Hysteresis[3:0] Ch5-LA[11:8] Ch5-LA[7:0] Ch5-HA Hysteresis[3:0] Ch5-HA[11:8] Ch5-HA[7:0] Ch6-LA Hysteresis[3:0] Ch6-LA[11:8] Ch6-LA[7:0] Ch6-HA Hysteresis[3:0] Ch6-HA[11:8] Ch6-HA[7:0] Ch7-LA Hysteresis[3:0] Ch7-LA[11:8] Ch7-LA[7:0] Ch7-HA Hysteresis[3:0] Ch7-HA[11:8] Ch7-HA[7:0] Page Selection Register Page (1) 0 0 0 0 0 0 0 Page Addr All registers are reset to the default values at power-on or at device reset using the register settings method. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 39 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com PAGE 0 REGISTER DESCRIPTIONS: ADS8638 This section provides bit-by-bit descriptions of each page 0 register. Channel Sequencing Control Registers for the ADS8638 There are two modes for channel sequencing: auto and manual mode. In auto-scan mode, the device automatically scans the preselected channels in sequential order with a new channel selected for every conversion. In manual mode, the channel is manually selected for the next conversion. In both modes, the preselected signal range is considered for each channel independently. Note that the range can be temporarily overriden. Manual: Manual Mode Register (Address = 04h; Page 0) 7 0 6 5 4 Channel Select[2:0] 3 2 1 Range Select[2:0] 0 Sel Temp Sensor This register selects device operation in manual scan mode, selects the channel for the next conversion, allows the preselected signal range to be temporarily overriden for the next conversion, and enables the device temperature to be read. Bit 7 Must always be set to '0' Bits[6:4] Channel Select[2:0] These bits select the channel for acquisition during the next frame. For example, if this register is written in frame number n, then the addressed channel signal is acquired in frame number n + 1 and the conversion result is available in frame number n + 2. 000 = Channel 0 001 = Channel 1 010 = Channel 2 011 = Channel 3 100 = Channel 4 101 = Channel 5 110 = Channel 6 111 = Channel 7 Bits[3:1] Range Select[2:0] These bits select the signal range for the channel acquired in the next frame. For example, if this register is written in frame number n, then the selected range is applicable for frame number n + 1. This is a dynamic range selection and overrides selection through the configuration registers (address 10h to 13h, page 0) only for the next frame. 000 = Ranges as selected through the configuration registers (address 10h to 13h, page 0) 001 = Range is set to 10V 010 = Range is set to 5V 011 = Range is set to 2.5V 100 = Reserved; do not use this setting 101 = Range is set to 0V to 10V 110 = Range is set to 0V to 5V 111 = Powers down the device immediately after the 16th SCLK falling edge Bit 0 Sel Temp Sensor This bit selects the temperature sensor for acquisition in the next frame. This selection overrides channel selection through bits[6:4]. Range selection is not applicable for the temperature sensor. 0 = Next conversion as per selection through bits[3:1] 1 = The temperature sensor is selected for acquisition in the next frame 40 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com Auto: Auto-Scan Mode Register (Address = 05h; Page 0) 7 Reset-Seq 6 0 5 4 0 0 3 2 1 Range Select[2:0] 0 Sel Temp Sensor This register selects device operation in auto-scan mode, allows the preselected signal range to be temporarily overriden for the next conversion, and enables the device temperature to be read. Bit 7 Reset-Seq This bit resets the auto-mode sequence counter. The counter is reset to the lowest channel number in the selected sequence. For example, if the Auto-Md Ch-Sel register is programmed to 01101100 (the auto-mode sequence channels are 2, 3, 5, 6, 2, 3, 5, 6...2, 3, 5, 6), and, if the Reset-Seq bit is programmed to '1' in frame n while channel 3 is sampled, then the auto-mode sequence counter is reset to channel 2 in frame n + 1. This setting means that channel 2 is sampled instead of channel 5 in frame n + 1. 0 = No reset (continue the sequence from the present channel number) 1 = Reset the channel sequncing counter Bits[6:4] Must always be set to '0' Bits[3:1] Range Select[2:0] These bits select the signal range for the channel acquired in the next frame. For example, if this register is written in frame number n, then the selected range is applicable for frame number n + 1. This is a dynamic range selection and overrides selection through the configuration registers (address 10h to 13h, page 0) only for the next frame. 000 = Ranges as selected through the configuration registers (address 10h to 13h) 001 = Range is set to 10V 010 = Range is set to 5V 011 = Range is set to 2.5V 100 = Reserved; do not use this setting 101 = Range is set to 0V to 10V 110 = Range is set to 0V to 5V 111 = Powers down the device immediately after the 16th SCLK falling edge Bit 0 Sel Temp Sensor This bit selects the temperature sensor for acquisition in the next frame. This selection overrides the channel selection through the auto sequence only for the next frame. The auto-mode sequence continues from where it was interrupted after the temperature sensing frame. For example, if the programmed auto sequence is channels 0, 1, 3, 0, 1, 3...0, 1, 3, and if the temperature sensor is selected in frame number n while channel 0 is sampled, then the temperature sensor is sampled in frame n + 1. The auto sequence resumes from frame n + 2 sampling channel 1. Range selection is not applicable for the temperature sensor. 0 = Next conversion as selected through bits[3:1] 1 = The temperature sensor is selected for acquisition in the next frame Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 41 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com Continued Operation in the Selected Mode for the ADS8638 Holding the DIN line low continuously (equivalent to writing '0' to all 16 bits) during device operation as per Figure 85, continues device operation in the last selected mode (auto or manual). The device follows the range selection from the configuration registers (address 10h to 13h). The the internal temperature sensor continues to be read if the temperature sensor was selected during the last auto/manual mode frame. Configuration Registers for the ADS8638 The configuration registers allow device configuration (signal range selection for individual channels, selection of channels for auto sequence, enabling/disabling of the internal reference and temperature sensor, and configuration of the AL_PD pin as either an alarm output or a power-down input). All registers can be reset to the default values using the configuration register. Reset-Device: Device Reset Register (Address = 01h; Page 0) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Reset-Dev This register resets the device and assigns default values to all internal registers. The reset value for this register is 00h; as a result, this bit is self-clearing. Bits[7:1] Must always be set to '0' Bit 0 Reset-Dev This bit initiates a software reset immediately after the 16th SCLK falling edge. All registers in the device are assigned the reset values mentioned in Table 11 and Table 12. 0 = No reset 1 = Device reset Aux-Config: Device Auxiliary Blocks Enable/Disable Control Register (Address = 06h; Page 0) 7 6 5 4 3 2 1 0 0 0 0 0 AL_PD Control Int VREF Enable Temp Sensor Enable 0 This register controls the functionality of the AL_PD pin and enables/disables blocks such as the internal reference and internal temperature sensor. Bits[7:4] Must always be set to '0' Bit 3 AL_PD Control This bit controls the functionality of the AL_PD pin. 0 = AL_PD pin functions as an alarm output pin 1 = AL_PD pin functions as a power-down control pin Bit 2 Int VREF Enable This bit powers up the internal VREF. 0 = Internal reference block is powered down at the next frame 1 = Internal reference block is powered up at the next frame Bit 1 Temp Sensor Enable This bit powers up the internal temperature sensor. 0 = Internal temperature sensor block is powered down from the next frame 1 = Internal temperature sensor block is powered up from the next frame Bit 0 42 Must always be set to'0' Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com Auto-Md Ch-Sel: Channel Selection Register for Auto-Scan Mode (Address = 0Ch; Page 0) 7 6 5 4 3 2 1 0 Sel Ch0 Sel Ch1 Sel Ch2 Sel Ch3 Sel Ch4 Sel Ch5 Sel Ch6 Sel Ch7 This register selects the channels for the auto-mode sequence. The device scans only the selected channels in ascending order during auto-scan mode, starting with the lowest channel selected. For example, if the Auto-Md Ch-Sel register is programmed to 01100100, then the auto-mode sequence is channels 2, 5, 6, 2, 5, 6...2, 5, 6. In this case, the sequence always starts at channel 2. Channel 0 is selected if this register is programmed to 00000000. Bit 7 Sel Ch0 This bit selects channel 0. 0 = Channel 0 not selected 1 = Channel 0 selected Bit 6 Sel Ch1 This bit selects channel 1. 0 = Channel 1 not selected 1 =Channel 1 selected Bit 5 Sel Ch2 This bit selects channel 2. 0 = Channel 2 not selected 1 = Channel 2 selected Bit 4 Sel Ch3 This bit selects channel 3. 0 = Channel 3 not selected 1 = Channel 3 selected Bit 3 Sel Ch4 This bit selects channel 4. 0 = Channel 4 not selected 1 = Channel 4 selected Bit 2 Sel Ch5 This bit selects channel 5. 0 = Channel 5 not selected 1 = Channel 5 selected Bit 1 Sel Ch6 This bit selects channel 6. 0 = Channel 6 not selected 1 = Channel 6 selected Bit 0 Sel Ch7 This bit selects channel 7. 0 = Channel 7 not selected 1 = Channel 7 selected Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 43 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com Ch0-1 Range to Ch6-7 Range: Range Selection Registers for Channels 0 to 7 (Address = 10h to 13h; Page 0) REGISTER Ch0-1 Range Ch2-3 Range Ch4-5 Range Ch6-7 Range ADDRESS ON PAGE 0 10h 11h 12h 13h Bit 7 0 0 0 0 Bit 6 Range Range Range Range Bit 5 Bit 4 Select Ch0[2:0] Select Ch2[2:0] Select Ch4[2:0] Select Ch6[2:0] Bit 3 0 0 0 0 Bit 2 Range Range Range Range Bit 1 Bit 0 Select Ch1[2:0] Select Ch3[2:0] Select Ch5[2:0] Select Ch7[2:0] A selection of signal ranges are featured for each channel. The selected range is automatically assigned for a channel during conversion, regardless of the channel scan mode (auto or manual). These registers (Ch0-1 Range to Ch6-7 Range) allow for range selection of all channels. Bit 7 Must always be set to '0' Bits[6:4] Range Select Chn[2:0] These bits select the signal range for channel n, where n is 0, 2, 4, or 6, depending on the register address. 000 = Reserved; do not use this setting 001 = Range is set to 10V 010 = Range is set to 5V 011 = Range is set to 2.5V 100 = Reserved; do not use this setting 101 = Range is set to 0V to 10V 110 = Range is set to 0V to 5V 111 = Reserved; do not use this setting Bit 3 Must always be set to '0' Bits[2:0] Range Select Chm[2:0] These bits select the signal range for channel m, where m is 1, 3, 5, or 7, depending on the register address. 000 = Reserved; do not use this setting 001 = Range is set to 10V 010 = Range is set to 5V 011 = Range is set to 2.5V 100 = Reserved; do not use this setting 101 = Range is set to 0V to 10V 110 = Range is set to 0V to 5V 111 = Reserved; do not use this setting 44 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com Alarm Flag Registers for the ADS8638 (Read-Only) The alarm conditions related to individual channels are stored in these registers. The flags can be read when an alarm interrupt is received on the AL_PD pin. There are two types of flag for every alarm: active and tripped. The active flag is set to '1' under the alarm condition (when data cross the alarm limit) and remains so as long as the alarm condition persists. The tripped flag turns on the alarm condition similar to the active flag, but it remains set until it is read. This feature relieves the device from having to track alarms. Temp Flag: Alarm Flags Register for Temperature Sensor (Address = 20h; Page 0) 7 6 5 4 3 2 1 0 Tripped Alarm Flag Temperature Low Tripped Alarm Flag Temperature High Active Alarm Flag Temperature Low Active Alarm Flag Temperature High 0 0 0 0 The Temp Flag register stores the alarm flags for the temperature sensor. There are two alarm thresholds, and for each threshold there are two flags. An active alarm flag is enabled when an alarm is triggered (when data cross the alarm threshold) and remains enabled as long as the alarm condition persists. A tripped alarm flag is enabled in the same manner as an active alarm flag, but it remains latched until it is read. Bit 7 Tripped Alarm Flag Temperature Low This bit indicates the tripped low alarm flag status for the temperature sensor. 0 = No alarm detected 1 = Alarm detected Bit 6 Tripped Alarm Flag Temperature High This bit indicates the tripped high alarm flag status for the temperature sensor. 0 = No alarm detected 1 = Alarm detected Bit 5 Active Alarm Flag Temperature Low This bit indicates the active low alarm flag status for the temperature sensor. 0 = No alarm 1 = Alarm detected Bit 4 Active Alarm Flag Temperature High This bit indicates the active-high alarm flag status for the temperature sensor. 0 = No alarm detected 1 = Alarm detected Bits[3:0] Always read '0' Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 45 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com Ch0-3 Tripped-Flag to Ch4-7 Active-Flag: Alarm Flags Register for Channels 0 to 7 (Address = 21h to 24h; Page 0) REGISTER Ch0-3 TrippedFlag ADDRESS ON PAGE 0 21h Ch0-3 Active-Flag 22h Ch4-7 TrippedFlag 23h Ch4-7 Active-Flag 24h Bit 7 Tripped Alarm Flag Ch0 Low Active Alarm Flag Ch0 Low Tripped Alarm Flag Ch4 Low Active Alarm Flag Ch4 Low Bit 6 Tripped Alarm Flag Ch0 High Active Alarm Flag Ch0 High Tripped Alarm Flag Ch4 High Active Alarm Flag Ch4 High Bit 5 Tripped Alarm Flag Ch1 Low Active Alarm Flag Ch1 Low Tripped Alarm Flag Ch5 Low Active Alarm Flag Ch5 Low Bit 4 Tripped Alarm Flag Ch1 High Active Alarm Flag Ch1 High Tripped Alarm Flag Ch5 High Active Alarm Flag Ch5 High Bit 3 Tripped Alarm Flag Ch2 Low Active Alarm Flag Ch2 Low Tripped Alarm Flag Ch6 Low Active Alarm Flag Ch6 Low Bit 2 Tripped Alarm Flag Ch2 High Active Alarm Flag Ch2 High Tripped Alarm Flag Ch6 High Active Alarm Flag Ch6 High Bit 1 Tripped Alarm Flag Ch3 Low Active Alarm Flag Ch3 Low Tripped Alarm Flag Ch7 Low Active Alarm Flag Ch7 Low Bit 0 Tripped Alarm Flag Ch3 High Active Alarm Flag Ch3 High Tripped Alarm Flag Ch7 High Active Alarm Flag Ch7 High There are two alarm thresholds (high and low) per channel, with two flags for each threshold. An active alarm flag is enabled when an alarm is triggered (when data cross the alarm threshold) and remains enabled as long as the alarm condition persists. A tripped alarm flag is enabled in the same manner as an active alarm flag, but it remains latched until it is read. Registers 21h to 24h on page 0 store the active and tripped alarm flags for all eight channels. Bits[7:0] Active/Tripped Alarm Flag Chn High/Low Each individual bit indicates an active/tripped, high/low alarm flag status for each channel, as per the Alarm Flags Register for channels 0 to 7. 0 = No alarm detected 1 = Alarm detected Page Selection Register for the ADS8638 The registers are arranged on two pages: page 0 and page 1. The page register selects the register page. Page: Page Selection Register (Address = 7Fh; Page 0) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Page Addr Bits[7:1] Must always be set to '0' Bit 0 Page Addr This bit selects the page address. 0 = Selects page 0 for the next register read or write command; all register read/write operations after this are performed on the page 0 registers until page 1 is selected 1 = Selects page 1 for the next register read or write command; all register read/write operations after this are performed on the page 1 registers until page 0 is selected 46 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com PAGE 1 REGISTER DESCRIPTIONS: ADS8638 This section provides bit-by-bit descriptions of each page 1 register. As described earlier, the device registers are mapped to two pages. Page 0 is selected by default at power-up and after reset. Page 1 can be selected by writing 01h to register address 7Fh. After selecting page 1, any register read/write action addresses the page 1 registers. Writing 00h to register address 7Fh selects page 0 for any further register operations. Alarm Threshold Setting Registers for the ADS8638 The ADS8634/8 feature high and low alarms individually for the temperature sensor and each of the eight channels. Each alarm threshold is 12 bits wide with a 4-bit hysteresis. This 16-bit setting is accomplished through two 8-bit registers associated with every high/low alarm. TLA MSB to THA LSB: Temperature Alarm Registers (Address = 00h to 03h; Page 1) REGISTER TLA MSB TLA LSB THA MSB THA LSB ADDRESS ON PAGE 1 Bit 7 Bit 6 Bit 5 TLA Hysteresis[3:0] Bit 4 Bit 3 Bit 2 Bit 1 TLA[11:8] Bit 0 TLA[7:0] THA Hysteresis[3:0] THA[11:8] THA[7:0] THA/LA MSB REGISTER Bits[7:4] THA/LA Hysteresis[3:0] These bits set the temperature high/low alarm hysteresis. 0000 = No hyeteresis 0001 = 1LSB hystetesis 0010 to 1110 = 2LSB to 14LSB hystetesis 1111 = 15LSB hystetesis Bits[3:0] THA/LA[11:8] These bits set the MSB nibble for the 12-bit temperature high/low alarm. For example, the temperature high alarm threshold is AFFh when the THA MSB register (address 02h, page 1) setting is Ah and the THA LSB register (address 03h, page 1) register setting is FFh. 0000 = MSB nibble is 0h 0001 = MSB nibble is 1h 0010 to 1110 = MSB nibble is 2h to Eh 1111 = MSB nibble is Fh THA/LA LSB REGISTER Bits[7:0] THA/LA[7:0] These bits set the LSB byte for the 12-bit temperature high alarm. For example, the temperature low alarm threshold is F02h when the TLA LSB register (address 01h) setting is 02h and the TLS MSB register (address 00h, page 1) register setting is Fh. 0000 0000 = LSB byte is 0h 0000 0001 = LSB byte is 1h 0000 0010 to 1110 1111 = LSB byte is 02h to EFh 1111 1111 = LSB byte is FFh Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 47 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com Ch0LA MSB to Ch7HA LSB: Channels 0 to 7 Alarm Registers (Address = 04h to 23h; Page 1) REGISTER Ch0LA MSB Ch0LA LSB Ch0HA MSB Ch0HA LSB Ch1LA MSB Ch1LA LSB Ch1HA MSB Ch1HA LSB Ch2LA MSB Ch2LA LSB Ch2HA MSB Ch2HA LSB Ch3LA MSB Ch3LA LSB Ch3HA MSB Ch3HA LSB Ch4LA MSB Ch4LA LSB Ch4HA MSB Ch4HA LSB Ch5LA MSB Ch5LA LSB Ch5HA MSB Ch5HA LSB Ch6LA MSB Ch6LA LSB Ch6HA MSB Ch6HA LSB Ch7LA MSB Ch7LA LSB Ch7HA MSB Ch7HA LSB 48 ADDRESS ON PAGE 1 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h Bit 7 Bit 6 Bit 5 Ch0-LA Hysteresis[3:0] Bit 4 Bit 3 Bit 2 Bit 1 Ch0-LA[11:8] Bit 0 Ch0-LA[7:0] Ch0-HA Hysteresis[3:0] Ch0-HA[11:8] Ch0-HA[7:0] Ch1-LA Hysteresis[3:0] Ch1-LA[11:8] Ch1-LA[7:0] Ch1-HA Hysteresis[3:0] Ch1-HA[11:8] Ch1-HA[7:0] Ch2-LA Hysteresis[3:0] Ch2-LA[11:8] Ch2-LA[7:0] Ch2-HA Hysteresis[3:0] Ch2-HA[11:8] Ch2-HA[7:0] Ch3-LA Hysteresis[3:0] Ch3-LA[11:8] Ch3-LA[7:0] Ch3-HA Hysteresis[3:0] Ch3-HA[11:8] Ch3-HA[7:0] Ch4-LA Hysteresis[3:0] Ch4-LA[11:8] Ch4-LA[7:0] Ch4-HA Hysteresis[3:0] Ch4-HA[11:8] Ch4-HA[7:0] Ch5-LA Hysteresis[3:0] Ch5-LA[11:8] Ch5-LA[7:0] Ch5-HA Hysteresis[3:0] Ch5-HA[11:8] Ch5-HA[7:0] Ch6-LA Hysteresis[3:0] Ch6-LA[11:8] Ch6-LA[7:0] Ch6-HA Hysteresis[3:0] Ch6-HA[11:8] Ch6-HA[7:0] Ch7-LA Hysteresis[3:0] Ch7-LA[11:8] Ch7-LA[7:0] Ch7-HA Hysteresis[3:0] Ch7-HA[11:8] Ch7-HA[7:0] Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com CHANNEL N HA/LA MSB REGISTER Bits[7:4] Chn-HA/LA Hysteresis[3:0] These bits set the channel n high/low alarm hysteresis. For example, bits[7:4] of the channel 6 HA MSB register (address 1Eh, page 1) set the channel 6 high alarm hysteresis. 0000 = No hyeteresis 0001 = 1LSB hystetesis 0010 to 1110 = 2LSB to 14LSB hystetesis 1111 = 15-LSB hystetesis Bits[3:0] Chn-HA/LA[11:8] These bits set the MSB nibble for the 12-bit channel n high/low alarm. For example, the channel 7 high alarm threshold is AFFh when bits[3:0] of the channel 7 HA MSB register (address 22h, page 1) are set to Ah and the channel 7 HA LSB (address 23h, page 1) register setting is FFh. 0000 = MSB nibble is 0h 0001 = MSB nibble is 1h 0010 to 1110 = MSB nibble is 2h to Eh 1111 = MSB nibble is Fh CHANNEL N HA/LA LSB REGISTER Bits[7:0] Chn HA[7:0] These bits set the LSB byte for the 12-bit channel n high/low alarm. For example, the channel 2 low alarm threshold is F01h when the channel 2 LA LSB register (address 0Dh, page 1) setting is 01h and bits[3:0] of the channel 2 LA MSB (address 0Ch, page 1) are set to Fh. 0000 0000 = LSB byte is 0h 0000 0001 = LSB byte is 1h 0000 0010 to 1110 1111 = LSB byte is 02h to EFh 1111 1111 = LSB byte is FFh Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 49 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com REGISTER MAP: ADS8634 The ADS8634 internal registers are mapped in two pages: page 0 and page 1. Page 0 is selected by default at power-up and after reset. Any register read/write action while on page 0 addresses the page 0 registers. Writing 01h to register address 7Fh selects page 1 for any further register operations. Page 0 registers are used to select the channel sequencing mode, program the configuration registers, and to read the alarm flags. Page 1 resisters are used to program the alarm thresholds for each channel and for the temperature sensor. Table 13 details page 0 and Table 14 details page 1. Table 13. Page 0 Register Map for the ADS8634 REGISTER REGISTER ADDRESS BITS[15:9] DEFAULT VALUE (1) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Channel Sequencing Control Registers Manual 04h 00h 0 Auto 05h 00h Reset-Seq Channel Select[1:0] 0 0 X (2) Range Select[2:0] Sel Temp Sensor 0 Range Select[2:0] Sel Temp Sensor Holding DIN line continuously (equivalent to writing zero to all sixteen bits) during device operation as per Figure 85 continues device operation in the last selected mode (auto/manual) Configuration Registers Reset-Device 01h 00h 0 0 0 0 0 0 0 Reset-Dev 0 0 AL_PD Control Int VREF Enable Temp Sensor Enable 0 Sel Ch1 X Aux-Config 06h 08h 0 0 Auto-Md Ch-Sel 0Ch 00h Sel Ch0 X Sel Ch2 X Sel Ch3 X Ch0 Range 10h 11h 0 Range Select Ch0[2:0] 0 X X X Ch1 Range 11h 11h 0 Range Select Ch1[2:0] 0 X X X Ch2 Range 12h 11h 0 Range Select Ch2[2:0] 0 X X X Ch3 Range 13h 11h 0 Range Select Ch3[2:0] 0 X X X Temp-Flag 20h 00h Tripped Alarm Flag Temperature Low Tripped Alarm Flag Temperature High Active Alarm Flag Temperature Low Active Alarm Flag Temperature High 0 0 0 0 Ch0-1 Tripped-Flag 21h 00h Tripped Alarm Flag Ch0 Low Tripped Alarm Flag Ch0 High X X Tripped Alarm Flag Ch1 Low Tripped Alarm Flag Ch1 High X X Ch0-1 Active-Flag 22h 00h Active Alarm Flag Ch0 Low Active Alarm Flag Ch0 High X X Active Alarm Flag Ch1 Low Active Alarm Flag Ch1 High X X Ch2-3 Tripped-Flag 23h 00h Tripped Alarm Flag Ch2 Low Tripped Alarm Flag Ch2 High X X Tripped Alarm Flag Ch3 Low Tripped Alarm Flag Ch3 High X X Ch2-3 Active-Flag 24h 00h Active Alarm Flag Ch2 Low Active Alarm Flag Ch2 High X X Active Alarm Flag Ch3 Low Active Alarm Flag Ch3 High X X 7Fh 00h 0 0 0 0 0 0 0 Page Addr Alarm Flags (Read-Only) Page Selection Register Page (1) (2) 50 All registers are reset to the default values at power-on or at device reset using the register settings method. X = don't care. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com Table 14. Page 1 Register Map for the ADS8634 REGISTER REGISTER ADDRESS BITS[15:9] DEFAULT VALUE (1) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Alarm Threshold Registers TLA MSB 00h 00h TLA LSB 01h 00h THA MSB 02h 00h THA LSB 03h 00h Ch0LA MSB 04h 00h Ch0LA LSB 05h 00h Ch0HA MSB 06h 00h Ch0HA LSB 07h 00h No function 08h to 0Bh 00h Ch1LA MSB 0Ch 00h Ch1LA LSB 0Dh 00h Ch1 HA MSB 0Eh 00h Ch1 HA LSB 0Fh 00h No function 10h to 13h 00h Ch2 LA MSB 14h 00h Ch2 LA LSB 15h 00h Ch2 HA MSB 16h 00h Ch2 HA LSB 17h 00h No function 18h to 1Bh 00h Ch3 LA MSB 1Ch 00h TLA Hysteresis[3:0] TLA[11:8] TLA[7:0] THA Hysteresis[3:0] THA[11:8] THA[7:0] Ch0-LA Hysteresis[3:0] Ch0-LA[11:8] Ch0-LA[7:0] Ch0-HA Hysteresis[3:0] Ch0-HA[11:8] Ch0-HA[7:0] X (2) X X X X Ch1-LA Hysteresis[3:0] X X X Ch1-LA[11:8] Ch1-LA[7:0] Ch1-HA Hysteresis[3:0] Ch1-HA[11:8] Ch1-HA[7:0] X X X X X Ch2-LA Hysteresis[3:0] X X X Ch2-LA[11:8] Ch2-LA[7:0] Ch2-HA Hysteresis[3:0] Ch2-HA[11:8] Ch2-HA[7:0] X X X X X Ch3-LA Hysteresis[3:0] X X X Ch3-LA[11:8] Ch3 LA LSB 1Dh 00h Ch3 HA MSB 1Eh 00h Ch3-LA[7:0] Ch3 HA LSB 1Fh 00h No function 20h to 23h 00h X X X X X X X X 7Fh 00h 0 0 0 0 0 0 0 Page Addr Ch3-HA Hysteresis[3:0] Ch3-HA[11:8] Ch3-HA[7:0] Page Selection Register Page (1) (2) All registers are reset to the default values at power-on or at device reset using the register settings method. X = don't care. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 51 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com PAGE 0 REGISTER DESCRIPTIONS (ADS8634) This section provides bit-by-bit descriptions of each page 0 register. As described earlier, the device registers are mapped to two pages: page 0 and page 1. Page 0 is selected by default at power-up and after reset. Any register read/write action while on page 0 addresses the page 0 registers. Writing 01h to register address 7Fh selects page 1 for any further register operations. Channel Sequencing Control Registers for the ADS8634 There are two modes for channel sequencing: auto and manual mode. In auto-scan mode, the device automatically scans the preselected channels in chronological order; a new channel is selected for every conversion. In manual mode, the channel is selected for the next conversion. In both modes, the preselected signal range is considered for each channel independently; however, the range can be temporarily overriden. Manual: Manulal Mode Register (Address = 04h; Page 0) 7 0 (1) 6 5 4 Channel Select[1:0] X (1) 3 2 1 Range Select[2:0] 0 Sel Temp Sensor X = don't care. This register selects device operation in manual scan mode, selects channel for next conversion, allows the preselected signal range for the next conversion to be temporarialy overridden, and enables the device temperature to be read. Bit 7 Must always be set to '0' Bits[6:5] Channel Select[1:0] These bits select the channel for acquisition during the next frame. For example, if this register is written in frame number n, then the addressed channel signal is acquired in frame number n + 1 and the conversion result is available in frame number n + 2. 00 01 10 11 = Channel 0 = Channel 1 = Channel 2 = Channel 3 Bit 4 Don't care (can be 1 or 0); this bit has no function assigned Bits[3:1] Range Select[2:0] These bits select the signal range for the channel acquired in the next frame. For example, if this register is written in frame number n, then the selected range is applicable for frame number n + 1. This is a dynamic range selection and overrides selection through the configuration registers (addresses 10h to 13h, page 0) only for the next frame. 000 = Ranges as selected through the configuration registers (address 10h to 13h, page 0) 001 = Range is set to 10V 010 = Range is set to 5V 011 = Range is set to 2.5V 100 = Reserved; do not use this setting 101 = Range is set to 0V to 10V 110 = Range is set to 0V to 5V 111 = Powers down the device immediately after the 16th SCLK falling edge Bit 0 Sel Temp Sensor This bit selects the temperature sensor for acquisition in the next frame. This selection overrides channel selection through bits[6:4]. Range selection is not applicable for the temperature sensor. 0 = Next conversion as per selection through bits[3:1] 1 = Device selects the temperature sensor for acquisition in the next frame 52 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com Auto: Auto-Scan Mode Register (Address = 05h; Page 0) 7 Reset-Seq 6 0 5 4 0 0 3 2 1 Range Select[2:0] 0 Sel Temp Sensor This register selects device operation in auto-scan mode, allows the preselected signal range for the next conversion to be temporarily overriden, and enables the device temperature to be read. Bit 7 Reset-Seq This bit resets the auto-mode sequence counter. The counter is reset to the lowest channel number in the selected sequence. For example, if the Auto-Md Ch-Sel register is programmed to 01101100 (auto-mode sequence channels 2, 3, 5, 6, 2, 3, 5, 6...2, 3, 5, 6) and, if the auto register bit 7 is programmed to '1' in frame n while channel 3 is sampled, then the auto-mode sequence counter resets to channel 2 in frame n + 1. This setting means channel 2 is sampled instead of channel 5 in frame n + 1. 0 = No reset (continue sequence from the present channel number) 1 = Reset channel sequncing counter Bits[6:4] Must always be set to '0' Bits[3:1] Range Select[2:0] These bits select the signal range for the channel acquired in the next frame. For example, if this register is written in frame number n, then the selected range is applicable for frame number n + 1. This is a dynamic range selection and overrides selection through the configuration registers (address 10h to 13h, page 0) only for the next frame. 000 = Ranges as selected through the configuration registers (addresses 10h to 13h) 001 = Range is set to 10V 010 = Range is set to 5V 011 = Range is set to 2.5V 100 = Reserved; do not use this setting 101 = Range is set to 0V to 10V 110 = Range is set to 0V to 5V 111 = Powers down the device immediately after the 16th SCLK falling edge Bit 0 Sel Temp Sensor This bit selects the temperature sensor for acquisition in the next frame. This selection overrides channel selection through the auto sequence only for the next frame. The auto sequence continues from where it was interrupted after the temperature sensing frame. For example, if the programmed auto sequence is channels 0, 1, 3, 0, 1, 3...0, 1, 3 and, if the temperature sensor is selected in frame number n while channel 0 is sampled, then the temperature sensor is sampled in frame n + 1. The auto sequence resumes from frame n + 2 sampling channel 1. Range selection is not applicable for the temperature sensor. 0 = Next conversion as per selection through bits[3:1] 1 = The temperature sensor is selected for acquisition in the next frame Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 53 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com Continued Operation in the Selected Mode for the ADS8634 Holding the DIN line low continuously (equivalent to writing '0' to all 16 bits) during device operation as per Figure 85 continues device operation in the last selected mode (auto or manual). The device follows range selection through the configuration registers (address 10h to 13h). The internal temperature sensor continues to be read if the temperature sensor was selected during the last auto/manual mode frame. Configuration Registers for the ADS8634 These registers allow device configuration (such as signal range selection for individual channels, selection of channels for auto sequence, enabling/disabling of internal reference and temperature sensor, and configuration of the AL_PD pin as an alarm output or as a power-down input). All of the registers can be reset to the default values using the configuration register. Reset-Device: Device Reset Register (Address = 01h; Page 0) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Reset-Dev This register resets the device and assigns default values to all internal registers. The reset value for this register is 00h; as a result, this bit is self-clearing. Bits[7:1] Must always be set to '0' Bit 0 Reset-Dev This bit initiates a software reset immediately after the 16th SCLK falling edge. All registers in the device are assigned the reset values mentioned in and Table 11 and Table 12. 0 = No reset 1 = Reset device Aux-Config: Device Auxiliary Blocks Enable/Disable Control Register (Address = 06h; Page 0) 7 6 5 4 3 2 1 0 0 0 0 0 AL_PD Control Int VREF Enable Temp Sensor Enable 0 This register controls functionality of the AL_PD pin and enables/disables blocks such as the internal reference and the internal temperature sensor. Bits[7:4] Must always be set to '0' Bit 3 AL_PD Control This bit controls the functionality of the AL_PD pin. 0 = The AL_PD pin functions as an alarm output pin 1 = The AL_PD pin functions as a power-down control pin Bit 2 Int VREF Enable This bit powers up the internal VREF. 0 = Internal reference block is powered down from the next frame 1 = Internal reference block is powered up from the next frame Bit 1 Temp Sensor Enable This bit powers up the internal temperature sensor. 0 = Internal temperature sensor block is powered down from the next frame 1 = Internal temperature sensor block is powered up from the next frame Bit 0 54 Must always be set to '0' Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com Auto-Md Ch-Sel: Channel Selection Registers for Auto-Scan Mode (Address = 0Ch; Page 0) (1) 7 6 5 4 3 2 1 0 Sel Ch0 X (1) Sel Ch1 X Sel Ch2 X Sel Ch3 X X = don't care. This register selects channels for the auto-mode sequence. The device scans only the selected channels in ascending order during auto-scan mode, starting with the lowest channel selected. For example, if the Auto-Md Ch-Sel register is programmed to 01100100, then the auto-mode sequence is channels 2, 5, 6, 2, 5, 6...2, 5, 6, and in this case, the sequence always starts from channel 2. Channel 0 is selected if this register is programmed to 00000000. Bit 7 Sel Ch0 This bit selects channel 0. 0 = Channel 0 not selected 1 = Channel 0 selected Bit 6 Don't care (can be 1 or 0); this bit has no function assigned Bit 5 Sel Ch1 This bit selects channel 1. 0 = Channel 1 not selected 1 = Channel 1 selected Bit 4 Don't care (can be 1 or 0); this bit has no function assigned Bit 3 Sel Ch2 This bit selects channel 2. 0 = Channel 2 not selected 1 = Channel 2 selected Bit 2 Don't care (can be 1 or 0); this bit has no function assigned Bit 1 Sel Ch3 This bit selects channel 3. 0 = Channel 3 not selected 1 = Channel 3 selected Bit 0 Don't care (can be 1 or 0); this bit has no function assigned Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 55 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com Ch0 Range to Ch3 Range: Range Selection Registers for Channels 0 to 3 (Address = 10h to 13h; Page 0) REGISTER Ch0 Range Ch1 Range Ch2 Range Ch3 Range (1) ADDRESS ON PAGE 0 10h 11h 12h 13h Bit 7 0 0 0 0 Bit 6 Range Range Range Range Bit 5 Bit 4 Select Ch0[2:0] Select Ch1[2:0] Select Ch2[2:0] Select Ch3[2:0] Bit 3 0 0 0 0 Bit 2 X (1) X X X Bit 1 X X X X Bit 0 X X X X X = don't care. A selection of signal ranges are featured for each channel. The selected range is automatically assigned for a channel during conversion, regardless of the channel scan mode (auto or manual). These registers (Ch0 Range to Ch3 Range) allow for selection of ranges for all channels. Bit 7 Must always be set to '0' Bits[6:4] Range Select Chn[2:0] These bits select the signal range for channel n, where n is 0, 1, 2, or 3, depending on the register address. 000 = Reserved; do not use this setting 001 = Range is set to 10V 010 = Range is set to 5V 011 = Range is set to 2.5V 100 = Reserved; do not use this setting 101 = Range is set to 0V to 10V 110 = Range is set to 0V to 5V 111 = Reserved; do not use this setting Bit 3 Must always be set to '0' Bit 2 : 0 Don't care (can be 1 or 0); this bit has no function assigned 56 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com Alarm Flag Registers for the ADS8634 (Read-Only) The alarm conditions related to individual channels are stored in these registers. When an alarm interrupt is received, the flags can be read on the AL_PD pin. There are two types of flag for every alarm: active and tripped. An active alarm flag is enabled when an alarm is triggered (when data cross the alarm threshold) and remains enabled as long as the alarm condition persists. A tripped alarm flag is enabled in the same manner as an active alarm flag, but it remains latched until it is read. This feature relieves the device from having to track alarms. Temp Flag: Alarm Flags Register for the Temperature Sensor (Address = 20h; Page 0) 7 6 5 4 3 2 1 0 Tripped Alarm Flag Temperature Low Tripped Alarm Flag Temperature High Active Alarm Flag Temperature Low Active Alarm Flag Temperature High 0 0 0 0 The Temp Flag register stores alarm flags for the temperature sensor. There are two alarm thresholds, with two flags for each threshold. An active alarm flag is enabled when an alarm is triggered (when data cross the alarm threshold) and remains enabled as long as the alarm condition persists. A tripped alarm flag is enabled in the same manner as an active alarm flag, but it remains latched until it is read. Bit 7 Tripped Alarm Flag Temperature Low This bit indicates the tripped low alarm flag for the temperature sensor. 0 = No alarm detected 1 = Alarm detected Bit 6 Tripped Alarm Flag Temperature High This bit indicates the tripped high alarm flag for the temperature sensor. 0 = No alarm detected 1 = Alarm detected Bit 5 Active Alarm Flag Temperature Low This bit indicates the active low alarm flag for the temperature sensor. 0 = No alarm 1 = Alarm detected Bit 4 Active Alarm Flag Temperature High This bit indicates the active-high alarm flag for the temperature sensor. 0 = No alarm detected 1 = Alarm detected Bits[3:0] Always read '0' Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 57 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com Ch0-1 Tripped-Flag to Ch2-3 Active-Flag: Alarm Flags Register for Channels 0 to 3 (Address = 21h to 24h; Page 0) (1) REGISTER ADDRESS ON PAGE 0 Ch0-1 Tripped-Flag 21h Ch0-1 Active-Flag 22h Ch2-3 Tripped-Flag 23h Ch2-3 Active-Flag 24h Bit 7 Tripped Alarm Flag Ch0 Low Active Alarm Flag Ch0 Low Tripped Alarm Flag Ch2 Low Active Alarm Flag Ch2 Low Bit 6 Tripped Alarm Flag Ch0 High Active Alarm Flag Ch0 High Tripped Alarm Flag Ch2 High Active Alarm Flag Ch2 High Bit 5 Bit 4 X (1) X X X X X X X Bit 3 Tripped Alarm Flag Ch1 Low Active Alarm Flag Ch1 Low Tripped Alarm Flag Ch3 Low Active Alarm Flag Ch3 Low Bit 2 Tripped Alarm Flag Ch1 High Active Alarm Flag Ch1 High Tripped Alarm Flag Ch3 High Active Alarm Flag Ch3 High Bit 1 Bit 0 X X X X X X X X X = don't care. There are two alarm thresholds (High and Low) per channel and for each threshold there are two flags. An active alarm flag is enabled when an alarm is triggered (when data cross the alarm threshold) and remains enabled as long as the alarm condition persists. A tripped alarm flag is enabled in the same manner as an active alarm flag, but it remains latched until it is read. Registers addressed 21h to 24h on page 0 store active and tripped alarm flags for all four channels. Bits[7:6] Active/Tripped Alarm Flag Chn High/Low Each individual bit indicates an active/tripped, high/low alarm flag for each channel, as per the Ch0-1 Tripped-Flag to Ch2-3 Active-Flag register. 0 = No alarm detected 1 = Alarm detected Bits[5:4] Don't care (1 or 0), these bits do not have any function assigned Bits[3:2] Active/Tripped Alarm Flag Chn High/Low Each individual bit indicates an active/tripped, high/low alarm flag for each channel, as per the Ch0-1 Tripped-Flag to Ch2-3 Active-Flag register. 0 = No alarm detected 1 = Alarm detected Bits[1:0] Don't care (1 or 0), these bits do not have any function assigned Page Selection Register for the ADS8634 The registers are arranged on two pages: page 0 and page 1. The page register selects the register page. Page: Page Selection Register (Address = 7Fh; Page 0) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Page Addr Bits[7:1] Must always be set to '0' Bit 0 Page Addr This bit selects the page address. 0 = Selects page 0 for the next register read or write command; all register read/write operations after this are performed on the page 0 registers until page 1 is selected 1 = Selects page 1 for the next register read or write command; all register read/write operations after this are performed on the page 1 registers until page 0 is selected 58 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com PAGE 1 REGISTER DESCRIPTIONS (ADS8634) This section provides bit-by-bit descriptions of each page 1 register. As described earlier, the device registers are mapped to two pages: page 0 and page 1. Page 0 is selected by default at power-up and after reset. Page 1 can be selected by writing 01h to register address 7Fh. After selecting page 1, any register read/write action addresses page 1 registers after a page 1 selection. Writing 00h to register address 7Fh selects page 0 for any further register operations. Alarm Threshold Setting Registers for the ADS8634 The device features high and low alarms individually for the temperature sensor and each of the four channels. Each alarm threshold is 12-bits wide with 4-bit hysteresis. This 16-bit setting is accomplished with two 8-bit registers associated with every high/low alarm. TLA MSB to THA LSB: Temperature Alarm Registers (Address = 00h to 03h; Page 1) REGISTER TLA MSB TLA LSB THA MSB THA LSB ADDRESS ON PAGE 1 Bit 7 Bit 6 Bit 5 TLA Hysteresis[3:0] Bit 4 Bit 3 Bit 2 Bit 1 TLA[11:8] Bit 0 TLA[7:0] THA Hysteresis[3:0] THA[11:8] THA[7:0] THA/LA MSB Register Bits[7:4] THA/LA Hysteresis[3:0] These bits set the temperature high/low alarm hysteresis. 0000 = No hyeteresis 0001 = 1LSB hystetesis 0010 to 1110 = 2LSB to 14LSB hystetesis 1111 = 15LSB hystetesis Bits[3:0] THA/LA[11:8] These bits set the MSB nibble for the 12-bit temperature high/low alarm. For example, the temperature high alarm threshold is AFFh when the THA MSB register (address 02h, page 1) setting is Ah and the THA LSB register (address 03h, page 1) register setting is FFh. 0000 = MSB nibble is 0h 0001 = MSB nibble is 1h 0010 to 1110 = MSB nibble is 2h to Eh 1111 = MSB nibble is Fh THA/LA LSB Register Bits[7:0] THA/LA[7:0] These bits set the LSB byte for the 12-bit temperature high alarm. For example, the temperature low alarm threshold is F02h when the TLA LSB register (address 01h) setting is 02h and the TLS MSB register (address 00h, page 1) register setting is Fh. 0000 0000 = LSB byte is 0h 0000 0001 = LSB byte is 1h 0000 0010 to 1110 1111 = LSB byte is 02h to EFh 1111 1111 = LSB byte is FFh Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 59 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com Ch0LA MSB to Ch3HA LSB: Channels 0 to 3 Alarm Registers (Address = 04h to 23h; Page 1) REGISTER Ch0LA MSB Ch0LA LSB Ch0HA MSB Ch0HA LSB No function Ch1LA MSB Ch1LA LSB Ch1HA MSB Ch1HA LSB No function Ch2LA MSB Ch2LA LSB Ch2HA MSB Ch2HA LSB No function Ch3LA MSB Ch3LA LSB Ch3HA MSB Ch3HA LSB No function (1) ADDRESS ON PAGE 1 04h 05h 06h 07h 08h to 0Bh 0Ch 0Dh 0Eh 0Fh 10h to 13h 14h 15h 16h 17h 18h to 1Bh 1Ch 1Dh 1Eh 1Fh 20h to 23h Bit 7 Bit 6 Bit 5 Ch0-LA Hysteresis[3:0] Bit 4 Bit 3 Bit 2 Bit 1 Ch0-LA[11:8] Bit 0 Ch0-LA[7:0] Ch0-HA Hysteresis[3:0] X (1) X X Ch1-LA Hysteresis[3:0] Ch0-HA[11:8] Ch0-HA[7:0] X X X X Ch1-LA[11:8] X Ch1-LA[7:0] Ch1-HA Hysteresis[3:0] X X X Ch2-LA Hysteresis[3:0] Ch1-HA[11:8] Ch1-HA[7:0] X X X X Ch2-LA[11:8] X Ch2-LA[7:0] Ch2-HA Hysteresis[3:0] X X X Ch3-LA Hysteresis[3:0] Ch2-HA[11:8] Ch2-HA[7:0] X X X X Ch3-LA[11:8] X Ch3-LA[7:0] Ch3-HA Hysteresis[3:0] X X X Ch3-HA[11:8] Ch3-HA[7:0] X X X X X X = don't care. Channel N HA/LA MSB Register Bits[7:4] Chn-HA/LA Hysteresis[3:0] These bits set the channel n high/low alarm hysteresis. For example, bits[7:4] of the channel 2 HA MSB register (address 16h, page 1) set the channel 2 high alarm hysteresis. 0000 = No hyeteresis 0001 = 1LSB hystetesis 0010 to 1110 = 2LSB to 14LSB hystetesis 1111 = 15LSB hystetesis Bits[3:0] Chn-HA/LA[11:8] These bits set the MSB nibble for the 12-bit channel n high/low alarm. For example, the channel 3 high alarm threshold is AFFh when bits[3:0] of the channel 3 HA MSB register (address 1Eh, page 1) are set to Ah and the channel 3 HA LSB (address 1Fh, page 1) register setting is FFh. 0000 = MSB nibble is 0h 0001 = MSB nibble is 1h 0010 to 1110 = MSB nibble is 2h to Eh 1111 = MSB nibble is Fh Channel N HA/LA LSB Register Bits[7:0] Chn HA[7:0] These bits set the LSB byte for the 12-bit channel n high/low alarm. For example, the channel 1 low alarm threshold is F01h when the channel 1 LA LSB register (address 0Dh, page 1) setting is 01h and bits[3:0] of the channel 1 LA MSB (address 0Ch, page 1) are set to Fh. 0000 0000 = LSB byte is 0h 0000 0001 = LSB byte is 1h 0000 0010 to 1110 1111 = LSB byte is 02h to EFh 1111 1111 = LSB byte is FFh 60 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com APPLICATION INFORMATION DRIVING ANALOG SIGNAL INPUT The ADS8634/8 employ a sample-and-hold stage at the input. An 8pF sampling capacitor is connected during sampling. This configuration results in a glitch at the input terminals of the device at the start of the sample. The external circuit must be designed in such a way that the input can settle to the required accuracy during the chosen sampling time. Figure 91 shows a reccomended driving circuit for the analog inputs. VOPA+ +VA HVDD AVDD OPA140 + Analog Signal VRANGE VOPA+ 20 AINx VOPA 1200pF ADS8634/8 50 AINGND HVSS AGND VOPA Figure 91. Reccomended Driving Circuit The 8pF capacitor across the AINx and AINGND terminals decouples the driving op amp from the sampling glitch. The low-pass filter at the input limits noise bandwidth of the driving op amp. Select the filter bandwidth so that the full-scale step at the input can settle to the required accuracy during the sampling time. Equation 5, Equation 6, and Equation 7 are useful for filter component selection. Sampling Time Filter Time Constant (tAU) = Settling Resolution ln(2) Where: Settling resolution is the accuracy in LSB to which the input must settle. A typical settling resolution for the 12-bit device is 13 or 14. (5) Filter Time Constant (tAU) = R C (6) Filter Bandwidth = 1 2 p tAU (7) Also, make sure the driving op amp bandwidth does not limit the signal bandwidth to below the filter bandwidth. In many applications, signal bandwidth may be much lower than filter bandwidth. In this case, an additional low-pass filter may be used at the input of the driving op amp. This signal and filter bandwidth can be selected in accordance with the input signal bandwidth. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 61 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com POWER MANAGEMENT AT LOWER SPEEDS There are multiple data acquisition applications that require sampling speeds much lower than 1MSPS. The ADS8634/8 offer power saving while running at lower speeds. As shown in Figure 92, the ADS8634/8 consume dynamic power from a CS rising edge until the 16th SCLK falling edge. While using the ADS8634/8 at lower sampling speeds, it is recommended to use SCLK at the maximum specified frequency. This setting allows the maximum static period tSTATIC at any given sampling speed. The ADS8634/8 consume considerably lower static current (current during tSTATIC) from all three power supplies (AVDD, HVDD, and HVSS). This consumption helps lower the average currents from each of the supplies, resulting in a lower average power consumption while using the device at lower sampling speeds. tFRAME=1/fSAMPLE (Actual) tSTATIC tDYNAMIC = 1/fSAMPLE (Max) CS 16f 16f SCLK IDYNAMIC ISTATIC AVDD, HVDD, HVSS Current Figure 92. Supply Current Profile at Speeds Below 1MSPS Table 15 shows tFRAME, tDYNAMIC, and tSTATIC at a 0.1MSPS sampling speed. Table 15. Typical Static/Dynamic Time Distribution at Lower Speeds (0.1MSPS) fSAMPLE (MSPS) tFRAME (s) tDYNAMIC (s) tSTATIC (s) 0.1 10 1 9 The average device power consumption can be calculated with Equation 8 and Equation 9: Average Current, IAVERAGE = (IDYNAMIC x tDYNAMIC + ISTATIC x tSTATIC)/(tDYNAMIC + tSTATIC) Average Power = Supply Voltage x IAVERAGE (8) (9) Table 16 shows the average power calculations at 0.1MSPS. Table 16. Average Power Calculations at 0.1MSPS PARAMETER AVDD HVDD Typical supply voltage (V) 3.3 10 10 IDYNAMIC (mA) 2.50 0.27 0.35 tDYNAMIC (s) 1.0 1.0 1.0 ISTATIC (mA) 1.45 0.005 0.005 tSTATIC (s) 9.0 9.0 9.0 Average current, IAVERAGE (mA) 1.555 0.032 0.040 Average power (mW) 5.132 0.315 0.395 Total average power (mW) = PAVDD + PHVDD + PHVSS 62 HVSS Submit Documentation Feedback 5.842 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com PROGRAMMING SEQUENCE A typical programming sequence for the ADS8634/8 is shown in Figure 93. Device Powers Up Starts in Manual Mode channel 0, 10V input range. Are any of these to be enabled? a) AL_PD as Alarm Out b) Power-up INT REFGEN c) Power-up TEMP SENSOR No Yes Program the Internal Control Register (Page 0, Register 06h) Will the device be used in Auto Mode? Will channel selection be enabled? (Default = channel 0 enabled) No Yes Program the Internal Control Register (Page 0, Register 06h) Will any channel input range other than 10V be used? No Yes Program the Range Select Register (Page 0, Registers 10h to 13h) Will the alarm threshold be programmed with or without hysteresis? No Yes Go to Page 1 and Program the Page Select Register (Page 0, Register 7Fh) Write the Alarm Threshold and Hysteresis into the Alarm Register (Page 1, Registers 00h to 23h) Return to Page 0 and Program the Page Select Register (Page 1, Register 7Fh) Start Manual Mode Operation or Auto Mode Operation Manual Mode Auto Mode Manual Mode Operation Write to Page 0, Register 04h Change Mode Continue Auto Mode Operation Write to Page 0, Register 05h Continue Change Configuration Change Configuration Continue Operation in Configured Mode Write to Page 0, Register 00h Continue Figure 93. Programming Flowchart Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 63 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com DRIVING ANALOG SIGNAL INPUT WITHOUT AN OPERATIONAL AMPLIFIER There are some low input signal bandwidth applications, such as general-purpose programmable logic controllers (PLCs) I/O, where it is not required to operate an ADC at high sampling rates and it is desirable to avoid using a dedicated driving op amp from a cost perspective. In this case, the ADC input recognizes the impedance of the signal source (such as signal conditioning circuit, PGA, or sensor). This section elaborates on the effects of source impedance on sampling frequency. Equation 5 can be rewritten as Equation 10: Sampling Time = Filter Time Constant x Settling Resolution x ln(2) (10) As shown in Figure 94, it is recommended to use a bypass capacitor across the positive and negative ADC input terminals. AVDD RSOURCE R1 + AINx CBYPASS - AINGND Signal Source ADS8634/8 GND GND Figure 94. Driving Without an Operational Amplifier 64 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com The source impedance (RSOURCE + R1) combined with (CBYPASS + CSAMPLE) acts as a low-pass filter with Equation 11: Filter Time Constant = (RSOURCE + R1) x (CBYPASS + CSAMPLE) Where: CSAMPLE is the internal sampling capacitance of the ADC (equal to 32pF). (11) Table 17 lists the recommended bypass capacitor values and the filter-time constant for different source resistances. It is recommended to use a bypass capacitor with a minimum value of 100pF. Table 17 assumes R1 = 20; however, depending on the application, R1 can be bypassed (by shorting R1) and the extra 20 margin can be used for source resistance. Table 17. Filter-Time Constant versus Source Resistance RSOURCE () RSOURCE + R1 APPROXIMATE CBYPASS (pF) CBYPASS + CSAMPLE (pF) FILTER TIME CONSTANT (ns) 0 20 1200 1208 25 32 52 470 478 25 90 110 220 228 25 210 230 100 108 25 500 520 100 108 56 1000 1020 100 108 110 5000 5020 100 108 542 Typically, the settling resolution is selected as (ADC resolution + 2). For the ADS8634/8 (12-bit), the ideal settling resolution is 14. Using Equation 6 and Equation 7, the sampling time can be easily determined for a given source impedance. For source impedances greater than 210, the filter-time constant continues to increase beyond the 25ns required for a 250ns sampling time. This incrementation increases the minimum permissible sampling time for 12-bit settling and the device must be operated at a lower sampling rate. The device sampling rate can be maximized by using a 20MHz clock for even lower throughputs. Table 18 shows typical calculations for the ADS8634/8 (12-bit). Table 18. Sampling Frequency versus Source Impedance for the ADS8634/8 RSOURCE () CBYPASS (pF) SAMPLING TIME, tACQ (ns) CONVERSION TIME, tCONV (ns) CYCLE TIME, tACQ + tCONV (ns) SAMPLING RATE (MSPS) 210 100 250 750 (with 20MHz clock) 1000 1 500 100 545 750 (with 20MHz clock) 1295 0.8 1000 100 1070 750 (with 20MHz clock) 1820 0.5 5000 100 5260 750 (with 20MHz clock) 6010 0.2 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 65 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com PCB LAYOUT SCHEMATIC RECCOMENDATIONS ADCs are mixed-signal devices. For maximum performance, proper decoupling, grounding, and proper termination of digital signals is essential. Figure 95 and Figure 96 show the essential components around the ADC. All capacitors shown are ceramic. These decoupling capacitors must be placed close to the respective signal pins. Analog Signal Common R9 20 Common Analog/Digital Ground Plane 1200pF C8 C9 C10 1 F Analog Supply 1 AVDD AGND 2 AGND 3 NC AINGND 0.1 F 4 6 1200pF C7 5 AIN7 R8 20 R7 20 7 24 REF Reference C11 1200pF C6 AIN5 8 23 9 22 10 F REFGND R6 20 AIN4 1200pF C5 Digital To/From Host AL_PD ADS8638 AIN3 10 21 DVDD C12 R5 20 1200pF C4 AIN2 11 20 12 19 AIN1 0.1 F DOUT 18 DIN 17 SCLK 16 CS 15 HVSS 14 HVDD 13 50 AIN0 1 F DGND R4 20 1200pF C3 Digital Supply C13 R3 20 1200pF C2 R1 Digital Signals From/To Host Analog Input Signals AIN6 R2 20 C15 1200pF C1 C14 1 F 1 F Bipolar Power Supply Figure 95. Reccomended Schematic for the ADS8638 66 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com There is a 50 source series termination resistor shown on the DOUT signal. This resistor must be placed as close to DOUT as possible. Series terminations for SCLK and CS must be placed close to the host. Analog Signal Common Common Analog/Digital Ground Plane C10 1 F Analog Supply 1 AVDD AGND 2 AGND 3 4 NC AINGND 0.1 F 5 NC 6 Analog Input Signals C9 R7 20 NC 7 24 REF Reference C11 1200pF C6 AIN3 8 23 9 22 10 F REFGND R6 20 Digital To/From Host AL_PD ADS8634 AIN1 10 21 DVDD C12 R5 20 1200pF C4 AIN0 11 20 12 19 NC 0.1 F DOUT 18 DIN 17 SCLK 16 CS 15 HVSS 14 HVDD NC 13 50 C15 1 F DGND R4 20 1200pF C3 Digital Supply C13 R1 Digital Signals From/To Host AIN2 1200pF C5 C14 1 F 1 F Bipolar Power Supply Figure 96. Reccomended Schematic for the ADS8634 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 67 ADS8634 ADS8638 SBAS541A - MAY 2011 - REVISED AUGUST 2011 www.ti.com A common ground plane for both analog and digital often gives better results. Typically, the second printed circuit board (PCB) layer is the ground plane. The ADC ground pins are returned to the ground plane through multiple vias (PTH). It is a good practice to place analog components on one side and digital components on other side of the ADC (or ADCs). All signals must be routed, assuming there is a split ground plane for analog and digital. Furthermore, it is better to split the ground initially during layout. Route all analog and digital traces so that the traces see the respective ground all along the second layer. Then, short both grounds to form a common ground plane. Figure 97 Figure 98 show the reccomended layout around the ADS8638. The ADS8634 pinout is a subset of the ADS8638 pinout. It is possible to make a common layout for the ADS8634/8 . Or, one can delete the traces and components associated with the additional four channels of the ADS8638 to generate the ADS8634 layout. Figure 97. Reccomended Layout for the ADS8638 (Top layer) 68 Figure 98. Reccomended Layout for the ADS8638 (Bottom layer) Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8634 ADS8638 PACKAGE OPTION ADDENDUM www.ti.com 11-Aug-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) ADS8634SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS8634SRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS8638SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS8638SRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS8634SRGER VQFN RGE 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS8634SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS8638SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS8638SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8634SRGER VQFN RGE 24 3000 367.0 367.0 35.0 ADS8634SRGET VQFN RGE 24 250 210.0 185.0 35.0 ADS8638SRGER VQFN RGE 24 3000 367.0 367.0 35.0 ADS8638SRGET VQFN RGE 24 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI's terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers' products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers' products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI's goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or "enhanced plastic" are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such components to meet such requirements. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP(R) Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2012, Texas Instruments Incorporated