U2783B
TELEFUNKEN Semiconductors
Rev . A4, 17-Oct–97 1 (12)
1250 MHz / 400 MHz Twin PLL
Description
The IC U2783B is a low power twin PLL manufactured
with TEMIC’s advanced UHF process. The maximum
operating frequency is 1250 MHz and 400 MHz respec-
tively. It features a wide supply voltage range from 2.7 to
5.5 V. Prescaler and power down function for both PLL’s
is integrated. Applications are CT1, CT2, IS54 etc.
Electrostatic sensitive device.
Observe precautions for handling.
Features
D
Very low current consumption (typical 3 V/10 mA)
D
Supply voltage range 2.7 to 5.5 V
D
Maximum input frequency PLL1: 1250 MHz,
PLL2: 400 MHz
D
2 pins for separate power down functions
D
Output for PLL lock status
D
Prescaler 64/65 for PLL1 and 32/33 for PLL2
D
SSO-20 package
D
ESD protected according to MIL-STD 833
method 3015 cl.2
Benefits
D
Low current consumption leads to extended talk time
D
Twin PLL saves costs and space
D
One foot print for all TEMIC twin PLL’ s saves design-
in time
Block Diagram
12 bit reference divider 2
12 bit latch 2
15 bit latch 2
15 bit main divider 2
17 bit
Shift register
17 bit latch 1
17 bit main divider 1
12 bit reference divider 1
12 bit latch 1
16 bit latch
Control functions
Oscillator
on / off
divide by 2
64 / 65 Prescaler 1
32 / 33 Prescaler 2
3 bit
Load control
Phase
detector 1
Phase
detector 2
Charge
pump 1
Charge
pump 2
Pump
bias
Lock
select
Ports
Power
down Test
9
14
1
20
5I/Port 0
HPD1/Port 1
HPD2/Port 4
Port3
Lock Port2
10
3
17
CP1
VScp
19
18
Iset
CP2
7
8
4
2
6
15
VS analog
VS digital
DGND
AGND
OSCi
OSCo
5
RFi1
11
12
13
16
Clock
Data
Enable
RFi2
94 891
8
Figure 1.
U2783B
TELEFUNKEN Semiconductors
Rev . A4, 17-Oct–97
2 (12)
Ordering Information
Extended Type Number Package Remarks
U2783B-AFS SSO20 Rail, MOQ 830 pcs
U2783B-AFSG3 SSO20 Tape and reel, MOQ 4000 pcs
Pin Description
1
2
3
4
5
6
7
8
10
9
19
18
17
16
14
15
13
12
11
20 Port 3
Iset
CP 2
VScp
RFi 2
GNDA
HPD2/Port
4
Enable
Data
Clock
5I/Port 0
VS digital
CP 1
VS analog
RFi 1
GNDD
OSCi
OSCo
HPD1/Port 1
Lock/Port 2
95 9622
Pin Symbol Function
15I/Port 0 5I – Control input / o.c.output
2 VS digital Power supply digital section
3CP 1 Charge pump output of
synthesizer 1
4 VS analog Power supply analog section
5RFi 1 RF divider input synthesizer
6 GNDDGround for digital section
7 OSCiReference oscillator input
8 OSCoReference oscillator output
9HPD 1/
Port 1 Hardware power down input of
synthesizer 1 / o.c.output
10 Lock/
Port 2 Lock output / o.c.output /
testmode output
11 Clock 3-wire-bus: serial clock input
12 Data 3-wire-bus: serial data input
13 Enable 3-wire-bus: serial enable input
14 HPD 2/
Port 4 Hardware power down input of
synthesizer 2 / o.c.output
15 GNDAGround for analog section
16 RFi 2 RF divider input synthesizer 2
17 VScp Charge pump supply voltage
18 CP 2 Charge pump output of
synthesizer 2
19 Iset Reference pin for charge pump
currents
20 Port 3 o.c.output
Absolute Maximum Ratings
Parameters Symbol Value Unit
Supply voltage Pins 2, 4 and 17 VS, VScp 6 V
Input voltage Pins 1, 3, 5, 8, 9, 10, 11, 12,
13, 14, 15, 16, 18 and 20 Vi0 to VSV
Junction temperature Tj125 °C
Storage temperature range Tstg –40 to +125 °C
Operating Range
Parameters Symbol Value Unit
Supply voltage Pins 2, 4 and 17 VS, VScp 2.7 to 5.5 V
Ambient temperature range Tamb –40 to +85 °C
U2783B
TELEFUNKEN Semiconductors
Rev . A4, 17-Oct–97 3 (12)
Thermal Resistance
Parameters Symbol Value Unit
Junction ambient SSO20 Rthja 140 K/W
Electrical Characteristics
Tamb = 25
_
C, VS = 2.7 to 5.5 V, VScp = 5 V, unless otherwise specified
Parameters Test Conditions Symbol Min. T yp. Max. Unit
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DC Supply
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Supply current
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
VS = 3 V
ÁÁÁÁ
ÁÁÁÁ
IS
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
10
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
mA
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
Supply current CP
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
VCP = 5 V, PLL in lock
condition
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
ICP
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
1
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
µA
PLL 1
Input voltage fRFi1 = 200 – 1250 MHz VRFi1 20 200 mVRMS
Scaling factor prescaler SPSC 64/65
Scaling factor main
counter SM5 2047
Scaling factor swallow
counter SS0 63
Reference counter SR5 4096
PLL 2
Input voltage fRFi2 = 50 MHz VRFi2 40
20
200
200
mVRMS
fRFi2 = 100 – 400 MHz 20 200
Scaling factor prescaler SPSC 32/33
Scaling factor main
counter SM5 1023
Scaling factor swallow SS0 31
Reference counter SR5 4096
Reference oscillator
Recommended crystal
series resistance 10 200
W
External reference input
frequency AC coupled sinewave
RF/2 = 0
RF/2 = 1
OSCi1
120
40 MHz
External reference input
amplitude AC coupled sinewave 2) OSCi100 mVRMS
Logic input levels (Clock, Data, Enable, HPD1, HPD2, 5I)
High input level ViH 1.5 V
Low input level ViL 00.4 V
High input current IiH –5 5
m
A
Low input current IiL –5 5
m
A
Logic output levels (Port 0, 1, 2, 3, 4, Lock)
Leakage current VOH = 5.5 V IL10
m
A
Saturation voltage IOL = 0.5 mA VSL 0.4 V
Charge pump output (Rset = tbd.)
Source current VCP
x
VScp/2 PLL2
5I = L PLL1
5I = H PLL1 Isource
– 1
–0.2
–1 mA
Sink current VCP
x
VScp/2 PLL2
5I = L PLL1
5I = H PLL1 Isink
1
0.2
1mA
Leakage current VCP
x
VScp/2 IL
"
5 nA
U2783B
TELEFUNKEN Semiconductors
Rev . A4, 17-Oct–97
4 (12)
1) RMS voltage at 50
W
; 2) OSCo is open if an external reference frequency is applied
U2783B
TELEFUNKEN Semiconductors
Rev . A4, 17-Oct–97 5 (12)
Serial Bus Programming
Reference and programmable counters can be pro-
grammed by 3-wire-bus (Clock, Data and Enable). After
setting enable signal to high condition, the data status is
transfered bit by bit on the rising edge of the clock signal
into the shift register , starting with the MSB-bit. After the
Enable signal returns the addressed latch. Additional
leading bits are ignored and there is no check made how
many clock pulses arrived during enable high condition.
In powerdown mode the 3-wire-bus remains active and
the IC can be programmed.
Data is entered with the most significant bit first. The
leading bits deliver the divider or control information.
The trailing three bits are the address field. There are six
different addresses used. The trailing address bits are
decoded upon the falling edge of the Enable signal. The
internal Loadpulse is beginning with the falling edge of
the Enable signal and ending with the falling edge of the
Clock signal. Therefore a minimum holdtime
clock-enable tHCE is required.
Bit Allocation
MSB LSB
Bit
1Bit
2Bit
3Bit
4Bit
5Bit
6Bit
7Bit
8Bit
9Bit
10 Bit
11 Bit
12 Bit
13 Bit
14 Bit
15 Bit
16 Bit
17 Bit
18 Bit
19 Bit
20
data bits address bits
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
PLL1
M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S5 S4 S3 S2 S1 PLL1
S0 0 0 1
PLL1
R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 PLL1
R0 0 1 0
PLL
2 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 PLL2
S0 0 1 1
PLL2
R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 PLL2
R0 1 0 0
RF/
2Test 5IP TRI
2TRI
1PS2 PS1 H2P H1P LP
BLPA P4 P3 P2 P1 P0 1 0 1
SP
D 5I SP
D 2 SP
D 1 1 1 0
Scaling Factors
PGD of PLL1:
S0 ... S5: These bits are setting the swallow counter SS.
TS = S0*20 + S1*21 + ... + S4*24 + S5*25
allowed scalling factors for SS: 0 ... 63, TS < TM
M0 ... M10: These bits are setting the main counter SM.
TM = M0*20 + M1*21 + ... + M9*29 + M10*210
allowed scalling factors for SM: 5 ... 2047
SPGD: T otal scalling factor of the programmable counter:
SPGD = (64*SM) + SS Condition: SS < SM
PGD of PLL2:
S0 ... S4: These bits are setting the swallow counter SS.
TS = S0*20 + S1*21 + ... + S3*23 + S4*24
allowed scalling factors for SS: 0 ... 31, TS < TM
M0 ... M9: These bits are setting the main counter SM.
TM = M0*20 + M1*21 + ... + M8*28 + M9*29
allowed scalling factors for SM: 5 ... 1023
SPGD: T otal scalling factor of the programmable counter:
SPGD = (32*SM) + SS Condition: SS < SM
RFD of PLL1 and PLL2:
R0 ... R11: These bits are setting the reference counter SR.
SR = R0*20 + ... + R10*210 + R11*2 11
allowed scalling factors for SR: 5 ... 4096
RF/2 = 1: SRFD = 2 * SR
RF/2 = 0: SRFD = SR
U2783B
TELEFUNKEN Semiconductors
Rev . A4, 17-Oct–97
6 (12)
Serial Programming Bus
Control Bits:
P0 ... P4: o.c. output ports (1 = high impedance)
LPA, LPB: selection of P2 output or locksignal LPA LPB function of pin 10
0 0 o.c. output P2
0 1 locksignal of synthesizer 2
1 0 locksignal of synthesizer 1
1 1 wiredor locksignal of both synthesizer
H1P, H2P: selection of P1/4 output or hardware power down input of synthesizer 1/2 (0 = Port / 1 = HPD)
5IP: selection of P0 output or high current switching input for the charge pump current of synthesizer 1
(0 = Port / 1 = charge pump 1 current switch input)
PS1, PS2: phase selection of synthesizer 1 and synthesizer 2 (1 = normal / 0 = invers)
PS-PLL1/2 = 1 PS-PLL1/2 = 0
CP1/2 CP1/2
fR > fPIsink Isource
fR < fPIsource Isink
fR = fP0 0
RF/2: divide by 2 prescaler for reference divider (0 = off / 1 = on)
SPD1, SPD2: software power down bit of synthesizer 1/2 (0 = powerdown / 1 = powerup)
5I: software switch for the charge pump current of synthesizer 1 (0 = low current / 1 = high current)
TRI1, TRI2: enables tristate for the charge pump of synthesizer 1/2 (0 = normal / 1 = tristate)
TEST: enables counter testmode (0 = disabled / 1 = enabled)
TEST LPA LPB PS1 PS2 Testsignal
at pin 10
1 1 0 1 x RFD1
1 1 0 0 x PGD1
1 0 1 x 1 RFD2
1 0 1 x 0 PGD2
To operate the software power down mode the following condition must be set: HXP = 0; power up and power down
will be set by SPDX = 1 (on) and SPDX = 0 (off).
To operate the hardware power down mode the following condition must be set: HXP = 1; SPDX = 1; power up and
power down will be set by high and low state at the hardware power down pins 9/14.
High current of charge pump synthesizer 1 is active when 5I = 1 and if 5IP = 1 the charge pump current control input
pin 1 is in high state.
U2783B
TELEFUNKEN Semiconductors
Rev . A4, 17-Oct–97 7 (12)
Application Circuit
5I / P0
P3
RF2
HPD1 / PORT1
HPD2 / PORT4
RF1
CRYSTAL OSC.
CLOCK
DATA
ENABLE
LOCK / PORT2 / TEST
R1
C1
C2
R1
C1
C2
12
12
47u 10n
R
47u 10n
12
12
47u 10n
18
10n 18
10n 10n
10n
18 18
1851 10n 47u
10n
5118
10n
10n
51
VCO1 VCO2
INPUT
94 9621
V VCO
S
VScp
VS
Figure 2.
U2783B
TELEFUNKEN Semiconductors
Rev . A4, 17-Oct–97
8 (12)
Timing Diagram Serial Bus
tSEC tCH tCL
tEL
tHEC
tHCE
tSDC tHDC
Data
Clock
Enable
Internal
Loadpulse 96 11828
Clock High Time tCH > 750 ns
Clock Low Time tCL > 350 ns
Clock Period tPER > 1100 ns
Set up Time Data to Clock tSDC > 100 ns
Hold Time Data to Clock tHDC > 400 ns
Hold Time Clock to Enable tHCE > 400 ns
Hold Time Enable to Clock tHEC > 400 ns
Enable Low Time tEL > 200 ns
Set up Time Enable to Clock tSEC > 4000 ns
U2783B
TELEFUNKEN Semiconductors
Rev . A4, 17-Oct–97 9 (12)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
3000 30000 300000
Icp / mA
R19/
W
96 11679
5 I = 1
Figure 3. Charge pump characteristics
1
10
100
1000
0 200 400 600 800 1000 1200 1400
1m Veff on 50
Frequency/ MHz96 11681
Guaranteed Area
W
Figure 4. Input sensitivity of PLL1
1
10
100
1000
0 100 200 300 400 500 600
1m Veff on 50
Frequency/ MHz96 11682
Guaranteed Area
W
Figure 5. Input sensitivity of PLL2
U2783B
TELEFUNKEN Semiconductors
Rev . A4, 17-Oct–97
10 (12)
Input Impedance of PLL1 and PLL2
–0.2j
–0.5j
–j
–2j
–5j
0
0.2j
0.5j
j
2j
5j
ÁÁ
ÁÁ
0.2
ÁÁ
ÁÁ
0.5
1
Á
Á
2
5
1
96 11687
1 GHz
500 MHz
100 MHz
1.5 GHz
Z0 = 50
W
PLL1
PLL2
U2783B
TELEFUNKEN Semiconductors
Rev . A4, 17-Oct–97 11 (12)
Package Information
13007
technical drawings
according to DIN
specifications
Package SSO20
Dimensions in mm 6.75
6.50
0.25
0.65 5.85
1.30
0.15
0.05
5.7
5.3
4.5
4.3
6.6
6.3
0.15
20 11
110
U2783B
TELEFUNKEN Semiconductors
Rev . A4, 17-Oct–97
12 (12)
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and
forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban
on these substances.
TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of
continuous improvements to eliminate the use of ODSs listed in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
TEMIC can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain
such substances.
We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer
application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized
application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of,
directly or indirectly, any claim of personal damage, injury or death associated with such unintended or
unauthorized use.
TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423