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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN5400
,
SN54LS00
,
SN54S00
SN7400
,
SN74LS00
,
SN74S00
SDLS025D –DECEMBER 1983–REVISED MAY 2017
SNx400, SNx4LS00, and SNx4S00 Quadruple 2-Input Positive-NAND Gates
1
1 Features
1• Package Options Include:
– Plastic Small-Outline (D, NS, PS)
– Shrink Small-Outline (DB)
– Ceramic Flat (W)
– Ceramic Chip Carriers (FK)
– Standard Plastic (N)
– Ceramic (J)
• Also Available as Dual 2-Input Positive-NAND
Gate in Small-Outline (PS) Package
• Inputs Are TTL Compliant; VIH = 2 V and
VIL = 0.8 V
• Inputs Can Accept 3.3-V or 2.5-V Logic Inputs
• SN5400, SN54LS00, and SN54S00 are
Characterized For Operation Over the Full Military
Temperature Range of –55ºC to 125ºC
2 Applications
• AV Receivers
• Portable Audio Docks
• Blu-Ray Players
• Home Theater
• MP3 Players or Recorders
• Personal Digital Assistants (PDAs)
3 Description
The SNx4xx00 devices contain four independent,
2-input NAND gates. The devices perform the
Boolean function Y = A .B or Y = A + B in positive
logic.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LS00DB SSOP (14) 6.20 mm × 5.30 mm
SN7400D,
SN74LS00D,
SN74S00D SOIC (14) 8.65 mm × 3.91 mm
SN74LS00NSR PDIP (14) 19.30 × 6.35 mm
SNJ5400J,
SNJ54LS00J,
SNJ54S00J CDIP (14) 19.56 mm × 6.67 mm
SNJ5400W,
SNJ54LS00W,
SNJ54S00W CFP (14) 9.21 mm × 5.97 mm
SN54LS00FK,
SN54S00FK LCCC (20) 8.89 mm × 8.89 mm
SN7400NS,
SN74LS00NS,
SN74S00NS SO (14) 10.30 mm × 5.30 mm
SN7400PS,
SN74LS00PS SO (8) 6.20 mm × 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram, Each Gate (Positive Logic)
2
SN5400
,
SN54LS00
,
SN54S00
SN7400
,
SN74LS00
,
SN74S00
SDLS025D –DECEMBER 1983–REVISED MAY 2017
www.ti.com
Product Folder Links: SN5400 SN54LS00 SN54S00 SN7400 SN74LS00 SN74S00
Submit Documentation Feedback Copyright © 1983–2017, Texas Instruments Incorporated
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings: SN74LS00.......................................... 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics: SNx400............................ 6
6.6 Electrical Characteristics: SNx4LS00 ....................... 6
6.7 Electrical Characteristics: SNx4S00 ......................... 6
6.8 Switching Characteristics: SNx400........................... 7
6.9 Switching Characteristics: SNx4LS00....................... 7
6.10 Switching Characteristics: SNx4S00....................... 7
6.11 Typical Characteristics............................................ 8
7 Parameter Measurement Information .................. 9
7.1 Propagation Delays, Setup and Hold Times, and
Pulse Width................................................................ 9
8 Detailed Description............................................ 10
8.1 Overview................................................................. 10
8.2 Functional Block Diagram....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes....................................... 10
9 Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application.................................................. 11
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support................. 14
12.1 Documentation Support ........................................ 14
12.2 Related Links ........................................................ 14
12.3 Receiving Notification of Documentation Updates 14
12.4 Community Resources.......................................... 14
12.5 Trademarks........................................................... 14
12.6 Electrostatic Discharge Caution............................ 14
12.7 Glossary................................................................ 14
13 Mechanical, Packaging, and Orderable
Information........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (November 2016) to Revision D Page
• Changed Typical Application Diagram see Application and Implementation section............................................................. 1
Changes from Revision B (October 2003) to Revision C Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.................................................................................................. 1
• Changed Ordering Information table to Device Comparison Table; see Package Option Addendum at the end of the
data sheet............................................................................................................................................................................... 1
• Changed Package thermal impedance, RθJA, values in Thermal Information table From: 86°C/W To: 90.9°C/W (D),
From: 96°C/W To: 102.8°C/W (DB), From: 80°C/W To: 54.8°C/W (N), and From: 76°C/W To: 89.7°C/W (NS)................... 6
41Y
5NC
62A
7NC
82B
92Y
10
GND
11
NC
12
3Y
13
3A
14 3B
15 NC
16 4Y
17 NC
18 4A
19 4B
20 VCC
1 NC
2 1A
3 1B
Not to scale
11A 8 VCC
21B 7 2B
31Y 6 2A
4GND 5 2Y
Not to scale
11A 14 4Y
21B 13 4B
31Y 12 4A
4VCC 11 GND
52Y 10 3B
62A 9 3A
72B 8 3Y
Not to scale
3
SN5400
,
SN54LS00
,
SN54S00
SN7400
,
SN74LS00
,
SN74S00
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SDLS025D –DECEMBER 1983–REVISED MAY 2017
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5 Pin Configuration and Functions
SN5400 J, SN54xx00 J and W, SN74x00 D, N, and NS, or
SN74LS00 D, DB, N, and NS Packages
14-Pin CDIP, CFP, SOIC, PDIP, SO, or SSOP
Top View
SN5400 W Package
14-Pin CFP
Top View
SN74xx00 PS Package
18-Pin SO
Top View
SN54xx00 FK Package
20-Pin LCCC
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME CDIP, CFP, SOIC,
PDIP, SO, SSOP SO
(SN74xx00) CFP
(SN5400) LCCC
1A 1 1 1 2 I Gate 1 input
1B 2 2 2 3 I Gate 1 input
1Y 3 3 3 4 O Gate 1 output
2A 4 6 6 6 I Gate 2 input
2B 5 7 7 8 I Gate 2 input
2Y 6 5 5 9 O Gate 2 output
3A 10 — 9 13 I Gate 3 input
3B 9 — 10 14 I Gate 3 input
4
SN5400
,
SN54LS00
,
SN54S00
SN7400
,
SN74LS00
,
SN74S00
SDLS025D –DECEMBER 1983–REVISED MAY 2017
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Pin Functions (continued)
PIN I/O DESCRIPTION
NAME CDIP, CFP, SOIC,
PDIP, SO, SSOP SO
(SN74xx00) CFP
(SN5400) LCCC
3Y 8 — 8 12 O Gate 3 output
4A 13 — 12 18 I Gate 4 input
4B 12 — 13 19 I Gate 4 input
4Y 11 — 14 16 O Gate 4 output
GND 7 4 11 10 — Ground
NC — — — 1, 5, 7,
11, 15, 17 — No connect
VCC 14 8 4 20 — Power supply
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltage values are with respect to network ground terminal.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VCC(2) 7 V
Input voltage SNx400 and SNxS400 5.5 V
SNx4LS00 7
Junction temperature, TJ150 °C
Storage temperature, Tstg –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance. ESD
Tested on SN74LS00N package.
6.2 ESD Ratings: SN74LS00 VALUE UNIT
V(ESD) Electrostatic
discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±2000
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
VCC Supply voltage SN54xx00 4.5 5 5.5 V
SN74xx00 4.75 5 5.25
VIH High-level input voltage 2 V
VIL Low-level input voltage SNx400, SN7LS400, and SNx4S00 0.8 V
SN54LS00 0.7
IOH High-level output current SN5400, SN54LS00, and SN74LS00 –0.4 mA
SNx4S00 –1
IOL Low-level output current
SNx400 16
mA
SN5LS400 4
SN7LS400 8
SNx4S00 20
5
SN5400
,
SN54LS00
,
SN54S00
SN7400
,
SN74LS00
,
SN74S00
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
TAOperating free-air temperature SN54xx00 –55 125 °C
SN74xx00 0 70
6
SN5400
,
SN54LS00
,
SN54S00
SN7400
,
SN74LS00
,
SN74S00
SDLS025D –DECEMBER 1983–REVISED MAY 2017
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Product Folder Links: SN5400 SN54LS00 SN54S00 SN7400 SN74LS00 SN74S00
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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The package thermal impedance is calculated in accordance with JESD 51-7.
6.4 Thermal Information
THERMAL METRIC(1)(2) SN74LS00
UNITD (SOIC) DB (SSOP) N (PDIP) NS (SO)
14 PINS 14 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 90.9 102.8 54.8 89.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 51.9 53.3 42.1 48.1 °C/W
RθJB Junction-to-board thermal resistance 48 53.4 34.8 50.1 °C/W
ψJT Junction-to-top characterization parameter 18.6 16.5 26.9 16.7 °C/W
ψJB Junction-to-board characterization parameter 47.8 52.9 34.7 49.8 °C/W
6.5 Electrical Characteristics: SNx400
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIK VCC = MIN and II= –12 mA –1.5 V
VOH VCC = MIN, VIL = 0.8 V, and IOH = –0.4 mA 2.4 3.4 V
VOL VCC = MIN, VIH = 2 V, and IOL = 16 mA 0.2 0.4 V
IIVCC = MAX and VI= 5.5 V 1 mA
IIH VCC = MAX and VI= 2.4 V 40 µA
IIL VCC = MAX and VI= 0.4 V –1.6 mA
IOS VCC = MAX SN5400 –20 –55 mA
SN7400 –18 –55
ICCH VCC = MAX and VI= 0 V 4 8 mA
ICCL VCC = MAX and VI= 4.5 V 12 22 mA
6.6 Electrical Characteristics: SNx4LS00
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIK VCC = MIN and II= –18 mA –1.5 V
VOH VCC = MIN, VIL = MAX, and IOH = –0.4 mA 2.5 3.4 V
VOL VCC = MIN and VIH = 2 V IOL = 4 mA 0.25 0.4 V
IOL = 8 mA (SN74LS00) 0.35 0.5
IIVCC = MAX and VI= 7 V 0.1 mA
IIH VCC = MAX and VI= 2.7 V 20 µA
IIL VCC = MAX and VI= 0.4 V –0.4 mA
IOS VCC = MAX –20 –100 mA
ICCH VCC = MAX and VI= 0 V 0.8 1.6 mA
ICCL VCC = MAX and VI= 4.5 V 2.4 4.4 mA
6.7 Electrical Characteristics: SNx4S00
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIK VCC = MIN and II= –18 mA –1.2 V
VOH VCC = MIN, VIL = 0.8 V, and IOH = –1 mA 2.5 3.4 V
VOL VCC = MIN, VIH = 2 V, and IOL = 20 mA 0.5 V
IIVCC = MAX and VI= 5.5 V 1 mA
IIH VCC = MAX and VI= 2.7 V 50 µA
IIL VCC = MAX and VI= 0.5 V –2 mA
7
SN5400
,
SN54LS00
,
SN54S00
SN7400
,
SN74LS00
,
SN74S00
www.ti.com
SDLS025D –DECEMBER 1983–REVISED MAY 2017
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Electrical Characteristics: SNx4S00 (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOS VCC = MAX –40 –100 mA
ICCH VCC = MAX and VI= 0 V 10 16 mA
ICCL VCC = MAX and VI= 4.5 V 20 36 mA
6.8 Switching Characteristics: SNx400
VCC = 5 V, TA= 25°C, and over operating free-air temperature range (unless otherwise noted). See Figure 2.
PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
tPLH A or B Y RL= 400 Ωand CL= 15 pF 11 22 ns
tPHL 7 15
6.9 Switching Characteristics: SNx4LS00
VCC = 5 V, TA= 25°C, and over operating free-air temperature range (unless otherwise noted). See Figure 2.
PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
tPLH A or B Y RL= 2 kΩand CL= 15 pF 9 15 ns
tPHL 10 15
6.10 Switching Characteristics: SNx4S00
VCC = 5 V, TA= 25°C, and over operating free-air temperature range (unless otherwise noted). See Figure 2.
PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
tPLH A or B Y RL= 280 Ωand CL= 15 pF 3 4.5
ns
RL= 280 Ωand CL= 50 pF 4.5
tPHL A or B Y RL= 280 Ωand CL= 15 pF 3 5
RL= 280 Ωand CL= 50 pF 5
8
SN5400
,
SN54LS00
,
SN54S00
SN7400
,
SN74LS00
,
SN74S00
SDLS025D –DECEMBER 1983–REVISED MAY 2017
www.ti.com
Product Folder Links: SN5400 SN54LS00 SN54S00 SN7400 SN74LS00 SN74S00
Submit Documentation Feedback Copyright © 1983–2017, Texas Instruments Incorporated
6.11 Typical Characteristics
CL= 15 pF
Figure 1. TPHL (Across Devices)
tPHL tPLH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
1 kΩ
NOTES: A. CLincludes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. All input pulses are supplied by generators having the following characteristics: PRR ≤1 MHz, ZO≈50 Ω; trand tf≤7 ns for Series
54/74 devices and trand tf≤2.5 ns for Series 54S/74S devices.
F. The outputs are measured one at a time with one input transition per measurement.
S1
S2
tPHZ
tPLZ
tPZL
tPZH
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
Waveform 1
(see Notes C
and D)
Waveform 2
(see Notes C
and D)
≈1.5 V
VOH − 0.5 V
VOL + 0.5 V
≈1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
tw
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
VOH
VOL
9
SN5400
,
SN54LS00
,
SN54S00
SN7400
,
SN74LS00
,
SN74S00
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7 Parameter Measurement Information
7.1 Propagation Delays, Setup and Hold Times, and Pulse Width
Figure 2. Load Circuits and Voltage Waveforms
A
B
Y
10
SN5400
,
SN54LS00
,
SN54S00
SN7400
,
SN74LS00
,
SN74S00
SDLS025D –DECEMBER 1983–REVISED MAY 2017
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Product Folder Links: SN5400 SN54LS00 SN54S00 SN7400 SN74LS00 SN74S00
Submit Documentation Feedback Copyright © 1983–2017, Texas Instruments Incorporated
8 Detailed Description
8.1 Overview
The SNx4xx00 devices are quadruple, 2-input NAND gates which perform the Boolean function Y = A .B or Y =
A + B in positive logic.
8.2 Functional Block Diagram
8.3 Feature Description
The operating voltage of SN74xx00 is from 4.75-V to 5.25-V VCC. The operating voltage of SN54xx00 is from 4.5-
V to 5.5-V VCC. The SN54xx00 devices are rated from –55°C to 125°C whereas SN74xx00 device are rated from
0°C to 70°C.
8.4 Device Functional Modes
Table 1 lists the functions of the devices.
Table 1. Functional Table (Each Gate)
INPUTS OUTPUT
A B Y
H H L
L X H
X L H
Error1
Error2
Error Flag
Sensor1
Sensor2
11
SN5400
,
SN54LS00
,
SN54S00
SN7400
,
SN74LS00
,
SN74S00
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SNx4xx00 devices are quadruple, 2-input NAND gate. A typical application of NAND gate can be as an error
indicator as shown in Figure 3. If either of the sensor has an error, the error flag is high to indicate system error.
9.2 Typical Application
Figure 3. Typical Application Diagram
9.2.1 Design Requirements
These devices use BJT technology and have unbalanced output drive with IOL and IOH specified as per the
Recommended Operating Conditions.
9.2.2 Detailed Design Procedure
• Recommended Input Conditions:
– The inputs are TTL compliant.
– Because the base-emitter junction at the inputs breaks down, no voltage greater than 5.5 V must be
applied to the inputs.
– Specified high and low levels: See VIH and VIL in Recommended Operating Conditions.
• Recommended Output Conditions:
– No more than one output must be shorted at a time as per the Electrical Characteristics: SNx400 for
thermal stability and reliability.
– For high-current applications, consider thermal characteristics of the package listed in Thermal
Information.
Device
TPLH(ns)
1 2 3
0
5
10
15
20
25
D001
TpLHmax D1 '00, D2 'LS00, D3 'S00
TpLHtyp D1 '00, D2 'LS00, D3 'S00
12
SN5400
,
SN54LS00
,
SN54S00
SN7400
,
SN74LS00
,
SN74S00
SDLS025D –DECEMBER 1983–REVISED MAY 2017
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Typical Application (continued)
9.2.3 Application Curve
CL= 15 pF
Figure 4. TPLH (Across Devices)
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions for each of the SNx4LS00, SNx4S00, and SNx400 devices.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,
0.1 µF is recommended; if there are multiple VCC pins, then 0.01 µF or 0.022 µF is recommended for each power
pin. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. A 0.1 µF and a
1 µF are commonly used in parallel. The bypass capacitor must be installed as close to the power pin as
possible for best results.
Output
&
Input
Rs
VCC
CC(min)
S(max)
IH
V 2.4 V
Rn I
CCP
S(min)
V 5.5 V
R1mA
13
SN5400
,
SN54LS00
,
SN54S00
SN7400
,
SN74LS00
,
SN74S00
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11 Layout
11.1 Layout Guidelines
When using multiple bit logic, devices inputs must never float.
Devices with multiple-emitter inputs (SN74 and SN74S series) need special care. Because no voltage greater
than 5.5 V must be applied to the inputs (if exceeded, the base-emitter junction at the inputs breaks down), the
inputs of these devices must be connected to the supply voltage, VCC, through series resistor, RS(see Figure 5).
This resistor must be dimensioned such that the current flowing into the gate or gates, which results from
overvoltage, does not exceed 1 mA. However, because the high-level input current of the circuits connected to
the gate flows through this resistor, the resistor must be dimensioned so that the voltage drop across it still
allows the required high level. Equation 1 and Equation 2 are for dimensioning resistor, RS, and several inputs
can be connected to a high level through a single resistor if the following conditions are met.
(1)
where
• n = number of inputs connected
• IIH = high input current (typical 40 µA)
• VCC(min) = minimum supply voltage, VCC
• VCCP = maximum peak voltage of the supply voltage, VCC (about 7 V) (2)
11.2 Layout Example
Figure 5. Series Resistor Connected to Unused Inputs of Multiple-Emitter Transistors
14
SN5400
,
SN54LS00
,
SN54S00
SN7400
,
SN74LS00
,
SN74S00
SDLS025D –DECEMBER 1983–REVISED MAY 2017
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Product Folder Links: SN5400 SN54LS00 SN54S00 SN7400 SN74LS00 SN74S00
Submit Documentation Feedback Copyright © 1983–2017, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Designing With Logic (SDYA009)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
SN5400 Click here Click here Click here Click here Click here
SN54LS00 Click here Click here Click here Click here Click here
SN54S00 Click here Click here Click here Click here Click here
SN7400 Click here Click here Click here Click here Click here
SN74LS00 Click here Click here Click here Click here Click here
SN74S00 Click here Click here Click here Click here Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
15
SN5400
,
SN54LS00
,
SN54S00
SN7400
,
SN74LS00
,
SN74S00
www.ti.com
SDLS025D –DECEMBER 1983–REVISED MAY 2017
Product Folder Links: SN5400 SN54LS00 SN54S00 SN7400 SN74LS00 SN74S00
Submit Documentation FeedbackCopyright © 1983–2017, Texas Instruments Incorporated
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Jan-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
JM38510/00104BCA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
00104BCA
JM38510/00104BDA ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
00104BDA
JM38510/07001BCA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
07001BCA
JM38510/07001BDA ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
07001BDA
JM38510/30001B2A ACTIVE LCCC FK 20 1 Non-RoHS
& Green POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
30001B2A
JM38510/30001BCA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
30001BCA
JM38510/30001BDA ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
30001BDA
JM38510/30001SCA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/30001S
CA
JM38510/30001SDA ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/30001S
DA
M38510/00104BCA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
00104BCA
M38510/00104BDA ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
00104BDA
M38510/07001BCA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
07001BCA
M38510/07001BDA ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
07001BDA
M38510/30001B2A ACTIVE LCCC FK 20 1 Non-RoHS
& Green POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
30001B2A
M38510/30001BCA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
30001BCA
M38510/30001BDA ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
30001BDA
PACKAGE OPTION ADDENDUM
www.ti.com 24-Jan-2021
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
M38510/30001SCA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/30001S
CA
M38510/30001SDA ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/30001S
DA
SN5400J ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 SN5400J
SN54LS00J ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 SN54LS00J
SN54S00J ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 SN54S00J
SN7400D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 7400
SN7400DG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 7400
SN7400N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN7400N
SN7400NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN7400N
SN74LS00D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS00
SN74LS00DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS00
SN74LS00DG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS00
SN74LS00DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS00
SN74LS00DRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS00
SN74LS00N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74LS00N
SN74LS00NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74LS00N
SN74LS00NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 74LS00
SN74LS00NSRG4 ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 74LS00
SN74LS00PSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS00
SN74LS00PSRG4 ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS00
PACKAGE OPTION ADDENDUM
www.ti.com 24-Jan-2021
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74S00D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 S00
SN74S00DE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 S00
SN74S00N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74S00N
SNJ5400J ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 SNJ5400J
SNJ5400W ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 SNJ5400W
SNJ54LS00FK ACTIVE LCCC FK 20 1 Non-RoHS
& Green POST-PLATE N / A for Pkg Type -55 to 125 SNJ54LS00FK
SNJ54LS00J ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 SNJ54LS00J
SNJ54LS00W ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 SNJ54LS00W
SNJ54S00FK ACTIVE LCCC FK 20 1 Non-RoHS
& Green POST-PLATE N / A for Pkg Type -55 to 125 SNJ54S
00FK
SNJ54S00J ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 SNJ54S00J
SNJ54S00W ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 SNJ54S00W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Jan-2021
Addendum-Page 4
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN5400, SN54LS00, SN54LS00-SP, SN54S00, SN7400, SN74LS00, SN74S00 :
•Catalog: SN7400, SN74LS00, SN54LS00, SN74S00
•Military: SN5400, SN54LS00, SN54S00
•Space: SN54LS00-SP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LS00DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LS00NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Dec-2020
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LS00DR SOIC D 14 2500 853.0 449.0 35.0
SN74LS00NSR SO NS 14 2000 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Dec-2020
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
14X .008-.014
[0.2-0.36]
TYP
-15
0
AT GAGE PLANE
-.314.308 -7.977.83[ ]
14X -.026.014 -0.660.36[ ]
14X -.065.045 -1.651.15[ ]
.2 MAX TYP
[5.08] .13 MIN TYP
[3.3]
TYP-.060.015 -1.520.38[ ]
4X .005 MIN
[0.13]
12X .100
[2.54]
.015 GAGE PLANE
[0.38]
A
-.785.754 -19.9419.15[ ]
B -.283.245 -7.196.22[ ]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
78
14
1
PIN 1 ID
(OPTIONAL)
SCALE 0.900
SEATING PLANE
.010 [0.25] C A B
www.ti.com
EXAMPLE BOARD LAYOUT
ALL AROUND
[0.05] MAX.002
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
METAL
(.063)
[1.6]
(R.002 ) TYP
[0.05]
14X ( .039)
[1]
( .063)
[1.6]
12X (.100 )
[2.54]
(.300 ) TYP
[7.62]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
SEE DETAIL A SEE DETAIL B
SYMM
SYMM
1
78
14
DETAIL A
SCALE: 15X
SOLDER MASK
OPENING
METAL
DETAIL B
13X, SCALE: 15X
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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