Features * High Performance, Low Power AVR(R) 8-Bit Microcontroller * Advanced RISC Architecture * * * * * * * * - 120 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation Non-volatile Program and Data Memories - 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny25/45/85) * Endurance: 10,000 Write/Erase Cycles - 128/256/512 Bytes In-System Programmable EEPROM (ATtiny25/45/85) * Endurance: 100,000 Write/Erase Cycles - 128/256/512 Bytes Internal SRAM (ATtiny25/45/85) - Programming Lock for Self-Programming Flash Program and EEPROM Data Security Peripheral Features - 8-bit Timer/Counter with Prescaler and Two PWM Channels - 8-bit High Speed Timer/Counter with Separate Prescaler * 2 High Frequency PWM Outputs with Separate Output Compare Registers * Programmable Dead Time Generator - Universal Serial Interface with Start Condition Detector - 10-bit ADC * 4 Single Ended Channels * 2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x) - Programmable Watchdog Timer with Separate On-chip Oscillator - On-chip Analog Comparator Special Microcontroller Features - debugWIRE On-chip Debug System - In-System Programmable via SPI Port - External and Internal Interrupt Sources - Low Power Idle, ADC Noise Reduction, and Power-down Modes - Enhanced Power-on Reset Circuit - Programmable Brown-out Detection Circuit - Internal Calibrated Oscillator I/O and Packages - Six Programmable I/O Lines - 8-pin SOIC - 20-pin QFN Operating Voltage - 2.7 - 5.5V for ATtiny25/45/85 Speed Grade - ATtiny25/45/85: 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V Automotive Temperature Range - -40C to +125C Low Power Consumption - Active Mode: * 1 MHz, 2.7V: 300A - Power-down Mode: * 0.2A at 2.7V 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash ATtiny25 ATtiny45 ATtiny85 Automotive 7598H-AVR-07/09 1. Pin Configurations Figure 1-1. Pinout ATtiny25/45/85 SOIC (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/XTAL1/OC1B/ADC3) PB3 (PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4 GND 1 2 3 4 8 7 6 5 VCC PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2) PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1) PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0) 2. Overview The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 2.1 Block Diagram Figure 2-1. Block Diagram 8-BIT DATABUS CALIBRATED INTERNAL OSCILLATOR PROGRAM COUNTER STACK POINTER PROGRAM FLASH SRAM WATCHDOG TIMER TIMING AND CONTROL VCC MCU CONTROL REGISTER MCU STATUS REGISTER GND INSTRUCTION REGISTER INSTRUCTION DECODER CONTROL LINES GENERAL PURPOSE REGISTERS TIMER/ COUNTER0 X Y Z TIMER/ COUNTER1 ALU UNIVERSAL SERIAL INTERFACE STATUS REGISTER INTERRUPT UNIT PROGRAMMING LOGIC DATA EEPROM DATA REGISTER PORT B DATA DIR. REG.PORT B OSCILLATORS ADC / ANALOG COMPARATOR PORT B DRIVERS RESET PB0-PB5 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. 3 7598H-AVR-07/09 The ATtiny25/45/85 provides the following features: 2/4/8K byte of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel(R)'s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 2.2 Automotive Quality Grade The ATtiny25/45/85 have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949. This data sheet contains limit values extracted from the results of extensive characterization (Temperature and Voltage). The quality and reliability of the ATtiny25/45/85 have been verified during regular product qualification as per AEC-Q100 grade 1. As indicated in the ordering information paragraph, the products are available in three different temperature grades, but with equivalent quality and reliability objectives. Different temperature identifiers have been defined as listed in Table 2-1. Table 2-1. Temperature 4 Temperature Grade Identification for Automotive Products Temperature Identifier Comments -40 ; +85 T Similar to Industrial Temperature Grade but with Automotive Quality -40 ; +105 T1 Reduced Automotive Temperature Range -40 ; +125 Z Full AutomotiveTemperature Range ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 2.3 2.3.1 Pin Descriptions VCC Supply voltage. 2.3.2 GND Ground. 2.3.3 Port B (PB5..PB0) Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny25/45/85 as listed on page 54. 2.3.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 8-1 on page 37. Shorter pulses are not guaranteed to generate a reset. 3. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. 4. AVR CPU Core 4.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 5 7598H-AVR-07/09 4.2 Architectural Overview Figure 4-1. Block Diagram of the AVR Architecture Data Bus 8-bit Flash Program Memory Program Counter Status and Control 32 x 8 General Purpose Registrers Control Lines Direct Addressing Instruction Decoder Indirect Addressing Instruction Register Interrupt Unit Watchdog Timer ALU Analog Comparator I/O Module1 Data SRAM I/O Module 2 I/O Module n EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture - with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File - in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. 6 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions are 16-bits wide. There are also 32-bit instructions. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. 4.3 ALU - Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories - arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the "Instruction Set" section for a detailed description. 4.4 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. The AVR Status Register - SREG - is defined as: Bit 7 6 5 4 3 2 1 0 I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG 7 7598H-AVR-07/09 * Bit 7 - I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. * Bit 6 - T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. * Bit 5 - H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the "Instruction Set Description" for detailed information. * Bit 4 - S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two's Complement Overflow Flag V. See the "Instruction Set Description" for detailed information. * Bit 3 - V: Two's Complement Overflow Flag The Two's Complement Overflow Flag V supports two's complement arithmetics. See the "Instruction Set Description" for detailed information. * Bit 2 - N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. * Bit 1 - Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. * Bit 0 - C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. 8 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 4.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: * One 8-bit output operand and one 8-bit result input * Two 8-bit output operands and one 8-bit result input * Two 8-bit output operands and one 16-bit result input * One 16-bit output operand and one 16-bit result input Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 4-2. AVR CPU General Purpose Working Registers 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 ... R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 ... R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 4-2, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 9 7598H-AVR-07/09 4.5.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3. Figure 4-3. The X-, Y-, and Z-registers 15 X-register XH XL 7 0 R27 (0x1B) 15 Y-register 0 R26 (0x1A) YH YL 7 0 R29 (0x1D) Z-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.6 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit Read/Write Initial Value 10 15 14 13 12 11 10 9 8 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 4.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 4-4. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 4-5. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 4.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in "Interrupts" on page 45. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request 0. 11 7598H-AVR-07/09 When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction - RETI - is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.. Assembly Code Example in r16, SREG cli ; store SREG value ; disable interrupts during timed sequence sbi EECR, EEMWE ; start EEPROM write sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ 12 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 4.8.1 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 5. AVR ATtiny25/45/85 Memories This section describes the different memories in the ATtiny25/45/85. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny25/45/85 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 5.1 In-System Re-programmable Flash Program Memory The ATtiny25/45/85 contains 2/4/8K byte On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 1024/2048/4096 x 16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny25/45/85 Program Counter (PC) is 10/11/12 bits wide, thus addressing the 1024/2048/4096 Program memory locations. "Memory Programming" on page 134 contains a detailed description on Flash data serial downloading using the SPI pins. Constant tables can be allocated within the entire Program memory address space (see the LPM - Load Program memory instruction description). Timing diagrams for instruction fetch and execution are presented in "Instruction Execution Timing" on page 11. 13 7598H-AVR-07/09 Figure 5-1. Program Memory Map Program Memory 0x0000 0x03FF/0x07FF 5.2 SRAM Data Memory Figure 5-2 shows how the ATtiny25/45/85 SRAM Memory is organized. The lower 224/352/607 Data memory locations address both the Register File, the I/O memory and the internal data SRAM. The first 32 locations address the Register File, the next 64 locations the standard I/O memory, and the last 128/256/512 locations address the internal data SRAM. The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers. The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of internal data SRAM in the ATtiny25/45/85 are all accessible through all these addressing modes. The Register File is described in "General Purpose Register File" on page 9. Figure 5-2. Data Memory Map Data Memory 32 Registers 64 I/O Registers 0x0000 - 0x001F 0x0020 - 0x005F 0x0060 Internal SRAM (128/256/512 x 8) 0x0DF/0x015F/0x025F 14 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 5.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 5-3. Figure 5-3. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction 5.3 Next Instruction EEPROM Data Memory The ATtiny25/45/85 contains 128/256/512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. For a detailed description of Serial data downloading to the EEPROM, see page 138. 5.3.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in Table 5-1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See "Preventing EEPROM Corruption" on page 20 for details on how to avoid problems in these situations. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to "Atomic Byte Programming" on page 18 and "Split Byte Programming" on page 18 for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. 15 7598H-AVR-07/09 5.3.2 EEPROM Address Register High - EEARH Bit 7 6 5 4 3 2 1 0 - - - - - - - EEAR8 Read/Write R R R R R R R R/W Initial Value X X X X X X X X EEARH * Bit 7..1 - Res6..0: Reserved Bits These bits are reserved for future use and will always read as 0 in ATtiny25/45/85. * Bits 0 - EEAR8: EEPROM Address The EEPROM Address Register - EEARH - specifies the high EEPROM address in the 128/256/512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 127/255/511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. 5.3.3 EEPROM Address Register - EEARL Bit 7 6 5 4 3 2 1 0 EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X EEARL * Bits 7..0 - EEAR7..0: EEPROM Address The EEPROM Address Register - EEARL - specifies the low EEPROM address in the 128/256/512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 127/255/511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. 5.3.4 EEPROM Data Register - EEDR Bit 7 6 5 4 3 2 1 0 EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X EEDR * Bits 7..0 - EEDR7..0: EEPROM Data For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 5.3.5 EEPROM Control Register - EECR Bit 7 6 5 4 3 2 1 0 - - EEPM1 EEPM0 EERIE EEMPE EEPE EERE Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0 EECR * Bit 7 - Res: Reserved Bit This bit is reserved for future use and will always read as 0 in ATtiny25/45/85. For compatibility with future AVR devices, always write this bit to zero. After reading, mask out this bit. 16 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 * Bit 6 - Res: Reserved Bit This bit is reserved in the ATtiny25/45/85 and will always read as zero. * Bits 5, 4 - EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bits setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 5-1. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 5-1. EEPROM Mode Bits EEPM1 EEPM0 Programming Time 0 0 3.4 ms Erase and Write in one operation (Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.8 ms Write Only 1 1 - Operation Reserved for future use * Bit 3 - EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant interrupt when Non-volatile memory is ready for programming. * Bit 2 - EEMPE: EEPROM Master Program Enable The EEMPE bit determines whether writing EEPE to one will have effect or not. When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles. * Bit 1 - EEPE: EEPROM Program Enable The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM. When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. When the write access time has elapsed, the EEPE bit is cleared by hardware. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed. * Bit 0 - EERE: EEPROM Read Enable The EEPROM Read Enable Signal - EERE - is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register. 17 7598H-AVR-07/09 5.3.6 Atomic Byte Programming Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the user must write the address into the EEAR Register and data into EEDR Register. If the EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the erase/write operation. Both the erase and write cycle are done in one operation and the total programming time is given in Table 20-1. The EEPE bit remains set until the erase and write operations are completed. While the device is busy with programming, it is not possible to do any other EEPROM operations. 5.3.7 Split Byte Programming It is possible to split the erase and write cycle in two different operations. This may be useful if the system requires short access time for some limited period of time (typically if the power supply voltage falls). In order to take advantage of this method, it is required that the locations to be written have been erased before the write operation. But since the erase and write operations are split, it is possible to do the erase operations when the system allows doing time-critical operations (typically after Power-up). 5.3.8 Erase To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writing the EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (programming time is given in Table 20-1). The EEPE bit remains set until the erase operation completes. While the device is busy programming, it is not possible to do any other EEPROM operations. 5.3.9 Write To write a location, the user must write the address into EEAR and the data into EEDR. If the EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger the write operation only (programming time is given in Table 20-1). The EEPE bit remains set until the write operation completes. If the location to be written has not been erased before write, the data that is stored must be considered as lost. While the device is busy with programming, it is not possible to do any other EEPROM operations. The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the requirements described in "Oscillator Calibration Register - OSCCAL" on page 26. The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions 18 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set Programming mode ldi r16, (0<<EEPM1)|(0<<EEPM0) out EECR, r16 ; Set up address (r17) in address register out EEARL, r17 ; Write data (r16) to data register out EEDR,r16 ; Write logical one to EEMWE sbi EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret C Code Example void EEPROM_write(unsigned char ucAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<<EEPE)) ; /* Set Programming mode */ EECR = (0<<EEPM1)|(0>>EEPM0) /* Set up address and data registers */ EEARL = ucAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); } 19 7598H-AVR-07/09 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_read ; Set up address (r17) in address register out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ; Read data from data register in r16,EEDR ret C Code Example unsigned char EEPROM_read(unsigned char ucAddress) { /* Wait for completion of previous write */ while(EECR & (1<<EEPE)) ; /* Set up address register */ EEARL = ucAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR; } 5.3.10 Preventing EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low. EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 20 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 5.4 I/O Memory The I/O space definition of the ATtiny25/45/85 is shown in "Register Summary" on page 182. All ATtiny25/45/85 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. The I/O and Peripherals Control Registers are explained in later sections. 6. System Clock and Clock Options 6.1 Clock Systems and their Distribution Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in "Power Management and Sleep Modes" on page 31. The clock systems are detailed below. Figure 6-1. Clock Distribution General I/O Modules ADC CPU Core Flash and EEPROM RAM clkPCK clkI/O clkCPU AVR Clock Control Unit clkFLASH clkADC Reset Logic Watchdog Timer Source clock Watchdog clock Clock Multiplexer External Clock Calibrated Crystal RC Oscillator clkPCK System Clock Prescaler Watchdog Oscillator Low-Frequency Crystal Oscillator PLL Oscillator Calibrated RC Oscillator 21 7598H-AVR-07/09 6.1.1 CPU Clock - clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. 6.1.2 I/O Clock - clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. 6.1.3 Flash Clock - clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. 6.1.4 ADC Clock - clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 6.1.5 Internal PLL for Fast Peripheral Clock Generation - clkPCK The internal PLL in ATtiny25/45/85 generates a clock frequency that is 8x multiplied from a source input. The source of the PLL input clock is the output of the internal RC oscillator having a frequency of 8.0 MHz. Thus the output of the PLL, the fast peripheral clock is 64 MHz. The fast peripheral clock, or a clock prescaled from that, can be selected as the clock source for Timer/Counter1. See the Figure 6-2 on page 23. The PLL is locked on the RC oscillator and adjusting the RC oscillator via OSCCAL register will adjust the fast peripheral clock at the same time. However, even if the RC oscillator is taken to a higher frequency than 8 MHz, the fast peripheral clock frequency saturates at 85 MHz (worst case) and remains oscillating at the maximum frequency. It should be noted that the PLL in this case is not locked any longer with the RC oscillator clock. Therefore, it is recommended not to take the OSCCAL adjustments to a higher frequency than 8 MHz in order to keep the PLL in the correct operating range. The internal PLL is enabled only when the PLLE bit in PLLCSR is set or the PLLCK fuse is programmed (`0'). The bit PLOCK from PLLCSR is set when PLL is locked. Both internal RC oscillator and PLL are switched off in power down and stand-by sleep modes. 22 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Figure 6-2. PCK Clocking System OSCCAL PLLE PLLCK & CKSEL FUSES CLKPS3..0 PLOCK Lock Detector RC OSCILLATOR 8.0 MHz / 6.4 MHz PCK PLL 8x / 4x 64 / 25.6 MHz DIVIDE BY 4 XTAL1 XTAL2 6.2 System Clock Prescaler SYSTEM CLOCK OSCILLATORS Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 6-1. Device Clocking Options Select(1) Device Clocking Option CKSEL3..0 External Clock 0000 PLL Clock 0001 Calibrated Internal RC Oscillator 8.0 MHz 0010 Watchdog Oscillator 128 kHz 0100 External Low-frequency Crystal 0110 External Crystal/Ceramic Resonator Reserved Note: 1000-1111 0101, 0111, 0011 1. For all fuses "1" means unprogrammed while "0" means programmed. The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down or Power-save, the selected clock source is used to time the start-up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 6-2. 23 7598H-AVR-07/09 Table 6-2. 6.3 Number of Watchdog Oscillator Cycles Typ Time-out Number of Cycles 4 ms 512 64 ms 8K (8,192) Default Clock Source The device is shipped with CKSEL = "0010", SUT = "10", and CKDIV8 programmed. The default clock source setting is therefore the Internal RC Oscillator running at 8 MHz with longest start-up time and an initial system clock prescaling of 8. This default setting ensures that all users can make their desired clock source setting using an In-System or High-voltage Programmer. 6.4 Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 6-3. Either a quartz crystal or a ceramic resonator may be used. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 6-3. For ceramic resonators, the capacitor values given by the manufacturer should be used. Figure 6-3. Crystal Oscillator Connections C2 C1 XTAL2 XTAL1 GND The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 6-3. Table 6-3. Crystal Oscillator Operating Modes CKSEL3..1 Frequency Range (MHz) Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) 100(1) 0.4 - 0.9 - 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 - 12 - 22 Notes: 1. This option should not be used with crystals, only with ceramic resonators. The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 6-4. 24 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Table 6-4. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 SUT1..0 Start-up Time from Power-down and Power-save 0 00 258 CK(1) 14CK + 4 ms Ceramic resonator, fast rising power 0 01 258 CK(1) 14CK + 64 ms Ceramic resonator, slowly rising power 0 10 1K CK(2) 14CK Ceramic resonator, BOD enabled 0 11 1K CK(2) 14CK + 4 ms Ceramic resonator, fast rising power 1 00 1K CK(2) 14CK + 64 ms Ceramic resonator, slowly rising power 1 01 16K CK 14CK Crystal Oscillator, BOD enabled 1 10 16K CK 14CK + 4 ms Crystal Oscillator, fast rising power 1 11 16K CK 14CK + 64 ms Crystal Oscillator, slowly rising power Notes: Additional Delay from Reset (VCC = 5.0V) Recommended Usage 1. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals. 2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. 6.5 Low-frequency Crystal Oscillator To use a 32.768 kHz watch crystal as the clock source for the device, the low-frequency crystal oscillator must be selected by setting CKSEL fuses to `0110'. The crystal should be connected as shown in Figure 6-3. Refer to the 32 kHz Crystal Oscillator Application Note for details on oscillator operation and how to choose appropriate values for C1 and C2. When this oscillator is selected, start-up times are determined by the SUT fuses as shown in Table 6-5. Table 6-5. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection SUT1..0 Start-up Time from Power Down and Power Save Additional Delay from Power On Reset (VCC = 5.0V) 00 1K CK(1) 4 ms Fast rising power or BOD enabled 01 1K CK(1) 64 ms Slowly rising power 10 32K CK 64 ms Stable frequency at start-up 11 Notes: Recommended usage Reserved 1. These options should only be used if frequency stability at start-up is not important for the application. 25 7598H-AVR-07/09 6.6 Calibrated Internal RC Oscillator The calibrated internal RC Oscillator provides an 8.0 MHz clock. The frequency is the nominal value at 3V and 25C. If the frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse must be programmed in order to divide the internal frequency by 8 during start-up. See "System Clock Prescaler" on page 29. for more details. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 6-6. If selected, it will operate with no external components. During reset, hardware loads the calibration byte into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. At 3V and 25C, this calibration gives a frequency within 1% of the nominal frequency. When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section "Calibration Byte" on page 137. Table 6-6. Note: Internal Calibrated RC Oscillator Operating Modes CKSEL3..0 Nominal Frequency 0010(1) 8.0 MHz 1. The device is shipped with this option selected. When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 6-7. Table 6-7. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection SUT1..0 Start-up Time from Power-down Additional Delay from Reset (VCC = 5.0V) 00 6 CK 14CK + 4 ms BOD enabled 01 6 CK 14CK + 4 ms Fast rising power 6 CK 14CK + 64 ms Slowly rising power 10 (1) 11 Note: 6.6.1 Recommended Usage Reserved 1. The device is shipped with this option selected. Oscillator Calibration Register - OSCCAL Bit Read/Write Initial Value 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W OSCCAL Device Specific Calibration Value * Bits 7..0 - CAL7..0: Oscillator Calibration Value Writing the calibration byte to this address will trim the internal Oscillator to remove process variations from the Oscillator frequency. This is done automatically during Chip Reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal Oscillator. Writing 0xFF to the register gives the highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 8.8 MHz frequency. Otherwise, the EEPROM or Flash write may fail. 26 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80. The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range. Incrementing CAL6..0 by 1 will give a frequency increment of less than 2% in the frequency range 7.3 - 8.1 MHz. Avoid changing the calibration value in large steps when calibrating the calibrated internal RC Oscillator to ensure stable operation of the MCU. A variation in frequency of more than 2% from one cycle to the next can lead to unpredicatble behavior. Changes in OSCCAL should not exceed 0x20 for each calibration. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency Table 6-8. 6.7 Internal RC Oscillator Frequency Range OSCCAL Value Min Frequency in Percentage of Nominal Frequency Max Frequency in Percentage of Nominal Frequency 0x00 50% 100% 0x3F 75% 150% 0x7F 100% 200% External Clock To drive the device from an external clock source, CLKI should be driven as shown in Figure 6-4. To run the device on an external clock, the CKSEL Fuses must be programmed to "00". Figure 6-4. External Clock Drive Configuration EXTERNAL CLOCK SIGNAL CLKI GND When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 6-9. Table 6-9. Start-up Times for the External Clock Selection SUT1..0 Start-up Time from Power-down and Power-save Additional Delay from Reset 00 6 CK 14CK 01 6 CK 14CK + 4 ms Fast rising power 10 6 CK 14CK + 64 ms Slowly rising power 11 Recommended Usage BOD enabled Reserved 27 7598H-AVR-07/09 Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to "System Clock Prescaler" on page 29 for details. 6.7.1 High Frequency PLL Clock - PLLCLK There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator for the use of the Peripheral Timer/Counter1 and for the system clock source. When selected as a system clock source, by programming the CKSEL fuses to `0001', it is divided by four like shown in Table 6-10. When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 6-11. See also "PCK Clocking System" on page 23. Table 6-10. Table 6-11. 6.8 PLLCK Operating Modes CKSEL3..0 Nominal Frequency 0001 16 MHz Start-up Times for the PLLCK SUT1..0 Start-up Time from Power Down and Power Save Additional Delay from Reset (VCC = 5.0V) 00 1K CK 14CK + 8ms BOD enabled 01 16K CK 14CK + 8ms Fast rising power 10 1K CK 14CK + 68 ms Slowly rising power 11 16K CK 14CK + 68 ms Slowly rising power Recommended usage 128 kHz Internal Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The frequency is nominal at 3V and 25C. This clock may be select as the system clock by programming the CKSEL Fuses to "11". When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 6-12. Table 6-12. SUT1..0 Start-up Time from Power-down and Power-save Additional Delay from Reset 00 6 CK 14CK 01 6 CK 14CK + 4 ms Fast rising power 10 6 CK 14CK + 64 ms Slowly rising power 11 28 Start-up Times for the 128 kHz Internal Oscillator Recommended Usage BOD enabled Reserved ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 6.9 Clock Output Buffer The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system. Note that the clock will not be output during reset and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including the internal RC Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is used, it is the divided system clock that is output. 6.10 System Clock Prescaler The ATtiny25/45/85 system clock can be divided by setting the Clock Prescale Register - CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH are divided by a factor as shown in Table 6-13. 6.10.1 Clock Prescale Register - CLKPR Bit 7 6 5 4 3 2 1 0 CLKPCE - - - CLKPS3 CLKPS2 CLKPS1 CLKPS0 Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 CLKPR See Bit Description * Bit 7 - CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. * Bits 6..4 - Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. * Bits 3..0 - CLKPS3..0: Clock Prescaler Select Bits 3 - 0 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in Table 6-13. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. 29 7598H-AVR-07/09 The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to "0000". If CKDIV8 is programmed, CLKPS bits are reset to "0011", giving a division factor of eight at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selcted clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 6-13. 6.10.2 Clock Prescaler Select CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor 0 0 0 0 1 0 0 0 1 2 0 0 1 0 4 0 0 1 1 8 0 1 0 0 16 0 1 0 1 32 0 1 1 0 64 0 1 1 1 128 1 0 0 0 256 1 0 0 1 Reserved 1 0 1 0 Reserved 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved Switching Time When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting. 30 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 7. Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application's requirements. To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed. The SM1..0 bits in the MCUCR Register select which sleep mode (Idle, ADC Noise Reduction, or Power-down) will be activated by the SLEEP instruction. See Table 7-1 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Figure 6-1 on page 21 presents the different clock systems in the ATtiny25/45/85, and their distribution. The figure is helpful in selecting an appropriate sleep mode. 7.1 MCU Control Register - MCUCR The MCU Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR * Bit 7 - BODS: BOD Sleep BOD disable functionality is available in some devices, only. See "Limitations" on page 33. In order to disable BOD during sleep (see Table 7-2 on page 33) the BODS bit must be written to logic one. This is controlled by a timed sequence and the enable bit, BODSE in MCUCR. First,both BODS and BODSE must be set to one. Second, within four clock cycles, BODS must be set to one and BODSE must be set to zero. The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock cycles. In devices where Sleeping BOD has not been implemented this bit is unused and will always read zero. * Bit 5 - SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer's purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. * Bits 4, 3 - SM1..0: Sleep Mode Select Bits 2..0 These bits select between the three available sleep modes as shown in Table 7-1. 31 7598H-AVR-07/09 Table 7-1. Sleep Mode Select SM1 SM0 Sleep Mode 0 0 Idle 0 1 ADC Noise Reduction 1 0 Power-down 1 1 Stand-by mode * Bit 2 - BODSE: BOD Sleep Enable BOD disable functionality is available in some devices, only. See "Limitations" on page 33. The BODSE bit enables setting of BODS control bit, as explained on BODS bit description. BOD disable is controlled by a timed sequence. This bit is unused in devices where software BOD disable has not been implemented and will read as zero in those devices. 7.2 Idle Mode When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register - ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 7.3 ADC Noise Reduction Mode When the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the Watchdog to continue operating (if enabled). This sleep mode halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run. This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode. 7.4 Power-down Mode When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the Oscillator is stopped, while the external interrupts, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode halts all generated clocks, allowing operation of asynchronous modules only. 32 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to "External Interrupts" on page 58 for details.. Table 7-2. Active Clock Domains and Wake-up Sources in the Different Sleep Modes ADC Noise Reduction clkPCK Main Clock Source Enabled INT0 and Pin Change SPM/ EEPROM Ready USI Start Condition ADC Other I/O Watchdog Interrupt X X X X X X X X X X X X X(1) X X X X(1) Power-down Note: 7.5 Wake-up Sources clkADC Idle Oscillators clkIO clkFLASH Sleep Mode clkCPU Active Clock Domains X X X 1. For INT0, only level interrupt. Limitations BOD disable functionality has been implemented in the following devices, only: * ATtiny25, revision D, and newer * ATtiny45, revision D, and newer * ATtiny85, revision C, and newer 7.6 Power Reduction Register The Power Reduction Register, PRR, provides a method to stop the clock to individualperipherals to reduce power consumption. The current state of the peripheral is frozenand the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown. Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped. Bit 7 6 5 4 3 2 1 0 - - - - PRTIM1 PRTIM0 PRUSI PRADC Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PRR * Bits 7, 6, 5, 4- Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. * Bit 3- PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. 33 7598H-AVR-07/09 * Bit 2- PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. * Bit 1 - PRUSI: Power Reduction USI Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When waking up the USI again, the USI should be re initialized to ensure proper operation. * Bit 0 - PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. 7.7 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device's functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 7.7.1 Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to "Analog to Digital Converter" on page 111 for details on ADC operation. 7.7.2 Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to "Analog Comparator" on page 108 for details on how to configure the Analog Comparator. 7.7.3 Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to "Brown-out Detection" on page 38 for details on how to configure the Brown-out Detector. 7.7.4 Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to "Internal Voltage Reference" on page 40 for details on the start-up time. 34 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 7.7.5 Watchdog Timer If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to "Watchdog Timer" on page 41 for details on how to configure the Watchdog Timer. 7.7.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section "Digital Input Enable and Sleep Modes" on page 51 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an analog signal level close to VCC/2, the input buffer will use excessive power. For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). Refer to "Digital Input Disable Register 0 - DIDR0" on page 110 for details. 8. System Control and Reset 8.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP - Relative Jump - instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 8-1 shows the reset logic. Table 8-1 defines the electrical parameters of the reset circuitry. The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running. After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in "Clock Sources" on page 23. 8.2 Reset Sources The ATtiny25/45/85 has four sources of reset: * Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT). * External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. * Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled. * Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled. 35 7598H-AVR-07/09 Figure 8-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [1..0] Pull-up Resistor SPIKE FILTER Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[1:0] SUT[1:0] 8.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 8-1. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay, when VCC decreases below the detection level. 36 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Figure 8-2. MCU Start-up, RESET Tied to VCC V CCRR VCC VPORMAX VPORMIN RESET VRST tTOUT TIME-OUT INTERNAL RESET Figure 8-3. VCC MCU Start-up, RESET Extended Externally VPOT VRST RESET tTOUT TIME-OUT INTERNAL RESET Table 8-1. Symbol Power On Reset Specifications Parameter Power-on Reset Threshold Voltage (rising) VPOT Power-on Reset Threshold Voltage (falling) Typ Max Units 1.1 1.4 1.7 V 0.8 1.3 1.6 V 0.4 V VPORMAX VCC Max. start voltage to ensure internal Power-on Reset signal VPORMIN VCC Min. start voltage to ensure internal Power-on Reset signal -0.1 V VCCRR VCC Rise Rate to ensure Power-on Reset 0.01 V/ms VRST RESET Pin Threshold Voltage Note: 8.4 (1) Min 0.1 VCC 0.9VCC V 1. Before rising the supply has to be between VPORMIN and VPORMAX to ensure Reset. External Reset An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum pulse width (see Table 8-1) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage - VRST - on its positive edge, the delay counter starts the MCU after the Time-out period - tTOUT - has expired. 37 7598H-AVR-07/09 Figure 8-4. External Reset During Operation CC 8.5 Brown-out Detection ATtiny25/45/85 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2. Table 8-2. BODLEVEL Fuse Coding(1) BODLEVEL [2..0] Fuses Min VBOT 111 Max VBOT Units BOD Disabled 110 1.7 1.8 2.0 101 2.5 2.7 2.9 100 4.0 4.3 4.6 (2) 011 Note: Typ VBOT 2.3 V (2) 010 2.2 001 1.9(2) 000 2.0(2) 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. 2. Centered value, not tested. Table 8-3. Symbol Parameter Min (1) Typ Max Units VRAM RAM Retention Voltage 50 mV VHYST Brown-out Detector Hysteresis 50 mV tBOD Min Pulse Width on Brown-out Reset 2 s Notes: 38 Brown-out Characteristics 1. This is the limit to which VDD can be lowered without losing RAM data ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 When the BOD is enabled, and VCC decreases to a value below the trigger level (VBOT- in Figure 8-5), the Brown-out Reset is immediately activated. When VCC increases above the trigger level (VBOT+ in Figure 8-5), the delay counter starts the MCU after the Time-out period tTOUT has expired. The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than tBOD given in Table 8-1. Figure 8-5. Brown-out Reset During Operation VCC VBOT- VBOT+ RESET tTOUT TIME-OUT INTERNAL RESET 8.6 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 41 for details on operation of the Watchdog Timer. Figure 8-6. Watchdog Reset During Operation CC CK 39 7598H-AVR-07/09 8.7 MCU Status Register - MCUSR The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 7 6 5 4 3 2 1 0 - - - - WDRF BORF EXTRF PORF Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 MCUSR See Bit Description * Bits 7..4 - Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. * Bit 3 - WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. * Bit 2 - BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. * Bit 1 - EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. * Bit 0 - PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. 8.8 Internal Voltage Reference ATtiny25/45/85 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 8.8.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 8-4. To save power, the reference is not always turned on. The reference is on during the following situations: 1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse bits). 2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR). 3. When the ADC is enabled. Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or 40 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. Table 8-4. Symbol 8.9 Internal Voltage Reference Characteristics Parameter Condition Min Typ Max Units VCC = 1.1V / 2.7V, TA = 25C 1.0 1.1 1.2 V 70 s VBG Bandgap reference voltage tBG Bandgap reference start-up time VCC = 2.7V, TA = 25C 40 IBG Bandgap reference current consumption VCC = 2.7V, TA = 25C 15 A Watchdog Timer The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128 kHz. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 8-7 on page 43. The WDR - Watchdog Reset - instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATtiny25/45/85 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to Table 8-7 on page 43. The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using the Watchdog to wake-up from Power-down. To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse WDTON as shown in Table 8-5. Refer to "Timed Sequences for Changing the Configuration of the Watchdog Timer" on page 44 for details. Table 8-5. WDT Configuration as a Function of the Fuse Settings of WDTON Safety Level WDTON WDT Initial State How to Disable the WDT How to Change Time-out Unprogrammed 1 Disabled Timed sequence No limitations Programmed 2 Enabled Always enabled Timed sequence Watchdog Timer OSC/512K OSC/1024K OSC/256K OSC/64K OSC/128K OSC/8K OSC/4K OSC/2K WATCHDOG RESET OSC/32K WATCHDOG PRESCALER 128 kHz OSCILLATOR OSC/16K Figure 8-7. WDP0 WDP1 WDP2 WDP3 WDE MCU RESET 41 7598H-AVR-07/09 8.9.1 Watchdog Timer Control Register - WDTCR Bit 7 6 5 4 3 2 1 0 WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 X 0 0 0 WDTCR * Bit 7 - WDIF: Watchdog Timeout Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed. * Bit 6 - WDIE: Watchdog Timeout Interrupt Enable When this bit is written to one, WDE is cleared, and the I-bit in the Status Register is set, the Watchdog Time-out Interrupt is enabled. In this mode the corresponding interrupt is executed instead of a reset if a timeout in the Watchdog Timer occurs. If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is useful for keeping the Watchdog Reset security while using the interrupt. After the WDIE bit is cleared, the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set after each interrupt. Table 8-6. Watchdog Timer Configuration WDE WDIE Watchdog Timer State Action on Time-out 0 0 Stopped None 0 1 Running Interrupt 1 0 Running Reset 1 1 Running Interrupt * Bit 4 - WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. This bit must also be set when changing the prescaler bits. See "Timed Sequences for Changing the Configuration of the Watchdog Timer" on page 44. * Bit 3 - WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog. In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. See "Timed Sequences for Changing the Configuration of the Watchdog Timer" on page 44. 42 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 In safety level 1, WDE is overridden by WDRF in MCUSR. See "MCU Status Register - MCUSR" on page 40 for description of WDRF. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared before disabling the Watchdog with the procedure described above. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. Note: If the watchdog timer is not going to be used in the application, it is important to go through a watchdog disable procedure in the initialization of the device. If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset, which in turn will lead to a new watchdog reset. To avoid this situation, the application software should always clear the WDRF flag and the WDE control bit in the initialization routine. * Bits 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1, and 0 The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 8-7. Table 8-7. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V 0 0 0 0 2K cycles 16 ms 0 0 0 1 4K cycles 32 ms 0 0 1 0 8K cycles 64 ms 0 0 1 1 16K cycles 0.125 s 0 1 0 0 32K cycles 0.25 s 0 1 0 1 64K cycles 0.5 s 0 1 1 0 128K cycles 1.0 s 0 1 1 1 256K cycles 2.0 s 1 0 0 0 512K cycles 4.0 s 1 0 0 1 1024K cycles 8.0 s 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Note: Reserved(1) 1. If selected, one of the valid settings below 0b1010 will be used. 43 7598H-AVR-07/09 The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly Code Example(1) WDT_off: WDR ; Clear WDRF in MCUSR ldi r16, (0<<WDRF) out MCUSR, r16 ; Write logical one to WDCE and WDE ; Keep old prescaler setting to prevent unintentional Watchdog Reset in r16, WDTCR ori r16, (1<<WDCE)|(1<<WDE) out WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret C Code Example(1) void WDT_off(void) { _WDR(); /* Clear WDRF in MCUSR */ MCUSR = 0x00 /* Write logical one to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; } Note: 8.10 1. The example code assumes that the part specific header file is included. Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level. 8.10.1 Safety Level 1 In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to one without any restriction. A timed sequence is needed when disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as desired, but with the WDCE bit cleared. 44 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 8.10.2 Safety Level 2 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed: 1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence. 2. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant. 9. Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny25/45/85. For a general explanation of the AVR interrupt handling, refer to "Reset and Interrupt Handling" on page 11. 9.1 Interrupt Vectors in ATtiny25/45/85 Table 9-1. Reset and Interrupt Vectors Vector No. Program Address Source Interrupt Definition 1 0x0000 RESET External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset 2 0x0001 INT0 External Interrupt Request 0 3 0x0002 PCINT0 Pin Change Interrupt Request 0 4 0x0003 TIM1_COMPA Timer/Counter1 Compare Match A 5 0x0004 TIM1_OVF Timer/Counter1 Overflow 6 0x0005 TIM0_OVF Timer/Counter0 Overflow 7 0x0006 EE_RDY EEPROM Ready 8 0x0007 ANA_COMP Analog Comparator 9 0x0008 ADC ADC Conversion Complete 10 0x0009 TIM1_COMPB Timer/Counter1 Compare Match B 11 0x000A TIM0_COMPA Timer/Counter0 Compare Match A 12 0x000B TIM0_COMPB Timer/Counter0 Compare Match B 13 0x000C WDT Watchdog Time-out 14 0x000D USI_START USI START 15 0x000E USI_OVF USI Overflow 45 7598H-AVR-07/09 If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny25/45/85 is: Address Labels Code Comments 0x0000 rjmp RESET ; Reset Handler 0x0001 rjmp EXT_INT0 ; IRQ0 Handler 0x0002 rjmp PCINT0 ; PCINT0 Handler 0x0003 rjmp TIM1_COMPA ; Timer1 CompareA Handler 0x0004 rjmp TIM1_OVF ; Timer1 Overflow Handler 0x0005 rjmp TIM0_OVF ; Timer0 Overflow Handler 0x0006 rjmp EE_RDY ; EEPROM Ready Handler 0x0007 rjmp ANA_COMP ; Analog Comparator Handler 0x0008 rjmp ADC ; ADC Conversion Handler 0x0009 rjmp TIM1_COMPB ; Timer1 CompareB Handler 0x000A rjmp TIM0_COMPA ; 0x000B rjmp TIM0_COMPB ; 0x000C rjmp WDT ; 0x000D rjmp USI_START ; 0x000E rjmp USI_OVF ; 0x000F RESET: ldi 0x0010 ldi r17, high(RAMEND); Tiny85 has also SPH 0x0011 out SPL, r16 ; Set Stack Pointer to top of RAM 0x0012 out SPH, r17 ; Tiny85 has also SPH 0x0013 0x0014 ... r16, low(RAMEND); Main program start sei <instr> ... ; Enable interrupts xxx ... ... 10. I/O Ports 10.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in Figure 10-1. Refer to "Electrical Characteristics" on page 150 for a complete list of parameters. 46 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Figure 10-1. I/O Pin Equivalent Schematic Rpu Logic Pxn Cpin See Figure "General Digital I/O" for Details All registers and bit references in this section are written in general form. A lower case "x" represents the numbering letter for the port, and a lower case "n" represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers and bit locations are listed in "Register Description for I/O-Ports" on page 58. Three I/O memory address locations are allocated for each port, one each for the Data Register - PORTx, Data Direction Register - DDRx, and the Port Input Pins - PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable - PUD bit in MCUCR disables the pull-up function for all pins in all ports when set. Using the I/O port as General Digital I/O is described in "Ports as General Digital I/O" on page 47. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in "Alternate Port Functions" on page 52. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 10.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of one I/O-port pin, here generically called Pxn. 47 7598H-AVR-07/09 Figure 10-2. General Digital I/O(1) PUD Q D DDxn Q CLR WDx RESET DATA BUS RDx 1 Q Pxn D 0 PORTxn Q CLR RESET WRx WPx RRx SLEEP SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: SLEEP: clkI/O: Note: 10.2.1 PULLUP DISABLE SLEEP CONTROL I/O CLOCK WDx: RDx: WRx: RRx: RPx: WPx: WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN WRITE PINx REGISTER 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in "Register Description for I/O-Ports" on page 58, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 10.2.2 48 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 10.2.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b10) as an intermediate step. Table 10-1 summarizes the control signals for the pin value. Table 10-1. 10.2.4 Port Pin Configurations DDxn PORTxn PUD (in MCUCR) I/O Pull-up 0 0 X Input No Tri-state (Hi-Z) 0 1 0 Input Yes Pxn will source current if ext. pulled low. 0 1 1 Input No Tri-state (Hi-Z) 1 0 X Output No Output Low (Sink) 1 1 X Output No Output High (Source) Comment Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 10-2, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 10-3 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively. Figure 10-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min 49 7598H-AVR-07/09 Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the "SYNC LATCH" signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between 1/2 and 11/2 system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 10-4. The out instruction sets the "SYNC LATCH" signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is one system clock period. Figure 10-4. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK r16 INSTRUCTIONS 0xFF out PORTx, r16 nop in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. 50 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<<PB4)|(1<<PB1)|(1<<PB0) ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0) out PORTB,r16 out DDRB,r17 ; Insert nop for synchronization nop ; Read port pins in r16,PINB ... C Code Example unsigned char i; ... /* Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTB = (1<<PB4)|(1<<PB1)|(1<<PB0); DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0); /* Insert nop for synchronization*/ _NOP(); /* Read port pins */ i = PINB; ... Note: 10.2.5 1. For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1 and 4, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. Digital Input Enable and Sleep Modes As shown in Figure 10-2, the digital input signal can be clamped to ground at the input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2. SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in "Alternate Port Functions" on page 52. If a logic high level ("one") is present on an asynchronous external interrupt pin configured as "Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin" while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. 51 7598H-AVR-07/09 10.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pulldown. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output. 10.3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 10-5 shows how the port pin control signals from the simplified Figure 10-2 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 10-5. Alternate Port Functions(1) PUOExn PUOVxn 1 PUD 0 DDOExn DDOVxn 1 Q D DDxn 0 Q CLR WDx PVOExn RESET RDx 1 DATA BUS PVOVxn 1 Pxn Q 0 D 0 PORTxn PTOExn Q CLR DIEOExn WPx DIEOVxn RESET WRx 1 0 RRx SLEEP SYNCHRONIZER D SET Q RPx Q D PINxn L CLR Q CLR Q clk I/O DIxn AIOxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP: PTOExn: 52 Pxn PULL-UP OVERRIDE ENABLE Pxn PULL-UP OVERRIDE VALUE Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE Pxn PORT VALUE OVERRIDE ENABLE Pxn PORT VALUE OVERRIDE VALUE Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP CONTROL Pxn, PORT TOGGLE OVERRIDE ENABLE PUD: WDx: RDx: RRx: WRx: RPx: WPx: clkI/O: DIxn: AIOxn: PULLUP DISABLE WRITE DDRx READ DDRx READ PORTx REGISTER WRITE PORTx READ PORTx PIN WRITE PINx I/O CLOCK DIGITAL INPUT PIN n ON PORTx ANALOG INPUT/OUTPUT PIN n ON PORTx ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. All other signals are unique for each pin. Table 10-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 10-5 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 10-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits. DDOE Data Direction Override Enable If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit. DDOV Data Direction Override Value If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit. PVOE Port Value Override Enable If this signal is set and the Output Driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit. PVOV Port Value Override Value If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn Register bit. PTOE Port Toggle Override Enable If PTOE is set, the PORTxn Register bit is inverted. DIEOE Digital Input Enable Override Enable If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital Input Enable is determined by MCU state (Normal mode, sleep mode). DIEOV Digital Input Enable Override Value If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (Normal mode, sleep mode). DI Digital Input This is the Digital Input to alternate functions. In the figure, the signal is connected to the output of the schmitt-trigger but before the synchronizer. Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. AIO Analog Input/Output This is the Analog Input/Output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally. The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. 53 7598H-AVR-07/09 10.3.1 MCU Control Register - MCUCR Bit 7 6 5 4 3 2 1 0 BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR * Bit 6 - PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See "Configuring the Pin" on page 48 for more details about this feature. 10.3.2 Alternate Functions of Port B The Port B pins with alternate function are shown in Table 10-3. Table 10-3. Port B Pins Alternate Functions Port Pin Notes: Alternate Function PB5 RESET / dW / ADC0 / PCINT5(1) PB4 XTAL2 / CLKO / ADC2 / OC1B / PCINT4(2) PB3 XTAL1 / ADC3 / OC1B / PCINT3(3) PB2 SCK / ADC1 / T0 / USCK / SCL / INT0 / PCINT2(4) PB1 MISO / AIN1 / OC0B / OC1A / DO / PCINT1(5) PB0 MOSI / AIN0 / OC0A / OC1A / DI / SDA / AREF / PCINT0(6) 1. Reset Pin, debugWIRE I/O, ADC Input Channel or Pin Change Interrupt. 2. XOSC Output, Divided System Clock Output, ADC Input Channel, Timer/Counter1 Output Compare and PWM Output B, or Pin Change Interrupt. 3. XOSC Input / External Clock Input, ADC Input Channel, Timer/Counter1 Inverted Output Compare and PWM Output B, or Pin Change Interrupt. 4. Serial Clock Input, ADC Input Channel, Timer/Counter Clock Input, USI Clock (three-wire mode), USI Clock (two-wire mode), External Interrupt, or Pin Change Interrupt. 5. Serial Data Input, Analog Comparator Negative Input, Timer/Counter0 Output Compare and PWM Output B, Timer/Counter1 Output Compare and PWM Output A, USI Data Output (three-wire mode), or Pin Change Interrupt. 6. Serial Data Output, Analog Comparator Positive Input, Timer/Counter0 Output Compare and PWM Output A, Timer/Counter1 Inverted Output Compare and PWM Output A, USI Data Input (three-wire mode), USI Data (two-wire mode), Voltage Ref., or Pin Change Interrupt. * Port B, Bit 5 - RESET/dW/ADC0/PCINT5 RESET: External Reset input is active low and enabled by unprogramming ("1") the RSTDISBL Fuse. Pullup is activated and output driver and digital input are deactivated when the pin is used as the RESET pin. dW: When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE system within the target device is activated. The RESET port pin is configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the communication gateway between target and emulator. ADC0: Analog to Digital Converter, Channel 0. PCINT5: Pin Change Interrupt source 5. 54 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 * Port B, Bit 4- XTAL2/CLKO/ADC2/OC1B/PCINT4 XTAL2: Chip Clock Oscillator pin 2. Used as clock pin for all chip clock sources except internal calibrateble RC Oscillator and external clock. When used as a clock pin, the pin can not be used as an I/O pin. When using internal calibratable RC Oscillator or External clock as a Chip clock sources, PB4 serves as an ordinary I/O pin. CLKO: The devided system clock can be output on the pin PB4. The divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTB4 and DDB4 settings. It will also be output during reset. ADC2: Analog to Digital Converter, Channel 2. OC1B: Output Compare Match output: The PB4 pin can serve as an external output for the Timer/Counter1 Compare Match B when configured as an output (DDB4 set). The OC1B pin is also the output pin for the PWM mode timer function. PCINT4: Pin Change Interrupt source 4. * Port B, Bit 3 - XTAL1/ADC3/OC1B/PCINT3 XTAL1: Chip Clock Oscillator pin 1. Used for all chip clock sources except internal calibrateble RC oscillator. When used as a clock pin, the pin can not be used as an I/O pin. ADC3: Analog to Digital Converter, Channel 3. OC1B: Inverted Output Compare Match output: The PB3 pin can serve as an external output for the Timer/Counter1 Compare Match B when configured as an output (DDB3 set). The OC1B pin is also the inverted output pin for the PWM mode timer function. PCINT3: Pin Change Interrupt source 3. * Port B, Bit 2 - SCK/ADC1/T0/USCK/SCL/INT0/PCINT2 SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDPB2. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB2 bit. ADC1: Analog to Digital Converter, Channel 1. T0: Timer/Counter0 counter source. USCK: Three-wire mode Universal Serial Interface Clock. SCL: Two-wire mode Serial Clock for USI Two-wire mode. INT0: External Interrupt source 0. PCINT2: Pin Change Interrupt source 2. * Port B, Bit 1 - MISO/AIN1/OC0B/OC1A/DO/PCINT1 MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a Master, this pin is configured as an input regardless of the setting of DDB1. When the SPI is enabled as a Slave, the data direction of this pin is controlled by DDB1. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB1 bit. AIN1: Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. 55 7598H-AVR-07/09 OC0B: Output Compare Match output. The PB1 pin can serve as an external output for the Timer/Counter0 Compare Match B. The PB1 pin has to be configured as an output (DDB1 set (one)) to serve this function. The OC0B pin is also the output pin for the PWM mode timer function. OC1A: Output Compare Match output: The PB1 pin can serve as an external output for the Timer/Counter1 Compare Match B when configured as an output (DDB1 set). The OC1A pin is also the output pin for the PWM mode timer function. DO: Three-wire mode Universal Serial Interface Data output. Three-wire mode Data output overrides PORTB1 value and it is driven to the port when data direction bit DDB1 is set (one). PORTB1 still enables the pull-up, if the direction is input and PORTB1 is set (one). PCINT1: Pin Change Interrupt source 1. * Port B, Bit 0 - MOSI/AIN0/OC0A/OC1A/DI/SDA/AREF/PCINT0 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB0. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB0 bit. AIN0: Analog Comparator Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. OC0A: Output Compare Match output. The PB0 pin can serve as an external output for the Timer/Counter0 Compare Match A when configured as an output (DDB0 set (one)). The OC0A pin is also the output pin for the PWM mode timer function. OC1A: Inverted Output Compare Match output: The PB0 pin can serve as an external output for the Timer/Counter1 Compare Match B when configured as an output (DDB0 set). The OC1A pin is also the inverted output pin for the PWM mode timer function. SDA: Two-wire mode Serial Interface Data. AREF: External Analog Reference for ADC. Pullup and output driver are disabled on PB0 when the pin is used as an external reference or Internal Voltage Reference with external capacitor at the AREF pin. DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port functions, so pin must be configure as an input for DI function. PCINT0: Pin Change Interrupt source 0. 56 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Table 10-4 and Table 10-5 relate the alternate functions of Port B to the overriding signals shown in Figure 10-5 on page 52. Table 10-4. Overriding Signals for Alternate Functions in PB5..PB3 Signal Name PB5/RESET/ ADC0/PCINT5 PB4/ADC2/XTAL2/ OC1B/PCINT4 PB3/ADC3/XTAL1/ _OC1B/PCINT3 PUOE RSTDISBL(1) * DWEN(1) 0 0 PUOV 1 0 0 0 0 (1) * DWEN (1) DDOE RSTDISBL DDOV debugWire Transmit 0 0 PVOE 0 OC1B Enable _OC1B Enable PVOV 0 OC1B _OC1B PTOE 0 0 0 (1) DIEOE RSTDISBL + (PCINT5 * PCIE + ADC0D) PCINT4 * PCIE + ADC2D PCINT3 * PCIE + ADC3D DIEOV ADC0D ADC2D ADC3D DI PCINT5 Input PCINT4 Input PCINT3 Input AIO RESET Input, ADC0 Input ADC2 Input ADC3 Input Note: 1. 1 when the Fuse is "0" (Programmed). Table 10-5. Overriding Signals for Alternate Functions in PB3..PB0 Signal Name PB2/SCK/ADC1/T0/ USCK/SCL/INT0/PCINT2 PB1/MISO/DO/AIN1/ OC1A/OC0B/PCINT1 PB0/MOSI/DI/SDA/AIN0/AR EF/_OC1A/OC0A/ PCINT0 PUOE 0 0 0 PUOV 0 0 0 DDOE USI_TWO_WIRE 0 USI_TWO_WIRE DDOV (USI_SCL_HOLD + PORTB2) * DDB2 0 (SDA + PORTBO) * DDB0 PVOE USI_TWO_WIRE * DDB2 OC0B Enable + OC1A Enable + USI_THREE_WIRE OC0A Enable + _OC1A Enable + (USI_TWO_WIRE * DDB0) PVOV 0 OC0B + OC1A + DO OC0A + _OC1A PTOE USITC 0 0 DIEOE PCINT2 * PCIE + ADC1D + USISIE PCINT1 * PCIE + AIN1D PCINT0 * PCIE + AIN0D + USISIE DIEOV ADC1D AIN1D AIN0D DI T0/USCK/SCL/INT0/ PCINT2 Input PCINT1 Input DI/SDA/PCINT0 Input AIO ADC1 Input Analog Comparator Negative Input Analog Comparator Positive Input 57 7598H-AVR-07/09 10.4 10.4.1 Register Description for I/O-Ports Port B Data Register - PORTB Bit 10.4.2 7 6 5 4 3 2 1 0 - - PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Port B Data Direction Register - DDRB Bit 10.4.3 PORTB 7 6 5 4 3 2 1 0 - - DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DDRB Port B Input Pins Address - PINB Bit 7 6 5 4 3 2 1 0 - - PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 N/A N/A N/A N/A N/A N/A PINB 11. External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT5..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT5..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. Pin change interrupts PCI will trigger if any enabled PCINT5..0 pin toggles. The PCMSK Register control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT5..0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the MCU Control Register - MCUCR. When the INT0 interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an I/O clock, described in "Clock Systems and their Distribution" on page 21. Low level interrupt on INT0 is detected asynchronously. This implies that this interrupt can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in "System Clock and Clock Options" on page 21. 58 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 11.1 MCU Control Register - MCUCR The External Interrupt Control Register A contains control bits for interrupt sense control. Bit 7 6 5 4 3 2 1 0 BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR * Bits 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 11-1. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Table 11-1. 11.2 Interrupt 0 Sense Control ISC01 ISC00 Description 0 0 The low level of INT0 generates an interrupt request. 0 1 Any logical change on INT0 generates an interrupt request. 1 0 The falling edge of INT0 generates an interrupt request. 1 1 The rising edge of INT0 generates an interrupt request. General Interrupt Mask Register - GIMSK Bit 7 6 5 4 3 2 1 - INT0 PCIE - - - - 0 - Read/Write R R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 GIMSK * Bits 7, 4..0 - Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. * Bit 6 - INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU Control Register (MCUCR) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector. * Bit 5 - PCIE: Pin Change Interrupt Enable When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt is enabled. Any change on any enabled PCINT5..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI Interrupt Vector. PCINT5..0 pins are enabled individually by the PCMSK0 Register. 59 7598H-AVR-07/09 11.3 General Interrupt Flag Register - GIFR Bit 7 6 5 4 3 2 1 - INTF0 PCIF - - - - 0 - Read/Write R R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 GIFR * Bits 7, 4..0 - Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. * Bit 6 - INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt. * Bit 5 - PCIF: Pin Change Interrupt Flag When a logic change on any PCINT5..0 pin triggers an interrupt request, PCIF becomes set (one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. 11.4 Pin Change Mask Register - PCMSK Bit 7 6 5 4 3 2 1 0 - - PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 1 1 1 1 1 1 PCMSK * Bits 7, 6 - Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. * Bits 5..0 - PCINT5..0: Pin Change Enable Mask 5..0 Each PCINT5..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT5..0 is set and the PCIE bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT5..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 60 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 12. 8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event management) and wave generation. The main features are: * * * * * * * 12.1 Two Independent Output Compare Units Double Buffered Output Compare Registers Clear Timer on Compare Match (Auto Reload) Glitch Free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B) Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 12-1. For the actual placement of I/O pins, refer to "Pinout ATtiny25/45/85" on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the "8-bit Timer/Counter Register Description" on page 72. Figure 12-1. 8-bit Timer/Counter Block Diagram Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA Fixed TOP Value Waveform Generation = OCnB OCRnB TCCRnA 12.1.1 OCnB (Int.Req.) TCCRnB Registers The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0). 61 7598H-AVR-07/09 The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B). See "Output Compare Unit" on page 63. for details. The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt request. 12.1.2 Definitions Many register and bit references in this section are written in general form. A lower case "n" replaces the Timer/Counter number, in this case 0. A lower case "x" replaces the Output Compare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on. The definitions below are also used extensively throughout the document. 12.2 BOTTOM The counter reaches the BOTTOM when it becomes 0x00. MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment is dependent on the mode of operation. Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and prescaler, see "Timer/Counter Prescaler" on page 78. 12.3 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 12-2 shows a block diagram of the counter and its surroundings. Figure 12-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS Clock Select count TCNTn clear Control Logic clkTn Edge Detector Tn direction ( From Prescaler ) bottom 62 top ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter Control Register B (TCCR0B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare output OC0A. For more details about advanced counting sequences and waveform generation, see "Modes of Operation" on page 66. The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt. 12.4 Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers (OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (See "Modes of Operation" on page 66.). Figure 12-3 shows a block diagram of the Output Compare unit. 63 7598H-AVR-07/09 Figure 12-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x directly. 12.4.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0x) bit. Forcing Compare Match will not set the OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real Compare Match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or toggled). 12.4.2 Compare Match Blocking by TCNT0 Write All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. 64 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 12.4.3 Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes. Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the COM0x1:0 bits will take effect immediately. 12.5 Compare Match Output Unit The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Generator uses the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next Compare Match. Also, the COM0x1:0 bits control the OC0x pin output source. Figure 12-4 shows a simplified schematic of the logic affected by the COM0x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset occur, the OC0x Register is reset to "0". Figure 12-4. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCn Waveform Generator D Q 1 OCnx DATA BUS D 0 OCn Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visible on the pin. The port override function is independent of the Waveform Generation mode. 65 7598H-AVR-07/09 The design of the Output Compare pin logic allows initialization of the OC0x state before the output is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. See "8-bit Timer/Counter Register Description" on page 72. 12.5.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 12-1 on page 72. For fast PWM mode, refer to Table 12-2 on page 72, and for phase correct PWM refer to Table 12-3 on page 73. A change of the COM0x1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0x strobe bits. 12.6 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM0x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a Compare Match (See "Compare Match Output Unit" on page 65.). For detailed timing information refer to Figure 12-8, Figure 12-9, Figure 12-10 and Figure 12-11 in "Timer/Counter Timing Diagrams" on page 70. 12.6.1 Normal Mode The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare Unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 12.6.2 66 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 The timing diagram for the CTC mode is shown in Figure 12-5. The counter value (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. Figure 12-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following equation: f clk_I/O f OCnx = -----------------------------------------------------2 N ( 1 + OCRnx ) The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 12.6.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope operation. 67 7598H-AVR-07/09 This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 12-6. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0. Figure 12-6. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCn (COMnx1:0 = 2) OCn (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allowes the AC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 12-2 on page 72). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC0x Register at the Compare Match between OCR0x and TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = -------------------N 256 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. 68 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero. This feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 12.6.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match between TCNT0 and OCR0x while upcounting, and set on the Compare Match while down-counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 12-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0. Figure 12-7. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCn (COMnx1:0 = 2) OCn (COMnx1:0 = 3) Period 1 2 3 69 7598H-AVR-07/09 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 12-3 on page 73). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at Compare Match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = -------------------N 510 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in Figure 12-7 OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guaratee symmetry around BOTTOM. There are two cases that give a transition without Compare Match. * OCR0A changes its value from MAX, like in Figure 12-7. When the OCR0A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. * The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. 12.7 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 12-8 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. 70 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Figure 12-8. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 12-9 shows the same timing data, but with the prescaler enabled. Figure 12-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 12-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 12-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where OCR0A is TOP. 71 7598H-AVR-07/09 Figure 12-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 TOP OCRnx BOTTOM BOTTOM + 1 TOP OCFnx 12.8 8-bit Timer/Counter Register Description 12.8.1 Timer/Counter Control Register A - TCCR0A Bit 7 6 5 4 3 2 1 0 COM0A1 COM0A0 COM0B1 COM0B0 - - WGM01 WGM00 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A * Bits 7:6 - COM01A:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver. When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM02:0 bit setting. Table 12-1 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-PWM). Table 12-1. Compare Output Mode, non-PWM Mode COM01 COM00 Description 0 0 Normal port operation, OC0A disconnected. 0 1 Toggle OC0A on Compare Match 1 0 Clear OC0A on Compare Match 1 1 Set OC0A on Compare Match Table 12-2 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode. Table 12-2. 72 Compare Output Mode, Fast PWM Mode(1) COM01 COM00 0 0 Description Normal port operation, OC0A disconnected. ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Table 12-2. Compare Output Mode, Fast PWM Mode(1) COM01 COM00 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match, set OC0A at TOP 1 1 Set OC0A on Compare Match, clear OC0A at TOP Note: Description 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See "Fast PWM Mode" on page 67 for more details. Table 12-3 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 12-3. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. 1 1 Set OC0A on Compare Match when up-counting. Clear OC0A on Compare Match when down-counting. Note: Description 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See "Phase Correct PWM Mode" on page 69 for more details. * Bits 5:4 - COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin must be set in order to enable the output driver. When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the WGM02:0 bit setting. Table 12-1 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-PWM). Table 12-4. Compare Output Mode, non-PWM Mode COM01 COM00 Description 0 0 Normal port operation, OC0B disconnected. 0 1 Toggle OC0B on Compare Match 1 0 Clear OC0B on Compare Match 1 1 Set OC0B on Compare Match 73 7598H-AVR-07/09 Table 12-2 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM mode. Table 12-5. Compare Output Mode, Fast PWM Mode(1) COM01 COM00 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match, set OC0B at TOP 1 1 Set OC0B on Compare Match, clear OC0B at TOP Note: Description 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See "Fast PWM Mode" on page 67 for more details. Table 12-3 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 12-6. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting. 1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting. Note: Description 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See "Phase Correct PWM Mode" on page 69 for more details. * Bits 3, 2 - Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. * Bits 1:0 - WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 12-7. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see "Modes of Operation" on page 66). 74 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Table 12-7. Waveform Generation Mode Bit Description Timer/Counter Mode of Operation TOP Update of OCRx at TOV Flag Set on(1)(2) Mode WGM2 WGM1 WGM0 0 0 0 0 Normal 0xFF Immediate MAX 1 0 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 0 1 0 CTC OCRA Immediate MAX 3 0 1 1 Fast PWM 0xFF TOP MAX 4 1 0 0 Reserved - - - 5 1 0 1 PWM, Phase Correct OCRA TOP BOTTOM 6 1 1 0 Reserved - - - 7 1 1 1 Fast PWM OCRA TOP TOP Notes: 1. MAX = 0xFF 2. BOTTOM = 0x00 12.8.2 Timer/Counter Control Register B - TCCR0B Bit 7 6 5 4 3 2 1 0 FOC0A FOC0B - - WGM02 CS02 CS01 CS00 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B * Bit 7 - FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the forced compare. A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP. The FOC0A bit is always read as zero. * Bit 6 - FOC0B: Force Output Compare B The FOC0B bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the forced compare. 75 7598H-AVR-07/09 A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP. The FOC0B bit is always read as zero. * Bits 5:4 - Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. * Bit 3 - WGM02: Waveform Generation Mode See the description in the "Timer/Counter Control Register A - TCCR0A" on page 72. * Bits 2:0 - CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 12-8. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge. If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 12.8.3 Timer/Counter Register - TCNT0 Bit 7 6 5 4 3 2 1 0 TCNT0[7:0] TCNT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers. 12.8.4 Output Compare Register A - OCR0A Bit 7 6 5 4 3 2 1 0 OCR0A[7:0] OCR0A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0A pin. 76 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 12.8.5 Output Compare Register B - OCR0B Bit 7 6 5 4 3 2 1 0 OCR0B[7:0] OCR0B Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0B pin. 12.8.6 Timer/Counter Interrupt Mask Register - TIMSK Bit 7 6 5 4 3 2 1 0 - OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 - Read/Write R R R R R/W R/W R/W R Initial Value 0 0 0 0 0 0 0 0 TIMSK * Bits 7..4, 0 - Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. * Bit 3 - OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter Interrupt Flag Register - TIFR0. * Bit 2 - OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the Timer/Counter 0 Interrupt Flag Register - TIFR0. * Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Interrupt Flag Register - TIFR0. 12.8.7 Timer/Counter 0 Interrupt Flag Register - TIFR Bit 7 6 5 4 3 2 1 - OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 0 - Read/Write R R/W R/W R/W R/W R/W R/W R Initial Value 0 0 0 0 0 0 0 0 TIFR * Bits 7, 0 - Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. 77 7598H-AVR-07/09 * Bit 4- OCF0A: Output Compare Flag 0 A The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A - Output Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed. * Bit 3 - OCF0B: Output Compare Flag 0 B The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B - Output Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed. * Bit 1 - TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 12-7, "Waveform Generation Mode Bit Description" on page 75. 13. Timer/Counter Prescaler The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a frequency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024. 13.1 Prescaler Reset The prescaler is free running, i.e., operates independently of the Clock Select logic of the Timer/Counter. Since the prescaler is not affected by the Timer/Counter's clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution. 78 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 13.2 External Clock Source An external clock source applied to the T0 pin can be used as Timer/Counter clock (clkT0). The T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 13-1 shows a functional equivalent block diagram of the T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 13-1. T0 Pin Sampling Tn D Q D Q D Tn_sync (To Clock Select Logic) Q LE clk I/O Synchronization Edge Detector The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. 79 7598H-AVR-07/09 Figure 13-2. Prescaler for Timer/Counter0 clk I/O Clear PSR10 T0 Synchronization clkT0 Note: 13.2.1 1. The synchronization logic on the input pins (T0) is shown in Figure 13-1. General Timer/Counter Control Register - GTCCR Bit 7 6 5 4 3 2 1 0 TSM PWM1B COM1B1 COM1B0 FOC1B FOC1A PSR1 PSR0 Read/Write R/W R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR * Bit 7 - TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR0 bit is kept, hence keeping the Prescaler Reset signal asserted. This ensures that the Timer/Counter is halted and can be configured without the risk of advancing during configuration. When the TSM bit is written to zero, the PSR0 bit is cleared by hardware, and the Timer/Counter start counting. * Bit 0 - PSR0: Prescaler Reset Timer/Counter0 When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. 80 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 14. Counter and Compare Units Figure 14-1 shows the Timer/Counter1 prescaler that supports two clocking modes, a synchronous clocking mode and an asynchronous clocking mode. The synchronous clocking mode uses the system clock (CK) as the clock timebase and asynchronous mode uses the fast peripheral clock (PCK) as the clock time base. The PCKE bit from the PLLCSR register enables the asynchronous mode when it is set (`1'). Figure 14-1. Timer/Counter1 Prescaler PSR1 T1CK T1CK/16384 T1CK/8192 T1CK/4096 T1CK/2048 T1CK/1024 T1CK/512 T1CK/256 T1CK/128 T1CK/64 T1CK/32 T1CK/16 T1CK/8 0 T1CK/4 14-BIT T/C PRESCALER T1CK/2 CK S PCK 64/32 MHz A T1CK PCKE CS10 CS11 CS12 CS13 TIMER/COUNTER1 COUNT ENABLE In the asynchronous clocking mode the clock selections are from PCK to PCK/16384 and stop, and in the synchronous clocking mode the clock selections are from CK to CK/16384 and stop. The clock options are described in Table 14-2 on page 84 and the Timer/Counter1 Control Register, TCCR1. Setting the PSR1 bit in GTCCR register resets the prescaler. The PCKE bit in the PLLCSR register enables the asynchronous mode. The frequency of the fast peripheral clock is 64 MHz (or 32 MHz in Low Speed Mode). 14.1 Timer/Counter1 The Timer/Counter1 general operation is described in the asynchronous mode and the operation in the synchronous mode is mentioned only if there are differences between these two modes. Figure 14-2 shows Timer/Counter 1 synchronization register block diagram and synchronization delays in between registers. Note that all clock gating details are not shown in the figure. The Timer/Counter1 register values go through the internal synchronization registers, which cause the input synchronization delay, before affecting the counter operation. The registers TCCR1, GTCCR, OCR1A, OCR1B, and OCR1C can be read back right after writing the register. The read back values are delayed for the Timer/Counter1 (TCNT1) register and flags (OCF1A, OCF1B, and TOV1), because of the input and output synchronization. The Timer/Counter1 features a high resolution and a high accuracy usage with the lower prescaling opportunities. It can also support two accurate, high speed, 8-bit Pulse Width Modulators using clock speeds up to 64 MHz ( or 32 MHz in Low Speed Mode). In this mode, Timer/Counter1 and the output compare registers serve as dual stand-alone PWMs with non-overlapping non-inverted and inverted outputs. Refer to page 90 for a detailed description on this function. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. 81 7598H-AVR-07/09 Figure 14-2. Timer/Counter 1 Synchronization Register Block Diagram. 8-BIT DATABUS IO-registers Input synchronization registers OCR1A OCR1A_SI OCR1B OCR1B_SI OCR1C OCR1C_SI TCCR1 TCCR1_SI GTCCR GTCCR_SI TCNT1 TCNT1_SI Timer/Counter1 Output synchronization registers TCNT1 TCNT_SO OCF1A OCF1A_SO TCNT1 OCF1B OCF1B_SO OCF1A OCF1A_SI OCF1B OCF1B_SI TOV1 TOV1_SI TOV1 TOV1_SO PCKE CK S A S PCK A SYNC MODE 1/2 CK Delay 1 CK Delay 1 CK Delay 1/2 CK Delay ASYNC MODE 1 - 2 PCK Delay 1 PCK Delay ~1 CK Delay No Delay Timer/Counter1 and the prescaler allow running the CPU from any clock source while the prescaler is operating on the fast 64 MHz (or 32 MHz in Low Speed Mode) PCK clock in the asynchronous mode. Note that the system clock frequency must be lower than one third of the PCK frequency. The synchronization mechanism of the asynchronous Timer/Counter1 needs at least two edges of the PCK when the system clock is high. If the frequency of the system clock is too high, it is a risk that data or control values are lost. The following Figure 14-3 shows the block diagram for Timer/Counter1. 82 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Figure 14-3. Timer/Counter1 Block Diagram T/C1 OVER- T/C1 COMPARE T/C1 COMPARE FLOW IRQ MATCH A IRQ MATCH B IRQ OC1A (PB1) OC1B (PB4) OC1A (PB0) DEAD TIME GENERATOR PSR1 FOC1B FOC1A COM1B0 PWM1B GLOBAL T/C CONTROL REGISTER (GTCCR) COM1B1 CS10 CS11 CS12 CS13 COM1A0 COM1A1 CTC1 TOV1 T/C CONTROL REGISTER 1 (TCCR1) PWM1A TOV1 TOV0 OCF1B OCF1A OCF1A TIMER INT. FLAG REGISTER (TIFR) OCF1B TOIE1 TOIE0 OCIE1B OCIE1A DEAD TIME GENERATOR TIMER INT. MASK REGISTER (TIMSK) OC1B (PB3) TIMER/COUNTER1 TIMER/COUNTER1 (TCNT1) T/C CLEAR T/C1 CONTROL LOGIC 8-BIT COMPARATOR 8-BIT COMPARATOR 8-BIT COMPARATOR T/C1 OUTPUT COMPARE REGISTER (OCR1A) T/C1 OUTPUT COMPARE REGISTER (OCR1B) T/C1 OUTPUT COMPARE REGISTER (OCR1C) CK PCK 8-BIT DATABUS Three status flags (overflow and compare matches) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Registers TCCR1 and GTCCR. The interrupt enable/disable settings are found in the Timer/Counter Interrupt Mask Register - TIMSK. The Timer/Counter1 contains three Output Compare Registers, OCR1A, OCR1B, and OCR1C as the data source to be compared with the Timer/Counter1 contents. In normal mode the Output Compare functions are operational with all three output compare registers. OCR1A determines action on the OC1A pin (PB1), and it can generate Timer1 OC1A interrupt in normal mode and in PWM mode. Likewise, OCR1B determines action on the OC1B pin (PB3) and it can generate Timer1 OC1B interrupt in normal mode and in PWM mode. OCR1C holds the Timer/Counter maximum value, i.e. the clear on compare match value. In the normal mode an overflow interrupt (TOV1) is generated when Timer/Counter1 counts from $FF to $00, while in the PWM mode the overflow interrupt is generated when Timer/Counter1 counts either from $FF to $00 or from OCR1C to $00. The inverted PWM outputs OC1A and OC1B are not connected in normal mode. In PWM mode, OCR1A and OCR1B provide the data values against which the Timer Counter value is compared. Upon compare match the PWM outputs (OC1A, OC1A, OC1B, OC1B) are generated. In PWM mode, the Timer Counter counts up to the value specified in the output compare register OCR1C and starts again from $00. This feature allows limiting the counter "full" value to a specified value, lower than $FF. Together with the many prescaler options, flexible PWM frequency selection is provided. Table 14-6 lists clock selection and OCR1C values to obtain PWM frequencies from 20 kHz to 250 kHz in 10 kHz steps and from 250 kHz to 500 kHz in 50 kHz steps. Higher PWM frequencies can be obtained at the expense of resolution. 83 7598H-AVR-07/09 14.1.1 Timer/Counter1 Control Register - TCCR1 Bit 7 6 5 4 3 2 1 0 $30 ($50) CTC1 PWM1A COM1A1 COM1A0 CS13 CS12 CS11 CS10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCCR1 * Bit 7- CTC1 : Clear Timer/Counter on Compare Match When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value. If the control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match. * Bit 6- PWM1A: Pulse Width Modulator A Enable When set (one) this bit enables PWM mode based on comparator OCR1A in Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value. * Bits 5,4 - COM1A1, COM1A0: Comparator A Output Mode, Bits 1 and 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match with compare register A in Timer/Counter1. Output pin actions affect pin PB1 (OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1A is not connected in normal mode. Table 14-1. Comparator A Mode Select COM1A1 COM1A0 Description 0 0 Timer/Counter Comparator A disconnected from output pin OC1A. 0 1 Toggle the OC1A output line. 1 0 Clear the OC1A output line. 1 1 Set the OC1A output line In PWM mode, these bits have different functions. Refer to Table 14-4 on page 90 for a detailed description. * Bits 3 .. 0 - CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0 The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. Table 14-2. 84 Timer/Counter1 Prescale Select Asynchronous Clocking Mode Synchronous Clocking Mode 0 T/C1 stopped T/C1 stopped 0 1 PCK CK 0 1 0 PCK/2 CK/2 0 0 1 1 PCK/4 CK/4 0 1 0 0 PCK/8 CK/8 0 1 0 1 PCK/16 CK/16 0 1 1 0 PCK/32 CK/32 CS13 CS12 CS11 CS10 0 0 0 0 0 0 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Table 14-2. Timer/Counter1 Prescale Select (Continued) Asynchronous Clocking Mode Synchronous Clocking Mode 1 PCK/64 CK/64 0 0 PCK/128 CK/128 0 0 1 PCK/256 CK/256 1 0 1 0 PCK/512 CK/512 1 0 1 1 PCK/1024 CK/1024 1 1 0 0 PCK/2048 CK/2048 1 1 0 1 PCK/4096 CK/4096 1 1 1 0 PCK/8192 CK/8192 1 1 1 1 PCK/16384 CK/16384 CS13 CS12 CS11 CS10 0 1 1 1 0 1 The Stop condition provides a Timer Enable/Disable function. 14.1.2 General Timer/Counter1 Control Register - GTCCR Bit 7 6 5 4 3 2 1 0 $2C ($4C) TSM PWM1B COM1B1 COM1B0 FOC1B FOC1A PSR1 PSR0 Read/Write R/W R/W R/W R/W W W R/W R/W Initial value 0 0 0 0 0 0 0 0 GTCCR * Bit 6- PWM1B: Pulse Width Modulator B Enable When set (one) this bit enables PWM mode based on comparator OCR1B in Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value. * Bits 5,4 - COM1B1, COM1B0: Comparator B Output Mode, Bits 1 and 0 The COM1B1 and COM1B0 control bits determine any output pin action following a compare match with compare register B in Timer/Counter1. Output pin actions affect pin PB3 (OC1B). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1B is not connected in normal mode. Table 14-3. Comparator B Mode Select COM1B1 COM1B0 Description 0 0 Timer/Counter Comparator B disconnected from output pin OC1B. 0 1 Toggle the OC1B output line. 1 0 Clear the OC1B output line. 1 1 Set the OC1B output line In PWM mode, these bits have different functions. Refer to Table 14-4 on page 90 for a detailed description. 85 7598H-AVR-07/09 * Bit 3- FOC1B: Force Output Compare Match 1B Writing a logical one to this bit forces a change in the compare match output pin PB3 (OC1B) according to the values already set in COM1B1 and COM1B0. If COM1B1 and COM1B0 written in the same cycle as FOC1B, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1B1 and COM1B0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1B bit always reads as zero. FOC1B is not in use if PWM1B bit is set. * Bit 2- FOC1A: Force Output Compare Match 1A Writing a logical one to this bit forces a change in the compare match output pin PB1 (OC1A) according to the values already set in COM1A1 and COM1A0. If COM1A1 and COM1A0 written in the same cycle as FOC1A, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1A1 and COM1A0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1A bit always reads as zero. FOC1A is not in use if PWM1A bit is set. * Bit 1- PSR1 : Prescaler Reset Timer/Counter1 When this bit is set (one), the Timer/Counter prescaler (TCNT1 is unaffected) will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always read as zero. 14.1.3 Timer/Counter1 - TCNT1 Bit 7 6 5 4 3 2 1 0 $2F ($4F) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCNT1 This 8-bit register contains the value of Timer/Counter1. Timer/Counter1 is realized as an up counter with read and write access. Due to synchronization of the CPU, Timer/Counter1 data written into Timer/Counter1 is delayed by one and half CPU clock cycles in synchronous mode and at most one CPU clock cycles for asynchronous mode. 14.1.4 Timer/Counter1 Output Compare RegisterA - OCR1A Bit 7 6 5 4 3 2 1 0 $2E ($4E) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 OCR1A The output compare register A is an 8-bit read/write register. The Timer/Counter Output Compare Register A contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does only occur if Timer/Counter1 counts to the OCR1A value. A software write that sets TCNT1 and OCR1A to the same value does not generate a compare match. A compare match will set the compare interrupt flag OCF1A after a synchronization delay following the compare event. 86 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 14.1.5 Timer/Counter1 Output Compare RegisterB - OCR1B Bit 7 6 5 4 3 2 1 0 $2D ($4D) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 OCR1B The output compare register B is an 8-bit read/write register. The Timer/Counter Output Compare Register B contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does only occur if Timer/Counter1 counts to the OCR1B value. A software write that sets TCNT1 and OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag OCF1B after a synchronization delay following the compare event. 14.1.6 Timer/Counter1 Output Compare RegisterC - OCR1C Bit 7 6 5 4 3 2 1 0 $2B ($4B) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 1 1 1 1 1 1 1 1 OCR1C The output compare register C is an 8-bit read/write register. The Timer/Counter Output Compare Register C contains data to be continuously compared with Timer/Counter1. A compare match does only occur if Timer/Counter1 counts to the OCR1C value. A software write that sets TCNT1 and OCR1C to the same value does not generate a compare match. If the CTC1 bit in TCCR1 is set, a compare match will clear TCNT1. This register has the same function in normal mode and PWM mode. 14.1.7 Timer/Counter Interrupt Mask Register - TIMSK Bit 7 6 5 4 3 2 1 $39 ($59) - OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 0 - Read/Write R R/W R/W R/W R/W R/W R/W R Initial value 0 0 0 0 0 0 0 0 TIMSK * Bit 7 - Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. * Bit 6 - OCIE1A: Timer/Counter1 Output Compare Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchA, interrupt is enabled. The corresponding interrupt at vector $003 is executed if a compare matchA occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register. * Bit 5 - OCIE1B: Timer/Counter1 Output Compare Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchB, interrupt is enabled. The corresponding interrupt at vector $009 is executed if a compare matchB occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register. 87 7598H-AVR-07/09 * Bit 4- OCIE0A: Timer/Counter Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match A interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0A bit is set in the Timer/Counter Interrupt Flag Register - TIFR0. * Bit 3 - OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counte Interrupt Flag Register - TIFR0. * Bit 2 - TOIE1: Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR. * Bit 0 - Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. 14.1.8 Timer/Counter Interrupt Flag Register - TIFR Bit 7 6 5 4 3 2 1 $38 ($58) - OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 0 - Read/Write R R/W R/W R R R/W R/W R Initial value 0 0 0 0 0 0 0 0 TIFR * Bit 7 - Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. * Bit 6 - OCF1A: Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 A compare match interrupt is executed. * Bit 5 - OCF1B: Output Compare Flag 1B The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1B - Output Compare Register 1A. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1B is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1B, and OCF1B are set (one), the Timer/Counter1 B compare match interrupt is executed. * Bit 2 - TOV1: Timer/Counter1 Overflow Flag In normal mode (PWM1A=0 and PWM1B=0) the bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. The bit TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared, after synchronization clock cycle, by writing a logical one to the flag. 88 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 In PWM mode (either PWM1A=1 or PWM1B=1) the bit TOV1 is set (one) when compare match occurs between Timer/Counter1 and data value in OCR1C - Output Compare Register 1C. Clearing the Timer/Counter1 with the bit CTC1 does not generate an overflow. When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed. * Bit 0 - Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. 14.1.9 PLL Control and Status Register - PLLCSR Bit 7 6 5 4 3 2 1 0 $27 ($27) LSM - - - - PCKE PLLE PLOCK Read/Write R/W R R R R R/W R/W R Initial value 0 0 0 0 0 0 0/1 0 PLLCSR * Bit 7- LSM: Low Speed Mode The high speed mode is enabled as default and the fast peripheral clock is 64 MHz, but the low speed mode can be set by writing the LSM bit to one. Then the fast peripheral clock is scaled down to 32 MHz. The low speed mode must be set, if the supply voltage is below 2.7 volts, because the Timer/Counter1 is not running fast enough on low voltage levels. It is highly recommended that Timer/Counter1 is stopped whenever the LSM bit is changed. * Bit 6.. 3- Res : Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and always read as zero. * Bit 2- PCKE: PCK Enable The PCKE bit change the Timer/Counter1 clock source. When it is set, the asynchronous clock mode is enabled and fast 64 MHz (or 32 MHz in Low Speed Mode) PCK clock is used as Timer/Counter1 clock source. If this bit is cleared, the synchronous clock mode is enabled, and system clock CK is used as Timer/Counter1 clock source. This bit can be set only if PLLE bit is set. It is safe to set this bit only when the PLL is locked i.e the PLOCK bit is 1. The bit PCKE can only be set, if the PLL has been enabled earlier. * Bit 1- PLLE: PLL Enable When the PLLE is set, the PLL is started and if needed internal RC-oscillator is started as a PLL reference clock. If PLL is selected as a system clock source the value for this bit is always 1. * Bit 0- PLOCK: PLL Lock Detector When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable PCK for Timer/Counter1. After the PLL is enabled, it takes about 100 micro seconds for the PLL to lock. 14.1.10 Timer/Counter1 Initialization for Asynchronous Mode To change Timer/Counter1 to the asynchronous mode, first enable PLL, wait 100 s before polling the PLOCK bit until it is set, and then set the PCKE bit. 89 7598H-AVR-07/09 14.1.11 Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1 and the Output Compare Register C OCR1C form a dual 8-bit, free-running and glitch-free PWM generator with outputs on the PB1(OC1A) and PB3(OC1B) pins and inverted outputs on pins PB0(OC1A) and PB2(OC1B). As default non-overlapping times for complementary output pairs are zero, but they can be inserted using a Dead Time Generator (see description on page 100). Figure 14-4. The PWM Output Pair PWM1x PWM1x t non-overlap =0 t non-overlap =0 x = A or B When the counter value match the contents of OCR1A or OCR1B, the OC1A and OC1B outputs are set or cleared according to the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1 Control Register A - TCCR1, as shown in Table 14-4. Timer/Counter1 acts as an up-counter, counting from $00 up to the value specified in the output compare register OCR1C, and starting from $00 up again. A compare match with OC1C will set an overflow interrupt flag (TOV1) after a synchronization delay following the compare event. Table 14-4. Compare Mode Select in PWM Mode COM11 COM10 Effect on Output Compare Pins 0 0 OC1x not connected. OC1x not connected. 0 1 OC1x cleared on compare match. Set whenTCNT1 = $01. OC1x set on compare match. Cleared when TCNT1 = $00. 1 0 OC1x cleared on compare match. Set when TCNT1 = $01. OC1x not connected. 1 1 OC1x Set on compare match. Cleared when TCNT1= $01. OC1x not connected. Note that in PWM mode, writing to the Output Compare Registers OCR1A or OCR1B, the data value is first transferred to a temporary location. The value is latched into OCR1A or OCR1B when the Timer/Counter reaches OCR1C. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A or OCR1B. See Figure 14-5 for an example. 90 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Figure 14-5. Effects of Unsynchronized OCR Latching Compare Value changes Counter Value Compare Value PWM Output OC1x Synchronized OC1x Latch Compare Value changes Counter Value Compare Value PWM Output OC1x Glitch Unsynchronized OC1x Latch During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A or OCR1B. When OCR1A or OCR1B contain $00 or the top value, as specified in OCR1C register, the output PB1(OC1A) or PB3(OC1B) is held low or high according to the settings of COM1A1/COM1A0. This is shown in Table 14-5. Table 14-5. PWM Outputs OCR1x = $00 or OCR1C, x = A or B COM1x1 COM1x0 OCR1x Output OC1x Output OC1x 0 1 $00 L H 0 1 OCR1C H L 1 0 $00 L Not connected. 1 0 OCR1C H Not connected. 1 1 $00 H Not connected. 1 1 OCR1C L Not connected. In PWM mode, the Timer Overflow Flag - TOV1 is set when the TCNT1 counts to the OCR1C value and the TCNT1 is reset to $00. The Timer Overflow Interrupt1 is executed when TOV1 is set provided that Timer Overflow Interrupt and global interrupts are enabled. This also applies to the Timer Output Compare flags and interrupts. The frequency of the PWM will be Timer Clock 1 Frequency divided by (OCR1C value + 1). See the following equation: f TCK1 f PWM = ----------------------------------( OCR1C + 1 ) 91 7598H-AVR-07/09 Resolution shows how many bit is required to express the value in the OCR1C register. It is calculated by following equation ResolutionPWM = log2(OCR1C + 1). Table 14-6. 92 Timer/Counter1 Clock Prescale Select in the Asynchronous Mode PWM Frequency Clock Selection CS13..CS10 OCR1C RESOLUTION 20 kHz PCK/16 0101 199 7.6 30 kHz PCK/16 0101 132 7.1 40 kHz PCK/8 0100 199 7.6 50 kHz PCK/8 0100 159 7.3 60 kHz PCK/8 0100 132 7.1 70 kHz PCK/4 0011 228 7.8 80 kHz PCK/4 0011 199 7.6 90 kHz PCK/4 0011 177 7.5 100 kHz PCK/4 0011 159 7.3 110 kHz PCK/4 0011 144 7.2 120 kHz PCK/4 0011 132 7.1 130 kHz PCK/2 0010 245 7.9 140 kHz PCK/2 0010 228 7.8 150 kHz PCK/2 0010 212 7.7 160 kHz PCK/2 0010 199 7.6 170 kHz PCK/2 0010 187 7.6 180 kHz PCK/2 0010 177 7.5 190 kHz PCK/2 0010 167 7.4 200 kHz PCK/2 0010 159 7.3 250 kHz PCK 0001 255 8.0 300 kHz PCK 0001 212 7.7 350 kHz PCK 0001 182 7.5 400 kHz PCK 0001 159 7.3 450 kHz PCK 0001 141 7.1 500 kHz PCK 0001 127 7.0 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 15. Dead Time Generator The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving external power control switches safely. The Dead Time Generator is a separate block that can be connected to Timer/Counter1 and it is used to insert dead times (non-overlapping times) for the Timer/Counter1 complementary output pairs (OC1A-OC1A and OC1B-OC1B). The sharing of tasks is as follows: the timer/counter generates the PWM output and the Dead Time Generator generates the non-overlapping PWM output pair from the timer/counter PWM signal. Two Dead Time Generators are provided, one for each PWM output. The non-overlap time is adjustable and the PWM output and it's complementary output are adjusted separately, and independently for both PWM outputs. Figure 15-1. Timer/Counter1 & Dead Time Generators PCKE TIMER/COUNTER1 T15M CK PWM GENERATOR PWM1A PWM1B PCK DT1AH DT1BH DEAD TIME GENERATOR DEAD TIME GENERATOR DT1AL DT1BL OC1A OC1B OC1A OC1B The dead time generation is based on the 4-bit down counters that count the dead time, as shown in Figure 46. There is a dedicated prescaler in front of the Dead Time Generator that can divide the Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8. This provides for large range of dead times that can be generated. The prescaler is controlled by two control bits DTPS11..10 from the I/O register at address 0x23. The block has also a rising and falling edge detector that is used to start the dead time counting period. Depending on the edge, one of the transitions on the rising edges, OC1x or OC1x is delayed until the counter has counted to zero. The comparator is used to compare the counter with zero and stop the dead time insertion when zero has been reached. The counter is loaded with a 4-bit DT1xH or DT1xL value from DT1x I/O register, depending on the edge of the PWM generator output when the dead time insertion is started. Figure 15-2. Dead Time Generator T/C1 CLOCK DTPS11..10 COMPARATOR OC1x DEAD TIME PRESCALER CLOCK CONTROL 4-BIT COUNTER DT1xL DT1xH OC1x DT1x I/O REGISTER PWM1x 93 7598H-AVR-07/09 The length of the counting period is user adjustable by selecting the dead time prescaler setting in 0x23 register, and selecting then the dead time value in I/O register DT1x. The DT1x register consists of two 4-bit fields, DT1xH and DT1xL that control the dead time periods of the PWM output and its' complementary output separately. Thus the rising edge of OC1x and OC1x can have different dead time periods. The dead time is adjusted as the number of prescaled dead time generator clock cycles. Figure 15-3. The Complementary Output Pair PWM1x OC1x OC1x x = A or B t non-overlap / rising edge 15.1 t non-overlap / falling edge Timer/Counter1 Dead Time Prescaler register 1 - DTPS1 Bit 7 6 5 4 3 2 $23 ($43) 1 0 DTPS11 DTPS10 Read/Write R R R R R R R/W R/W Initial value 0 0 0 0 0 0 0 0 DTPS1 The dead time prescaler register, DTPS1 is a 2-bit read/write register. Bits 1 - 0 - DTPS1: Timer/Counter1 Dead Time Prescaler register 1 The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8 providing a large range of dead times that can be generated. The Dead Time prescaler is controlled by two bits DTPS11..10 from the Dead Time Prescaler register. These bits define the division factor of the Dead Time prescaler. The division factors are given in table 46.. Table 15-1. 94 Division factors of the Dead Time prescaler DTPS11 DTPS10 Prescaler divides the T/C1 clock by 0 0 1x (no division) 0 1 2x 1 0 4x 1 1 8x ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 15.2 Timer/Counter1 Dead Time A - DT1A Bit 7 6 5 4 3 2 1 0 DT1AH3 DT1AH2 DT1AH1 DT1AH0 DT1AL3 DT1AL2 DT1AL1 DT1AL0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 $25 ($45) DT1A The dead time value register A is an 8-bit read/write register. The dead time delay of is adjusted by the dead time value register, DT1A. The register consists of two fields, DT1AH3..0 and DT1AL3..0, one for each complementary output. Therefore a different dead time delay can be adjusted for the rising edge of OC1A and the rising edge of OC1A. * Bits 7..4- DT1AH3..DT1AH0: Dead Time Value for OC1A Output The dead time value for the OC1A output. The dead time delay is set as a number of the prescaled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15. * Bits 3..0- DT1AL3..DT1AL0: Dead Time Value for OC1A Output The dead time value for the OC1A output. The dead time delay is set as a number of the prescaled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15. 15.3 Timer/Counter1 Dead Time B - DT1B Bit 7 6 5 4 3 2 1 0 DT1BH3 DT1BH2 DT1BH1 DT1BH0 DT1BL3 DT1BL2 DT1BL1 DT1BL0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 $25 ($45) DT1B The dead time value register Bis an 8-bit read/write register. The dead time delay of is adjusted by the dead time value register, DT1B. The register consists of two fields, DT1BH3..0 and DT1BL3..0, one for each complementary output. Therefore a different dead time delay can be adjusted for the rising edge of OC1A and the rising edge of OC1A. * Bits 7..4- DT1BH3..DT1BH0: Dead Time Value for OC1B Output The dead time value for the OC1B output. The dead time delay is set as a number of the prescaled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15. * Bits 3..0- DT1BL3..DT1BL0: Dead Time Value for OC1B Output The dead time value for the OC1B output. The dead time delay is set as a number of the prescaled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15. 95 7598H-AVR-07/09 16. Universal Serial Interface - USI The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load. The main features of the USI are: * * * * * * 16.1 Two-wire Synchronous Data Transfer (Master or Slave, fSCLmax = fCK/16) Three-wire Synchronous Data Transfer (Master or Slave fSCKmax = fCK/4) Data Received Interrupt Wakeup from Idle Mode In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode Two-wire Start Condition Detector with Interrupt Capability Overview A simplified block diagram of the USI is shown on Figure 16-1. For the actual placement of I/O pins, refer to "Pinout ATtiny25/45/85" on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the "USI Register Descriptions" on page 103. Figure 16-1. Universal Serial Interface, Block Diagram Bit7 Bit0 D Q LE DO (Output only) DI/SDA (Input/Open Drain) USCK/SCL (Input/Open Drain) 3 2 USIDR 1 0 TIM0 COMP USIPF 4-bit Counter USIDC USISIF USIOIF DATA BUS USIDB 3 2 0 1 1 0 CLOCK HOLD [1] Two-wire Clock Control Unit USISR USITC USICLK USICS0 USICS1 USIWM0 USIWM1 USISIE USIOIE 2 USICR The 8-bit Shift Register is directly accessible via the data bus and contains the incoming and outgoing data. The register has no buffering so the data must be read as quickly as possible to ensure that no data is lost. The most significant bit is connected to one of two output pins depending of the wire mode configuration. A transparent latch is inserted between the Serial Register Output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration. The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the Serial Register and the counter are clocked simultaneously by the same clock source. 96 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges. In this case the counter counts the number of edges, and not the number of bits. The clock can be selected from three different sources: The USCK pin, Timer/Counter0 Compare Match or from software. The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It can also generate wait states by holding the clock pin low after a start condition is detected, or after the counter overflows. 16.2 16.2.1 Functional Descriptions Three-wire Mode The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the slave select (SS) pin functionality. However, this feature can be implemented in software if necessary. Pin names used by this mode are: DI, DO, and USCK. Figure 16-2. Three-wire Mode Operation, Simplified Diagram DO Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 DI Bit0 USCK SLAVE DO Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 DI Bit0 USCK PORTxn MASTER Figure 16-2 shows two USI units operating in Three-wire mode, one as Master and one as Slave. The two Shift Registers are interconnected in such way that after eight USCK clocks, the data in each register are interchanged. The same clock also increments the USI's 4-bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the Master device software by toggling the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR. 97 7598H-AVR-07/09 Figure 16-3. Three-wire Mode, Timing Diagram CYCLE ( Reference ) 1 2 3 4 5 6 7 8 USCK USCK DO MSB DI MSB A B C 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB D E The Three-wire mode timing is shown in Figure 16-3. At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes. In External Clock mode 0 (USICS0 = 0), DI is sampled at positive edges, and DO is changed (Data Register is shifted by one) at negative edges. External Clock mode 1 (USICS0 = 1) uses the opposite edges versus mode 0, i.e., samples data at negative and changes the output at positive edges. The USI clock modes corresponds to the SPI data mode 0 and 1. Referring to the timing diagram (Figure 16-3.), a bus transfer involves the following steps: 1. The Slave device and Master device sets up its data output and, depending on the protocol used, enables its output driver (mark A and B). The output is set up by writing the data to be transmitted to the Serial Data Register. Enabling of the output is done by setting the corresponding bit in the port Data Direction Register. Note that point A and B does not have any specific order, but both must be at least one half USCK cycle before point C where the data is sampled. This must be done to ensure that the data setup requirement is satisfied. The 4-bit counter is reset to zero. 2. The Master generates a clock pulse by software toggling the USCK line twice (C and D). The bit value on the slave and master's data input (DI) pin is sampled by the USI on the first edge (C), and the data output is changed on the opposite edge (D). The 4-bit counter will count both edges. 3. Step 2. is repeated eight times for a complete register (byte) transfer. 4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that the transfer is completed. The data bytes transferred must now be processed before a new transfer can be initiated. The overflow interrupt will wake up the processor if it is set to Idle mode. Depending of the protocol used the slave device can now set its output to high impedance. 16.2.2 SPI Master Operation Example The following code demonstrates how to use the USI module as a SPI Master: SPITransfer: sts USIDR,r16 ldi r16,(1<<USIOIF) sts USISR,r16 ldi r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC) SPITransfer_loop: sts 98 USICR,r16 lds r16, USISR sbrs r16, USIOIF ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 rjmp SPITransfer_loop lds r16,USIDR ret The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are enabled as output in the DDRE Register. The value stored in register r16 prior to the function is called is transferred to the Slave device, and when the transfer is completed the data received from the Slave is stored back into the r16 Register. The second and third instructions clears the USI Counter Overflow Flag and the USI counter value. The fourth and fifth instruction set Three-wire mode, positive edge Shift Register clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times. The following code demonstrates how to use the USI module as a SPI Master with maximum speed (fsck = fck/4): SPITransfer_Fast: sts USIDR,r16 ldi r16,(1<<USIWM0)|(0<<USICS0)|(1<<USITC) ldi r17,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)|(1<<USICLK) sts USICR,r16 ; MSB sts USICR,r17 sts USICR,r16 sts USICR,r17 sts USICR,r16 sts USICR,r17 sts USICR,r16 sts USICR,r17 sts USICR,r16 sts USICR,r17 sts USICR,r16 sts USICR,r17 sts USICR,r16 sts USICR,r17 sts USICR,r16 ; LSB sts USICR,r17 lds r16,USIDR ret 99 7598H-AVR-07/09 16.2.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ldi r16,(1<<USIWM0)|(1<<USICS1) sts USICR,r16 ... SlaveSPITransfer: sts USIDR,r16 ldi r16,(1<<USIOIF) sts USISR,r16 SlaveSPITransfer_loop: lds r16, USISR sbrs r16, USIOIF rjmp SlaveSPITransfer_loop lds r16,USIDR ret The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO is configured as output and USCK pin is configured as input in the DDR Register. The value stored in register r16 prior to the function is called is transferred to the master device, and when the transfer is completed the data received from the Master is stored back into the r16 Register. Note that the first two instructions is for initialization only and needs only to be executed once.These instructions sets Three-wire mode and positive edge Shift Register clock. The loop is repeated until the USI Counter Overflow Flag is set. 16.2.4 100 Two-wire Mode The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate limiting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA. ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Figure 16-4. Two-wire Mode Operation, Simplified Diagram VCC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL HOLD SCL Two-wire Clock Control Unit SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL PORTxn MASTER Figure 16-4 shows two USI units operating in Two-wire mode, one as Master and one as Slave. It is only the physical layer that is shown since the system operation is highly dependent of the communication scheme used. The main differences between the Master and Slave operation at this level, is the serial clock generation which is always done by the Master, and only the Slave uses the clock control unit. Clock generation must be implemented in software, but the shift operation is done automatically by both devices. Note that only clocking on negative edge for shifting data is of practical use in this mode. The slave can insert wait states at start or end of transfer by forcing the SCL clock low. This means that the Master must always check if the SCL line was actually released after it has generated a positive edge. Since the clock also increments the counter, a counter overflow can be used to indicate that the transfer is completed. The clock is generated by the master by toggling the USCK pin via the PORT Register. The data direction is not given by the physical layer. A protocol, like the one used by the TWI-bus, must be implemented to control the data flow. Figure 16-5. Two-wire Mode, Typical Timing Diagram SDA SCL S A B 1-7 8 9 1-8 9 1-8 9 ADDRESS R/W ACK DATA ACK DATA ACK C D E P F 101 7598H-AVR-07/09 Referring to the timing diagram (Figure 16-5.), a bus transfer involves the following steps: 1. The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift Register, or by setting the corresponding bit in the PORT Register to zero. Note that the Data Direction Register bit must be set to one for the output to be enabled. The slave device's start detector logic (Figure 16-6.) detects the start condition and sets the USISIF Flag. The flag can generate an interrupt if necessary. 2. In addition, the start detector will hold the SCL line low after the Master has forced an negative edge on this line (B). This allows the Slave to wake up from sleep or complete its other tasks before setting up the Shift Register to receive the address. This is done by clearing the start condition flag and reset the counter. 3. The Master set the first bit to be transferred and releases the SCL line (C). The Slave samples the data and shift it into the Serial Register at the positive edge of the SCL clock. 4. After eight bits are transferred containing slave address and data direction (read or write), the Slave counter overflows and the SCL line is forced low (D). If the slave is not the one the Master has addressed, it releases the SCL line and waits for a new start condition. 5. If the Slave is addressed it holds the SDA line low during the acknowledgment cycle before holding the SCL line low again (i.e., the Counter Register must be set to 14 before releasing SCL at (D)). Depending of the R/W bit the Master or Slave enables its output. If the bit is set, a master read operation is in progress (i.e., the slave drives the SDA line) The slave can hold the SCL line low after the acknowledge (E). 6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is given by the Master (F). Or a new start condition is given. If the Slave is not able to receive more data it does not acknowledge the data byte it has last received. When the Master does a read operation it must terminate the operation by force the acknowledge bit low after the last byte transmitted. Figure 16-6. Start Condition Detector, Logic Diagram USISIF D Q D Q CLR CLR SDA CLOCK HOLD SCL Write( USISIF) 16.2.5 Start Condition Detector The start condition detector is shown in Figure 16-6. The SDA line is delayed (in the range of 50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled in Two-wire mode. The start condition detector is working asynchronously and can therefore wake up the processor from the Power-down sleep mode. However, the protocol used might have restrictions on the SCL hold time. Therefore, when using this feature in this case the Oscillator start-up time set by the CKSEL Fuses (see "Clock Systems and their Distribution" on page 21) must also be taken into the consideration. Refer to the USISIF bit description on page 104 for further details. 102 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 16.3 Alternative USI Usage When the USI unit is not used for serial communication, it can be set up to do alternative tasks due to its flexible design. 16.3.1 Half-duplex Asynchronous Data Transfer By utilizing the Shift Register in Three-wire mode, it is possible to implement a more compact and higher performance UART than by software only. 16.3.2 4-bit Counter The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the counter is clocked externally, both clock edges will generate an increment. 16.3.3 12-bit Timer/Counter Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit counter. 16.3.4 Edge Triggered External Interrupt By setting the counter to maximum value (F) it can function as an additional external interrupt. The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature is selected by the USICS1 bit. 16.3.5 Software Interrupt The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe. 16.4 USI Register Descriptions 16.4.1 USI Data Register - USIDR Bit 7 6 5 4 3 2 1 MSB 0 LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 USIDR When accessing the USI Data Register (USIDR) the Serial Register can be accessed directly. If a serial clock occurs at the same cycle the register is written, the register will contain the value written and no shift is performed. A (left) shift operation is performed depending of the USICS1..0 bits setting. The shift operation can be controlled by an external clock edge, by a Timer/Counter0 Compare Match, or directly by software using the USICLK strobe bit. Note that even when no wire mode is selected (USIWM1..0 = 0) both the external data input (DI/SDA) and the external clock input (USCK/SCL) can still be used by the Shift Register. The output pin in use, DO or SDA depending on the wire mode, is connected via the output latch to the most significant bit (bit 7) of the Data Register. The output latch is open (transparent) during the first half of a serial clock cycle when an external clock source is selected (USICS1 = 1), and constantly open when an internal clock source is used (USICS1 = 0). The output will be changed immediately when a new MSB written as long as the latch is open. The latch ensures that data input is sampled and data output is changed on opposite clock edges. Note that the corresponding Data Direction Register to the pin must be set to one for enabling data output from the Shift Register. 103 7598H-AVR-07/09 16.4.2 USI Buffer Register - USIBR Bit 7 6 5 4 3 2 1 MSB 0 LSB Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 USIBR The content of the Serial Register is loaded to the USI Buffer Register when the trasfer is completed, and instead of accessing the USI Data Register (the Serial Register) the USI Data Buffer can be accessed when the CPU reads the received data. This gives the CPU time to handle other program tasks too as the controlling of the USI is not so timing critical. The USI flags as set same as when reading the USIDR register. 16.4.3 USI Status Register - USISR Bit 7 6 5 4 3 2 1 0 USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 USISR The Status Register contains Interrupt Flags, line Status Flags and the counter value. * Bit 7 - USISIF: Start Condition Interrupt Flag When Two-wire mode is selected, the USISIF Flag is set (to one) when a start condition is detected. When output disable mode or Three-wire mode is selected and (USICSx = 0b11 & USICLK = 0) or (USICS = 0b10 & USICLK = 0), any edge on the SCK pin sets the flag. An interrupt will be generated when the flag is set while the USISIE bit in USICR and the Global Interrupt Enable Flag are set. The flag will only be cleared by writing a logical one to the USISIF bit. Clearing this bit will release the start detection hold of USCL in Two-wire mode. A start condition interrupt will wakeup the processor from all sleep modes. * Bit 6 - USIOIF: Counter Overflow Interrupt Flag This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). An interrupt will be generated when the flag is set while the USIOIE bit in USICR and the Global Interrupt Enable Flag are set. The flag will only be cleared if a one is written to the USIOIF bit. Clearing this bit will release the counter overflow hold of SCL in Two-wire mode. A counter overflow interrupt will wakeup the processor from Idle sleep mode. * Bit 5 - USIPF: Stop Condition Flag When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is detected. The flag is cleared by writing a one to this bit. Note that this is not an Interrupt Flag. This signal is useful when implementing Two-wire bus master arbitration. * Bit 4 - USIDC: Data Output Collision This bit is logical one when bit 7 in the Shift Register differs from the physical pin value. The flag is only valid when Two-wire mode is used. This signal is useful when implementing Two-wire bus master arbitration. * Bits 3..0 - USICNT3..0: Counter Value These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or written by the CPU. 104 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 The 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe bits. The clock source depends of the setting of the USICS1..0 bits. For external clock operation a special feature is added that allows the clock to be generated by writing to the USITC strobe bit. This feature is enabled by write a one to the USICLK bit while setting an external clock source (USICS1 = 1). Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input (USCK/SCL) are can still be used by the counter. 16.4.4 USI Control Register - USICR Bit 7 6 5 4 3 2 1 0 USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC Read/Write R/W R/W R/W R/W R/W R/W W W Initial Value 0 0 0 0 0 0 0 0 USICR The Control Register includes interrupt enable control, wire mode setting, Clock Select setting, and clock strobe. * Bit 7 - USISIE: Start Condition Interrupt Enable Setting this bit to one enables the Start Condition detector interrupt. If there is a pending interrupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will immediately be executed. Refer to the USISIF bit description on page 104 for further details. * Bit 6 - USIOIE: Counter Overflow Interrupt Enable Setting this bit to one enables the Counter Overflow interrupt. If there is a pending interrupt when the USIOIE and the Global Interrupt Enable Flag is set to one, this will immediately be executed. Refer to the USIOIF bit description on page 104 for further details. * Bit 5..4 - USIWM1..0: Wire Mode These bits set the type of wire mode to be used. Basically only the function of the outputs are affected by these bits. Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and Shift Register can therefore be clocked externally, and data input sampled, even when outputs are disabled. The relations between USIWM1..0 and the USI operation is summarized in Table 16-1. 105 7598H-AVR-07/09 Table 16-1. Relations between USIWM1..0 and the USI Operation USIWM1 USIWM0 0 0 Outputs, clock hold, and start detector disabled. Port pins operates as normal. 1 Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORT Register in this mode. However, the corresponding DDR bit still controls the data direction. When the port pin is set as input the pins pull-up is controlled by the PORT bit. The Data Input (DI) and Serial Clock (USCK) pins do not affect the normal port operation. When operating as master, clock pulses are software generated by toggling the PORT Register, while the data direction is set to output. The USITC bit in the USICR Register can be used for this purpose. 0 Two-wire mode. Uses SDA (DI) and SCL (USCK) pins(1). The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and uses open-collector output drives. The output drivers are enabled by setting the corresponding bit for SDA and SCL in the DDR Register. When the output driver is enabled for the SDA pin, the output driver will force the line SDA low if the output of the Shift Register or the corresponding bit in the PORT Register is zero. Otherwise the SDA line will not be driven (i.e., it is released). When the SCL pin output driver is enabled the SCL line will be forced low if the corresponding bit in the PORT Register is zero, or by the start detector. Otherwise the SCL line will not be driven. The SCL line is held low when a start detector detects a start condition and the output is enabled. Clearing the Start Condition Flag (USISIF) releases the line. The SDA and SCL pin inputs is not affected by enabling this mode. Pull-ups on the SDA and SCL port pin are disabled in Two-wire mode. 1 Two-wire mode. Uses SDA and SCL pins. Same operation as for the Two-wire mode described above, except that the SCL line is also held low when a counter overflow occurs, and is held low until the Counter Overflow Flag (USIOIF) is cleared. 0 1 1 Note: Description 1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively to avoid confusion between the modes of operation. * Bit 3..2 - USICS1..0: Clock Source Select These bits set the clock source for the Shift Register and counter. The data output latch ensures that the output is changed at the opposite edge of the sampling of the data input (DI/SDA) when using external clock source (USCK/SCL). When software strobe or Timer/Counter0 Compare Match clock option is selected, the output latch is transparent and therefore the output is changed immediately. Clearing the USICS1..0 bits enables software strobe option. When using this option, writing a one to the USICLK bit clocks both the Shift Register and the counter. For external clock source (USICS1 = 1), the USICLK bit is no longer used as a strobe, but selects between external clocking and software clocking by the USITC strobe bit. 106 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Table 16-2 shows the relationship between the USICS1..0 and USICLK setting and clock source used for the Shift Register and the 4-bit counter. Table 16-2. Relations between the USICS1..0 and USICLK Setting USICS1 USICS0 USICLK Shift Register Clock Source 4-bit Counter Clock Source 0 0 0 No Clock No Clock 0 0 1 Software clock strobe (USICLK) Software clock strobe (USICLK) 0 1 X Timer/Counter0 Compare Match Timer/Counter0 Compare Match 1 0 0 External, positive edge External, both edges 1 1 0 External, negative edge External, both edges 1 0 1 External, positive edge Software clock strobe (USITC) 1 1 1 External, negative edge Software clock strobe (USITC) * Bit 1 - USICLK: Clock Strobe Writing a one to this bit location strobes the Shift Register to shift one step and the counter to increment by one, provided that the USICS1..0 bits are set to zero and by doing so the software clock strobe option is selected. The output will change immediately when the clock strobe is executed, i.e., in the same instruction cycle. The value shifted into the Shift Register is sampled the previous instruction cycle. The bit will be read as zero. When an external clock source is selected (USICS1 = 1), the USICLK function is changed from a clock strobe to a Clock Select Register. Setting the USICLK bit in this case will select the USITC strobe bit as clock source for the 4-bit counter (see Table 16-2). * Bit 0 - USITC: Toggle Clock Port Pin Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from 1 to 0. The toggling is independent of the setting in the Data Direction Register, but if the PORT value is to be shown on the pin the DDRE4 must be set as output (to one). This feature allows easy clock generation when implementing master devices. The bit will be read as zero. When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer is done when operating as a master device. 107 7598H-AVR-07/09 17. Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 17-1. Figure 17-1. Analog Comparator Block Diagram(2) BANDGAP REFERENCE ACBG ACME ADEN ADC MULTIPLEXER OUTPUT (1) Notes: 1. See Table 17-2 on page 110. 2. Refer to Figure 1-1 on page 2 and Table 10-5 on page 57 for Analog Comparator pin placement. 17.1 ADC Control and Status Register B - ADCSRB Bit 7 6 5 4 3 2 1 0 BIN ACME IPR - - ADTS2 ADTS1 ADTS0 Read/Write R R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB * Bit 6 - ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see "Analog Comparator Multiplexed Input" on page 110. 17.2 Analog Comparator Control and Status Register - ACSR Bit 7 6 5 4 3 2 1 0 ACD ACBG ACO ACI ACIE - ACIS1 ACIS0 Read/Write R/W R/W R R/W R/W R R/W R/W Initial Value 0 0 N/A 0 0 0 0 0 ACSR * Bit 7 - ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. 108 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. * Bit 6 - ACBG: Analog Comparator Bandgap Select When this bit is set an internal 1.1V / 2.56V reference voltage replaces the positive input to the Analog Comparator. The selection of the internal voltage reference is done by writing the REFS2..0 bits in ADMUX register. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. * Bit 5 - ACO: Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles. * Bit 4 - ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. * Bit 3 - ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated. When written logic zero, the interrupt is disabled. * Bit 2 - Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and will always read as zero. * Bits 1, 0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 17-1. Table 17-1. ACIS1/ACIS0 Settings ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle. 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge. 1 1 Comparator Interrupt on Rising Output Edge. When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. 109 7598H-AVR-07/09 17.3 Analog Comparator Multiplexed Input It is possible to select any of the ADC3..0 pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX1..0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in Table 17-2. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog Comparator. Table 17-2. 17.3.1 Analog Comparator Multiplexed Input ACME ADEN MUX1..0 Analog Comparator Negative Input 0 x xx AIN1 1 1 xx AIN1 1 0 00 ADC0 1 0 01 ADC1 1 0 10 ADC2 1 0 11 ADC3 Digital Input Disable Register 0 - DIDR0 Bit 7 6 5 4 3 2 1 0 - - ADC0D ADC2D ADC3D ADC1D AIN1D AIN0D Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DIDR0 * Bits 1, 0 - AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 110 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 18. Analog to Digital Converter 18.1 Features * * * * * * * * * * * * * * * * * 10-bit Resolution 0.5 LSB Integral Non-linearity 2 LSB Absolute Accuracy 65 - 260 s Conversion Time Up to 15 kSPS at Maximum Resolution Four Multiplexed Single Ended Input Channels Two differential input channels with selectable gain Temperature sensor input channel Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 1.1V / 2.56V ADC Voltage Reference Free Running or Single Conversion Mode ADC Start Conversion by Auto Triggering on Interrupt Sources Interrupt on ADC Conversion Complete Sleep Mode Noise Cancele Unipolar / Bibilar Input Mode Input Polarity Reversal Mode The ATtiny25/45/85 features a 10-bit successive approximation ADC. The ADC is connected to a 4-channel Analog Multiplexer which allows one differential voltage input and four single-ended voltage inputs constructed from the pins of Port B. The differential input (PB3, PB4 or PB2, PB5) is equipped with a programmable gain stage, providing amplification step of 26 dB (20x) on the differential input voltage before the A/D conversion. The single-ended voltage inputs refer to 0V (GND). The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion. A block diagram of the ADC is shown in Figure 18-1. Internal voltage references of nominally 1.1V or 2.56V are provided On-chip and these voltage references can optionally be externally decoupled at the AREF (PB0) pin by a capacitor, for better noise performance. Alternatively, VCC can be used as voltage reference for single ended channels. There is also an option to use an external voltage reference and turn-off the internal voltage reference. These options are selected using the REFS2..0 bits of the ADMUX control register. 111 7598H-AVR-07/09 Figure 18-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] AREF INTERNAL 1.1V/2.56V REFERENCE PRESCALER START CONVERSION LOGIC TEMPERATURE SENSOR SAMPLE & HOLD COMPARATOR 10-BIT DAC ADC4 ADC3 ADC2 ADC[9:0] ADPS1 ADPS0 ADPS2 ADIF ADSC ADATE ADEN ADLAR MUX1 MUX0 MUX DECODER CHANNEL SELECTION VCC 0 ADC DATA REGISTER (ADCH/ADCL) TRIGGER SELECT GAIN SELECTION REFS2..0 BIN IPR 15 ADC CTRL. & STATUS A REGISTER (ADCSRA) ADC MULTIPLEXER SELECT (ADMUX) MUX2 ADC CTRL. & STATUS B REGISTER (ADCSRB) ADIE ADIF 8-BIT DATA BUS + SINGLE ENDED / DIFFERENTIAL SELECTION INPUT MUX ADC1 ADC0 + GAIN AMPLIFIER ADC MULTIPLEXER OUTPUT NEG. INPUT MUX 18.2 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on VCC, the voltage on the AREF pin or an internal 1.1V / 2.56V voltage reference. The voltage reference for the ADC may be selected by writing to the REFS2..0 bits in ADMUX. The VCC supply, the AREF pin or an internal 1.1V / 2.56V voltage reference may be selected as the ADC voltage reference. Optionally the internal 1.1V / 2.56V voltage reference may be decoupled by an external capacitor at the AREF pin to improve noise immunity. The analog input channel and differential gain are selected by writing to the MUX3..0 bits in ADMUX. Any of the four ADC input pins ADC3..0 can be selected as single ended inputs to the ADC. ADC2 or ADC0 can be selected as positive input and ADC0, ADC1, ADC2 or ADC3 can be selected as negative input to the differential gain amplifier. If differential channels are selected, the differential gain stage amplifies the voltage difference between the selected input pair by the selected gain factor, 1x or 20x, according to the setting of the MUX3..0 bits in ADMUX. This amplified value then becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is bypassed altogether. 112 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 If ADC0 or ADC2 is selected as both the positive and negative input to the differential gain amplifier (ADC0-ADC0 or ADC2-ADC2), the remaining offset in the gain stage and conversion circuitry can be measured directly as the result of the conversion. This figure can be subtracted from subsequent conversions with the same gain setting to reduce offset error to below 1 LSW. The on-chip temperature sensor is selected by writing the code "1111" to the MUX3..0 bits in ADMUX register when the ADC4 channel is used as an ADC input. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX. If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost. 18.3 Starting a Conversion A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change. Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (see description of the ADTS bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a method of starting conversions at fixed intervals. If the trigger signal still is set when the conversion completes, a new conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event. 113 7598H-AVR-07/09 Figure 18-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. 18.4 Prescaling and Conversion Timing Figure 18-3. ADC Prescaler ADEN START Reset 7-BIT ADC PRESCALER CK/64 CK/128 CK/32 CK/8 CK/16 CK/4 CK/2 CK ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate. It is not recommended to use a higher input clock frequency than 1 MHz. 114 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 14.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization logic. In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, see Table 18-1. Figure 18-4. ADC Timing Diagram, First Conversion (Single Conversion Mode) Next Conversion First Conversion Cycle Number 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 ADC Clock ADEN ADSC ADIF Sign and MSB of Result ADCH LSB of Result ADCL MUX and REFS Update Sample & Hold Conversion Complete MUX and REFS Update 115 7598H-AVR-07/09 Figure 18-5. ADC Timing Diagram, Single Conversion One Conversion Cycle Number 1 2 3 4 5 6 7 8 Next Conversion 9 10 11 12 13 1 2 3 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete MUX and REFS Update MUX and REFS Update Figure 18-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion Cycle Number 1 2 3 4 5 6 7 8 Next Conversion 10 9 11 12 13 1 2 ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Prescaler Reset Sample & Hold Conversion Complete Prescaler Reset MUX and REFS Update Figure 18-7. ADC Timing Diagram, Free Running Conversion One Conversion Cycle Number 11 12 Next Conversion 13 1 2 3 4 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Conversion Complete 116 Sample & Hold MUX and REFS Update ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Table 18-1. ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Total Conversion Time (Cycles) First conversion 13.5 25 Normal conversions 1.5 13 2 13.5 Condition Auto Triggered conversions 18.5 Changing Channel or Reference Selection The MUX3..0 and REFS2..0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and voltage reference selection only takes place at a safe point during the conversion. The channel and voltage reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and voltage reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or voltage reference selection values to ADMUX until one ADC clock cycle after ADSC is written. If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings. If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways: a. When ADATE or ADEN is cleared. b. During conversion, minimum one ADC clock cycle after the trigger event. c. After a conversion, before the Interrupt Flag used as trigger source is cleared. When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion. 18.5.1 ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection. In Free Running mode, always select the channel before starting the first conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the channel selection. Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. 117 7598H-AVR-07/09 18.5.2 18.6 ADC Voltage Reference The voltage reference for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either VCC, or internal 1.1V / 2.56V voltage reference, or external AREF pin. The first ADC conversion result after switching voltage reference source may be inaccurate, and the user is advised to discard this result. ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: a. Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled. b. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted. c. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU before the ADC conversion is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed. Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption. 18.6.1 Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 18-8. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path). The ADC is optimized for analog signals with an output impedance of approximately 10 k or less. If such a source is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor. Signal components higher than the Nyquist frequency (fADC/2) should not be present to avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. 118 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Figure 18-8. Analog Input Circuitry IIH ADCn 1..100 kohm CS/H= 14 pF IIL VCC/2 18.6.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. 18.6.3 b. Use the ADC noise canceler function to reduce induced noise from the CPU. c. If any port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and V REF in 2 n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal behavior: * Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 18-9. Offset Error Output Code Ideal ADC Actual ADC Offset Error VREF Input Voltage 119 7598H-AVR-07/09 * Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 18-10. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage * Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 18-11. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF Input Voltage * Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. 120 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Figure 18-12. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 VREF Input Voltage * Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always 0.5 LSB. * Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. Ideal value: 0.5 LSB. 18.7 ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). The form of the conversion result depends on the type of the conversio as there are three types of conversions: single ended conversion, unipolar differential conversion and bipolar differential conversion. 18.7.1 Single Ended Conversion For single ended conversion, the result is V IN 1024 ADC = ---------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 18-3 on page 123 and Table 18-4 on page 124). 0x000 represents analog ground, and 0x3FF represents the selected voltage reference minus one LSB. The result is presented in one-sided form, from 0x3FF to 0x000. 18.7.2 Unipolar Differential Conversion If differential channels and an unipolar input mode are used, the result is ( V POS - V NEG ) 1024 ADC = ----------------------------------------------------------- GAIN V REF 121 7598H-AVR-07/09 where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin, and VREF the selected voltage reference (see Table 18-3 on page 123 and Table 18-4 on page 124). The voltage on the positive pin must always be larger than the voltage on the negative pin or otherwise the voltage difference is saturated to zero. The result is presented in one-sided form, from 0x000 (0d) to 0x3FF (+1023d). The GAIN is either 1x or 20x. 18.7.3 Bipolar Differential Conversion As default the ADC converter operates in the unipolar input mode, but the bipolar input mode can be selected by writting the BIN bit in the ADCSRB to one. In the bipolar input mode two-sided voltage differences are allowed and thus the voltage on the negative input pin can also be larger than the voltage on the positive input pin. If differential channels and a bipolar input mode are used, the result is ( V POS - V NEG ) 512 ADC = ------------------------------------------------------- GAIN V REF where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin, and VREF the selected voltage reference. The result is presented in two's complement form, from 0x200 (-512d) through 0x000 (+0d) to 0x1FF (+511d). The GAIN is either 1x or 20x. However, if the signal is not bipolar by nature (9 bits + sign as the 10th bit), this scheme loses one bit of the converter dynamic range. Then, if the user wants to perform the conversion with the maximum dynamic range, the user can perform a quick polarity check of the result and use the unipolar differential conversion with selectable differential input pairs (see the Input Polarity Reversal mode ie. the IPR bit in the ADCSRB register on page 135). When the polarity check is performed, it is sufficient to read the MSB of the result (ADC9 in ADCH). If the bit is one, the result is negative, and if this bit is zero, the result is positive. 18.7.4 Temperature Measurement (Preliminary description) The temperature measurement is based on an on-chip temperature sensor that is coupled to a single ended ADC4 channel. Selecting the ADC4 channel by writing the MUX3..0 bits in ADMUX register to "1111" enables the temperature sensor. The internal 1.1V voltage reference must also be selected for the ADC voltage reference source in the temperature sensor measurement. When the temperature sensor is enabled, the ADC converter can be used in single conversion mode to measure the voltage over the temperature sensor. The measured voltage has a linear relationship to the temperature as described in Table 51. The voltage sensitivity is approximately 1 mV / C and the accuracy of the temperature measurement is +/- 10C after bandgap calibration. Table 18-2. Temperature vs. Sensor Output Voltage (Typical Case) Temperature / C Voltage / mV 122 -45C +25C 242 mV +105C 314 mv 403 mV ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 The values described in Table 51 are typical values. However, due to the process variation the temperature sensor output voltage varies from one chip to another. To be capable of achieving more accurate results the temperature measurement can be calibrated in the application software. The software calibration requires that a calibration value is measured and stored in a register or EEPROM for each chip, as a part of the production test. The sofware calibration can be done utilizing the formula: Temperature = k V TEMP + T OS where VTEMP is the ADC reading of the temperature sensor signal, k is a fixed coefficient and TOS is the temperature sensor offset value determined and stored into EEPROM as a part of production test. 18.7.5 ADC Multiplexer Selection Register - ADMUX Bit 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR REFS2 MUX3 MUX2 MUX1 MUX0 Read/Write R R/W R/W R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADMUX * Bit 7..6,4 - REFS2..REFS0: Voltage Reference Selection Bits These bits select the voltage reference (VREF) for the ADC, as shown in Table 18-3. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). Whenever these bits are changed, the next conversion will take 25 ADC clock cycles. If active channels are used, using VCC or an external AREF higher than (VCC - 1V) as a voltage reference is not recommended, as this will affect the ADC accuracy. Table 18-3. 1. Voltage Reference Selections for ADC REFS2 REFS1 REFS0 Voltage Reference (VREF) Selection 0 0 0 VCC used as Voltage Reference, disconnected from PB0 (AREF). 0 0 1 External Voltage Reference at PB0 (AREF) pin, Internal Voltage Reference turned off. 0 1 0 Internal 1.1V Voltage Reference without external bypass capacitor, disconnected from PB0 (AREF). 0 1 1 Internal 1.1V Voltage Reference with external bypass capacitor at PB0 (AREF) pin. 1 1 0 Internal 2.56V Voltage Reference without external bypass capacitor, disconnected from PB0 (AREF). (1) 1 1 1 Internal 2.56V Voltage Reference with external bypass capacitor at PB0 (AREF) pin.(1) The device requires a supply voltage of 3V in order to generate 2.56V reference voltage. * Bit 5 - ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conversions. For a comple te description of this bit, see "The ADC Data Register - ADCL and ADCH" on page 126. 123 7598H-AVR-07/09 * Bits 3:0 - MUX3:0: Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. In case of differential input (ADC0 - ADC1 or ADC2 - ADC3), gain selection is also made with these bits. Selecting ADC2 or ADC0 as both inputs to the differential gain stage enables offset measurements. Selecting the single-ended channel ADC4 enables the temperature sensor. Refer to Table 18-4 for details. If these bits are changed during a conversion, the change will not go into effect until this conversion is complete (ADIF in ADCSRA is set). Table 18-4. Input Channel Selections MUX3..0 Single Ended Input 0000 ADC0 (PB5) 0001 ADC1 (PB2) 0010 ADC2 (PB4) 0011 ADC3 (PB3) Positive Differential Input Negative Differential Input Gain N/A 0100 ADC2 (PB3) ADC2 (PB3) 1x ADC2 (PB3) ADC2 (PB3) 20x ADC2 (PB3) ADC3 (PB4) 1x ADC2 (PB3) ADC3 (PB4) 20x 1000 ADC0 (PB5) ADC0 (PB5) 1x 1001 ADC0 (PB5) ADC0 (PB5) 20x 1010 ADC0 (PB5) ADC1 (PB2) 1x 1011 ADC0 (PB5) ADC1 (PB2) 20x 0101 (1) 0110 0111 N/A 1100 1.1V/2.56V 1101 0V 1110 N/A 1111 ADC4 N/A 18.7.6 (2) 1. For offset calibration only . See "Operation" on page 112. 2. For Temperature Sensor ADC Control and Status Register A - ADCSRA Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRA * Bit 7 - ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. * Bit 6 - ADSC: ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. 124 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect. * Bit 5 - ADATE: ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB. * Bit 4 - ADIF: ADC Interrupt Flag This bit is set when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. * Bit 3 - ADIE: ADC Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated. * Bits 2:0 - ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the system clock frequency and the input clock to the ADC. Table 18-5. ADC Prescaler Selections ADPS2 ADPS1 ADPS0 Division Factor 0 0 0 2 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 125 7598H-AVR-07/09 18.7.7 18.7.7.1 The ADC Data Register - ADCL and ADCH ADLAR = 0 Bit Read/Write Initial Value 18.7.7.2 15 14 13 12 11 10 9 8 - - - - - - ADC9 ADC8 ADCH ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADLAR = 1 Bit Read/Write Initial Value 15 14 13 12 11 10 9 8 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH ADC1 ADC0 - - - - - - ADCL 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 When an ADC conversion is complete, the result is found in these two registers. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. * ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in "ADC Conversion Result" on page 121. 18.7.8 ADC Control and Status Register B - ADCSRB Bit 7 6 5 4 3 2 1 0 BIN ACME IPR - - ADTS2 ADTS1 ADTS0 Read/Write R/W R/W R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB * Bit 7- BIN: Bipolar Input Mode The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected by writing the BIN bit in the ADCSRB register. In the unipolar mode only one-sided conversions are supported and the voltage on the positive input must always be larger than the voltage on the negative input. Otherwise the result is saturated to the voltage reference. In the bipolar mode two-sided conversions are supported and the result is represented in the two's complement form. In the unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits + 1 sign bit. 126 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 * Bit 5 - IPR: Input Polarity Mode The Input Polarity mode allows software selectable differential input pairs and full 10 bit ADC resolution, in the unipolar input mode, assuming a pre-determined input polarity. If the input polarity is not known it is actually possible to determine the polarity first by using the bipolar input mode (with 9 bit resolution + 1 sign bit ADC measurement). And once determined, set or clear the polarity reversal bit, as needed, for a succeeding 10 bit unipolar measurement. * Bits 4..3 - Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. * Bits 2:0 - ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set. Table 18-6. 18.7.9 ADC Auto Trigger Source Selections ADTS2 ADTS1 ADTS0 Trigger Source 0 0 0 Free Running mode 0 0 1 Analog Comparator 0 1 0 External Interrupt Request 0 0 1 1 Timer/Counter Compare Match A 1 0 0 Timer/Counter Overflow 1 0 1 Timer/Counter Compare Match B 1 1 0 Pin Change Interrupt Request Digital Input Disable Register 0 - DIDR0 Bit 7 6 5 4 3 2 1 0 - - ADC0D ADC2D ADC3D ADC1D AIN1D AIN0D Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DIDR0 * Bits 5..2 - ADC3D..ADC0D: ADC3..0 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC3..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 127 7598H-AVR-07/09 19. debugWIRE On-chip Debug System 19.1 Features * * * * * * * * * * 19.2 Complete Program Flow Control Emulates All On-chip Functions, Both Digital and Analog , except RESET Pin Real-time Operation Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs) Unlimited Number of Program Break Points (Using Software Break Points) Non-intrusive Operation Electrical Characteristics Identical to Real Device Automatic Configuration System High-Speed Operation Programming of Non-volatile Memories Overview The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the program flow, execute AVR instructions in the CPU and to program the different non-volatile memories. 19.3 Physical Interface When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE system within the target device is activated. The RESET port pin is configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the communication gateway between target and emulator. Figure 19-1. The debugWIRE Setup 1.8 - 5.5V VCC dW dW(RESET) GND Figure 19-1 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses. 128 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 When designing a system where debugWIRE will be used, the following observations must be made for correct operation: * Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 k. However, the pull-up resistor is optional. * Connecting the RESET pin directly to VCC will not work. * Capacitors inserted on the RESET pin must be disconnected when using debugWire. * All external reset sources must be disconnected. 19.4 Software Break Points debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a Break Point in AVR Studio(R) will insert a BREAK instruction in the Program memory. The instruction replaced by the BREAK instruction will be stored. When program execution is continued, the stored instruction will be executed before continuing from the Program memory. A break can be inserted manually by putting the BREAK instruction in the program. The Flash must be re-programmed each time a Break Point is changed. This is automatically handled by AVR Studio through the debugWIRE interface. The use of Break Points will therefore reduce the Falsh Data retention. Devices used for debugging purposes should not be shipped to end customers. 19.5 Limitations of debugWIRE The debugWIRE communication pin (dW) is physically located on the same pin as External Reset (RESET). An External Reset source is therefore not supported when the debugWIRE is enabled. The debugWIRE system accurately emulates all I/O functions when running at full speed, i.e., when the program in the CPU is running. When the CPU is stopped, care must be taken while accessing some of the I/O Registers via the debugger (AVR Studio). A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse should be disabled when debugWire is not used. 19.6 debugWIRE Related Register in I/O Memory The following section describes the registers used with the debugWire. 19.6.1 debugWire Data Register - DWDR Bit 7 6 5 4 3 2 1 0 DWDR[7:0] DWDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The DWDR Register provides a communication channel from the running program in the MCU to the debugger. This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations. 129 7598H-AVR-07/09 20. Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory. The Program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased. The temporary page buffer is filled one word at a time using SPM and the buffer can be filled either before the Page Erase command or between a Page Erase and a Page Write operation: Alternative 1, fill the buffer before a Page Erase * Fill temporary page buffer * Perform a Page Erase * Perform a Page Write Alternative 2, fill the buffer after Page Erase * Perform a Page Erase * Fill temporary page buffer * Perform a Page Write If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be re-written. When using alternative 1, the Boot Loader provides an effective Read-Modify-Write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. If alternative 2 is used, it is not possible to read the old data while loading since the page is already erased. The temporary page buffer can be accessed in a random sequence. It is essential that the page address used in both the Page Erase and Page Write operation is addressing the same page. 20.1 Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write "00000011" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. * The CPU is halted during the Page Erase operation. 20.2 Filling the Temporary Buffer (Page Loading) To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write "00000001" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The content of PCWORD in the Z-register is used to address the data in the temporary buffer. The temporary buffer will auto-erase after a Page Write operation or by writing the CTPB bit in SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 130 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 20.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write "00000101" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. * The CPU is halted during the Page Write operation. 20.4 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. Bit 15 14 13 12 11 10 9 8 ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 7 6 5 4 3 2 1 0 Since the Flash is organized in pages (see Table 21-6 on page 137), the Program Counter can be treated as having two different sections. One section, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. This is shown in Figure 20-1. Note that the Page Erase and Page Write operations are addressed independently. Therefore it is of major importance that the software addresses the same page in both the Page Erase and Page Write operation. The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. Figure 20-1. Addressing the Flash During SPM(1) BIT 15 ZPCMSB ZPAGEMSB Z - REGISTER 1 0 0 PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE PCWORD WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: 1. The different variables used in Figure 20-1 are listed in Table 21-6 on page 137. 131 7598H-AVR-07/09 20.4.1 Store Program Memory Control and Status Register - SPMCSR The Store Program Memory Control and Status Register contains the control bits needed to control the Program memory operations. Bit 7 6 5 4 3 2 1 0 - - - CTPB RFLB PGWRT PGERS SPMEN Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPMCSR * Bits 7..5 - Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and always read as zero. * Bit 4 - CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost. * Bit 3 - RFLB: Read Fuse and Lock Bits An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See "EEPROM Write Prevents Writing to SPMCSR" on page 133 for details. * Bit 2 - PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation. * Bit 1 - PGERS: Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation. * Bit 0 - SPMEN: Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. Writing any other combination than "10001", "01001", "00101", "00011" or "00001" in the lower five bits will have no effect. 132 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 20.4.2 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. 20.4.3 Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with 0x0001 and set the RFLB and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the RFLB and SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register. The RFLB and SPMEN bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles. When RFLB and SPMEN are cleared, LPM will work as described in the Instruction set Manual. Bit 7 6 5 4 3 2 1 0 Rd - - - - - - LB2 LB1 The algorithm for reading the Fuse Low byte is similar to the one described above for reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the RFLB and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the RFLB and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be loaded in the destination register as shown below. Refer to Table 21-5 on page 136 for a detailed description and mapping of the Fuse Low byte. Bit 7 6 5 4 3 2 1 0 Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0 Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruction is executed within three cycles after the RFLB and SPMEN bits are set in the SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below. Refer to Table 21-4 for detailed description and mapping of the Fuse High byte. Bit 7 6 5 4 3 2 1 0 Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0 Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read as one. 20.4.4 Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. 133 7598H-AVR-07/09 Flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an external low VCC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 2. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCSR Register and thus the Flash from unintentional writes. 20.4.5 Programming Time for Flash when Using SPM The calibrated RC Oscillator is used to time Flash accesses. Table 20-1 shows the typical programming time for Flash accesses from the CPU. Table 20-1. SPM Programming Time Symbol Min Programming Time Max Programming Time Flash write (Page Erase, Page Write, and write Lock bits by SPM) 3.7 ms 4.5 ms 21. Memory Programming This section describes the different methods for Programming the ATtiny25/45/85 memories. 21.1 Program And Data Memory Lock Bits The ATtiny25/45/85 provides two Lock bits which can be left unprogrammed ("1") or can be programmed ("0") to obtain the additional security listed in Table 21-2. The Lock bits can only be erased to "1" with the Chip Erase command. Program memory can be read out via the debugWIRE interface when the DWEN fuse is programmed, even if the Lock Bits are set. Thus, when Lock Bit security is required, should always debugWIRE be disabled by clearing the DWEN fuse. Table 21-1. Lock Bit Byte() Lock Bit Byte Description Default Value 7 - 1 (unprogrammed) 6 - 1 (unprogrammed) 5 - 1 (unprogrammed) 4 - 1 (unprogrammed) 3 - 1 (unprogrammed) 2 - 1 (unprogrammed) LB2 1 Lock bit 1 (unprogrammed) LB1 0 Lock bit 1 (unprogrammed) Note: 134 Bit No 1. "1" means unprogrammed, "0" means programmed ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Table 21-2. Lock Bit Protection Modes(1)(2) Memory Lock Bits Protection Type LB Mode LB2 LB1 1 1 1 No memory lock features enabled. 0 Further programming of the Flash and EEPROM is disabled in High-voltage and Serial Programming mode. The Fuse bits are locked in both Serial and High-voltage Programming mode.(1) debugWire is disabled. 0 Further programming and verification of the Flash and EEPROM is disabled in High-voltage and Serial Programming mode. The Fuse bits are locked in both Serial and High-voltage Programming mode.(1) debugWire is disabled. 2 1 3 Notes: 0 1. Program the Fuse bits before programming the LB1 and LB2. 2. "1" means unprogrammed, "0" means programmed 21.2 Fuse Bytes The ATtiny25/45/85 has three Fuse bytes. Table 21-4, Table 21-5 and Table61 describe briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, "0", if they are programmed. Table 21-3. Fuse Extended Byte Fuse High Byte SELFPRGEN Table 21-4. Bit No Description Default Value 7 - 1 (unprogrammed) 6 - 1 (unprogrammed) 5 - 1 (unprogrammed) 4 - 1 (unprogrammed) 3 - 1 (unprogrammed) 2 - 1 (unprogrammed) 1 - 1 (unprogrammed) 0 Self-Programming Enable 1 (unprogrammed) Fuse High Byte Fuse High Byte Description Default Value 7 External Reset disable 1 (unprogrammed) DWEN(2) 6 DebugWIRE Enable 1 (unprogrammed) SPIEN(3) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog. enabled) WDTON(4) 4 Watchdog Timer always on 1 (unprogrammed) EESAVE 3 EEPROM memory is preserved through the Chip Erase 1 (unprogrammed, EEPROM not preserved) RSTDISBL (1) Bit No 135 7598H-AVR-07/09 Table 21-4. Fuse High Byte Fuse High Byte Description Default Value 2 Brown-out Detector trigger level 1 (unprogrammed) BODLEVEL1 1 Brown-out Detector trigger level 1 (unprogrammed) BODLEVEL0(5) 0 Brown-out Detector trigger level 1 (unprogrammed) (5) (5) BODLEVEL2 Notes: Bit No 1. See "Alternate Functions of Port B" on page 54 for description of RSTDISBL and DWEN Fuses. 2. DWEN must be unprogrammed when Lock Bit security is required. See "Program And Data Memory Lock Bits" on page 134. 3. The SPIEN Fuse is not accessible in SPI Programming mode. 4. See "Watchdog Timer Control Register - WDTCR" on page 42 for details. 5. See Table 8-2 on page 38 for BODLEVEL Fuse decoding. 6. When programming the RSTDISBL Fuse, High-voltage Serial programming has to be used to change fuses to perform further programming. Table 21-5. Fuse Low Byte Fuse Low Byte Description Default Value 7 Divide clock by 8 0 (unprogrammed) 6 Clock Output Enable 1 (unprogrammed) SUT1 5 Select start-up time 1 (unprogrammed)(3) SUT0 4 Select start-up time 0 (programmed)(3) CKSEL3 3 Select Clock source 0 (programmed)(4) CKSEL2 2 Select Clock source 0 (programmed)(4) CKSEL1 1 Select Clock source 1 (unprogrammed)(4) CKSEL0 0 Select Clock source 0 (programmed)(4) (1) (2) CKDIV8 CKOUT Notes: Bit No 1. See "System Clock Prescaler" on page 29 for details. 2. The CKOUT Fuse allows the system clock to be output on PORTB4. See "Clock Output Buffer" on page 30 for details. 3. The default value of SUT1..0 results in maximum start-up time for the default clock source. See Table 6-7 on page 26 for details. 4. The default setting of CKSEL1..0 results in internal RC Oscillator @ 8.0 MHz. See Table 6-6 on page 26 for details. The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits. 21.2.1 136 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 21.3 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and High-voltage Programming mode, also when the device is locked. The three bytes reside in a separate address space. 21.3.1 ATtiny25 Signature Bytes 1. 0x000: 0x1E (indicates manufactured by Atmel). 2. 0x001: 0x91 (indicates 2 KB Flash memory). 3. 0x002: 0x08 (indicates ATtiny25 device when 0x001 is 0x91). 21.3.2 ATtiny45 Signature Bytes 1. 0x000: 0x1E (indicates manufactured by Atmel). 2. 0x001: 0x92 (indicates 4 KB Flash memory). 3. 0x002: 0x06 (indicates ATtiny45 device when 0x001 is 0x92). 21.3.3 ATtiny85 Signature Bytes 1. 0x000: 0x1E (indicates manufactured by Atmel). 2. 0x001: 0x93 (indicates 8 KB Flash memory). 3. 0x002: 0x0B (indicates ATtiny85 device when 0x001 is 0x93). 21.4 Calibration Byte Signature area of the ATtiny25/45/85 has one byte of calibration data for the internal RC Oscillator. This byte resides in the high byte of address 0x000. During reset, this byte is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated RC Oscillator. 21.5 Page Size Table 21-6. Device No. of Words in a Page and No. of Pages in the Flash Flash Size Page Size PCWORD No. of Pages PCPAGE PCMSB ATtiny25 1K words (2K bytes) 16 words PC[3:0] 64 PC[9:4] 9 ATtiny45 2K words (4K bytes) 32 words PC[4:0] 64 PC[10:5] 10 ATtiny85 4K words (8K bytes) 32 words PC[4:0] 128 PC[11:5] 11 Table 21-7. No. of Words in a Page and No. of Pages in the EEPROM EEPROM Size Page Size PCWORD No. of Pages PCPAGE EEAMSB ATtiny25 128 bytes 4 bytes EEA[1:0] 32 EEA[6:2] 6 ATtiny45 256 bytes 4 bytes EEA[1:0] 64 EEA[7:2] 7 ATtiny85 512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8 Device 137 7598H-AVR-07/09 21.6 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 21-8 on page 138, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface. Figure 21-1. Serial Programming and Verify(1) +4.5 - 5.5V VCC MOSI MISO SCK RESET GND Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the CLKI pin. Table 21-8. Pin Mapping Serial Programming Symbol Pins I/O Description MOSI PB0 I Serial Data in MISO PB1 O Serial Data out SCK PB2 I Serial Clock When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF. Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz 21.6.1 Serial Programming Algorithm When writing serial data to the ATtiny25/45/85, data is clocked on the rising edge of SCK. When reading data from the ATtiny25/45/85, data is clocked on the falling edge of SCK. See Figure 21-2 and Figure 21-3 for timing details. 138 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 To program and verify the ATtiny25/45/85 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 21-10): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to "0". In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to "0". 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 5 LSB of the address and data together with the Load Program memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program memory Page is stored by loading the Write Program memory Page instruction with the 6 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 21-9.) Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. 5. A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling (RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 21-9.) In a chip erased device, no 0xFFs in the data file(s) need to be programmed. B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time by supplying the 2 LSB of the address and data together with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with the 6 MSB of the address. When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is not used, the used must wait at least tWD_EEPROM before issuing the next page (See Table 21-7). In a chip erased device, no 0xFF in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to "1". Turn VCC power off. 139 7598H-AVR-07/09 Table 21-9. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 4.0 ms tWD_ERASE 4.0 ms tWD_FUSE 4.5 ms Figure 21-2. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Table 21-10. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Operation Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. 0010 H000 0000 000a bbbb bbbb oooo oooo Read H (high or low) data o from Program memory at word address a:b. 0100 H000 000x xxxx xxxb bbbb iiii iiii Write H (high or low) data i to Program memory page at word address b. Data low byte must be loaded before Data high byte is applied within the same address. Write Program Memory Page 0100 1100 0000 000a bbxx xxxx xxxx xxxx Write Program memory Page at address a:b. Read EEPROM Memory 1010 0000 000x xxxx xxbb bbbb oooo oooo Read data o from EEPROM memory at address b. Write EEPROM Memory 1100 0000 000x xxxx xxbb bbbb iiii iiii Write data i to EEPROM memory at address b. Read Program Memory Load Program Memory Page 140 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Table 21-10. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Operation 1100 0001 0000 0000 0000 00bb iiii iiii Load data i to EEPROM memory page buffer. After data is loaded, program EEPROM page. 1100 0010 00xx xxxx xxbb bb00 xxxx xxxx 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits. "0" = programmed, "1" = unprogrammed. See Table 21-1 on page 134 for details. 1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits. Set bits = "0" to program Lock bits. See Table 21-1 on page 134 for details. 0011 0000 000x xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b. Write Fuse bits 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = "0" to program, "1" to unprogram. See Table 21-5 on page 136 for details. Write Fuse High bits 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = "0" to program, "1" to unprogram. See Table 21-4 on page 135 for details. 1010 1100 1010 0100 xxxx xxxx xxxx xxxi Set bits = "0" to program, "1" to unprogram. See Table 21-3 on page 135 for details. 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse bits. "0" = programmed, "1" = unprogrammed. See Table 21-5 on page 136 for details. 0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse High bits. "0" = pro-grammed, "1" = unprogrammed. See Table 21-4 on page 135 for details. 0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. "0" = pro-grammed, "1" = unprogrammed. See Table 21-3 on page 135 for details. 0011 1000 000x xxxx 0000 0000 oooo oooo 1111 0000 0000 0000 xxxx xxxx xxxx xxxo Load EEPROM Memory Page (page access) Write EEPROM Memory Page (page access) Read Lock bits Write Lock bits Read Signature Byte Write Extended Fuse Bits Read Fuse bits Read Fuse High bits Read Extended Fuse Bits Read Calibration Byte Poll RDY/BSY Note: Write EEPROM page at address b. Read Calibration Byte If o = "1", a programming operation is still busy. Wait until this bit returns to "0" before applying another command. a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don't care 141 7598H-AVR-07/09 21.6.2 Serial Programming Characteristics Figure 21-3. Serial Programming Timing MOSI tSHOX tOVSH SCK tSLSH tSHSL MISO tSLIV Table 21-11. Serial Programming Characteristics, TA = -40C to 125C, VCC = 2.7 - 5.5V (Unless Otherwise Noted) Symbol Parameter 1/tCLCL Oscillator Frequency (ATtiny25/45/85V) Oscillator Period (ATtiny25/45/85V) tCLCL 1/tCLCL Oscillator Period (ATtiny25/45/85L, VCC = 2.7 5.5V) tCLCL 0 Typ Max Units 4 MHz 250 0 ns 10 100 MHz ns Oscillator Frequency (ATtiny25/45/85, VCC = 4.5V 5.5V) 0 tCLCL Oscillator Period (ATtiny25/45/85, VCC = 4.5V - 5.5V) 50 ns tSHSL SCK Pulse Width High 2 tCLCL* ns tSLSH SCK Pulse Width Low 2 tCLCL* ns tOVSH MOSI Setup to SCK High tCLCL ns tSHOX MOSI Hold after SCK High 2 tCLCL ns 1/tCLCL Note: 21.7 Oscillator Frequency (ATtiny25/45/85L, VCC = 2.7 5.5V) Min 20 MHz 1. 2 tCLCL for fck < 12 MHz, 3 tCLCL for fck >= 12 MHz High-voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROM Data memory, Lock bits and Fuse bits in the ATtiny25/45/85. 142 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Figure 21-4. High-voltage Serial Programming Table 21-12. Pin Name Mapping Signal Name in High-voltage Serial Programming Mode Pin Name I/O Function SDI PB0 I Serial Data Input SII PB1 I Serial Instruction Input SDO PB2 O Serial Data Output SCI PB3 I Serial Clock Input (min. 220ns period) Table 21-13. High-voltage Serial Programming Characteristics TA = 25C 10%, VCC = 5.0V 10% (Unless otherwise noted) Symbol Parameter Min Typ Max Units tSHSL SCI (PB3) Pulse Width High 125 ns tSLSH SCI (PB3) Pulse Width Low 125 ns tIVSH SDI (PB0), SII (PB1) Valid to SCI (PB3) High 50 ns tSHIX SDI (PB0), SII (PB1) Hold after SCI (PB3) High 50 ns tSHOV SCI (PB3) High to SDO (PB2) Valid 16 ns tWLWH_PFB Wait after Instr. 3 for Write Fuse Bits 2.5 ms Table 21-14. Pin Values Used to Enter Programming Mode Pin Symbol Value SDI Prog_enable[0] 0 SII Prog_enable[1] 0 SDO Prog_enable[2] 0 143 7598H-AVR-07/09 21.8 High-voltage Serial Programming Algorithm Sequence To program and verify the ATtiny25/45/85 in the High-voltage Serial Programming mode, the following sequence is recommended (See instruction formats in Table 21-16): 21.8.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device in High-voltage Serial Programming mode: 1. Apply 4.5 - 5.5V between VCC and GND. 2. Set RESET pin to "0" and toggle SCI at least six times. 3. Set the Prog_enable pins listed in Table 21-14 to "000" and wait at least 100 ns. 4. Apply VHVRST - 5.5V to RESET. Keep the Prog_enable pins unchanged for at least tHVRST after the High-voltage has been applied to ensure the Prog_enable signature has been latched. 5. Shortly after latching the Prog_enable signature, the device will activly output data on the Prog_enable[2]/SDO pin, and the resulting drive contention may increase the power consumption. To minimize this drive contention, release the Prog_enable[2] pin after tHVRST has elapsed. 6. Wait at least 50 s before giving any serial instructions on SDI/SII. Table 21-15. High-voltage Reset Characteristics RESET Pin High-voltage Threshold Minimum High-voltage Period for Latching Prog_enable VCC VHVRST tHVRST 4.5V 11.5V 100 ns 5.5V 11.5V 100 ns Supply Voltage 21.8.2 Considerations for Efficient Programming The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered. * The command needs only be loaded once when writing or reading multiple memory locations. * Skip writing the data value 0xFF that is the contents of the entire EEPROM (unless the EESAVE Fuse is programmed) and Flash after a Chip Erase. * Address High byte needs only be loaded before programming or reading a new 256 word window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes reading. 21.8.3 Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits are not reset until the Program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are re-programmed. Note: 1. The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed. 1. Load command "Chip Erase" (see Table 21-16). 2. Wait after Instr. 3 until SDO goes high for the "Chip Erase" cycle to finish. 3. Load Command "No Operation". 144 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 21.8.4 Programming the Flash The Flash is organized in pages, see Table 21-10 on page 140. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: 1. Load Command "Write Flash" (see Table 21-16). 2. Load Flash Page Buffer. 3. Load Flash High Address and Program Page. Wait after Instr. 3 until SDO goes high for the "Page Programming" cycle to finish. 4. Repeat 2 through 3 until the entire Flash is programmed or until all data has been programmed. 5. End Page Programming by Loading Command "No Operation". When writing or reading serial data to the ATtiny25/45/85, data is clocked on the rising edge of the serial clock, see Figure 21-6, Figure 21-7 and Table 21-17 for details. Figure 21-5. Addressing the Flash which is Organized in Pages PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: INSTRUCTION WORD 00 01 02 PAGEEND Figure 21-6. High-voltage Serial Programming Waveforms SDI PB0 MSB LSB SII PB1 MSB LSB SDO PB2 SCI PB3 MSB 0 LSB 1 2 3 4 5 6 7 8 9 10 145 7598H-AVR-07/09 21.8.5 Programming the EEPROM The EEPROM is organized in pages, see Table 21-11 on page 142. When programming the EEPROM, the data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM Data memory is as follows (refer to Table 21-16): 1. Load Command "Write EEPROM". 2. Load EEPROM Page Buffer. 3. Program EEPROM Page. Wait after Instr. 2 until SDO goes high for the "Page Programming" cycle to finish. 4. Repeat 2 through 3 until the entire EEPROM is programmed or until all data has been programmed. 5. End Page Programming by Loading Command "No Operation". 21.8.6 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to Table 21-16): 1. Load Command "Read Flash". 2. Read Flash Low and High Bytes. The contents at the selected address are available at serial output SDO. 21.8.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to Table 21-16): 1. Load Command "Read EEPROM". 2. Read EEPROM Byte. The contents at the selected address are available at serial output SDO. 21.8.8 Programming and Reading the Fuse and Lock Bits The algorithms for programming and reading the Fuse Low/High bits and Lock bits are shown in Table 21-16. 21.8.9 Reading the Signature Bytes and Calibration Byte The algorithms for reading the Signature bytes and Calibration byte are shown in Table 21-16. 21.8.10 Power-off sequence Set SCI to "0". Set RESET to "1". Turn VCC power off. 146 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Table 21-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 Instruction Format Instruction Chip Erase Load "Write Flash" Command Load Flash Page Buffer Instr.1/5 Instr.2/6 Instr.3 SDI 0_1000_0000_00 0_0000_0000_00 0_0000_0000_00 SII 0_0100_1100_00 0_0110_0100_00 0_0110_1100_00 SDO x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx SDI 0_0001_0000_00 SII 0_0100_1100_00 SDI 0_ bbbb_bbbb _00 0_eeee_eeee_00 0_dddd_dddd_00 0_0000_0000_00 SII 0_0000_1100_00 0_0010_1100_00 0_0011_1100_00 0_0111_1101_00 SDO x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx SDI 0_0000_0000_00 SII 0_0111_1100_00 Load EEPROM Page Buffer Program EEPROM Page Write EEPROM Byte Load "Read EEPROM" Command Instr 5. 0_0000_000a_00 0_0000_0000_00 0_0000_0000_00 0_0001_1100_00 0_0110_0100_00 0_0110_1100_00 x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx 0_0000_0010_00 SII 0_0100_1100_00 Wait after Instr 3 until SDO goes high. Repeat Instr. 2 - 3 for each loaded Flash Page until the entire Flash or all data is programmed. Repeat Instr. 1 for a new 256 byte page. See Note 1. Enter Flash Read mode. SDO x_xxxx_xxxx_xx SDI 0_bbbb_bbbb_00 0_0000_000a_00 0_0000_0000_00 0_0000_0000_00 SII 0_0000_1100_00 0_0001_1100_00 0_0110_1000_00 0_0110_1100_00 x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx q_qqqq_qqqx_xx 0_0000_0000_00 0_0000_0000_00 SII 0_0111_1000_00 0_0111_1100_00 SDO x_xxxx_xxxx_xx p_pppp_pppx_xx SDI 0_0001_0001_00 SII 0_0100_1100_00 Enter EEPROM Programming mode. x_xxxx_xxxx_xx SDI 0_00bb_bbbb_00 0_eeee_eeee_00 0_0000_0000_00 0_0000_0000_00 SII 0_0000_1100_00 0_0010_1100_00 0_0110_1101_00 0_0110_1100_00 SDO x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx SDI 0_0000_0000_00 0_0000_0000_00 SII 0_0110_0100_00 0_0110_1100_00 x_xxxx_xxxx_xx x_xxxx_xxxx_xx SDI 0_00bb_bbbb_00 0_eeee_eeee_00 0_0000_0000_00 0_0000_0000_00 SII 0_0000_1100_00 0_0010_1100_00 0_0110_1101_00 0_0110_0100_00 SDO x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx SDI 0_0000_0000_00 SII 0_0110_1100_00 x_xxxx_xxxx_xx SDI 0_0000_0011_00 SII 0_0100_1100_00 Repeat Instr. 1 - 4 until the entire page buffer is filled or until all data within the page is filled. See Note 2. Wait after Instr. 2 until SDO goes high. Repeat Instr. 1 - 2 for each loaded EEPROM page until the entire EEPROM or all data is programmed. SDO SDO Repeat Instr. 1, 3 - 6 for each new address. Repeat Instr. 2 for a new 256 byte page. Instr 5 - 6. SDO SDO Repeat after Instr. 1 - 5 until the entire page buffer is filled or until all data within the page is filled. See Note 1. x_xxxx_xxxx_xx SDI Read Flash Low SDO and High Bytes SDI Load "Write EEPROM" Command Enter Flash Programming code. x_xxxx_xxxx_xx Load Flash High SDI Address and SII Program Page SDO Operation Remarks Wait after Instr.3 until SDO goes high for the Chip Erase cycle to finish. SDO SDO Load "Read Flash" Command Instr.4 Repeat Instr. 1 - 5 for each new address. Wait after Instr. 5 until SDO goes high. See Note 3. Instr. 5 Enter EEPROM Read mode. x_xxxx_xxxx_xx 147 7598H-AVR-07/09 Table 21-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 (Continued) Instruction Format Instruction SDI Read EEPROM SII Byte SDO Write Fuse Low Bits 0_bbbb_bbbb_00 0_aaaa_aaaa_00 0_0000_0000_00 0_0000_0000_00 0_0000_1100_00 0_0001_1100_00 0_0110_1000_00 0_0110_1100_00 x_xxxx_xxxx_xx x_xxxx_xxxx_xx q_qqqq_qqq0_00 0_A987_6543_00 0_0000_0000_00 0_0000_0000_00 SII 0_0100_1100_00 0_0010_1100_00 0_0110_0100_00 0_0110_1100_00 x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx 0_0100_0000_00 0_000F_EDCB_00 0_0000_0000_00 0_0000_0000_00 0_0100_1100_00 0_0010_1100_00 0_0111_0100_00 0_0111_1100_00 SDO x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx SDI 0_0010_0000_00 0_0000_0021_00 0_0000_0000_00 0_0000_0000_00 SII 0_0100_1100_00 0_0010_1100_00 0_0110_0100_00 0_0110_1100_00 x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx 0_0000_0100_00 0_0000_0000_00 0_0000_0000_00 0_0100_1100_00 0_0110_1000_00 0_0110_1100_00 x_xxxx_xxxx_xx x_xxxx_xxxx_xx A_9876_543x_xx 0_0000_0100_00 0_0000_0000_00 0_0000_0000_00 0_0100_1100_00 0_0111_1010_00 0_0111_1110_00 x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxFE_DCBx_xx SDI 0_0000_0100_00 0_0000_0000_00 0_0000_0000_00 SII 0_0100_1100_00 0_0111_1000_00 0_0111_1100_00 SDI Read Fuse High SII Bits SDO x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_x21x_xx 0_0000_00bb_00 0_0000_0000_00 0_0000_0000_00 SII 0_0100_1100_00 0_0000_1100_00 0_0110_1000_00 0_0110_1100_00 x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx q_qqqq_qqqx_xx 0_0000_1000_00 0_0000_0000_00 0_0000_0000_00 0_0000_0000_00 0_0100_1100_00 0_0000_1100_00 0_0111_1000_00 0_0111_1100_00 x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx p_pppp_pppx_xx 0_0000_0000_00 SII 0_0100_1100_00 SDO Wait after Instr. 4 until SDO goes high. Write A - 3 = "0" to program the Fuse bit. Wait after Instr. 4 until SDO goes high. Write F - B = "0" to program the Fuse bit. Wait after Instr. 4 until SDO goes high. Write 2 - 1 = "0" to program the Lock Bit. Reading 2, 1 = "0" means the Lock bit is programmed. 0_0000_1000_00 SDI Repeat Instr. 1, 3 - 4 for each new address. Repeat Instr. 2 for a new 256 byte page. Reading F - B = "0" means the Fuse bit is programmed. SDO SDO Operation Remarks Reading A - 3 = "0" means the Fuse bit is programmed. SDI SDI Read Calibration SII Byte SDO Load "No Operation" Command Instr.4 x_xxxx_xxxx_xx SDI Read Fuse Low SII Bits SDO Read Signature Bytes Instr.3 0_0100_0100_00 SDO Read Lock Bits Instr.2/6 SDI SDI Write Fuse High SII Bits SDO Write Lock Bits Instr.1/5 Repeats Instr 2 4 for each signature byte address. x_xxxx_xxxx_xx Note: a = address high bits, b = address low bits, d = data in high bits, e = data in low bits, p = data out high bits, q = data out low bits, x = don't care, 1 = Lock Bit1, 2 = Lock Bit2, 3 = CKSEL0 Fuse, 4 = CKSEL1 Fuse, 5 = SUT0 Fuse, 6 = SUT1 Fuse, 7 = CKDIV8, Fuse, 8 = WDTON Fuse, 9 = EESAVE Fuse, A = SPIEN Fuse, B = RSTDISBL Fuse, C = BODLEVEL0 Fuse, D= BODLEVEL1 Fuse, E = MONEN Fuse, F = SPMEN Fuse Notes: 1. For page sizes less than 256 words, parts of the address (bbbb_bbbb) will be parts of the page address. 2. For page sizes less than 256 bytes, parts of the address (bbbb_bbbb) will be parts of the page address. 3. The EEPROM is written page-wise. But only the bytes that are loaded into the page are actually written to the EEPROM. Page-wise EEPROM access is more efficient when multiple bytes are to be written to the same page. Note that auto-erase of EEPROM is not available in High-voltage Serial Programming, only in SPI Programming. 148 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 21.9 High-voltage Serial Programming Characteristics Figure 21-7. High-voltage Serial Programming Timing CC CK Table 21-17. High-voltage Serial Programming Characteristics TA = 25C 10%, VCC = 5.0V 10% (Unless otherwise noted) Symbol Parameter Min tSHSL SCI (PB3) Pulse Width High 110 ns tSLSH SCI (PB3) Pulse Width Low 110 ns tIVSH SDI (PB0), SII (PB1) Valid to SCI (PB3) High 50 ns tSHIX SDI (PB0), SII (PB1) Hold after SCI (PB3) High 50 ns tSHOV SCI (PB3) High to SDO (PB2) Valid 16 ns Wait after Instr. 3 for Write Fuse Bits 2.5 ms tWLWH_PFB Typ Max Units 149 7598H-AVR-07/09 22. Electrical Characteristics 22.1 Absolute Maximum Ratings* Operating Temperature.................................. -40C to +125C *NOTICE: Storage Temperature ..................................... -65C to +150C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum Operating Voltage ............................................ 6.0V DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins................................ 200.0 mA Table 22-1. DC Characteristics TA = -40C to 125C, VCC = 2.7V to 5.5V (unless otherwise noted)(1) . Max.(3) Units -0.5 0.3VCC V XTAL pin -0.5 0.1VCC V Input Low Voltage RESET pin -0.5 0.1VCC V VIH Input High-voltage Except RESET and XTAL pins 0.6VCC(3) VCC +0.5 V VIH1 Input High-voltage XTAL pin 0.9VCC(3) VCC +0.5 V VIH2 Input High-voltage RESET pin 0.9VCC(3) VCC +0.5 V 0.6 0.5 V V Symbol Parameter Condition VIL Input Low Voltage Except RESET and XTAL pins VIL1 Input Low Voltage VIL2 (4) Min.(2) Typ. VOL Output Low Voltage (Port B) except PB5 IOL = 8 mA, VCC = 5V IOL = 5 mA, VCC = 3V VOH Output High-voltage(5) (Port B) except PB5 IOH = -8 mA, VCC = 5V IOH = -5 mA, VCC = 3V VOL1 Output Low Voltage(4) PB5 IOL = 1 mA VOH1 Output High-voltage(5) PB5 IOH = -200A, VCC = 5V IIL Input Leakage Current I/O Pin except RESET Vcc = 5.5V, pin low (absolute value) 50 nA IIH Input Leakage Current I/O Pin except RESET Vcc = 5.5V, pin high (absolute value) 50 nA RRST Reset Pull-up Resistor 30 60 k Rpu I/O Pin Pull-up Resistor 20 50 k 150 4.1 2.3 V V 0.6 3.2 V V ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 DC Characteristics TA = -40C to 125C, VCC = 2.7V to 5.5V (unless otherwise noted)(1) . Table 22-1. Symbol Parameter Power Supply Current ICC(6) Power-down mode(7) Notes: Typ. Max.(3) Units Active 4MHz, VCC = 3V 1.25 3 mA Active 8MHz, VCC = 5V 5 10 mA Active 16MHz, VCC = 5V 10 15 mA Idle 4MHz, VCC = 3V 0.4 0.5 mA Idle 8MHz, VCC = 5V 1.2 2 mA Idle 16MHz, VCC = 5V 2.5 5 mA WDT enabled, VCC = 3V 5 30 A WDT disabled, VCC = 3V 2 24 A WDT enabled, VCC = 5V 9 50 A WDT disabled, VCC = 5V 3 36 A Condition Min.(2) 1. All DC Characteristics contained in this data sheet result from actual silicon characterization. 2. "Max" means the highest value where the pin is guaranteed to be read as low. 3. "Min" means the lowest value where the pin is guaranteed to be read as high. 4. Although each I/O port can sink more than the test conditions (8 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1] The sum of all IOL, for all ports, should not exceed 60 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 5. Although each I/O port can source more than the test conditions (8 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1] The sum of all IOH, for all ports, should not exceed 60 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 6. All I/O modules are turned off (PRR = 0xFF) for all ICC values. 7. Brown-Out Detection (BOD) disabled. 22.2 External Clock Drive Waveforms Figure 22-1. External Clock Drive Waveforms V IH1 V IL1 151 7598H-AVR-07/09 22.3 External Clock Drive Table 22-2. External Clock Drive(1). PRELIMINARY VCC = 4.5 5.5V VCC = 2.7 - 5.5V Min. Max. Min. Max. Units 0 8 0 16 MHz Symbol Parameter 1/tCLCL Clock Frequency tCLCL Clock Period 100 50 ns tCHCX High Time 40 20 ns tCLCX Low Time 40 20 ns tCLCH Rise Time 1.6 0.5 s tCHCL Fall Time 1.6 0.5 s tCLCL Change in period from one clock cycle to the next 2 2 % Note: 1. All DC Characteristics contained in this data sheet result from actual silicon characterization. Figure 22-2. Maximum Frequency vs. VCC 16 MHz 8 MHz Safe Operating Area 2.7V 152 4.5V 5.5V ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 22.4 ADC Characteristics - Preliminary Data ADC Characteristics, Single Ended Channels. -40C - 125C. (1). PRELIMINARY Table 22-3. Symbol Parameter Resolution Single Ended Conversion Max(1) Units 10 Bits LSB Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1 MHz 3 LSB Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz Noise Reduction Mode 1.5 LSB Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1 MHz Noise Reduction Mode 2.5 LSB Integral Non-linearity (INL) Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz 1 LSB Differential Non-linearity (DNL) Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz 0.5 LSB Gain Error Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz 2.5 LSB Offset Error Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz 1.5 LSB Conversion Time Free Running Conversion Analog Supply Voltage Input Voltage 13 VINT Internal Voltage Reference RAIN Analog Input Resistance 260 50 VCC - 0.3 1.1 100 kHz (3) VCC + 0.3 V VREF-50mV V 38.5 1.0 s 1000 (2) GND Input Bandwidth Note: Typ(1) 2 Clock Frequency VIN Min(1) Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz Absolute accuracy (Including INL, DNL, quantization error, gain and offset error) AVCC Condition kHz 1.2 V M 1. All DC Characteristics contained in this data sheet result from actual silicon characterization. 2. Minimum for AVCC is 2.7V. 3. Maximum for AVCC is 5.5V. 153 7598H-AVR-07/09 22.5 Calibrated RC Oscillator Accuracy Table 22-4. Calibration Accuracy of Internal RC Oscillator Factory Calibration User Calibration Frequency Vcc Temperature Calibration Accuracy 8.0 MHz 3V 25C 1% 7.3 - 8.1 MHz 2.7V - 5.5V -40C - +125C 14% 23. Typical Characteristics The data contained in this section is extracted from preliminary silicon characterization and will be updated upon final characterization. The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with railtorail output is used as clock source. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. 154 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 23.1 Active Supply Current Figure 23-1. Active Supply Current vs. Frequency (0.1 - 1.0 MHz) 0.040 5.5 V 0.035 5.0 V 0.030 4.5 V 4.0 V 0.025 0.020 3.3 V 2.7 V 0.015 0.010 0.005 0.000 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Fre que nc y (MHz ) Figure 23-2. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE S UP P LY CURRENT vs . FREQUENCY 1 - 20MHz 14 5.5 V 12 5.0 V ICC (mA) 10 4.5 V 8 4.0 V 6 3.3 V 4 2.7 V 2 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) 155 7598H-AVR-07/09 Figure 23-3. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) ACTIVE S UP P LY CURRENT vs . VC C INTERNAL RC OSCILLATOR, 128 KHz 0.25 125 85 25 -40 ICC(mA) 0.2 C C C C 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE S UP P LY CURRENT vs . VC C INTERNAL RC OSCILLATOR, 1 MHz 1.8 1.6 125 85 25 -40 1.4 ICC (mA) 1.2 C C C C 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 156 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Figure 23-5. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE S UP P LY CURRENT vs . V CC INTERNAL RC OSCILLATOR, 8 MHz 8 7 125 85 25 -40 ICC (mA) 6 C C C C 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 23.2 Idle Supply Current Figure 23-6. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE S UP P LY CURRENT vs . LOW FREQUENCY 0.1 - 1.0 MHz 0.25 5.5 V 0.2 5.0 V Idle (mA) 4.5 V 4.0 V 0.15 3.3 V 2.7 V 0.1 1.8 V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) 157 7598H-AVR-07/09 Figure 23-7. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE S UP P LY CURRENT vs . FREQUENCY 1 - 20MHz Idle (mA) 4 3.5 5.5 V 3 5.0 V 2.5 4.5 V 2 4.0 V 1.5 3.3 V 1 2.7 V 0.5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 23-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) IDLE S UP P LY CURRENT vs . VC C INTERNAL RC OSCILLATOR, 128 KHz 0.25 125 85 25 -40 0.2 C C C C ICC 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 158 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Figure 23-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) IDLE S UP P LY CURRENT vs . VC C INTERNAL RC OSCILLATOR, 1 MHz 0.6 0.5 Idle (mA) 0.4 125 85 25 -40 C C C C 125 85 25 -40 C C C C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE S UP P LY CURRENT vs . VC C INTERNAL RC OSCILLATOR, 8 MHz 2 1.8 Idle (mA) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 159 7598H-AVR-07/09 23.2.1 Using the Power Reduction Register The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See "Power Reduction Register" on page 33 for details. Table 23-1. PRR bit Additional Current Consumption for the different I/O modules (absolute values) Typical numbers VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRTIM1 43 uA 270 uA 1090 uA PRTIM0 5.0 uA 28 uA 116 uA PRUSI 4.0 uA 25 uA 102 uA PRADC 13 uA 84 uA 351 uA Table 23-2. Additional Current Consumption (percentage) in Active and Idle mode PRR bit Additional Current consumption compared to Active with external clock (see Figure 23-1 and Figure 23-2) Additional Current consumption compared to Idle with external clock (see Figure 23-6 and Figure 23-7) PRTIM1 17.3% 68.4 % PRTIM0 1.8 % 7.3 % PRUSI 1.6 % 6.4 % PRADC 5.4 % 21.4 % It is possible to calculate the typical current consumption based on the numbers from Table 2 for other VCC and frequency settings than listed in Table 1. 23.2.1.1 Example 1 Calculate the expected current consumption in idle mode with USI, TIMER0, and ADC enabled at VCC = 2.0V and F = 1MHz. From Table 23-2, third column, we see that we need to add 6.4% for the USI, 7.3% for the TIMER0 module, and 21.4% for the ADC module. Reading from Figure 23-9, we find that the idle current consumption is ~0,25mA at VCC = 3.0V and F = 1MHz. The total current consumption in idle mode with USI, TIMER0, and ADC enabled, gives: I CC total ( 0,25 )mA * ( 1 + 0,064 + 0,073 + 0,214 ) 0,337mA 160 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 23.3 Power-Down Supply Current Figure 23-11. Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) P OWER-DOWN S UP P LY CURRENT vs . VC C WATCHDOG TIMER DISABLED 4 125 C 3.5 3 ICC (uA) 2.5 2 1.5 1 85 C 0.5 -40 C 25 C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-12. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) P OWER-DOWN S UP P LY CURRENT vs . VC C WATCHDOG TIMER ENABLED 12 10 125 C -40 C 25 C 85 C ICC (uA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 161 7598H-AVR-07/09 23.4 Pin Pull-up Figure 23-13. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 1.8V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE Vcc = 1.8V 60 50 IOP (uA) 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 -40 25 85 2 125 C C C C V OP (V) Figure 23-14. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE Vcc = 2.7V 90 80 70 IOP (uA) 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 125 85 25 3 -40 C C C C V OP (V) 162 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Figure 23-15. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 5.0V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE Vcc = 5.0V 160 140 120 IOP (uA) 100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 125 C 85 C 25 C 5 -40 C V OP (V) Figure 23-16. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE Vcc = 1.8V 40 35 IRE S E T (uA) 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 125 85 25 2 -40 C C C C V RES ET (V) 163 7598H-AVR-07/09 Figure 23-17. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE Vcc = 2.7V 70 60 IRE S E T (uA) 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 125 85 25 -40 C C C C V RES ET (V) Figure 23-18. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 5.0V) RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE Vcc = 5.0V 140 120 IRE S E T (uA) 100 80 60 40 20 0 0 1 2 3 4 5 125 85 25 6 -40 C C C C V RES ET (V) 164 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 23.5 Pin Driver Strength Figure 23-19. I/O Pin Source Current vs. Output Voltage (VCC = 1.8V) I/O P IN S INK CURRENT vs . OUTP UT VOLTAGE V CC = 1.8V 12 -40 C 10 25 C 85 C 125 C IOL (mA) 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 V OL (V) Figure 23-20. I/O Pin Source Current vs. Output Voltage (VCC = 3V) I/O P IN OUTP UT VOLTAGE vs . S INK CURRENT Vc c = 3.0V 1.2 125 1 85 V OL (V) 0.8 25 0.6 -40 0.4 0.2 0 0 5 10 15 20 25 IOL (V) 165 7598H-AVR-07/09 Figure 23-21. I/O Pin Source Current vs. Output Voltage (VCC = 5V) I/O P IN OUTP UT VOLTAGE vs . S INK CURRENT Vc c = 5.0V 0.7 125 0.6 85 V OL (V) 0.5 25 -40 0.4 0.3 0.2 0.1 0 0 5 10 15 20 25 IOL (V) Figure 23-22. I/O Pin Sink Current vs. Output Voltage (VCC = 1.8V) I/O P IN S OURCE CURRENT vs . OUTP UT VOLTAGE V CC = 1.8V 9 8 25 C 7 IOH (mA) 6 -40 C 85 C 5 125 C 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 V OH (V) 166 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Figure 23-23. I/O Pin Sink Current vs. Output Voltage (VCC = 3V) I/O P IN OUTP UT VOLTAGE vs . S OURCE CURRENT Vc c = 3V 3.5 3 V OH (V 2.5 -40 25 85 125 2 1.5 1 0.5 0 0 5 10 15 20 25 IOH (mA) Figure 23-24. I/O Pin Sink Current vs. Output Voltage (VCC = 5.0V) I/O P IN OUTP UT VOLTAGE vs . S OURCE CURRENT Vc c = 5.0V 5.1 5 4.9 V OH (V) 4.8 4.7 4.6 -40 4.5 25 85 125 4.4 4.3 0 5 10 15 20 25 IOH (mA) 167 7598H-AVR-07/09 23.6 Pin Thresholds and Hysteresis Figure 23-25. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read As '1') I/O P IN INP UT THRES HOLD VOLTAGE vs . V CC VIH, IO PIN READ AS '1' -40 25 85 125 3 2.5 C C C C Thre s hold 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-26. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read As '0') I/O P IN INP UT THRES HOLD VOLTAGE vs . VC C VIL, IO PIN READ AS '0' 125 85 25 -40 2.5 C C C C Thre s hold 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 168 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Figure 23-27. I/O Pin Input Hysteresis vs. VCC I/O P IN INP UT HYS TERES IS 0.8 0.7 Thre s hold 0.6 0.5 0.4 -40 25 85 125 0.3 0.2 C C C C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-28. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read As '1') RES ET INP UT THRES HOLD VOLTAGE vs . V C C VIH, IO PIN READ AS '1' 125 85 25 -40 2.5 C C C C Thre s hold 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 169 7598H-AVR-07/09 Figure 23-29. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read As '0') RES ET INP UT THRES HOLD VOLTAGE vs . CVC VIL, IO PIN READ AS '0' 125 85 25 -40 C C C C 125 85 25 5.5 -40 C C C C 2.5 Thre s hold 2 1.5 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-30. Reset Input Pin Hysteresis vs. VCC RES ET INP UT THRES HOLD VOLTAGE vs . CC V VIH, IO PIN READ AS '1' 0.25 Thre s hold 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 V CC (V) 170 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 23.7 BOD Thresholds and Analog Comparator Offset Figure 23-31. BOD Thresholds vs. Temperature (BODLEVEL Is 4.3V) BOD THRES HOLDS vs . TEMP ERATURE BODLEVEL = 4.3V 4.4 4.35 Ris ing Thre s hold (V) 4.3 Falling 4.25 4.2 4.15 4.1 4.05 4 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Temperature (C) Figure 23-32. BOD Thresholds vs. Temperature (BODLEVEL Is 2.7V) BOD THRES HOLDS vs . TEMP ERATURE BODLEVEL = 2.7V 2.8 Ris ing Thre s hold (V) 2.75 2.7 Falling 2.65 2.6 2.55 2.5 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Temperature (C) 171 7598H-AVR-07/09 Figure 23-33. BOD Thresholds vs. Temperature (BODLEVEL Is 1.8V) BOD THRES HOLDS vs . TEMP ERATURE BODLEVEL at 1.8V 1.9 1.85 Thre s hold (V) Ris ing Vcc 1.8 Falling Vcc 1.75 1.7 1.65 1.6 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Temperature (C) 23.8 Internal Oscillator Speed Figure 23-34. Watchdog Oscillator Frequency vs. VCC) WATCHDOC OS CILLATOR FREQUENCY vs . V CC 0.118 0.116 -40 C 0.114 25 C FRC (MHz ) 0.112 0.11 0.108 85 C 0.106 0.104 125 C 0.102 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 172 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Figure 23-35. Watchdog Oscillator Frequency vs. Temperature WATCHDOG OS CILLATOR FREQUENCY vs . TEMP ERATURE 0.118 0.116 0.114 FRC (MHz ) 0.112 0.11 0.108 1.8 V 0.106 2.7 3.6 4.0 5.5 0.104 0.102 0.1 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 V V V V 100 110 120 Temperature Figure 23-36. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE 8.4 5.0 V 3.0 V 8.3 8.2 FRC (MHz ) 8.1 8 7.9 7.8 7.7 7.6 7.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature 173 7598H-AVR-07/09 Figure 23-37. Calibrated 8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8MHz RC OS CILLATOR FREQUENCY vs . OP ERATING VOLTAGE 8.4 125 C 8.3 85 C 8.2 FRC (MHz ) 8.1 25 C 8 7.9 7.8 -40 C 7.7 7.6 7.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-38. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE 14 125 85 25 -40 12 C C C C FRC (MHz ) 10 8 6 4 2 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL (X1) 174 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 23.9 Current Consumption of Peripheral Units Figure 23-39. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs . CVC 35 125 85 25 -40 30 ICC (uA) 25 C C C C 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-40. Analog Comparator Current vs. VCC ANALOG COMP ARATOR CURRENT vs . V CC AREF = AVcc 350 150 C 300 125 C 85 C ICC (uA) 250 200 25 C 150 100 50 -40 C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 V CC (V) 175 7598H-AVR-07/09 23.10 Current Consumption in Reset and Reset Pulse width Figure 23-41. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current through the Reset Pull-up) RES ET S UP P LY CURRENT vs . CVC 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 0.14 5.5 V 0.12 5.0 V ICC (mA) 0.1 4.5 V 4.0 V 0.08 3.3 V 0.06 2.7 V 0.04 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 23-42. Reset Supply Current vs. VCC (1 - 24 MHz, Excluding Current through the Reset Pull-up) RES ET S UP P LY CURRENT vs . V C C 1 - 20 MHz , EXCLUDING CURRENT THROUGH THE RESET PULLUP 2.5 5.5 V 5.0 V 2 ICC (mA) 4.5 V 1.5 4.0 V 1 3.3 V 0.5 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) 176 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Figure 23-43. Reset Pulse Width vs. VCC MINIMUM RES ET P ULS E WIDTH vs . VC C 2500 Puls e width (ns ) 2000 1500 1000 125 85 25 -40 500 C C C C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 23.11 Analog to Digital Converter Figure 23-44. Analog to Digital Converter Differential mode OFFSET vs. VCC Analog to Digital Converter - OFFS ET Diffe re ntia l Inputs , Vc c = 4V, Vre f = 4V 2 1.5 1 0.5 Diff x1 0 -0.5 -1 -1.5 Diff x20 -2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Te mpe ra ture 177 7598H-AVR-07/09 Figure 23-45. Analog to Digital Converter Single Endded mode OFFSET vs. VCC Analog to Digital Converter - OFFS ET Single Ended, Vcc = 4V, Vref = 4V 2.5 2 LSB 1.5 1 0.5 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature Figure 23-46. Analog to Digital Converter Differential mode GAIN vs. VCC Analog to Digital Converter - GAIN Differential Inputs , Vcc = 5V, Vref = 4V -1 -1.2 -1.4 -1.6 Diff x20 LSB -1.8 -2 -2.2 -2.4 -2.6 Diff x1 -2.8 -3 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature 178 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Figure 23-47. Analog to Digital Converter Single Endded mode GAIN vs. VCC Analog to Digital Converter - GAIN Single Ended, Vcc = 4V, Vref = 4V 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 -0.5 LSB -1 -1.5 -2 -2.5 Temperature Figure 23-48. Analog to Digital Converter Differential mode DNL vs. VCC Analog to Digital Converter - Differential Non Linearity DNL Differential Inputs , Vcc = 4V, Vref = 4V 1.2 Diff x20 1 LSB 0.8 0.6 0.4 Diff x1 0.2 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature 179 7598H-AVR-07/09 Figure 23-49. Analog to Digital Converter Single Endded mode DNL vs. VCC Analog to Digital Converter - Differential Non Linearity DNL Single Ended, Vcc = 4V, Vref = 4V 0.57 0.56 0.55 0.54 LSB 0.53 0.52 0.51 0.5 0.49 0.48 0.47 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature Figure 23-50. Analog to Digital Converter differential mode INL vs. VCC Analog to Digital Converter - Integral Non Linearity INL Differential Inputs , Vcc = 4V, Vref = 4V 1.8 1.6 Diff x20 1.4 LSB 1.2 1 0.8 0.6 Diff x1 0.4 0.2 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature 180 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Figure 23-51. Analog to Digital Converter Single Endded mode INL vs. VCC Analog to Digital Converter - Integral Non Linearity INL Single Ended, Vcc = 4V, Vref = 4V 0.72 0.7 LSB 0.68 0.66 0.64 0.62 0.6 0.58 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature 181 7598H-AVR-07/09 24. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x3F SREG I T H S V N Z C Page page 7 0x3E SPH - - - - - - - SP8 page 10 0x3D SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 10 0x3C Reserved 0x3B GIMSK - INT0 PCIE - - - - - page 59 0x3A GIFR - INTF0 PCIF - - - - - page 60 0x39 TIMSK - OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 - page 77 0x38 TIFR - OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 - page 77 0x37 SPMCSR - - - CTPB RFLB PGWRT PGERS SPMEN page 132 0x36 Reserved 0x35 MCUCR BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 page 31, page 54, page 59 0x34 MCUSR - - - - WDRF BORF EXTRF PORF page 40 0x33 TCCR0B FOC0A FOC0B - - WGM02 CS02 CS01 CS00 page 75 0x32 TCNT0 Timer/Counter0 0x31 OSCCAL Oscillator Calibration Register 0x30 TCCR1 0x2F TCNT1 Timer/Counter1 page 86 0x2E OCR1A Timer/Counter1 Output Compare Register A page 86 0x2D OCR1C Timer/Counter1 Output Compare Register C 0x2C GTCCR - - CTC1 PWM1A COM1A1 TSM PWM1B COM1B1 COM0A1 COM0A0 COM0B1 COM1A0 CS13 COM1B0 FOC1B page 76 page 26 CS12 CS11 CS10 page 84 page 87 FOC1A PSR1 PSR0 WGM01 WGM00 Timer/Counter1 Output Compare Register B page 80, page 85 0x2B OCR1B 0x2A TCCR0A 0x29 OCR0A Timer/Counter0 - Output Compare Register A 0x28 OCR0B Timer/Counter0 - Output Compare Register B 0x27 PLLCSR SM - - - - PCKE PLLE PLOCK page 89 0x26 CLKPR CLKPCE - - - CLKPS3 CLKPS2 CLKPS1 CLKPS0 page 29 0x25 DT1A DT1AH3 DT1AH2 DT1AH1 DT1AH0 DT1AL3 DT1AL2 DT1AL1 DT1AL0 page 95 0x24 DT1B DT1BH3 DT1BH2 DT1BH1 DT1BH0 DT1BL3 DT1BL2 DT1BL1 DT1BL0 page 95 0x23 DTPS1 - - - - - - DTPS11 DTPS10 page 94 WDTIE WDP3 WDCE WDE WDP2 WDP1 WDP0 page 42 PRTIM1 PRTIM0 PRUSI PRADC page 33 EEAR8 page 16 page 16 COM0B0 page 87 - 0x22 DWDR 0x21 WDTCR WDTIF 0x20 PRR - 0x1F EEARH 0x1E EEARL 0x1D EEDR 0x1C EECR 0x1B Reserved - 0x1A Reserved - 0x19 Reserved 0x18 PORTB - - PORTB5 0x17 DDRB - - 0x16 PINB - 0x15 PCMSK 0x14 DIDR0 page 76 page 77 DWDR[7:0] EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 page 72 page 129 EEAR2 EEAR1 EEAR0 EERIE EEMWE EEWE EERE page 16 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 58 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 page 58 - PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 58 - - PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 page 60 - - ADC0D ADC2D ADC3D ADC1D EIN1D AIN0D page 110, page 127 EEPROM Data Register - - EEPM1 EEPM0 page 16 - 0x13 GPIOR2 General Purpose I/O Register 2 0x12 GPIOR1 General Purpose I/O Register 1 0x11 GPIOR0 General Purpose I/O Register 0 0x10 USIBR USI Buffer Register 0x0F USIDR USI Data Register 0x0E USISR USICIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 page 104 0x0D USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC page 105 0x0C Reserved - 0x0B Reserved - 0x0A Reserved - 0x09 Reserved - Notes: page 104 page 103 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 182 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x08 ACSR ACD ACBG ACO ACI ACIE - ACIS1 ACIS0 page 108 0x07 ADMUX REFS1 REFS0 ADLAR REFS2 MUX3 MUX2 MUX1 MUX0 page 123 0x06 ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 124 0x05 ADCH ADC Data Register High Byte 0x04 ADCL ADC Data Register Low Byte 0x03 ADCSRB 0x02 Reserved - 0x01 Reserved - 0x00 Reserved - Notes: BIN ACME IPR - - page 126 page 126 ADTS2 ADTS1 ADTS0 page 108, page 126 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 183 7598H-AVR-07/09 25. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd Rd * Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd Rd * K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V 1 1 EOR Rd, Rr Exclusive OR Registers Rd Rd Rr Z,N,V 1 COM Rd One's Complement Rd 0xFF -Rd Z,C,N,V 1 NEG Rd Two's Complement Rd 0x00 -Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd Rd * (0xFF - K) Z,N,V 1 INC Rd Increment Rd Rd + 1 Z,N,V 1 DEC Rd Decrement Rd Rd -1 Z,N,V 1 TST Rd Test for Zero or Minus Rd Rd * Rd Z,N,V 1 CLR Rd Clear Register Rd Rd Rd Z,N,V 1 SER Rd Set Register Rd 0xFF None 1 BRANCH INSTRUCTIONS RJMP k IJMP Relative Jump PC PC + k + 1 None 2 Indirect Jump to (Z) PC Z None 2 Relative Subroutine Call PC PC + k + 1 None 3 ICALL Indirect Call to (Z) PC Z None 3 RET Subroutine Return PC STACK None 4 RETI Interrupt Return PC STACK I 4 RCALL k CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None CP Rd,Rr Compare Rd -Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd -Rr -C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd -K Z, N,V,C,H SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC PC + 2 or 3 None 1/2/3 1 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N V= 1) then PC PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) 0 None 2 LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1)Rd(n),CRd(7) Z,C,N,V 1 184 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 Mnemonics Operands Description Operation Flags #Clocks ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n)Rd(n+1),CRd(0) Z,C,N,V ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1 1 SWAP Rd Swap Nibbles Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) None 1 BSET s Flag Set SREG(s) 1 SREG(s) 1 BCLR s Flag Clear SREG(s) 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) T None 1 SEC Set Carry C 1 C 1 CLC Clear Carry C 0 C 1 SEN Set Negative Flag N 1 N 1 CLN Clear Negative Flag N 0 N 1 SEZ Set Zero Flag Z 1 Z 1 CLZ Clear Zero Flag Z 0 Z 1 SEI Global Interrupt Enable I 1 I 1 CLI Global Interrupt Disable I 0 I 1 SES Set Signed Test Flag S 1 S 1 CLS Clear Signed Test Flag S 0 S 1 SEV Set Twos Complement Overflow. V 1 V 1 1 CLV Clear Twos Complement Overflow V 0 V SET Set T in SREG T 1 T 1 CLT Clear T in SREG T 0 T 1 SEH CLH Set Half Carry Flag in SREG Clear Half Carry Flag in SREG H 1 H 0 H H 1 Rd Rr Rd+1:Rd Rr+1:Rr None 1 None 1 1 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word LDI Rd, K Load Immediate Rd K None LD Rd, X Load Indirect Rd (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd (X), X X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X X - 1, Rd (X) None 2 LD Rd, Y Load Indirect Rd (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd (Y), Y Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y Y - 1, Rd (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd (Y + q) None 2 LD Rd, Z Load Indirect Rd (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd (Z), Z Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z Z - 1, Rd (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd (k) None 2 ST X, Rr Store Indirect (X) Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X X - 1, (X) Rr None 2 ST Y, Rr Store Indirect (Y) Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) Rr, Y Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y Y - 1, (Y) Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) Rr None 2 ST Z, Rr Store Indirect (Z) Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) Rr, Z Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z Z - 1, (Z) Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None 2 STS k, Rr Store Direct to SRAM (k) Rr None 2 Load Program Memory R0 (Z) None 3 LPM Rd, Z Load Program Memory Rd (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd (Z), Z Z+1 None 3 Store Program Memory (z) R1:R0 None LPM SPM IN Rd, P In Port Rd P None 1 OUT P, Rr Out Port P Rr None 1 PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr. for WDR/Timer) For On-chip Debug Only None None 1 N/A 185 7598H-AVR-07/09 26. Ordering Information Power Supply Notes: Speed (MHz) Ordering Code Package Operation Range 2.7 - 5.5V (3) 8 - 16 ATtiny25/45/85-15ST ATtiny25/45/85-15ST1 ATtiny25/45/85-15SZ T5 Automotive (-40C to +85C) Automotive (-40C to +105C) Automotive (-40C to 125C) 2.7 - 5.5V 8 - 16(3) ATtiny25/45/85-15MT ATtiny25/45/85-15MT1 ATtiny25/45/85-15MZ PC Automotive (-40C to 85C) Automotive (-40C to +105C) Automotive (-40C to +125C) 1. Green and ROHS packaging 2. Tape and Reel with Dry-pack delivery. 3. For Speed vs. VCC,see Figure 22-2 on page 152. Package Type T5 T5 - 8-lead, 0.208" Body Width Plastic Gull Wing Small Outline Package PC PC - 20-lead, 4.0x4.0 mm Body, 0.50 mm Pitch Quad Flat No Lead Package (QFN) 186 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 27. Packaging Information 27.1 T5 187 7598H-AVR-07/09 27.2 188 PC ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 28. Document Revision History 28.1 Revision 7598H - 07/09 1. Absolute Maximum Ratings updated 28.2 Revision 7598G - 03/08 1. Modified See "Power Management and Sleep Modes" on page 31. 2. Modified See "MCU Control Register - MCUCR" on page 31. 3. Modified Active Clock Domains and Wake-up Sources in the Different Sleep Modes33. 4. Added "Limitations" on page 33. 5. Modified "Power Reduction Register" on page 33. 28.3 Revision 7598F - 11/07 1. Correction to ICC Active, Table 22-1 on page 150. 28.4 Revision 7598E - 03/07 1. POR updated, see Section 8.3 on page 36. 28.5 Revision 7598D - 02/07 1. Clarification of Power On Reset Specifications table, Table 8-1 on page 37. 2. Errata list updated. 3. Added QFN packages. 28.6 Revision 7598C - 09/06 1. Correction of package codification and drawings. 28.7 Revision 7598B - 08/06 1. Clarification of several TBD values 2. Addition of the Power On Reset specification 3. DC characteristics Limits completed after corner run characterization 4. Typical Characteristic curves produced 28.8 Changes from Revision 2535A-09/01 to Revision 7598A-04/06 1. Automotive grade created: Features: - Change voltage and temperature range (2.7V - 5.5V), (-40C, +125C) - Adapt Stand-by current to automotive temperature range Packages: - PDIP removed - Ordering info limited to Automotive versions (green only, dry pack) DC & AC parameters - Only PRELIMINARY values are produced. 189 7598H-AVR-07/09 29. Errata The revision letter in this section refers to the revision of the ATtiny25/45/85 device. 29.1 ATtiny25, Revision E 1. No known errata. Flash security improvements. 29.2 ATtiny45, Revision G 1. No known errata. Flash security improvements. 29.3 ATtiny85, Revision C 1. No known errata. Flash security improvements. 190 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 30. Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 2 Overview ................................................................................................... 2 2.1 Block Diagram ...................................................................................................3 2.2 Automotive Quality Grade .................................................................................4 2.3 Pin Descriptions .................................................................................................5 3 About Code Examples ............................................................................. 5 4 AVR CPU Core .......................................................................................... 5 5 6 4.1 Introduction ........................................................................................................5 4.2 Architectural Overview .......................................................................................6 4.3 ALU - Arithmetic Logic Unit ...............................................................................7 4.4 Status Register ..................................................................................................7 4.5 General Purpose Register File ..........................................................................9 4.6 Stack Pointer ...................................................................................................10 4.7 Instruction Execution Timing ...........................................................................11 4.8 Reset and Interrupt Handling ...........................................................................11 AVR ATtiny25/45/85 Memories ............................................................. 13 5.1 In-System Re-programmable Flash Program Memory ....................................13 5.2 SRAM Data Memory ........................................................................................14 5.3 EEPROM Data Memory ..................................................................................15 5.4 I/O Memory ......................................................................................................21 System Clock and Clock Options ......................................................... 21 6.1 Clock Systems and their Distribution ...............................................................21 6.2 Clock Sources .................................................................................................23 6.3 Default Clock Source .......................................................................................24 6.4 Crystal Oscillator .............................................................................................24 6.5 Low-frequency Crystal Oscillator .....................................................................25 6.6 Calibrated Internal RC Oscillator .....................................................................26 6.7 External Clock .................................................................................................27 6.8 128 kHz Internal Oscillator ..............................................................................28 6.9 Clock Output Buffer .........................................................................................29 6.10 System Clock Prescaler ..................................................................................29 191 7598H-AVR-07/09 7 8 9 Power Management and Sleep Modes ................................................. 31 7.1 MCU Control Register - MCUCR ....................................................................31 7.2 Idle Mode .........................................................................................................32 7.3 ADC Noise Reduction Mode ............................................................................32 7.4 Power-down Mode ...........................................................................................32 7.5 Limitations .......................................................................................................33 7.6 Power Reduction Register ...............................................................................33 7.7 Minimizing Power Consumption ......................................................................34 System Control and Reset .................................................................... 35 8.1 Resetting the AVR ...........................................................................................35 8.2 Reset Sources .................................................................................................35 8.3 Power-on Reset ...............................................................................................36 8.4 External Reset .................................................................................................37 8.5 Brown-out Detection ........................................................................................38 8.6 Watchdog Reset ..............................................................................................39 8.7 MCU Status Register - MCUSR ......................................................................40 8.8 Internal Voltage Reference ..............................................................................40 8.9 Watchdog Timer ..............................................................................................41 8.10 Timed Sequences for Changing the Configuration of the Watchdog Timer ....44 Interrupts ................................................................................................ 45 9.1 Interrupt Vectors in ATtiny25/45/85 .................................................................45 10 I/O Ports .................................................................................................. 46 10.1 Introduction ......................................................................................................46 10.2 Ports as General Digital I/O .............................................................................47 10.3 Alternate Port Functions ..................................................................................52 10.4 Register Description for I/O-Ports ....................................................................58 11 External Interrupts ................................................................................. 58 11.1 MCU Control Register - MCUCR ....................................................................59 11.2 General Interrupt Mask Register - GIMSK ......................................................59 11.3 General Interrupt Flag Register - GIFR ..........................................................60 11.4 Pin Change Mask Register - PCMSK .............................................................60 12 8-bit Timer/Counter0 with PWM ............................................................ 61 192 12.1 Overview ..........................................................................................................61 12.2 Timer/Counter Clock Sources .........................................................................62 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 12.3 Counter Unit ....................................................................................................62 12.4 Output Compare Unit .......................................................................................63 12.5 Compare Match Output Unit ............................................................................65 12.6 Modes of Operation .........................................................................................66 12.7 Timer/Counter Timing Diagrams .....................................................................70 12.8 8-bit Timer/Counter Register Description ........................................................72 13 Timer/Counter Prescaler ....................................................................... 78 13.1 Prescaler Reset ...............................................................................................78 13.2 External Clock Source .....................................................................................79 14 Counter and Compare Units ................................................................. 81 14.1 Timer/Counter1 ................................................................................................81 15 Dead Time Generator ............................................................................. 93 15.1 Timer/Counter1 Dead Time Prescaler register 1 - DTPS1 ..............................94 15.2 Timer/Counter1 Dead Time A - DT1A .............................................................95 15.3 Timer/Counter1 Dead Time B - DT1B .............................................................95 16 Universal Serial Interface - USI ............................................................ 96 16.1 Overview ..........................................................................................................96 16.2 Functional Descriptions ...................................................................................97 16.3 Alternative USI Usage ...................................................................................103 16.4 USI Register Descriptions .............................................................................103 17 Analog Comparator ............................................................................. 108 17.1 ADC Control and Status Register B - ADCSRB ...........................................108 17.2 Analog Comparator Control and Status Register - ACSR ............................108 17.3 Analog Comparator Multiplexed Input ...........................................................110 18 Analog to Digital Converter ................................................................ 111 18.1 Features ........................................................................................................111 18.2 Operation .......................................................................................................112 18.3 Starting a Conversion ....................................................................................113 18.4 Prescaling and Conversion Timing ................................................................114 18.5 Changing Channel or Reference Selection ...................................................117 18.6 ADC Noise Canceler .....................................................................................118 18.7 ADC Conversion Result .................................................................................121 19 debugWIRE On-chip Debug System .................................................. 128 19.1 Features ........................................................................................................128 193 7598H-AVR-07/09 19.2 Overview ........................................................................................................128 19.3 Physical Interface ..........................................................................................128 19.4 Software Break Points ...................................................................................129 19.5 Limitations of debugWIRE .............................................................................129 19.6 debugWIRE Related Register in I/O Memory ................................................129 20 Self-Programming the Flash ............................................................... 130 20.1 Performing Page Erase by SPM ....................................................................130 20.2 Filling the Temporary Buffer (Page Loading) .................................................130 20.3 Performing a Page Write ...............................................................................131 20.4 Addressing the Flash During Self-Programming ...........................................131 21 Memory Programming ......................................................................... 134 21.1 Program And Data Memory Lock Bits ...........................................................134 21.2 Fuse Bytes .....................................................................................................135 21.3 Signature Bytes .............................................................................................137 21.4 Calibration Byte .............................................................................................137 21.5 Page Size ......................................................................................................137 21.6 Serial Downloading ........................................................................................138 21.7 High-voltage Serial Programming ..................................................................142 21.8 High-voltage Serial Programming Algorithm Sequence ................................144 21.9 High-voltage Serial Programming Characteristics .........................................149 22 Electrical Characteristics .................................................................... 150 22.1 Absolute Maximum Ratings* .........................................................................150 22.2 External Clock Drive Waveforms ...................................................................151 22.3 External Clock Drive ......................................................................................152 22.4 ADC Characteristics - Preliminary Data ........................................................153 22.5 Calibrated RC Oscillator Accuracy ................................................................154 23 Typical Characteristics ........................................................................ 154 194 23.1 Active Supply Current ....................................................................................155 23.2 Idle Supply Current ........................................................................................157 23.3 Power-Down Supply Current .........................................................................161 23.4 Pin Pull-up .....................................................................................................162 23.5 Pin Driver Strength ........................................................................................165 23.6 Pin Thresholds and Hysteresis ......................................................................168 23.7 BOD Thresholds and Analog Comparator Offset ..........................................171 23.8 Internal Oscillator Speed ...............................................................................172 ATtiny25/45/85 7598H-AVR-07/09 ATtiny25/45/85 23.9 Current Consumption of Peripheral Units ......................................................175 23.10 Current Consumption in Reset and Reset Pulse width .................................176 23.11 Analog to Digital Converter ............................................................................177 24 Register Summary .............................................................................. 182 25 Instruction Set Summary .................................................................... 184 26 Ordering Information ........................................................................... 186 27 Packaging Information ........................................................................ 187 27.1 T5 ..................................................................................................................187 27.2 PC ..................................................................................................................188 28 Document Revision History ................................................................ 189 28.1 Revision 7598H - 07/09 .................................................................................189 28.2 Revision 7598G - 03/08 .................................................................................189 28.3 Revision 7598F - 11/07 .................................................................................189 28.4 Revision 7598E - 03/07 .................................................................................189 28.5 Revision 7598D - 02/07 .................................................................................189 28.6 Revision 7598C - 09/06 .................................................................................189 28.7 Revision 7598B - 08/06 .................................................................................189 28.8 Changes from Revision 2535A-09/01 to Revision 7598A-04/06 ...................189 29 Errata ..................................................................................................... 190 29.1 ATtiny25, Revision E .....................................................................................190 29.2 ATtiny45, Revision G .....................................................................................190 29.3 ATtiny85, Revision C .....................................................................................190 30 Table of Contents ................................................................................. 191 195 7598H-AVR-07/09 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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