Integrated Device Technology. Inc. FAST CMOS OCTAL D REGISTERS (3-STATE) ptsayzarcts74/ATiCT/DT - 2574T/ATICT IDT54/74FCT374T/AT/CTIDT - 2374T/AT/CT IDT54/74FCTS34T/AT/CT FEATURES: Common features: Low input and output leakage <1pA (max.) CMOS power levels True TTL input and output compatibility VOH = 3.3V (typ.) VOL = 0.3V (typ.) Meets or exceeds JEDEC standard 18 specifications Product available in Radiation Tolerant and Radiation Enhanced versions Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages Features for FCT374T/FCT534T/FCT574T: Std., A. C and D speed grades High drive outputs (-15mA IOH, 48mA IoL) Features for FCT2374T/FCT2574T: Std., A, and C speed grades Resistor outputs (-15mA IOH, 12mA loL Com.) (-12mA IOH, 12mA IoL Mil.) Reduced system switching noise DESCRIPTION The FCT374T/FCT2374T, FCT534T and FCT574T/ FCT2574T are 8-bit registers built using an advanced dual metal CMOS technology. These registers consist of eight D- type flip-flops with a buffered common clock and buffered 3- state output control. When the output enable (OE) input is LOW, the eight outputs are enabled. When the OE input is HIGH, the outputs are in the high-impedance state. input data meeting the set-up and hold time requirements of the D inputs is transferred to the Q outputs on the LOW-to- HIGH transition of the clock input. The FCT2374T and FCT2574T have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall times-reducing the need for external series terminating resistors. FCT2xxxT parts are plug-in replacements for FCTxxxT parts. FUNCTIONAL BLOCK DIAGRAM FCT374/FCT2374T AND FCT574/FCT2574T Do Di De Ds Da Ds De D7 cP | 4 $ + & ity $ ei cp D cp DP cp DP cp P cp P cp P cp P cp P a a aq a a a a a I i T y i Qo Qi Q2 Q3 Qa Qs Q6 Q7 2589 drw 31 FUNCTIONAL BLOCK DIAGRAM FCT534T Do O1 De Ds Da Ds De D7 cp | 7 mee ee eT Se. cp ? cp cp P cp P cp P cp? cp ? cP Q Q Q Q Q Q Q Q OE ; | | | | | | | | | , | , + | qT T | tT T to L Qo ai Oz Gs Qa Os 6 Qr 259 orw 92 The IDT logo is a registered trademark of Integrated Device Technolagy. Inc MILITARY AND COMMERCIAL TEMPERATURE RANGES JUNE 1996 1996 Integrated Device Technology, Inc 6.13 2569/6IDT54/74FCT374T/AT/CTIDT - 2374T/ATICT, IDT54/74FCTS34T/ATICT, IDTS4/74FCTS7AT/ATICT/DY - 2574T/AT/ICT FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS IDT54/74FCT374T oEC 1 Vec Qo[_j 2 Q? Do [7] 3 Dz o Oty] 4 De De al] s5 o Qs CI S Ds D3s(_] 8 Da Q3 [J Q4 GND 0 Cc Lt ' P 2569 drw 03 DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW TOP VIEW IDT54/74FCTS74T GEL] 1 Vcc Do (_] 2 Qo Di 3 Q De] 4 Qa D3s{-] 5 Qa Da [T] 6 Qa Ds(_] 7 Qs De] 8 Q D7 [_j 9 Q?7 GND] 1 CP 2569 drw 04 DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW IDT54/74FCT534T INDEX Sn & S656 oe] 1 Voc Qo (Lj 2 Q7 Dr Do [77] 3 y De Di 4 6 _ Ls Q6 Qi] 5 Qs as @2zLI6 sozo-8 15 Qs Ds De [| 7 Ds Ds [[] 8 Da Q3((] 9 Qa oanos GND J[} 10 [] cP 2569 dew Lec DIP/SOIC/QSOP/CERPACK TOP VIEW TOP VIEWIDTS4/74FCT374T/AT/CTIDT - 2374T/ATICT, IDTS4/74FCTS34T/ATICT, IDTS4/74FCTS74T/AT/CT/DT - 2574T/ATICT FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN DESCRIPTION D data Clock Pulse for the register. Enters data on 3-state 3-state Active LOW 3-state Enable 2569 tbl 01 FUNCTION TABLE) 534 374/574 Inputs Outputs Internal Outputs Internal Function OE cp DN Qn Qn NC Hi-Z LOAD REGISTER Itrerfjrrt Iereir|x x NNT =IINN|D NNIecINN ririzls se 233 Sire z mreirls NOTE: 2569 tbl 02 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care 2 = High Impedance NC = No Change T = LOW-to-HIGH transition ABSOLUTE MAXIMUM RATINGS") CAPACITANCE (Ta = +25C, f = 1.0MHz) Symbol Rating Commercial|_ Military | Unit] | Symbol| Parameter !)__| Conditions | Typ. | Max. | Unit Vrerm(2)| Terminal Voltage | -0.5 to +7.0 | -0.5to+7.0] V CIN Input VIN = 0V 6 10 pF with Respect to Capacitance GND Cour | Output vour=ov | 8 | 12 | pF Vrerm(3)! Terminal Voltage -0.5 to -0.5 to v Capacitance with Respect to Vec +0.5 Vcc +0.5 GND NOTE: 2569 ink 04 7 1. This parameter is measured at characterization but not tested. TA Operating Oto+70 | -55t0+125| c P Temperature Teas Temperature 55 to +125 | -65 to +135) C Under Bias TsTG Storage -55 to +125 | -65 to +150] C Temperature PT Power Dissipation 0.5 0.5 WwW lout DC Output -60 to +120 | -60 to +120 | mA Current NOTES: 2569 Ink 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- INGS may cause permanent damage to the device. Thisis a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. . Input and Vcc terminals only. . Outputs and I/O terminals only. wr 6.13 3IDT54/74FCT374T/ATICTIDT - 2374T/ATICT, IDTS4/74FCTSS4T/ATICT, IDTS4/74FCTS74T/ATICTIDT - 2574T/ATICT FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Fotlowing Conditions Apply Uniess Otherwise Specified: Commercial: TA = 0C to +70C, Vcc = 5.0V + 5%; Military: Ta= 55C to +125C, Vcc = 5.0V + 10% Symbol Parameter Test Conditions) Min. | Typ.2)| Max. | Unit Vin Input HIGH Level Guaranteed Logic HIGH Level 2.0 _ Vv VIL Input LOW Level Guaranteed Logic LOW Level _ _ 0.8 v WH Input HIGH Current(4) Vcc = Max. Vi=2.7V = _ +1 pA tte input LOW Current(4) Vi=0.5V _ +1 lozH High Impedance Output Current Vcc = Max. Vo=2.7V _ +1 pA loz (3-State Output pins)4) Vo = 0.5V _ +1 {I Input HIGH Current) Vcc = Max., Vi= Voc (Max.) +1 pA Vik Clamp Diode Voltage Vec = Min., in =18mMA _ -0.7 | -1.2 Vv Vi Input Hysteresis _ _ 200 _ mV lec Quiescent Power Supply Current | Vcc = Max., VIN = GND or Vcc _ 0.01 1 mA 2568 Ink OS OUTPUT DRIVE CHARACTERISTICS FOR FCT3741/5341/574T Symbol Parameter Test Conditions() Min. | Typ.2)| Max. | Unit VOH Output HIGH Voitage Vec = Min. lOH = 6mA MIL. 2.4 3.3 Vv Vin = VIH or Vit loH = -8mA COM. loH = -12mA MIL. 2.0 3.0 _ Vv lou = -15mA COMIL. Vor Output LOW Voltage Vcc = Min. lol = 32mA MIL. _ 0.3 0.5 v VIN = ViH Or VIL lo = 48mA COMLL. los Short Circuit Current Voc = Max., Vo = GND) -60 | -120 | -2254) mA 2569 Ink 06 OUTPUT DRIVE CHARACTERISTICS FOR FCT2374T/2574T Symbol Parameter Test Conditions") Min. | Typ.2| Max.| Unit topL Output LOW Current Vcc = SV, VIN= VinorViL, VouT= 1.58) 16 48 _ mA lOoDH Output HIGH Current Vec = 5V, VIN = Vin or Vit, VouT= 1.5V8) -16 | 48 _ mA VOH Output HIGH Voltage Vcc = Min. 1oH = -12mA MIL. 2.4 3.3 Vv Vin = Vin or VIL lon = -15mA COM'L. VoL Output LOW Voltage Vec = Min. lot = 12mA _ 0.3 0.50 Vv VIN = Vitor VIL NOTES: 2569 Ink 07 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Voc = 5.0V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test shouid not exceed one second. 4. The test limit for this parameter is t5yA at Ta = S5C. 6.13 4IDTS4/74FCT374T/AT/CTIOT - 2374T/ATICT, IDTS4/74FCTS34T/ATICT, IDTS4/7SFCTS74T/AT/CT/DT - 2574T/AT/CT FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions() Min. | Typ.2)| Max. | Unit Alcc Quiescent Power Supply Current | Vcc = Max. _ 0.5 2.0 mA TTL Inputs HIGH Vin = 3.4V(3) Icco Dynamic Power Supply Vcc = Max. VIN = Veco | FCTxxxT _ 0.15 | 0.25 | mA/ Current!4) Outputs Open Vin = GND MHz OE = GND FCT2xxxT | | 0.06 | 0.12 One Input Toggling 50% Duty Cycle Ic Total Power Supply Current( Vcc = Max. Vin = Veco | FCTxxxT 1.5 3.5 mA Outputs Open Vin = GND for = 10MHz FCT2xxxT | 0.6 2.2 50% Duty Cycle OE = GND ViN=3.4 | FCToxT | | 2.0 | 55 fi = SMHz Vin = GND 50% Duty Cycle FCT2xxxT 11 4.2 One Bit Toggling Vcc = Max. ViN = Voc | FCTxxxT 3.8 | 7.36) Outputs Open Vin = GND fcP = 10MHz FCT2xxxT | 1.5 | 4.00) 50% Duty Cycle OE = GND VIN=3.4 | FCTxxT | | 6.0 | 16.36) Eight Bits Toggling Vin = GND fi = 2.5MHz FCT2xxxT _ 3.8 | 13.06) 50% Duty Cycle NOTES: 2569 tbl OB 1. For conditions shown as Max. or Min., use appropriate value specifted under Etectrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Per TTL driven input (Vin = 3.4). All other inputs at Vcc or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the tcc formula. These limits are guaranteed but not tested. 6. Ic ={QuiESCENT + IINPUTS + IDYNAMIC Ic = Ice + Alcc DHNT + Ieco (ferv2 + fiNi) lec = Quiescent Current Alcc = Power Supply Current for a TTL High Input (Vin = 3.4V} Dx = Duty Cycle for TTL Inputs High Nt = Number of TTL Inputs at DH lecp = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fcp = Clack Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and ail frequencies are in megahertz. 6.13 5IDTS4/74FCT374T/ATICTIDT - 2374T/ATICT, IDTS4/74FCTS34T/ATICT, IDTSA/74FCTS74T/ATICTIDT - 2574 T/ATICT MILITARY AND COMMERCIAL TEMPERATURE RANGES FAST CMOS OCTAL D REGISTERS (3-STATE) SWITCHING CHARACTERISTICS OVER OPERATING RANGE FCT374T/S34T/574T FCT374AT/S34A T/S74AT FCT2374T/2574T FCT2374AT/2574AT Com'l. Mil. Com't. Mil. Symboi Parameter Conditions(t? Min. | Max. | Min?) | Max. | Min.@?| Max. | Min? | Max. | Unit {PLH Propagation Delay Ci = 5OpF 2.0 10.0 | 2.0 11.0 ] 2.0 6.5 2.0 7.2 ns tPHL CP to Qn) Rt = 5000 1PZH Output Enable Time 1.5 12.5 1.5 14.0 1.5 6.5 15 75 ns tPZL tPHZ Output Disable Time 1.5 8.0 1.5 8.0 1.5 5.5 1.5 6.5 ns {PLZ tsu Set-up Time HIGH 2.0 _ 2.0 _ 2.0 _ 2.0 _ ns or LOW, DN to CP tH Hold Time HIGH 1.5 _ 1.5 _ 1.5 _ 1.5 _ ns or LOW, DN to CP tw CP Pulse Width 7.0 _ 7.0 _ 5.0 _ 6.0 ~ ns HIGH or LOW 2569 tbl 09 FCT374CT/S34CT/S74CT FCT2374C1T/2574CT FCT374DT/574DT Com't. Mil. Com'l. Mil. Symbol Parameter Conditions Min.@) | Max. | Min.@) | Max. | Min.@) | Max. | Min.@) | Max. | Unit tPLH Propagation Delay Ci = 50pF 2.0 5.2 2.0 6.2 2.0 4.2 _ _ ns tPHL CP to Qn) Rt = 5002 tPZH Output Enable Time 1.5 5.5 1.5 6.2 15 48 _ _ ns tpzu tPHZ Output Disable Time 1.5 5.0 1.5 5.7 1.5 4.0 ns tPLZ tsu Set-up Time HIGH 2.0 2.0 _ 2.0 _ _ ns or LOW, DN to CP tH Hoid Time HIGH 1.5 _ 1.5 _ 1.0 _ _ _ ns or LOW, DN to GP tw CP Pulse Width 5.0 _ 6.0 _ 3.0 _- _ _ ns HIGH or LOW) NOTES: 2568 to! 10 1. See test circuit and waveforms. 2. Minimum fimits are guaranteed but not tested on Propagation Delays. 3. On for FCT374/2374T and FCTS74/2574T, On for FCTS34T. 4. This parameter is guaranteed but not tested. 6.13 6FAST CMOS Integrated Device Technology, Inc. OCTAL D FLIP-FLOP WITH CLOCK ENABLE IDTS4/74FCT377T/AT/CT/DT FEATURES: Std., A, C and D speed grades Low input and output leakage <1pA (max.} * CMOS power levels * True TTL input and output compatibility VOH = 3.3V (typ.) VOL = 0.3V (typ.) High drive outputs (-15mA IoH, 48mA ToL) Power off disable outputs permit live insertion Meets or exceeds JEDEC standard 18 specifications Product available in Radiation Tolerant and Radiation Enhanced versions Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Available in DIP, SOIC, QSOP, CERPACK and LCC packages DESCRIPTION: The IDT54/74FCT377T/AT/CT/DT are octal D flip-flops built using an advanced dual metal CMOS technology. The IDT54/ 74FCT377T/AT/CT/DT have eight edge-triggered, D-type flip- flops with individual D inputs and O outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flops O output. The CE input must be stable only one set-up time prior to the LOW-to-HIGH transi- tion for predictable operation. FUNCTIONAL BLOCK DIAGRAM Do 7 Da D3 | Nh > | DQ DQ DQ DQ Da DQ DQ DQ DCP DCP >CP DCP DCP Nera >CP No ep ee ee el et Oo Or 02 03 O4 Os a6 O7 2630 drw 01 The IDT logo 1s a registered trademark of integrated Device Technology, inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES JUNE 1996 6.14 2630/4 1996 Integrated Device Technology. Inc. 1IDTS4/74FCT374T/AT/CT/DT - 2374T/ATICT, IDTS4/74FCTS34T/ATICT, IDTS4/74FCTS74T/ATICT/DT - 2574T/ATICT FAST CMOS OCTAL D REGISTERS (3-STATE) ORDERING INFORMATION (DT XX Temp. Range FCT x Family XXXX x X Device Type Package Process so L E PY Q 374T 574T 534T 374AT 574AT 534AT 374CT 574CT 534CT 374DT 5740T | Blank {2 |54 |74 MILITARY AND COMMERCIAL TEMPERATURE RANGES Commercial MIL-STD-883, Class B Plastic DIP CERDIP Smail Outline iC Leadless Chip Carrier CERPACK Shrink Small Outline Package Quarter-size Small Outline Package Non-Inverting Octal D Register Non-inverting Octal D Register Inverting Octal D Register High Drive Balanced Drive ~55C to +125C OC to +70C 2569 drw 11 6.13