NC7SZ175L6X - Fairchild Semiconductor Corporation

May 1998

Revised August 2004

NC7SZ175 TinyLogic



UHS D-Type Flip-Flop wit h Async hronous Clear

NC7SZ175

TinyLogic UHS D-Type Flip-Flop

with Asynchronous Clear

General Description

The NC7SZ175 is a single positive edge-triggered D-type

CMOS Flip-Flop with Asynchronous Clear from Fairchild’s

Ultra High Speed Series of TinyLogic in the space saving

SC70 6-lead package. The device is fabricated with

advanced CMOS technology to achieve ultra high speed

with high output drive while maintaining low static power

dissipation over a very broad VCC operating range. The

device is spe cified to operate over the 1.6 5V to 5.5V VCC

range. The inputs and output are high impedance when

VCC is 0V. Inputs tolerate voltages up to 7V independent of

VCC operating voltage. This single flip-flop will store the

state of the D input that meets the setup and hold time

requirements on the LOW-to-HIGH Clock (CP) transition. A

LOW input to Clear sets the Q output to LOW level. The

Clear input is independent of clock.

Features

■Space saving SC70 6-lead package

■Ultra small MicroPak leadless packa ge

■Ultra High Speed; tPD 2.6 ns Typ into 50 pF at 5V VCC

■High Output Drive; ±24 mA at 3V VCC

■Broad VCC Operating Range; 1.65V to 5.5V

■Matches the performance of LCX when operated at

3.3V VCC

■Power down high impedance inputs/output

■Overvoltage tolerant inputs facilitate 5V to 3V translation

Ordering Code:

TinyLogic is a reg is t ered trademark of F airc hild Semiconduc t or Corpo ration.

MicroPak is a trad em ark of Fairchild Sem icond uc t or Corporation.

Order Package Product Code Package Description Supplied As

Number Number To p Mark

NC7SZ175P6X MAA06A Z75 6-Lead SC70, EIAJ SC88, 1.25mm Wide 3k Units on Tape and Reel

NC7SZ175L6X MAC06A C4 6-Lead MicroPak, 1.0mm Wide 5k Units on Tape and Reel

■Proprietary noise/EMI reduction circuitry implemented

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NC7SZ175

Logic Symbol

IEEE/IEC

Function Table

H = HIGH Logi c Level Qn = No change in dat a

L = LOW Logic Lev el X = Immaterial

Pin Descriptions

Connection Diagrams

Pin Assignments for SC70

(Top View)

Pin One Orientation Diagram

AAA represen t s P roduct Code Top Mark - see o rdering code

Note: Orientation of Top Mark determines Pin One location. Read the top

produc t co de mark lef t to right, Pin On e is th e lower lef t pi n (see dia gram).

Pad Assignments fo r MicroPak

(Top Thru View)

Inputs Output

CP D C Q



LH L



HH H



XHQn

XXL L

Pin Names Description

D Data Input

CP Clock Pulse Input

CClear Input

Q Flip-Flop Output

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NC7SZ175

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions (Note 2)

Note 1: The “Absolute Maximum Ratings”: are t hos e v alues bey ond whic h

the saf ety of the device cannot be gu aranteed. Th e device shou ld not be

operated at these limits. The parametric values defined in the Electrical

Char ac teri s t ics tables are not guarant eed at t he abs olute maxim um rati ngs.

The “R ecomm ended Ope rating Co ndition s” table will define the condit ions

for actu al device operation.

Note 2: Unused inputs must be held HIGH or LOW. They may not float.

DC Electrical Characteristics

Supply Voltage (VCC)−0.5V to +7.0V

DC In put Voltage (VIN)−0.5V to +7.0V

DC Output Voltage (VOUT)−0.5V to +7.0V

DC Input Diode Current (IIK)

VIN < 0V −50 mA

DC Output Diode Current (IOK)

VOUT < 0V −50 mA

DC Output (IOUT) Source/Sink Current ±50 mA

DC VCC/GND Current (ICC/IGND)±50 mA

Storage Temperature Range (TSTG)−65°C to +150°C

Junction Temperature under Bias (TJ)150°C

Junction Lead Temperature (TL)

(Soldering, 10 seconds) 260°C

Power D is sipation (PD) @+85°C180 mW

Power Supply

Operating (VCC) 1.65V to 5.5V

Data Retention 1.5V to 5.5V

Input Voltage (VIN) 0V to 5.5V

Output Voltage (VOUT)0V to V

Input Rise and Fall Time (tr, tf)

VCC = 1.8V, 2.5V ± 0.2V 0 to 20 ns/V

VCC = 3.3V ± 0.3V 0 to 10 ns/V

VCC = 5.5V ± 0.5V 0 to 5 ns/V

Operating Temperature (TA)−40°C to +85°C

Thermal Resistance (θJA) 350° C/W

Symbol Parameter VCC TA = +25°CT

A = −40°C to +85°CUnit Conditions

(V) Min Typ Max Min Max

VIH HIGH Level Control 1.65 to 1.95 0.75 VCC 0.75 VCC V

Input Voltage 2.3 to 5.5 0.7 VCC 0.7 VCC

VIL LOW Level Control 1.65 to 1.95 0.25 VCC 0.25 VCC V

Input Voltage 2.3 to 5.5 0.3 VCC 0.3 VCC

VOH HIGH Level Control 1.65 1.55 1.65 1.55

IOH = −100 µA

Output Voltage 1.8 1.7 1.8 1.7

2.3 2.2 2.3 2.2

3.0 2.9 3.0 2.9

4.5 4.4 4.5 4.4 VIN = VIH

1.65 1.24 1.52 1.29 or VIL IOH = −4 mA

2.3 1.9 2.15 1.9 IOH = −8 mA

3.0 2.4 2.8 2.4 IOH = −16 mA

3.0 2.3 2.68 2.3 IOH = −24 mA

4.5 3.8 4.2 3.8 IOH = −32 mA

VOL LOW Level Control 1.65 0.0 0.1 0.1

IOL = 100 µA

Output Voltage 1.8 0.0 0.1 0.1

2.3 0.0 0.1 0.1

3.0 0.0 0.1 0.1

4.5 0.0 0.1 0.1 VIN = VIL

1.65 0.08 0.24 0.24 or VIH IOL = 4 mA

2.3 0.10 0.3 0.3 IOL = 8 mA

3.0 0.15 0.4 0.4 IOL = 16 mA

3.0 0.22 0.55 0.55 IOL = 24 mA

4.5 0.22 0.55 0.55 IOL = 32 mA

IIN Input Leakage Current 0 to 5.5 ±0.1 ±1.0 µA0 ≤ VIN ≤ 5.5V

IOFF Power Off Leakage Current 0.0 1.0 10 µAV

IN or VOUT = 5.5V

ICC Quiescent Supply Current 1.65 to 5.5 1.0 10.0 µAV

IN = 5.5V, GND

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NC7SZ175

AC Electrical Characteristics

Capacitance (Note 3)

Note 3: TA = +25C, f = 1MHz.

Note 4: CPD is defined as the value of th e internal equivalent c apacita nc e which is deriv ed from dy namic operat ing current con su m pt ion (ICCD) at no output

loading and operating at 50% duty cycle. (See Figure 2)

CPD is related to ICCD dynam ic operatin g c urrent by the expres s ion: ICCD = (CPD)(VCC)(fIN) + (ICCstatic).

Symbol Parameter VCC TA = +25°CT

A = −40°C to +85°CUnits Conditions Figure

(V) Min Typ Max Min Max Number

fMAX Maximum Clock 1.65 100

MHz Figures

1, 4

Frequency 1.8 100

2.5 ± 0.2 125 CL = 50 pF

3.3 ± 0.3 150 RL = 500 Ω

5.0 ± 0.5 175

tPLH Propagation Delay 1.65 2.5 9.8 15.0 2.5 16.5

Figures

1, 3

tPHL CP to Q 1.8 2.5 6.5 10.0 2.5 11.0

2.5 ± 0.2 2.0 3.8 6.5 2.0 7.0 CL = 15 pF

3.3 ± 0.3 1.5 2.8 4.5 1.4 5.0 RL = 1 MΩ

5.0 ± 0.5 1.0 2.2 3.5 1.0 3.8

3.3 ± 0.3 2.0 3.4 5.5 1.6 6.2 CL = 50 pF Figures

1, 3

5.0 ± 0.5 1.5 2.6 4.0 1.4 4.7 RL = 500 Ω

tPHL Propagation Delay 1.65 2.5 9.8 13.5 2.5 15.0

Figures

1, 3

C to Q 1.8 2.5 6.5 9.0 2.5 10.0

2.5 ± 0.2 2.0 3.8 6.0 2.0 6.4 CL = 15 pF

3.3 ± 0.3 1.5 2.8 4.3 1.2 4.6 RL = 1 MΩ

5.0 ± 0.5 1.5 2.2 3.2 1.0 3.5

3.3 ± 0.3 1.5 3.4 5.3 1.5 5.8 CL = 50 pF Figures

1, 3

5.0 ± 0.5 1.0 2.7 4.0 1.2 4.5 RL = 500 Ω

tSSetup Time 2.5 ± 0.2 2.5 ns CL = 50 pF Figures

1, 4

CP to D 3.3 ± 0.3 2.0 RL = 500 Ω

5.0 ± 0.5 1.5

tHHold Time, 2.5 ± 0.2 1.5 ns CL = 50 pF Figures

1, 4

CP to D 3.3 ± 0.3 1.5 RL = 500 Ω

5.0 ± 0.5 1.5

tWPulse Width, CP 2.5 ± 0.2 3.0 CL = 50 pF Figures

1, 4

3.3 ± 0.3 2.8 ns RL = 500 Ω

5.0 ± 0.5 2.5

Pulse Width, C 2.5 ± 0.2 3.0 Clock HIGH or LOW Figures

1, 4

3.3 ± 0.3 2.8 ns CL = 50 pF

5.0 ± 0.5 2.5 RL = 500 Ω

trec Recovery Time, 2.5 ± 0.2 1.0 CL = 50 pF Figures

1, 4

C to CP 3.3 ± 0.3 1.0 ns RL = 500 Ω

5.0 ± 0.5 1.0

Symbol Parameter Typ Max Units Conditions

CIN Input Capacitance 3 pF VCC = Open, VIN = 0V or VCC

COUT Output Capacitance 4 pF VCC = 3.3V, VIN = 0V or VCC

CPD Power Dissipation Capacitance 10 pF VCC = 3.3V

(Note 4) 12 VCC = 5.0V

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NC7SZ175

AC Loading and Waveforms

CL include s l oad and str ay c apacitan ce

Input PRR = 1.0 MHz, t w = 500 ns

FIGURE 1. AC Test Circuit

CP Input = AC Waveform; tr = tf = 1.8 ns;

CP Input PRR = 10 MHz; Duty Cycle = 50%

D Input PRR = 5MHz; Duty Cycle = 50 %

FIGURE 2. ICCD Test Circuit

FIGURE 3. AC Waveforms

FIGURE 4. AC Waveforms

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NC7SZ175

Tape and Reel Specification

TAPE FORMAT for SC70

TAPE DIMENSIONS inches (millimeters)

Package Tape Number Cavity Cover Tape

Designator Section Cavities Status Status

Leader (St art E nd) 125 (typ) E mp ty Sea l ed

P6X Carrier 3000 Filled Sealed

Trailer (Hub End) 75 (typ) Empty Sealed

Package Tape Size DIM A DIM B DIM F DIM KoDIM P1 DIM W

SC70-6 8 mm 0.093 0.096 0.138 ± 0.004 0.053 ± 0.004 0.157 0.315 ± 0.004

(2.35) (2.45) (3.5 ± 0.10) ( 1.35 ± 0.1 0) (4) (8 ± 0.1)

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NC7SZ175

Tape and Reel Specifi cation (Continu ed)

TAPE FORMAT for MicroPak

REEL DIMENSIONS inches (millimeters)

Package Tape Number Cavity Cover Tape

Designator Section Cavities Status Status

Leader (Start End) 125 (typ) Empty Sealed

L6X Carrier 5000 Filled Sealed

Trailer (Hub End) 75 (typ) E m pty Se al ed

Tape

Size ABCDN W1 W2 W3

8 mm 7.0 0.059 0.512 0.795 2.165 0.331 + 0.059/−0.000 0.567 W1 + 0.078/−0.039

(177.8) (1.50) (13.00) (20.20) (55.00) (8.40 + 1.50/−0.00) (14.40) (W1 + 2.00/−1.00)

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NC7SZ175

Physical Dimensions inches (millimeters) unless otherwise noted

6-Lead SC70, EIAJ SC88, 1.25mm Wide

Package Number MAA06A

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NC7SZ175 TinyLogic



UHS D-Type Flip-Flop wit h Async hronous Clear

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

6-Lead Micr oPak, 1.0mm Wide

Package Number MAC06A

Fairchild does not assume an y responsibility fo r use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life sup por t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A crit ical com ponen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife suppor t

device or system, or to affect its safety or effectiveness.