CMOS 300 MSPS Complete DDS
AD9852
Rev. D
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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FEATURES
300 MHz internal clock rate
FSK, BPSK, PSK, chirp, AM operation
Dual integrated 12-bit D/A converters
Ultrahigh speed comparator, 3 ps rms jitter
Excellent dynamic performance:
80 dB SFDR at 100 MHz (±1 MHz) AOUT
4× to 20× programmable reference clock multiplier
Dual 48-bit programmable frequency registers
Dual 14-bit programmable phase offset registers
12-bit programmable amplitude modulation and shaped
on/off keying function
Single-pin FSK and BPSK data interfaces
PSK capability via I/O interface
Linear or nonlinear FM chirp functions with single pin
frequency HOLD function
Frequency ramped FSK
<25 ps rms total jitter in clock generator mode
Automatic bidirectional frequency sweeping
SIN(x)/x correction
Simplified control interface
10 MHz serial 2-wire or 3-wire SPI®-compatible, or
100 MHz parallel 8-bit programming
3.3 V single supply
Multiple power-down functions
Single-ended or differential input reference clock
Small 80-lead LQFP packaging
APPLICATIONS
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
Test and measurement equipment
Commercial and amateur RF exciter
FUNCTIONAL BLOCK DIAGRAM
DIGITAL MULTIPLIERS
SYSTEM
CLOCK
DAC R
SET
INV.
SINC
FILTER
FREQUENCY
ACCUMULATOR
ACC 1
I/O PORT BUFFERS
COMPARATOR
PROGRAMMING REGISTERS
4× TO 20×
REFCLK
MULTIPLIER
DIFF/SINGLE
SELECT
REFERENCE
CLOCK IN
FSK/BPSK/HOLD
DATA IN
BIDIRECTIONAL
INTERNAL/EXTERNA
L
I/O UPDATE CLOCK
READ WRITE SERIAL/
PARALLEL
SELECT
6-BIT ADDRESS
OR SERIAL
PROGRAMMING
LINES
8-BIT
PARALLEL
LOAD
MASTER
RESET
+V
S
GND
CLOCK
OUT
ANALOG
IN
OSK
ANALOG
OUT
ANALOG
OUT
INTERNAL
PROGRAMMABLE
UPDATE CLOCK
PHASE-TO-
AMPLITUDE
CONVERTER
PROGRAMMABLE
AMPLITUDE AND
RATE CONTROL
DQ
CLK ÷2
INT
EXT
SYSTEM
CLOCK
REFCLK
BUFFER
SYSTEM
CLOCK
MUX
DELTA
FREQUENCY
RATE TIMER
SYSTEM
CLOCK
DELTA
FREQUENCY
WORD
FREQUENCY
TUNING
WORD 1
FREQUENCY
TUNING
WORD 2
FIRST 14-BIT
PHASE/OFFSET
WORD
SECOND 14-BIT
PHASE/OFFSET
WORD
AM
MODULATION 12-BIT DC
CONTROL
MUX
SYSTEM CLOCK
PHASE
ACCUMULATOR
ACC 2
DDS CORE 12-BIT
COSINE
DAC
12-BIT
CONTROL
DAC
I
Q
12
MUX MUX
MUX
MUX
SYSTEM
CLOCK
SYSTEM
CLOCK
48 48 48 14 14
BUS
12
12
12
14
17
17
4848
48
AD9852
MODE SELECT
2
3
DEMUX
00634-001
Figure 1.
AD9852
Rev. D | Page 2 of 52
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description......................................................................... 4
Overview........................................................................................ 4
Specifications..................................................................................... 5
Absolute Maximum Ratings............................................................ 9
Explanation of Test Levels........................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 13
Typical Applications....................................................................... 17
Modes of Operation ....................................................................... 19
Single-Tone (Mode 000) ............................................................ 19
Unramped FSK (Mode 001)...................................................... 20
Ramped FSK (Mode 010).......................................................... 20
Chirp (Mode 011)....................................................................... 23
BPSK (Mode 100) ....................................................................... 26
Using the AD9852 .......................................................................... 28
Internal and External Update Clock........................................ 28
On/Off Output Shaped Keying (OSK) .................................... 28
Cosine DAC ................................................................................ 30
Control DAC ............................................................................... 30
Inverse Sinc Function ................................................................ 30
REFCLK Multiplier.................................................................... 30
High Speed Comparator............................................................ 31
Power-Down ............................................................................... 31
Programming the AD9852............................................................ 32
MASTER RESET ........................................................................ 32
Parallel I/O Operation ............................................................... 32
Serial Port I/O Operation.......................................................... 32
General Operation of the Serial Interface ................................... 35
Instruction Byte.......................................................................... 35
Serial Interface Port Pin Descriptions..................................... 36
MSB/LSB Transfers .................................................................... 36
Control Register Descriptions .................................................. 37
Power Dissipation and Thermal Considerations ....................... 39
Thermal Impedance................................................................... 39
Junction Temperature Considerations .................................... 39
Evaluation of Operating Conditions............................................ 41
Thermally Enhanced Package Mounting Guidelines............ 41
Evaluation Board ............................................................................ 43
Evaluation Board Instructions.................................................. 43
General Operating Instructions ............................................... 43
Using the Provided Software .................................................... 45
Outline Dimensions ....................................................................... 52
Ordering Guide .......................................................................... 52
AD9852
Rev. D | Page 3 of 52
REVISION HISTORY
12/05—Rev. C to Rev. D
Updated Format..................................................................Universal
Changes to General Description .....................................................4
Changes to Explanation of Test Levels Section .............................9
Change to Pin Configuration ........................................................10
Changes to Figure 65 ......................................................................47
Changes to Outline Dimensions ...................................................52
Changes to Ordering Guide...........................................................52
4/04—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Figure 1...........................................................................1
Changes to General Description .....................................................3
Changes to Table 1 ............................................................................4
Changes to Footnote 2 ......................................................................6
Changes to Figure 2...........................................................................8
Changes to Table 5 ..........................................................................17
Changes to Equation in Ramped FSK (Mode 010).....................19
Changes to Evaluation Board Instructions..................................39
Changes to General Operating Instructions Section..................39
Changes to Using the Provided Software Section.......................42
Changes to Figure 65 ......................................................................43
Changes to Figure 66 ......................................................................44
Changes to Figure 72 and Figure 73 .............................................48
Changes to Ordering Guide...........................................................48
3/02—Rev. A to Rev. B
Changes to General Description.....................................................1
Changes to Functional Block Diagram ..........................................1
Changes to Specifications ................................................................3
Changes to Absolute Maximum Ratings........................................5
Changes to Pin Function Descriptions ..........................................6
Changes to Figure 3 ..........................................................................8
Deleted Two TPCs ..........................................................................11
Changes to Figure 18 and Figure 19 .............................................11
Changes to BPDK Mode Section ..................................................21
Changes to Differential Refclk Enable Section ...........................24
Changes to Master Reset Section ..................................................24
Changes to Parallel I/O Operation Section .................................24
Changes to General Operation of the Serial
Interface Section..............................................................................27
Changes to Figure 50 ......................................................................27
Changes to Figure 65 ......................................................................36
AD9852
Rev. D | Page 4 of 52
GENERAL DESCRIPTION
The AD9852 digital synthesizer is a highly integrated device
that uses advanced DDS technology, coupled with an internal
high speed, high performance D/A converter to form a digitally
programmable agile synthesizer function. When referenced to
an accurate clock source, the AD9852 generates a highly stable
frequency-, phase-, and amplitude-programmable cosine output
that can be used as an agile LO in communications, radar, and
many other applications. The AD9852’s innovative high speed
DDS core provides 48-bit frequency resolution (1 µHz tuning
resolution with 300 MHz SYSCLK). Maintaining 17 bits ensures
excellent SFDR.
The AD9852’s circuit architecture allows the generation of
output signals at frequencies up to 150 MHz, which can be
digitally tuned at a rate of up to 100 million new frequencies
per second. The (externally filtered) cosine wave output can be
converted to a square wave by the internal comparator for agile
clock generator applications. The device provides two 14-bit
phase registers and a single pin for BPSK operation. For high
order PSK operation, the I/O interface can be used for phase
changes. The 12-bit cosine DAC, coupled with the innovative
DDS architecture, provides excellent wideband and narrow-
band output SFDR. When configured with the comparator, the
12-bit control DAC facilitates static duty cycle control in the
high speed clock generator applications. The 12-bit digital
multiplier permits programmable amplitude modulation,
shaped on/off keying, and precise amplitude control of the
cosine DAC output. Chirp functionality is also included for
wide bandwidth frequency sweeping applications. The
AD9852’s programmable 4× to 20× REFCLK multiplier cir-
cuit generates the 300 MHz system clock internally from a
lower frequency external reference clock.
This saves the user the expense and difficulty of implementing a
300 MHz system clock source. Direct 300 MHz clocking is also
accommodated with either single-ended or differential inputs.
Single-pin, conventional FSK and the enhanced spectral
qualities of ramped FSK are supported. The AD9852 uses
advanced 0.35 CMOS technology to provide this high level of
functionality on a single 3.3 V supply.
The AD9852 is available in a space-saving 80-lead LQFP surface-
mount package and a thermally enhanced 80-lead LQFP package.
The AD9852 is pin-for-pin compatible with the AD9854 single-
tone synthesizer. The AD9852 is specified to operate over the
extended industrial temperature range of −40°C to +85°C.
OVERVIEW
The AD9852 digital synthesizer is a highly flexible device that
addresses a wide range of applications. The device consists of
an NCO with a 48-bit phase accumulator, a programmable
reference clock multiplier, an inverse sinc filter, a digital
multiplier, two 12-bit/300 MHz DACs, a high speed analog
comparator, and an interface logic. This highly integrated
device can be configured to serve as a synthesized LO agile
clock generator and FSK/BPSK modulator. The theory of
operation for the functional blocks of the device and a technical
description of the signal flow through a DDS device is provided
by Analog Devices in the tutorial “A Te chnical Tutorial on
Digital Signal Synthesis.” The tutorial also provides basic
applications information for a variety of digital synthesis
implementations.
AD9852
Rev. D | Page 5 of 52
SPECIFICATIONS
VS = 3.3 V ± 5%, RSET = 3.9 kΩ, external reference clock frequency = 30 MHz with REFCLK multiplier enabled at 10× for AD9852ASQ,
external reference clock frequency = 20 MHz with REFCLK multiplier enabled at 10× for AD9852AST, unless otherwise noted.
Table 1.
AD9852ASQ AD9852AST
Parameter Temp
Test
Level Min Typ Max Min Typ Max Unit
REF CLOCK INPUT CHARACTERISTICS1
Internal System Clock Frequency Range
REFCLK Multiplier Enabled Full VI 20 300 20 200 MHz
REFCLK Multiplier Disabled Full VI DC 300 DC 200 MHz
External REF Clock Frequency Range
REFCLK Multiplier Enabled Full VI 5 75 5 50 MHz
REFCLK Multiplier Disabled Full VI DC 300 DC 200 MHz
Duty Cycle 25°C IV 45 50 55 45 50 55 %
Input Capacitance 25°C IV 3 3 pF
Input Impedance 25°C IV 100 100 kΩ
Differential Common-Mode Voltage Range
Minimum Signal Amplitude2 25°C IV 400 400 mV p-p
Common-Mode Range 25°C IV 1.6 1.75 1.9 1.6 1.75 1.9 V
VIH (Single-Ended Mode) 25°C IV 2.3 2.3 V
VIL (Single-Ended Mode) 25°C IV 1 1 V
DAC STATIC OUTPUT CHARACTERISTICS
Output Update Speed Full I 300 200 MSPS
Resolution 25°C IV 12 12 Bits
Cosine and Control DAC Full-Scale Output Current 25°C IV 5 10 20 5 10 20 mA
Gain Error 25°C I −6 +2.25 −6 +2.25 % FS
Output Offset 25°C I 2 2 μA
Differential Nonlinearity 25°C I 0.3 1.25 0.3 1.25 LSB
Integral Nonlinearity 25°C I 0.6 1.66 0.6 1.66 LSB
Output Impedance 25°C IV 100 100 kΩ
Voltage Compliance Range 25°C I −0.5 +1.0 −0.5 +1.0 V
DAC DYNAMIC OUTPUT CHARACTERISTICS
DAC Wideband SFDR
1 MHz to 20 MHz AOUT 25°C V 58 58 dBc
20 MHz to 40 MHz AOUT 25°C V 56 56 dBc
40 MHz to 60 MHz AOUT 25°C V 52 52 dBc
60 MHz to 80 MHz AOUT 25°C V 48 48 dBc
80 MHz to 100 MHz AOUT 25°C V 48 48 dBc
100 MHz to 120 MHz AOUT 25°C V 48 dBc
DAC Narrow-Band SFDR
10 MHz AOUT (±1 MHz) 25°C V 83 83 dBc
10 MHz AOUT (±250 kHz) 25°C V 83 83 dBc
10 MHz AOUT (±50 kHz) 25°C V 91 91 dBc
41 MHz AOUT (±1 MHz) 25°C V 82 82 dBc
41 MHz AOUT (±250 kHz) 25°C V 84 84 dBc
41 MHz AOUT (±50 kHz) 25°C V 89 89 dBc
119 MHz AOUT (±1 MHz) 25°C V 71 dBc
119 MHz AOUT (±250 kHz) 25°C V 77 dBc
119 MHz AOUT (±50 kHz) 25°C V 83 dBc
AD9852
Rev. D | Page 6 of 52
AD9852ASQ AD9852AST
Parameter Temp
Test
Level Min Typ Max Min Typ Max Unit
Residual Phase Noise
(AOUT = 5 MHz, External CLK = 30 MHz, REFCLK
Multiplier Engaged at 10×)
1 kHz Offset 25°C V 140 140 dBc/Hz
10 kHz Offset 25°C V 138 138 dBc/Hz
100 kHz Offset 25°C V 142 142 dBc/Hz
(AOUT = 5 MHz, External CLK = 300 MHz, REFCLK
Multiplier Bypassed)
1 kHz Offset 25°C V 142 142 dBc/Hz
0 kHz Offset 25°C V 148 148 dBc/Hz
100 kHz Offset 25°C V 152 152 dBc/Hz
PIPELINE DELAYS3 , 4, 5
DDS Core (Phase Accumulator and Phase-to-Amp
Converter)
25°C IV 33 33 SYSCLK
cycles
Frequency Accumulator 25°C IV 26 26 SYSCLK
cycles
Inverse Sinc Filter 25°C IV 16 16 SYSCLK
cycles
Digital Multiplier 25°C IV 9 9 SYSCLK
cycles
DAC 25°C IV 1 1 SYSCLK
cycles
I/O Update Clock (Internal Mode) 25°C IV 2 2 SYSCLK
cycles
I/O Update Clock (External Mode) 25°C IV 3 3 SYSCLK
cycles
MASTER RESET DURATION 25°C IV 10 10 SYSCLK
cycles
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance 25°C V 3 3 pF
Input Resistance 25°C IV 500 500 kΩ
Input Current 25°C I ± 1 ± 5 ± 1 ± 5 μA
Hysteresis 25°C IV 10 20 10 20 mV p-p
COMPARATOR OUTPUT CHARACTERISTICS
Logic 1 Voltage, High Z Load Full VI 3.1 3.1 V
Logic 0 Voltage, High Z Load Full VI 0.16 0.16 V
Output Power, 50 Ω Load, 120 MHz Toggle Rate 25°C I 9 11 9 11 dBm
Propagation Delay 25°C IV 3 3 ns
Output Duty Cycle Error6 25°C I −10 ± 1 +10 −10 ± 1 +10 %
Rise/Fall Time, 5 pF Load 25°C V 2 2 ns
Toggle Rate, High Z Load 25°C IV 300 350 300 350 MHz
Toggle Rate, 50 Ω Load 25°C IV 375 400 375 400 MHz
Output Cycle-to-Cycle Jitter7 25°C IV 4.0 4.0 ps rms
AD9852
Rev. D | Page 7 of 52
AD9852ASQ AD9852AST
Parameter Temp
Test
Level Min Typ Max Min Typ Max Unit
COMPARATOR NARROW-BAND SFDR8
10 MHz (±1 MHz) 25°C V 84 84 dBc
10 MHz (±250 MHz) 25°C V 84 84 dBc
10 MHz (±50 kHz) 25°C V 92 92 dBc
41 MHz (±1 MHz) 25°C V 76 76 dBc
41 MHz (±250 kHz) 25°C V 82 82 dBc
41 MHz (±50 kHz) 25°C V 89 89 dBc
119 MHz (±1 MHz) 25°C V 73 dBc
119 MHz (±250 kHz) 25°C V 73 dBc
119 MHz (±50 kHz) 25°C V 83 dBc
CLOCK GENERATOR OUTPUT JITTER8
5 MHz AOUT 25°C V 23 23 ps rms
40 MHz AOUT 25°C V 12 12 ps rms
100 MHz AOUT 25°C V 7 7 ps rms
PARALLEL I/O TIMING CHARACTERISTICS
TASU (Address Setup Time to WR Signal Active) Full IV 8.0 7.5 8.0 7.5 ns
TADHW (Address Hold Time to WR Signal Inactive) Full IV 0 0 ns
TDSU (Data Setup Time to WR Signal Inactive) Full IV 3.0 1.6 3.0 1.6 ns
TDHD (Data Hold Time to WR Signal Inactive) Full IV 0 0 ns
TWRLOW (WR Signal Minimum Low Time) Full IV 2.5 1.8 2.5 1.8 ns
TWRHIGH (WR Signal Minimum High Time) Full IV 7 7 ns
TWR (Minimum WR Time) Full IV 10.5 10.5 ns
TADV (Address-to-Data Valid Time) Full V 15 15 15 15 ns
TADHR (Address Hold Time to RD Signal Inactive) Full IV 5 5 ns
TRDLOV (RD Low-to-Output Valid) Full IV 15 15 ns
TRDHOZ (RD High-to-Data Three-State) Full IV 10 10 ns
SERIAL I/O TIMING CHARACTERISTICS
TPRE (CS Setup Time) Full IV 30 30 ns
TSCLK (Period of Serial Data Clock) Full IV 100 100 ns
TDSU (Serial Data Setup Time) Full IV 30 30 ns
TSCLKPWH (Serial Data Clock Pulse Width High) Full IV 40 40 ns
TSCLKPWL (Serial Data Clock Pulse Width Low) Full IV 40 40 ns
TDHLD (Serial Data Hold Time) Full IV 0 0 ns
TDV (Data Valid Time) Full V 30 30 ns
CMOS LOGIC INPUTS 9
Logic 1 Voltage 25°C I 2.2 2.2 V
Logic 0 Voltage 25°C I 0.8 0.8 V
Logic 1 Current 25°C IV ± 5 ± 12 μA
Logic 0 Current 25°C IV ± 5 ± 12 μA
Input Capacitance 25°C V 3 3 pF
AD9852
Rev. D | Page 8 of 52
AD9852ASQ AD9852AST
Parameter Temp
Test
Level Min Typ Max Min Typ Max Unit
POWER SUPPLY10
+VS Current11 25°C I 815 922 585 660 mA
+VS Current12 25°C I 640 725 465 520 mA
+VS Current13 25°C I 585 660 425 475 mA
PDISS 11 25°C I 2.70 3.20 1.93 2.39 W
PDISS 12 25°C I 2.12 2.52 1.53 1.81 W
PDISS 13 25°C I 1.93 2.29 1.40 1.65 W
PDISS Power-Down Mode 25°C I 1 50 1 50 mW
1 The reference clock inputs are configured to accept a 1 V p-p (typical) dc offset square or sine waves centered at one-half the applied VDD or a 3 V TTL-level pulse input.
2 An internal 400 mV p-p differential voltage swing equates to 200 mV p-p applied to both REFCLK input pins.
3 Pipeline delays of each individual block are fixed; however, if the eight top MSBs of a tuning word are all zeros, the delay appears longer. This is due to insufficient
phase accumulation per a system clock period to produce enough LSB amplitude to the D/A converter.
4 If a feature such as inverse sinc, which has 16 pipeline delays, can be bypassed, the total delay is reduced by that amount.
5 The I/O UD CLK transfers data from the I/O port buffers to the programming registers. This transfer is measured in system clocks.
6 A change in duty cycle from 1 MHz to 100 MHz with 1 V p-p sine wave input and 0.5 V threshold.
7 Represents the comparator’s inherent cycle-to-cycle jitter contribution. Input signal is a 1 V, 40 MHz square wave. Measurement device is the Wavecrest DTS-2075.
8 Comparator input originates from analog output section via external 7-pole elliptic LPF. Single-ended input, 0.5 V p-p. Comparator output terminated in 50 Ω.
9 Avoid overdriving digital inputs. (Refer to equivalent circuits in Figure 3.)
10 Simultaneous operation at the maximum ambient temperature of 85°C and at the maximum internal clock frequency of 200 MHz for the 80-lead LQFP, or 300 MHz for
the thermally enhanced 80-lead LQFP, can cause the maximum die junction temperature of 150°C to be exceeded. Refer to the Power Dissipation and Thermal
Considerations section for derating and thermal management information.
11 All functions engaged.
12 All functions except inverse sinc engaged.
13 All functions except inverse sinc and digital multipliers engaged.
AD9852
Rev. D | Page 9 of 52
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Maximum Junction Temperature 150°C
VS 4 V
Digital Inputs −0.7 V to +VS
Digital Output Current 5 mA
Storage Temperature −65°C to +150°C
Operating Temperature −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Maximum Clock Frequency (ASQ) 300 MHz
Maximum Clock Frequency (AST) 200 MHz
θJA (ASQ) 16°C/W
θJC (ASQ) 2°C/W
θJA (AST) 38°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
Table 3.
Test Level Description
I 100% production tested.
III Sample tested only.
IV Parameter is guaranteed by design and
characterization testing.
V Parameter is a typical value only.
VI Devices are 100% production tested at 25°C and
guaranteed by design and characterization testing
for industrial operating temperature range.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD9852
Rev. D | Page 10 of 52
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
2
D6
3
D5
4
D4
7
D1
6
D2
5
D3
1
D7
8
D0
9
DVDD
10
DVDD
12
DGND
13
NC
14
A5
15
A4
16
A3
17
A2/IO RESET
18
A1/SDO
19
A0/SDIO
20
I/O UD CLK
11
DGND
59
58
57
54
55
56
60
53
52
AGND
NC
NC
AVDD
DACBP
DAC R
SET
AVDD
AGND
IOUT2
51
IOUT2
49
IOUT1
48
IOUT1
47
AGND
46
AGND
45
AGND
44
AVDD
43
VINN
42
VINP
41
AGND
50
AVDD
NC = NO CONNECT
21
WR/SCLK
22
RD/CS
23
DVDD
24
DVDD
25
DVDD
26
DGND
27
DGND
28
DGND
29
FSK/BPSK/HOLD
30
OSK
31
AVDD
32
AVDD
33
AGND
34
AGND
35
NC
36
VOUT
37
AVDD
38
AVDD
39
AGND
40
AGND
80
DVDD
79
DVDD
78
DGND
77
DGND
76
DGND
75
DGND
74
DVDD
73
DVDD
72
DGND
71
MASTER RESET
70
S/P SELECT
69
REFCLK
68
REFCLK
67
AGND
66
AGND
65
AVDD
64
DIFF CLK ENABLE
63
NC
62
AGND
61
PLL FILTER
PIN 1
AD9852
TOP VIEW
(Not to Scale)
00634-002
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin Number Mnemonic Description
1 to 8 D7 to D0 8-Bit Bidirectional Parallel Programming Data Inputs. Used only in parallel programming mode.
9, 10, 23, 24, 25, 73, 74,
79, 80
DVDD Connections for the Digital Circuitry Supply Voltage. Nominally 3.3 V, and more positive than
AGND and DGND.
11, 12, 26, 27, 28, 72,
75 to 78
DGND Connections for Digital Circuitry Ground Return. Same potential as AGND.
13, 35, 57, 58, 63 NC No Internal Connection.
14 to 16 A5 to A3 Parallel Address Inputs for Program Registers (Part of 6-Bit Parallel Address Inputs for Program
Register, A5:A0). Used only in parallel programming mode.
17 A2/IO RESET
Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program
Register, A5:A0)/IO Reset. A2 is used only in parallel programming mode. IO RESET is used when
the serial programming mode is selected, allowing an IO RESET of the serial communication bus
that is unresponsive due to improper programming protocol. Resetting the serial bus in this
manner does not affect previous programming, nor does it invoke the default programming
values seen in Table 8. Active high.
18 A1/SDO Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program
Register, A5:A0)/Unidirectional Serial Data Output. A1 is used only in parallel programming
mode. SDO is used in 3-wire serial communication mode when the serial programming mode is
selected.
AD9852
Rev. D | Page 11 of 52
Pin Number Mnemonic Description
19 A0/SDIO Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program
Register, A5:A0)/Bidirectional Serial Data Input/Output. A0 is used only in parallel programming
mode. SDIO is used in 2-wire serial communication mode.
20 I/O UD CLK Bidirectional I/O Update Clock. Direction is selected in control register. If selected as an input, a
rising edge transfers the contents of the I/O port buffers to the programming registers. If I/O UD
CLK is selected as an output (default), an output pulse (low to high) with a duration of eight
system clock cycles indicates that an internal frequency update has occurred.
21 WR/SCLK Write Parallel Data to I/O Port Buffers. Shared function with SCLK. Serial clock signal associated
with the serial programming bus. Data is registered on the rising edge. This pin is shared with
WR when the parallel mode is selected. Mode dependent on Pin 70 (S/P SELECT).
22 RD/CS Read Parallel Data from Programming Registers. Shared function with CS. Chip select signal
associated with the serial programming bus. Active low. This pin is shared with RD when the
parallel mode is selected.
29 FSK/BPSK/HOLD
Multifunction Pin. Functions according to the mode of operation selected in the programming
control register. If in the FSK mode, logic low selects F1, logic high selects F2. If in the BPSK
mode, logic low selects Phase 1, logic high selects Phase 2. In chirp mode, logic high engages
the HOLD function, causing the frequency accumulator to halt at its current location. To resume
or commence chirp, logic low is asserted.
30 OSK
Output Shaped Keying. Must first be selected in the programming control register to function.
A logic high causes the cosine DAC outputs to ramp up from zero-scale to full-scale amplitude
at a preprogrammed rate. Logic low causes the full-scale output to ramp down to zero scale at
the preprogrammed rate.
31, 32, 37, 38, 44, 50, 54,
60, 65
AVDD Connections for the Analog Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND
and DGND.
33, 34, 39, 40, 41, 45, 46,
47, 53, 59, 62, 66, 67
AGND Connections for Analog Circuitry Ground Return. Same potential as DGND.
36 VOUT Internal High Speed Comparator’s Noninverted Output Pin. Designed to drive 10 dBm to 50 Ω
loads as well as standard CMOS logic levels.
42 VINP Voltage Input Positive. The internal high speed comparator’s noninverting input.
43 VINN Voltage Input Negative. The internal high speed comparator’s inverting input.
48 IOUT1 Unipolar Current Output of the Cosine DAC (refer to Figure 3).
49 IOUT1 Complementary Unipolar Current Output of the Cosine DAC.
51 IOUT2 Complementary Unipolar Current Output of the Control DAC.
52 IOUT2 Unipolar Current Output of the Control DAC.
55 DACBP Common Bypass Capacitor Connection for Both DACs. A 0.01 μF chip cap from this pin to AVDD
improves harmonic distortion and SFDR slightly. No connect is permissible (slight SFDR
degradation).
56 DAC RSET Common Connection for Both DACs. Used to set the full-scale output current. RSET = 39.9/ IOUT.
Normal RSET range is from 8 kΩ (5 mA) to 2 kΩ (20 mA).
61 PLL FILTER Connection for the External Zero Compensation Network of the REFCLK Multiplier’s PLL Loop
Filter. The zero compensation network consists of a 1.3 kΩ resistor in series with a 0.01 μF
capacitor. The other side of the network should be connected to AVDD as close as possible to
Pin 60. For optimum phase-noise performance, the REFCLK multiplier can be bypassed by
setting the bypass PLL bit in Control Register 1E hex.
64 DIFF CLK ENABLE Differential REFCLK Enable. A high level of this pin enables the differential clock inputs, REFCLK
and REFCLK (Pin 69 and Pin 68, respectively).
68 REFCLK Complementary (180° Out-of-Phase) Differential Clock Signal. User should tie this pin high or
low when single-ended clock mode is selected. Same signal levels as REFCLK.
69 REFCLK Single-Ended (CMOS Logic Levels Required) Reference Clock Input or One of Two Differential
Clock Signals. In differential reference clock mode, both inputs can be CMOS logic levels or have
greater than 400 mV p-p square or sine waves centered about 1.6 V dc.
70 S/P SELECT Selects between serial programming mode (logic low) and parallel programming mode
(logic high).
71 MASTER RESET
Initializes the serial/parallel programming bus to prepare for user programming, and sets
programming registers to a do-nothing state defined by the default values listed in Table 8.
Active on logic high. Asserting MASTER RESET is essential for proper operation upon power-up.
AD9852
Rev. D | Page 12 of 52
VINP/
VINN
AVDD
I
OUT
I
OUTB
MUST TERMINATE OUTPUTS
FOR CURRENT FLOW. DO
NOT EXCEED THE OUTPUT
V
OLTAGE COMPLIANCE RATING
.
COMPARATOR
OUT
AVDD
DVDD
DIGITAL
IN
AVOID OVERDRIVING
DIGITAL INPUTS. FORWARD
BIASING ESD DIODES MAY
COUPLE DIGITAL NOISE
ONTO POWER PINS.
A. DAC Outputs B. Comparator Output C. Comparator Input D. Digital Inputs
AVDD
00634-003
Figure 3. Equivalent Input and Output Circuits
AD9852
Rev. D | Page 13 of 52
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4 to Figure 9 indicate the wideband harmonic distortion performance of the AD9852 from 19.1 MHz to 119.1 MHz fundamental
output, reference clock = 30 MHz, REFCLK multiplier = 10. Each graph is plotted from 0 MHz to 150 MHz (Nyquist).
0
START 0Hz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–
100 15MHz/ STOP 150MHz
00634-004
Figure 4. Wideband SFDR, 19.1 MHz
0
START 0Hz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–
100 15MHz/ STOP 150MHz
00634-005
Figure 5. Wideband SFDR, 39.1 MHz
0
START 0Hz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–
100 15MHz/ STOP 150MHz
00634-006
Figure 6. Wideband SFDR, 59.1 MHz
0
START 0Hz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–
100 15MHz/ STOP 150MHz
00634-007
Figure 7. Wideband SFDR, 79.1 MHz
0
START 0Hz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–
100 15MHz/ STOP 150MHz
00634-008
Figure 8. Wideband SFDR, 99.1 MHz
0
START 0Hz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–
100 15MHz/ STOP 150MHz
00634-009
Figure 9. Wideband SFDR, 119.1 MHz
AD9852
Rev. D | Page 14 of 52
Figure 10 to Figure 15 show the trade-off in elevated noise floor, increased phase noise, and discrete spurious energy when the internal
REFCLK multiplier circuit is engaged. Plots with wide (1 MHz) and narrow (50 kHz) spans are shown.
Compare the noise floor of Figure 11 and Figure 12 to that of Figure 14 and Figure 15. The improvement seen in Figure 11 and Figure 12
is a direct result of sampling the fundamental at a higher rate. Sampling at a higher rate spreads the quantization noise of the DAC over a
wider bandwidth, which effectively lowers the noise floor.
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–
100 100kHz/ SPAN 1MHz
00634-010
Figure 10. Narrow-band SFDR, 39.1 MHz, 1 MHz BW, 300 MHz REFCLK
with REFCLK Multiplier Bypassed
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–
100 5kHz/ SPAN 50kHz
00634-011
Figure 11. Narrow-band SFDR, 39.1 MHz, 50 kHz BW, 300 MHz REFCLK
with REFCLK Multiplier Bypassed
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–
100 5kHz/ SPAN 50kHz
00634-012
Figure 12. Narrow-band SFDR, 39.1 MHz, 50 kHz BW, 100 MHz REFCLK
with REFCLK Multiplier Bypassed
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–
100 100kHz/ SPAN 1MHz
00634-013
Figure 13. Narrow-band SFDR, 39.1 MHz, 1 MHz BW, 30 MHz REFCLK
with REFCLK Multiply = 10×
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–
100 5kHz/ SPAN 50kHz
00634-014
Figure 14. Narrow-band SFDR, 39.1 MHz, 50 kHz BW, 30 MHz REFCLK
with REFCLK Multiplier = 10×
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–
100 5kHz/ SPAN 50kHz
00634-015
Figure 15. Narrow-band SFDR, 39.1 MHz, 50 kHz BW, 10 MHz REFCLK
with REFCLK Multiplier = 10×
AD9852
Rev. D | Page 15 of 52
Figure 18 and Figure 19 shows the narrow-band performance of the AD9852 when operating with a 30 MHz reference clock with the
REFCLK multiplier enabled at 10× vs. a 300 MHz reference clock with the REFCLK multiplier bypassed.
0
CENTER 112.469MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–
100 50kHz/ SPAN 500kHz
00634-016
Figure 16. A Slight Change in Tuning Word Yields Dramatically Better Results;
112.469 MHz with All Spurs Shifted Out-of-Band, RECLK is 300 MHz
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–
100 5kHz/ SPAN 50kHz
00634-017
Figure 17. Narrow-band SFDR, 39.1 MHz, 50 kHz BW, 200 MHz REFCLK
with REFCLK Multiplier Bypassed
FREQUENCY (Hz)
–100
–110
–150
–120
–130
–140
–160
–17010 1M100 100k10k1k
PHASE NOISE (dBc/Hz)
A
OUT
= 80MHz
A
OUT
= 5MHz
00634-018
Figure 18. Residual Phase Noise, 300 MHz REFCLK
with REFCLK Multiplier Bypassed
FREQUENCY (Hz)
–90
–100
–140
–110
–120
–130
–150
–16010 1M100 100k10k1k
PHASE NOISE (dBc/Hz)
A
OUT
= 80MHz
A
OUT
= 5MHz
00634-019
Figure 19. Residual Phase Noise, 30 MHz REFCLK
with REFCLK Multiplier = 10×
DAC CURRENT (mA)
55
0
SFDR (dBc)
54
53
52
51
50
49
48 5 1015202
5
00634-020
Figure 20. SFDR vs. DAC Current, 59.1 AOUT, 300 MHz REFCLK
with REFCLK Multiplier Bypassed
FREQUENCY (MHz)
620
0
SUPPLY CURRENT (mA)
615
610
605
600
595
590 20 40 60 80 100 120 140
00634-021
Figure 21. Supply Current vs. Output Frequency; Variation Is Minimal,
Expressed as a Percentage, and Heavily Dependent on Tuning Word
AD9852
Rev. D | Page 16 of 52
RISE TIME
1.04ns
500ps/DIV 232mV/DIV 50Ω INPUT
JITTER
[10.6ps RMS]
–33ps 0ps +33ps
00634-022
Figure 22. Typical Comparator Output Jitter, 40 MHz AOUT, 300 MHz REFCLK
with REFCLK Multiplier Bypassed
REF1 RISE
1.174ns
C1 FALL
1.286ns
CH1 500mVΩM 500ps CH1 980mV
00634-023
Figure 23. Comparator Rise/Fall Times
FREQUENCY (MHz)
1200
0
AMPLITUDE (mV p-p)
1000
800
600
400
200
0100 200 300 400 500
MINIMUM COMPARATOR
INPUT DRIVE
V
CM
= 0.5V
00634-024
Figure 24. Comparator Toggle Voltage Requirement
AD9852
Rev. D | Page 17 of 52
TYPICAL APPLICATIONS
RF/IF
INPUT BASEBAND
REFCLK COS
AD9852 LOW-PASS
FILTER
00634-025
Figure 25. Synthesized LO Application for the AD9852
I
Q
Rx
RF IN
DUAL
8-/10-BIT
ADC
DIGITAL
DEMODULATOR
Rx BASEBAND
DIGITAL
DATA OUT
8
8
I/Q MIXER
AND
LOW-PASS
FILTER
VCA
ADC ENCODE
ADC CLOCK FREQUENCY
LOCKED TO Tx CHIP/
SYMBOL/PN RATE
REFERENCE
CLOCK
48
CHIP/SYMBOL/PN
RATE DATA
AD9852
CLOCK
GENERATOR
AGC
00634-026
Figure 26. Chip Rate Generator in Spread Spectrum Application
50Ω
BAND-PASS
FILTER
50Ω
I
OUT
AD9852
FUNDAMENTAL
F
C
– F
O
IMAGE
FCLK
FC + FO
IMAGE
BAND-PASS
FILTER
F
C
+ F
O
IMAGE
AD9852
SPECTRUM FINAL OUTPUT
SPECTRUM
AMPLIFIER
00634-027
Figure 27. Using an Aliased Image to Generate a High Frequency
LOOP
FILTER
PHASE
COMPARATOR
REFERENCE
CLOCK
FILTER
AD9852
DDS
TUNING
WORD
REFCLK IN
RF FREQUENCY
OUT
DAC OUT
PROGRAMMABLE
DIVIDE-BY-N FUNCTION
(WHERE N = 2
48
/TUNING WORD)
VCO
00634-028
Figure 28. Programmable Fractional Divide-by-N Synthesizer
AD9852
Rev. D | Page 18 of 52
TUNING
WORD
LOOP
FILTER
PHASE
COMPARATOR
REFERENCE
CLOCK RF FREQUENCY
OUT
FILTER
AD9852
DDS
DIVIDE-BY-N
VCO
00634-029
Figure 29. Agile High Frequency Synthesizer
REFERENCE
CLOCK
50Ω
1:1 TRANSFORMER
THAT IS, MINI-CIRCUITS
®
T1-1T
FILTER 50Ω
DIFFERENTIAL
TRANSFORMER-COUPLED
OUTPUT
AD9852
DDS
I
OUT
I
OUT
00634-030
Figure 30. Differential Output Connection for Reduction of Common-Mode Signals
μPROCESSOR/
CONTROLLER
FPGA, ETC.
R
SET
8-BIT PARALLEL OR
SERIAL PROGRAMMING
DATA AND CONTROL
SIGNALS
AD9852
CMOS LOGIC CLOCK OUT
REFERENCE
CLOCK
300MHz MAX DIRECT
MODE OR 15MHz TO 75MHz
MAX IN THE 4× TO 20× CLOCK
MULTIPLIER MODE
2kΩ
COSINE
DAC NOTES
I
OUT
= APPROXIMATELY 20mA MAX WHEN R
SET
= 2kΩ
SWITCH POSITION 1 PROVIDES COMPLEMENTARY
SINUSOIDAL SIGNALS TO THE COMPARATOR TO
PRODUCE A FIXED 50% DUTY CYCLE FROM THE
COMPARATOR.
SWITCH POSITION 2 PROVIDES A USER-PROGRAMMABLE
DC THRESHOLD VOLTAGE TO ALLOW SETTING OF THE
COMPARATOR DUTY CYCLE.
LOW-PASS
FILTER
LOW-PASS
FILTER
CONTROL
DAC
1
2
00634-031
Figure 31. Frequency Agile Clock Generator Applications for the AD9852
AD9852
Rev. D | Page 19 of 52
MODES OF OPERATION
There are five programmable modes of operation of the AD9852.
Selecting a mode requires that three bits in the control register
(Parallel Address 1F hex) be programmed as shown in Table 5.
Table 5. Mode Selection Table
Mode 2 Mode 1 Mode 0 Result
0 0 0 Single-tone
0 0 1 FSK
0 1 0 Ramped FSK
0 1 1 Chirp
1 0 0 BPSK
In each mode, engaging certain functions may not be
permitted.
Tabl e 6 shows a listing of some important functions and their
availability for each mode.
SINGLE-TONE (MODE 000)
When MASTER RESET is asserted, single-tone mode becomes
the default. The user may also access this mode by programming
it into the control register. The phase accumulator, responsible
for generating an output frequency, is presented with a 48-bit
value from the Frequency Tuning Word 1 registers with default
values of 0. Default values from the remaining applicable registers
further define the single-tone output signal qualities.
The default values after a MASTER RESET configures the
device with an output signal of 0 Hz and 0 phase. Upon power-
up and reset, the output from both DACs is a dc value equal to
the midscale output current. This is the default mode amplitude
setting of 0. Refer to the REFCLK Multiplier section for further
explanation of the output amplitude control. It is necessary to
program all or some of the 28 program registers to produce a
user-defined output signal.
Figure 32 graphically shows the transition from the default
condition (0 Hz) to a user-defined output frequency (F1).
As with all Analog Devices DDSs, the value of the frequency
tuning word is determined using the following equation:
FTW = (Desired Output Frequency × 2N)/SYSCLK
where:
N is the phase accumulator resolution (48 bits in this instance).
Desired Output Frequency is expressed in hertz.
FTW (frequency tuning word) is a decimal number.
Once a decimal number has been calculated, it must be rounded
to an integer and then converted to binary format—a series of
48 binary-weighted 1s and 0s. The fundamental sine wave DAC
output frequency range is from dc to one-half SYSCLK.
Changes in frequency are phase-continuous, thus the first
sampled phase value of the new frequency is referenced in time
from the last sampled phase value of the previous frequency.
The 14-bit phase register adjusts the cosine DAC’s output phase.
The single-tone mode allows the user to control the following
signal qualities:
• Output frequency to 48-bit accuracy
• Output amplitude to 12-bit accuracy
o Fixed, user-defined amplitude control
o Variable, programmable amplitude control
o Automatic, programmable, single-pin-controlled,
shaped on/off keying
• Output phase to 14-bit accuracy
Furthermore, all of these qualities can be changed or modulated
via the 8-bit parallel programming port at a 100 MHz parallel-
byte rate, or at a 10 MHz serial rate. Incorporating this attribute
permits FM, AM, PM, FSK, PSK, and ASK operation in the
single-tone mode.
000 (SINGLE TONE)MODE
F1TW1
000 (DEFAULT)
0
F1
0
FREQUENCY
MASTER RESET
I/O UD CLK
00634-032
Figure 32. Default State to User-Defined Output Transition
AD9852
Rev. D | Page 20 of 52
Table 6. Function Availability vs. Mode of Operation
Function Single-Tone Mode FSK Mode Ramped FSK Mode Chirp Mode BPSK Mode
Phase Adjust 1 ● ● ● ● ●
Phase Adjust 2
●
Single-Pin FSK/BPSK or HOLD ● ● ● ●
Single-Pin Shaped Keying ● ● ● ● ●
Phase Offset or Modulation ● ● ● ●
Amplitude Control or Modulation ● ● ● ● ●
Inverse Sinc Filter ● ● ● ● ●
Frequency Tuning Word 1 ● ● ● ● ●
Frequency Tuning Word 2 ● ●
Automatic Frequency Sweep ● ●
UNRAMPED FSK (MODE 001)
When selected, the output frequency of the DDS is a function
of the values loaded into Frequency Tuning Word Register 1
and Frequency Tuning Word Register 2 and the logic level of
Pin 29 (FSK/BPSK/HOLD). A logic low on Pin 29 chooses F1
(Frequency Tuning Word 1, Parallel Address 4 hex to Parallel
Address 9 hex), and a logic high chooses F2 (Frequency Tuning
Word 2, Parallel Register Address A hex to Parallel Register
Address F hex). Changes in frequency are phase-continuous
and are internally coincident with the FSK data pin (29);
however, there is deterministic pipeline delay between the FSK
data signal and the DAC output (see Table 1).
The unramped FSK mode (see Figure 33) is representative of
traditional FSK, radio teletype (RTTY), or teletype (TTY)
transmission of digital data. FSK is a very reliable means of
digital communication; however, it makes inefficient use of the
bandwidth in the RF spectrum. Ramped FSK, shown in
Figure 34, is a method of conserving the bandwidth.
RAMPED FSK (MODE 010)
In this method of FSK, changes from F1 to F2 are not
instantaneous but are accomplished in a frequency sweep or
ramped fashion. The ramped notation implies the sweep is
linear. While linear sweeping, or frequency ramping, is easily
and automatically accomplished, it is only one of many
possibilities. Other frequency transition schemes may be
implemented by changing the ramp rate and ramp step size at
any time during operation.
Frequency ramping, whether linear or nonlinear, necessitates
that many intermediate frequencies between F1 and F2 are
output in addition to the primary F1 and F2 frequencies.
Figure 34 and Figure 35 graphically depict the frequency vs.
time characteristics of a linear ramped FSK signal.
In ramped FSK mode, the delta frequency word (DFW) is
required to be programmed as a positive twos complement
value. Another requirement is that the lowest frequency (F1) be
programmed in the Frequency Tuning Word 1 registers.
F1
F2
0
FREQUENCY
MODE
TW1
TW2
FSK DATA (PIN 29
)
001 (FSK NO RAMP)
F1
F2
000 (DEFAULT)
0
0
I/O UD CLK
00634-033
Figure 33. Traditional FSK Mode
AD9852
Rev. D | Page 21 of 52
I/O UD CLK
F1
F2
0
FREQUENCY
MODE
TW1
TW2
010 (RAMPED FSK)
F1
F2
000 (DEFAULT)
0
0
REQUIRES A POSITIVE TWOS COMPLEMENT VALUE
RAMP RATE
DFW
FSK DATA (PIN 29)
00634-034
Figure 34. Ramped FSK Mode (Start at F1)
F1
F2
0
FREQUENCY
MODE
TW1
TW2
FSK DATA
010 (RAMPED FSK)
F1
F2
000 (DEFAULT)
0
0
I/O UD CLK
00634-035
Figure 35. Ramped FSK Mode (Start at F2)
The purpose of ramped FSK is to provide better bandwidth
containment than can be achieved using traditional FSK. In
ramped FSK, the instantaneous frequency changes of traditional
FSK are replaced with more gradual, user-defined frequency
changes. The dwell time at F1 and F2 can be equal to or much
greater than the time spent at each intermediate frequency. The
user controls the dwell time at F1 and F2, the number of
intermediate frequencies, and the time spent at each frequency.
Unlike unramped FSK, ramped FSK requires the lowest
frequency to be loaded into F1 registers and the highest
frequency to be loaded into F2 registers.
Several registers must be programmed to instruct the DDS
regarding the resolution of intermediate frequency steps (48 bits)
and the time spent at each step (20 bits). Furthermore, the CLR
ACC1 bit in the control register should be toggled (low-high-low)
prior to operation to ensure that the frequency accumulator is
starting from an all 0s output condition.
For piecewise, nonlinear frequency transitions, it is necessary
to reprogram the registers while the frequency transition is in
progress to affect the desired response.
Parallel Register Address 1A hex to Parallel Register Address 1C
hex comprise the 20-bit ramp rate clock registers. This is a
countdown counter that outputs a single pulse whenever the
count reaches 0. The counter is activated any time a logic level
change occurs on the FSK input, Pin 29. This counter is run at the
system clock rate, 300 MHz maximum. The time period between
each output pulse is
(N + 1)(System Clock Period × 2)
where N is the 20-bit ramp rate clock value programmed by
the user.
The allowable range of N is from 1 to (220 – 1). The output of
this counter clocks the 48-bit frequency accumulator shown in
AD9852
Rev. D | Page 22 of 52
Figure 35. The ramp rate clock determines the amount of time
spent at each intermediate frequency between F1 and F2.
The counter stops automatically when the destination
frequency is achieved. The dwell time spent at F1 and F2 is
determined by the duration that the FSK input, Pin 29, is held
high or low after the destination frequency has been reached.
Parallel Register Address 10 hex to Parallel Register Address 15 hex
comprise the 48-bit, twos complement delta frequency word
registers. This 48-bit word is accumulated (added to the
accumulator’s output) every time it receives a clock pulse from
the ramp rate counter. The output of this accumulator is added
to or subtracted from the F1 or F2 frequency word, which is
then fed into the input of the 48-bit phase accumulator that
forms the numerical phase steps for the sine and cosine wave
outputs. In this fashion, the output frequency is ramped up and
down in frequency according to the logic state of Pin 29. The
rate at which this happens is a function of the 20-bit ramp rate
clock. Once the destination frequency is achieved, the ramp
rate clock is stopped, which halts the frequency accumulation
process.
Generally speaking, the delta frequency word is a much smaller
value compared to the value of the F1 or F2 tuning word. For
example, if F1 and F2 are 1 kHz apart at 13 MHz, the delta
frequency word might be only 25 Hz.
Figure 40 shows that premature toggling causes the ramp to
immediately reverse itself and proceed at the same rate and
resolution back to the original frequency.
The control register contains a triangle bit at Parallel Register
Address 1F hex. Setting this bit high in Mode 010 causes an
automatic ramp-up and ramp-down between F1 and F2 to
occur without having to toggle Pin 29 as shown in Figure 37.
In fact, the logic state of Pin 29 has no effect once the triangle
bit is set high. This function uses the ramp-rate clock time
period and the step size of the delta frequency word to form a
continuously sweeping linear ramp from F1 to F2 and back to
F1 with equal dwell times at every frequency. Use this function
to automatically sweep between any two frequencies from dc to
Nyquist.
In the ramped FSK mode with the triangle bit set high, an
automatic frequency sweep begins at either F1 or F2, according
to the logic level on Pin 29 (FSK input pin) when the triangle
bit’s rising edge occurs as shown in Figure 38. If the FSK data bit
is high instead of low, F2 rather than F1 is chosen as the start
frequency.
FREQUENCY
TUNING
WORD 2
FREQUENCY
TUNING
WORD 1
20-BIT
RAMP RATE
CLOCK
48-BIT DELTA
FREQUENCY
WORD (TWOS
COMPLEMENT)
FREQUENCY
ACCUMULATOR
PHASE
ACCUMULATOR
INSTANTANEOUS
PHASE OUT
ADDER
FSK (PIN 29)
SYSTEM
CLOCK
00634-036
Figure 36. Block Diagram of Ramped FSK Function
F1
F2
0
FREQUENCY
MODE
TW1
TW2
FSK DATA
TRIANGLE
BIT
010 (RAMPED FSK)
F1
F2
I/O UD CLK
00634-037
Figure 37. Effect of Triangle Bit in Ramped FSK Mode
F2
F1
0
FREQUENCY
MODE
TW1
TW2
FSK DATA
T
RIANGLE BI
T
000 (DEFAULT)
0
0
010 (RAMPED FSK)
F1
F2
00634-038
Figure 38. Automatic Linear Ramping Using the Triangle Bit
AD9852
Rev. D | Page 23 of 52
Additional flexibility in the ramped FSK mode is provided by
the AD9852’s ability to respond to changes in the 48-bit delta
frequency word and/or the 20-bit ramp-rate counter at any time
during the ramping from F1 to F2 or vice versa. To create these
nonlinear frequency changes, it is necessary to combine several
linear ramps with different slopes in a piecewise fashion. This is
done by programming and executing a linear ramp at a rate or
slope and then altering the slope (by changing the ramp rate
clock or delta frequency word, or both). Changes in slope can
be made as often as needed before the destination frequency has
been reached to form the desired nonlinear frequency sweep
response. These piecewise changes can be precisely timed using
the 32-bit internal update clock (see the Internal and External
Update Clock section).
Nonlinear ramped FSK has the appearance of the chirp function
shown in Figure 41. The major difference between a ramped
FSK function and a chirp function is that FSK is limited to
operation between F1 and F2. Chirp operation has no F2 limit
frequency.
Two additional control bits are available in the ramped FSK
mode that allow more options. Setting CLR ACC1 (Register
Address 1F hex) high clears the 48-bit frequency accumulator
(ACC1) output with a retriggerable one-shot pulse of one
system clock duration. If the CLR ACC1 bit is left high, a one-
shot pulse is delivered on the rising edge of every update clock.
The effect is to interrupt the current ramp, reset the frequency
back to the start point (F1 or F2), and then continue to ramp up
(or down) at the previous rate. This occurs even when a static
F1 or F2 destination frequency has been achieved.
Next, CLR ACC2 control bit (Register Address 1F hex) can be
used to clear both the frequency accumulator (ACC1) and the
phase accumulator (ACC2). When this bit is set high, the
output of the phase accumulator results in 0 Hz output from the
DDS. As long as this bit is set high, the frequency and phase
accumulators are cleared, resulting in 0 Hz output. To return to
previous DDS operation, CLR ACC2 must be set to logic low.
CHIRP (MODE 011)
Chirp mode is also known as pulsed FM. Most chirp systems
use a linear FM sweep pattern, but the AD9852 can also support
nonlinear patterns. In radar applications, use of chirp or pulsed
FM allows operators to significantly reduce the output power
needed to achieve the same result a single frequency radar
system produces. Figure 41 represents a very low resolution
nonlinear chirp that demonstrates the different slopes created
by varying the time steps (ramp rate) and frequency steps (delta
frequency word).
The AD9852 permits precise internally generated linear,
or externally programmed nonlinear, pulsed or continuous
FM over the complete frequency range, duration, frequency
resolution, and sweep direction(s). All of these are user-
programmable. A block diagram of the FM chirp components
is shown in Figure 39.
F1
F2
0
FREQUENCY
MODE
TW1
TW2
FSK DATA
F1
F2
000 (DEFAULT)
0
0
010 (RAMPED FSK)
I/O UD CLK
00634-039
Figure 39. FM Chirp Components
AD9852
Rev. D | Page 24 of 52
OUT
ADDER
CLR ACC2
CLR ACC1
HOLD
00634-040
PHASE
ACCUMULATOR
SYSTEM
CLOCK
FREQUENCY
TUNING
WORD 1
20-BIT
RAMP RATE
CLOCK
48-BIT DELTA
FREQUENCY
WORD (TWOS
COMPLEMENT)
FREQUENCY
ACCUMULATOR
Figure 40. Effect of Premature Ramped FSK Data
F1
0
FREQUENCY
010 (RAMPED FSK)
F1
000 (DEFAULT)
0
MODE
TW1
DFW
RAMP RATE
I/O UD CLK
00634-041
Figure 41. Example of a Nonlinear Chirp
Basic FM Chirp Programming Steps
1. Program a start frequency into Frequency Tuning Word 1
(Parallel Register Address 4 hex to Parallel Register
Address 9 hex), hereafter called FTW1.
2. Program the frequency step resolution into the 48-bit, twos
complement, delta frequency word (Parallel Register
Address 10 hex to Parallel Register Address 15 hex).
3. Program the rate of change (time at each frequency) into
the 20-bit ramp rate clock (Parallel Register Address 1A hex
to Parallel Register Address 1C hex).
When programming is complete, an I/O update pulse at Pin 20
engages the program commands.
The necessity for a twos complement delta frequency word is to
define the direction in which the FM chirp moves. If the 48-bit
delta frequency word is negative (MSB is high), the incremental
frequency changes are in a negative direction from FTW1. If the
48-bit word is positive (MSB is low), the incremental frequency
changes are in a positive direction.
It is important to note that FTW1 is only a starting point for
FM chirp. There is no built-in restraint requiring a return to
FTW1. Once the FM chirp has begun, it is free to move (under
program control) within the Nyquist bandwidth (dc to one-half
the system clock). However, instant return to FTW1 is easily
achieved.
Two control bits are available in the FM chirp mode that allow
the device to return to the beginning frequency, FTW1, or to
0 Hz. First, when the CLR ACC1 bit (Register Address 1F hex)
is set high, the 48-bit frequency accumulator (ACC1) output is
cleared with a retriggerable one-shot pulse of 1 system clock
duration. The 48-bit delta frequency word input to the accumulator
is unaffected by the CLR ACC1 bit. If the CLR ACC1 bit is held
high, a one-shot pulse is delivered to the frequency accumulator
(ACC1) on every rising edge of the I/O update clock.
The effect is to interrupt the current chirp, reset the frequency back
to FTW1, and continue the chirp at the previously programmed
rate and direction. Figure 42 shows clearing of the frequency
accumulator output in chirp mode.
AD9852
Rev. D | Page 25 of 52
Shown in the diagram is the I/O update clock, which is either
user-supplied or internally generated. See the Internal and
External Update Clock section for a discussion of the I/O
update.
Next, the CLR ACC2 control bit (Register Address 1F hex) is
available to clear both the frequency accumulator (ACC1) and
the phase accumulator (ACC2). When this bit is set high, the
output of the phase accumulator results in 0 Hz output from the
DDS. As long as this bit is set high, the frequency and phase
accumulators are cleared, resulting in 0 Hz output. To return to
the previous DDS operation, CLR ACC2 must be set to logic
low. This bit is useful in generating pulsed FM.
Figure 43 graphically illustrates the effect of CLR ACC2 bit on
the DDS output frequency. Reprogramming the registers while
the CLR ACC2 bit is high, allows a new FTW1 frequency and
slope to be loaded.
Another function available only in the chirp mode is the
HOLD pin, Pin 29. This function stops the clock signal to the
ramp rate counter, thereby halting any further clocking pulses
to the frequency accumulator, ACC1.
The effect is to halt the chirp at the frequency existing just
before HOLD was pulled high. When the HOLD pin is returned
low, the clocks are resumed and chirp continues. During a hold
condition, the user may change the programming registers;
however, the ramp rate counter must resume operation at its
previous rate until a count of 0 is obtained before a new ramp
rate count can be loaded. Figure 44 illustrates the effect of the
HOLD function on the DDS output frequency.
I/O UD CL
K
F1
0
FREQUENCY
MODE
FTW1
DFW
F1
000 (DEFAULT)
0
RAMP
RATE RAMP RATE
011 (CHIRP)
DELTA FREQUENCY WORD
CLR ACC1
00634-042
Figure 42. Effect of CLR ACC1 in FM Chirp Mode
CLR ACC2
F1
0
FREQUENCY
MODE
TW1
DPW
000 (DEFAULT)
0
RAMP RATE
011 (CHIRP)
I/O UD CLK
00634-043
Figure 43. Effect of CLR ACC2 in FM Chirp Mode
AD9852
Rev. D | Page 26 of 52
HOLD
F1
0
FREQUENCY
MODE
TW1
DFW
000 (DEFAULT)
0
RAMP RATE
011 (CHIRP)
F1
DELTA FREQUENCY WORD
RAMP RATE
I/O UD CLK
00634-044
Figure 44. Illustration of HOLD Function
The 32-bit automatic I/O update counter can be used to
construct complex chirp or ramped FSK sequences. Because
this internal counter is synchronized with the AD9852 system
clock, it allows precisely timed program changes to be invoked.
Therefore, the user is only required to reprogram the desired
registers before the automatic I/O update clock is generated.
In chirp mode, the destination frequency is not directly speci-
fied. If the user fails to control the chirp, the DDS naturally
confines itself to the frequency range between dc and Nyquist.
Unless terminated by the user, the chirp continues until power
is removed.
When the chirp destination frequency is reached, there are
several possible outcomes:
1. Stop at the destination frequency using the HOLD pin, or
by loading all 0s into the delta frequency word registers of
the frequency accumulator (ACC1).
2. Use the HOLD pin function to stop the chirp, and then ramp
down the output amplitude using the digital multiplier stages
and the shaped-keying pin, Pin 30, or via program register
control (Address 21 hex to Address 24 hex).
3. Abruptly terminate the transmission with Bit CLR ACC2.
4. Continue chirp by reversing the direction and returning to
the previous, or another, destination frequency in a linear
or user-directed manner. If this involves going down in
frequency, a negative 48-bit delta frequency word (the
MSB is set to 1) must be loaded into Register 10 hex to
Register 15 hex. Any decreasing frequency step of the delta
frequency word requires the MSB to be set to logic high.
5. Continue chirp by immediately returning to the beginning
frequency (F1) in a sawtooth fashion, and repeat the
previous chirp process. This is where the CLR ACC1
control bit is used. An automatic repeating chirp can be set
up using the 32-bit update clock to issue the CLR ACC1
command at precise time intervals. Adjusting the timing
intervals or changing the delta frequency word changes the
chirp range. It is incumbent upon the user to balance the
chirp duration and frequency resolution to achieve the
proper frequency range.
BPSK (MODE 100)
Binary, biphase, or bipolar phase shift keying is a means to
rapidly select between two preprogrammed, 14-bit output phase
offsets. The logic state of BPSK, Pin 29, controls the selection of
Phase Adjust Register 1 or Phase Adjust Register 2. When low,
BPSK selects Phase Adjust Register 1; when high, it selects
Phase Adjust Register 2. Figure 45 illustrates phase changes
made to four cycles of an output carrier.
Basic BPSK Programming Steps
1. Program a carrier frequency into Frequency Tuning Word 1.
2. Program appropriate 14-bit phase words into Phase Adjust
Register 1 and Phase Adjust Register 2.
3. Attach the BPSK data source to Pin 29.
4. Activate the I/O update clock when ready.
If higher order PSK modulation is desired, the user can select
single-tone mode and program Phase Adjust Register 1 using
the serial or high speed parallel programming bus.
AD9852
Rev. D | Page 27 of 52
BPSK DATA
360
0
PHASE
MODE
FTW1
PHASE ADJUST 1
000 (DEFAULT)
0
PHASE ADJUST 2
100 (BPSK)
F1
270°
90°
I/O UD CLK
00634-045
Figure 45. BPSK Mode
AD9852
Rev. D | Page 28 of 52
USING THE AD9852
INTERNAL AND EXTERNAL UPDATE CLOCK
The update clock function is comprised of a bidirectional
I/O UD CLK pin, Pin 20, and a programmable 32-bit down-
counter. In order for programming changes to be transferred
from the I/O buffer registers to the active core of the DDS, a
clock signal (low-to-high edge) must be externally supplied to
Pin 20 or internally generated by the 32-bit update clock.
When the user provides an external update clock, it is internally
synchronized with the system clock to prevent partial transfer
of program register information due to violation of data setup
or hold times. This mode gives the user complete control of
when updated program information becomes effective. The
default mode for the update clock is internal (internal/external
update clock control register bit is logic high). To switch to
external update clock mode, the internal/external update clock
control register bit must be set to logic low. The internal update
mode generates automatic, periodic update pulses with a user-
defined time period.
An internally generated update clock can be established by
programming the 32-bit update clock registers (Address 16 hex
to Address 19 hex) and setting the internal/external update
clock (Address 1F hex) control register bit to logic high. The
update clock countdown counter function operates at half the
rate of the system clock (150 MHz maximum) and counts down
from a 32-bit binary value (programmed by the user). When the
count reaches 0, an automatic I/O update of the DDS output or
the DDS functions is generated. The update clock is internally
and externally routed on Pin 20 to allow users to synchronize
programming of update information with the update clock rate.
The time period between update pulses is given as
(N + 1) × System Clock Period
where N is the 32-bit value programmed by the user, and the
allowable range of N is from 1 to (232 − 1).
The internally generated update pulse output on Pin 20 has a
fixed high time of eight system clock cycles.
Programming the update clock register for values less than 5
causes the I/O UD CLK pin to remain high. The update clock
functionality still works; however, the user cannot use the signal
as an indication that data is transferring. This is an effect of the
minimum high pulse time when I/O UD CLK is an output.
ON/OFF OUTPUT SHAPED KEYING (OSK)
This feature allows the user to control the amplitude vs. time
slope of the cosine DAC output signal. This function is used in
burst transmissions of digital data to reduce the adverse spectral
impact of short, abrupt bursts of data. Users must first enable
the digital multiplier by setting the OSK EN bit (Control
Register Address 20 hex) to logic high in the control register.
If the OSK EN bit is set low, the digital multiplier responsible
for amplitude control is bypassed, and the cosine DAC output is
set to full-scale amplitude. In addition to setting the OSK EN bit,
a second control bit, OSK INT (also at Address 20 hex), must be
set to logic high. Logic high selects the linear internal control of
the output ramp-up or ramp-down function. A logic low in the
OSK INT bit switches control of the digital multiplier to a user-
programmable 12-bit register, allowing users to dynamically shape
the amplitude transition in practically any fashion. The 12-bit
register, labeled output shape key, is located at Address 21 hex
to Address 22 hex, as shown in Table 8. The maximum output
amplitude is a function of the RSET resistor and is not programmable
when OSK INT is enabled.
ABRUPT ON/OFF KEYING
SHAPED ON/OFF KEYING
ZERO
S
CALE
ZERO
S
CALE
FULL
SCALE
FULL
SCALE
00634-046
Figure 46. Shaped On/Off Keying
The transition time from zero scale to full scale must also be
programmed. The transition time is a function of two fixed
elements and one variable. The variable element is the
programmable 8-bit ramp-rate counter. This is a countdown
counter that is clocked at the system clock rate (300 MHz
maximum) and generates one pulse whenever the counter
reaches 0. This pulse is routed to a 12-bit counter that
increments with each pulse received.
The outputs of the 12-bit counter are connected to the 12-bit
digital multiplier. When the digital multiplier has a value of all
0s at its inputs, the input signal is multiplied by 0, producing
zero scale.
When the multiplier has a value of all 1s, the input signal is
multiplied by a value of 4095/4096, producing nearly full scale.
There are 4094 remaining fractional multiplier values that produce
output amplitudes scaled according to their binary values.
AD9852
Rev. D | Page 29 of 52
The two fixed elements of the transition time are the period of
the system clock (which drives the ramp-rate counter) and the
number of amplitude steps (4096). For example, assume the
system clock of the AD9852 is 100 MHz (10 ns period). If the
ramp-rate counter is programmed for a minimum count of 3, it
takes two system clock periods (one rising edge loads the count-
down value, and the next edge decrements the counter from 3
to 2). If the count-down value is less than 3, the ramp rate counter
stalls and, therefore, produces a constant scaling value to the digital
multiplier. This stall condition may have application to the user.
The relationship of the 8-bit count-down value to the time
period between output pulses is given as
(N + 1) × System Clock Period
where N is the 8-bit count-down value.
It takes 4096 of these pulses to advance the 12-bit up-counter
from zero scale to full scale. Therefore, the minimum shaped
keying ramp time for a 100 MHz system clock is 4096 × 4 ×
10 ns = approximately 164 µs. The maximum ramp time is
4096 × 256 × 10 ns = approximately 10.5 ms
Finally, by changing the logic state of Pin 30, shaped keying
automatically performs the programmed output envelope
functions when OSK INT is high. A logic high on Pin 30 causes
the outputs to linearly ramp up to full-scale amplitude and hold
until the logic level is changed to low, causing the outputs to
ramp down to zero scale.
12-BIT DIGITAL
MULTIPLIER
12 12
(BYPASS MULTIPLIER)
OSK EN = 0
OSK EN = 1
OSK EN = 0
OSK EN = 1
12
12
DIGITAL
SIGNAL IN
USER-PROGRAMMABLE
12-BIT MULTIPLIER
OUTPUT SHAPE
KEY MULT REGISTER
12 OSK INT = 1
OSK INT = 0
18-BIT RAMP
RATE
COUNTER
SYSTEM
CLOCK
SHAPED ON/OFF
KEYING PIN
12-BIT
UP/DOWN
COUNTER
DDS DIGITAL
OUTPUT COSINE
DAC
00634-047
Figure 47. Block Diagram of the Digital Multiplier Section Responsible for Shaped Keying Function
AD9852
Rev. D | Page 30 of 52
COSINE DAC
The cosine output of the DDS drives the cosine DAC (300 MSPS
maximum). Its maximum output amplitude is set by the DAC RSET
resistor at Pin 56. This is a current-output DAC with a full-scale
maximum output of 20 mA; however, a nominal 10 mA output
current provides best spurious-free dynamic range (SFDR)
performance. The value of RSET = 39.93/IOUT, where IOUT is in
amps. DAC output compliance specification limits the maximum
voltage developed at the outputs to –0.5 V to +1 V. Voltages
developed beyond this limitation cause excessive DAC distortion
and possibly permanent damage. The user must choose a proper
load impedance to limit the output voltage swing to the compliance
limits. Both DAC outputs should be terminated equally for best
SFDR, especially at higher output frequencies, where harmonic
distortion errors are more prominent.
The cosine DAC is preceded by an inverse SIN(x)/x filter
(also called an inverse sinc filter) that precompensates for
DAC output amplitude variations over frequency to achieve
flat amplitude response from dc to Nyquist. This DAC can be
powered down by setting the DAC PD bit high (Address 1D hex
of the control register) when not needed. Cosine DAC outputs
are designated as IOUT1 (Pin 48) and IOUT1 (Pin 49).
CONTROL DAC
The control DAC output can provide dc control levels to
external circuitry, generate ac signals, or enable duty cycle
control of the on-board comparator. The input to the control
DAC is configured to accept twos complement data supplied by
the user. Data is channeled through the serial or parallel inter-
face to the 12-bit control DAC register (Address 26 hex and
Address 27 hex) at a maximum 100 MHz data rate. This DAC is
clocked at the system clock, 300 MSPS (maximum), and has the
same maximum output current capability as that of the cosine
DAC. The single RSET resistor on the AD9852 sets the full-scale
output current for both DACs. The control DAC can be powered
down separately for power conservation when it is not needed
by setting the control DAC power-down bit high (Address 1D hex).
Control DAC outputs are designated as IOUT2 (Pin 52) and
IOUT2 (Pin 51).
FREQUENCY NORMALIZED TO SAMPLE RATE
4.0
0 0.1
–0.5
0
dB
3.5
3.0
2.5
2.0
1.5
1.0
0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0 0.2 0.3 0.4 0.5
SYSTEM
ISF
SINC
00634-048
Figure 48. Inverse Sinc Filter Response
INVERSE SINC FUNCTION
This filter precompensates input data to the cosine DAC for
the SIN(x)/x roll-off characteristic inherent in the DAC’s
output spectrum. This allows wide bandwidth signals (such
as QPSK) to be output from the DAC without appreciable
amplitude variations as a function of frequency. The inverse
sinc function can be bypassed to significantly reduce power
consumption, especially at higher clock speeds.
Inverse sinc is engaged by default and is bypassed by bringing
the bypass inverse sinc bit high in Control Register 20 hex, as
shown in Table 8.
REFCLK MULTIPLIER
This is a programmable PLL-based reference clock multiplier,
which allows the user to select an integer clock multiplying
value over the range of 4× to 20×. Use of this function allows
users to input as little as 15 MHz at the REFCLK input to
produce a 300 MHz internal system clock. Five bits in Control
Register 1E hex set the multiplier value, as described in Table 7.
The REFCLK multiplier function can be bypassed to allow
direct clocking of the AD9852 from an external clock source.
The system clock for the AD9852 is either the output of the
REFCLK multiplier (if it is engaged) or the REFCLK inputs.
REFCLK can be either a single-ended or differential input by
setting Pin 64, DIFF CLK ENABLE, low or high, respectively.
PLL Range Bit
The PLL range bit selects the frequency range of the REFCLK
multiplier PLL. For operation from 200 MHz to 300 MHz,
(internal system clock rate) the PLL range bit should be set to
Logic 1. For operation below 200 MHz, set the PLL range bit to
Logic 0. The PLL range bit adjusts the PLL loop parameters for
optimized phase noise performance within each range.
AD9852
Rev. D | Page 31 of 52
PLL Filter
The PLL FILTER pin, Pin 61, provides the connection for the
external zero compensation network of the PLL loop filter. The
zero compensation network consists of a 1.3 kΩ resistor in
series with a 0.01 µF capacitor. The other side of the network
should be connected as close as possible to Pin 60, AVDD. For
optimum phase noise performance, the clock multiplier can be
bypassed by setting the Bypass PLL bit in Control Register
Address 1E hex.
Differential REFCLK Enable
A high level on the DIFF CLK ENABLE pin enables the differential
clock inputs, REFCLK (Pin 69) and REFCLK (Pin 68). The min-
imum differential signal amplitude required is 400 mV p-p at
the REFCLK input pins. The center point or common-mode
range of the differential signal can range from 1.6 V to 1.9 V.
When Pin 64 (DIFF CLK ENABLE) is tied low, REFCLK (Pin 69)
is the only active clock input. This is referred to as single-ended
mode. In this mode, Pin 68 (REFCLK) should be tied low or high.
HIGH SPEED COMPARATOR
The comparator is optimized for high speed and has a >300 MHz
toggle rate, low jitter, sensitive input, and built-in hysteresis. It
also has an output level of 1 V p-p minimum into 50 Ω or CMOS
logic levels into high impedance loads. The comparator can be
powered down separately to conserve power. This comparator
is used in clock generator applications to square up the filtered
sine wave generated by the DDS.
POWER-DOWN
Several individual stages may be powered down to reduce
power consumption via the programming registers while still
maintaining functionality of desired stages. These stages are
identified in the Register Layout table (Table 8) in the Address
1D hex section. Power-down is achieved by setting the specified
bits to logic high. A logic low indicates that the stages are
powered up.
Furthermore, and perhaps most significantly, the inverse sinc
filters and the digital multiplier stages can be bypassed to achieve
significant power reduction through programming of the control
registers in Address 20 hex. Again, logic high causes the stage to
be bypassed. Of particular importance is the inverse sinc filter
because this stage consumes a significant amount of power.
A full power-down occurs when all four PD bits in Control
Register 1D hex are set to logic high. This reduces power
consumption to approximately 10 mW (3 mA).
AD9852
Rev. D | Page 32 of 52
PROGRAMMING THE AD9852
The AD9852 Register Layout table (Table 8) contains information
for programming a chip for a desired functionality. While many
applications require very little programming to configure the
AD9852, some make use of all 12 accessible register banks. The
AD9852 supports an 8-bit parallel I/O operation or an SPI-
compatible serial I/O operation. All accessible registers can be
written and read back in either I/O operating mode.
S/P SELECT, Pin 70, is used to configure the I/O mode. Systems
that use a parallel I/O mode must connect the S/P SELECT pin
to VDD. Systems that operate in the serial I/O mode must tie the
S/P SELECT pin to GND.
Regardless of the mode, the I/O port data is written to a buffer
memory that does not affect operation of the part until the
contents of the buffer memory are transferred to the register
banks. This transfer of information occurs synchronously to
the system clock in one of two ways:
1. The transfer is internally controlled at a rate programmed
by the user.
2. The transfer is externally controlled by the user. I/O
operations can occur in the absence of REFCLK, but data
cannot be moved from the buffer memory to the register
bank without REFCLK. (See the Internal and External
Update Clock section for details.)
MASTER RESET
Logic high active must be held high for a minimum of 10 system
clock cycles. This causes the communication bus to be initialized
and loads the default values listed in Table 8.
PARALLEL I/O OPERATION
With the S/P SELECT pin tied high, the parallel I/O mode is
active. The I/O port is compatible with industry-standard DSPs
and microcontrollers. Six address bits, eight bidirectional data
bits, and separate write/read control inputs make up the I/O
port pins.
Parallel I/O operation allows write access to each byte of any
register in a single I/O operation up to 1/10.5 ns. Readback
capability for each register is included to ease designing with
the AD9852.
Reads are not guaranteed at 100 MHz, because they are
intended for software debugging only.
Parallel I/O operation timing diagrams are shown in Figure 49
and Figure 50.
Table 7. REFCLK Multiplier Control Register Values
Ref Mult
Multiplier Value Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
4 0 0 1 0 0
5 0 0 1 0 1
6 0 0 1 1 0
7 0 0 1 1 1
8 0 1 0 0 0
9 0 1 0 0 1
10 0 1 0 1 0
11 0 1 0 1 1
12 0 1 1 0 0
13 0 1 1 0 1
14 0 1 1 1 0
15 0 1 1 1 1
16 1 0 0 0 0
17 1 0 0 0 1
18 1 0 0 1 0
19 1 0 0 1 1
20 1 0 1 0 0
SERIAL PORT I/O OPERATION
With the S/P SELECT pin tied low, the serial I/O mode is active.
The AD9852 serial port is a flexible, synchronous, serial commu-
nication port allowing easy interface to many industry-standard
microcontrollers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats, including both the
Motorola 6905/11 SPI and Intel® 8051 SSR protocols. The interface
allows read/write access to all 12 registers that configure the
AD9852 and can be configured as a single pin I/O (SDIO) or
two unidirectional pins for in/out (SDIO/SDO). Data transfers
are supported in most significant bit (MSB) first format or least
significant bit (LSB) first format at up to 10 MHz.
When configured for serial I/O operation, most pins from the
AD9852 parallel port are inactive; only some pins are used for
serial I/O operation. Table 9 describes pin requirements for
serial I/O operation.
When operating in the serial I/O mode, it is best to use the
external I/O update CLK mode to avoid an I/O update CLK
during a serial communication cycle. Such an occurrence can
cause incorrect programming due to partial data transfer. Thus,
the user writes between I/O update CLKs. To exit the default
internal update mode, program the device for external update
operation at power-up before starting the REFCLK signal, but
after a master reset. Starting the REFCLK causes this
information to transfer to the register bank, putting the device
into external update mode.
AD9852
Rev. D | Page 33 of 52
Shaded sections comprise the control register.
Table 8. Register Layout
AD9852 Register Layout
Parallel
Address
(Hex)
Serial
Address
(Hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Default
Value
(Hex)
00
01
0 Phase Adjust Register 1 <13:8> (Bits 15, 14, don’t care)
Phase Adjust Register 1 <7:0>
Phase 1 00
00
02
03
1 Phase Adjust Register 2 <13:8> (Bits 15, 14, don’t care)
Phase Adjust Register 2 <7:0>
Phase 2 00
00
04
05
06
07
08
09
2 Frequency Tuning Word 1 <47:40>
Frequency Tuning Word 1 <39:32>
Frequency Tuning Word 1 <31:24>
Frequency Tuning Word 1 <23:16>
Frequency Tuning Word 1 <15:8>
Frequency Tuning Word 1 <7:0>
Frequency 1 00
00
00
00
00
00
0A
0B
0C
0D
0E
0F
3 Frequency Tuning Word 2 <47:40>
Frequency Tuning Word 2 <39:32>
Frequency Tuning Word 2 <31:24>
Frequency Tuning Word 2 <23:16>
Frequency Tuning Word 2 <15:8>
Frequency Tuning Word 2 <7:0>
Frequency 2 00
00
00
00
00
00
10
11
12
13
14
15
Delta frequency word <47:40>
Delta frequency word <39:32>
Delta frequency word <31:24>
Delta frequency word <23:16>
Delta frequency word <15:8>
Delta frequency word <7:0>
00
00
00
00
00
00
16
17
18
19
5 Update clock <31:24>
Update clock <23:16>
Update clock <15:8>
Update clock <7:0>
00
00
00
00
1A
1B
1C
6 Ramp rate clock <19:16> (Bits 23, 22, 21, 20, don’t care)
Ramp rate clock <15:8>
Ramp rate clock <7:0>
00
00
00
1D 7 Don’t care
CR [31]
Don’t care Don’t
care
Comp
PD
Reserved,
always
low
Control
DAC PD
DAC PD DIG PD 10
1E Don’t care PLL range Bypass
PLL
Ref
Mult 4
Ref
Mult 3
Ref
Mult 2
Ref
Mult 1
Ref
Mult 0
64
1F CLR ACC1 CLR ACC2 Triangle Don’t
care
Mode 2 Mode 1 Mode 0 Int/Ext
update clock
01
20 Don’t care Bypass inv
sinc
OSK EN OSK INT Don’t
care
Don’t care LSB first SDO active
CR [0]
20
21
22
8 Output shape key multiplier <11:8> (Bits 15,14,13,12 don’t care)
Output shape key multiplier <7:0>
00
00
23
24
9 Don’t care
Don’t care
00
00
25 A Output shape key ramp rate <7:0> 80
26
27
B Control DAC <11:8> (Bits 15, 14, 13, 12 don’t care)
Control DAC <7:0> (Data is required to be in twos complement format)
00
00
AD9852
Rev. D | Page 34 of 52
A<5:0>
D<7:0>
RD
A1
D1
A2
D2
A3
D3
T
RDHOZ
T
RDLOV
T
AHD
T
ADV
SPECIFICATION
T
ADV
T
AHD
T
RDLOV
T
RDHOZ
VALUE
15ns
5ns
15ns
10ns
DESCRIPTION
ADDRESS TO DATA VALID TIME (MAXIMUM)
ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM)
RD LOW TO OUTPUT VALID (MAXIMUM)
RD HIGH TO DATA THREE-STATE (MAXIMUM)
00634-049
Figure 49. Parallel Port Read Timing Diagram
D<7:0> D1 D2 D3
SPECIFICATION
T
ASU
T
DSU
T
ADH
T
DHD
T
WRLOW
T
WRHIGH
T
WR
VALUE
8.0ns
3.0ns
0ns
0ns
2.5ns
7ns
10.5ns
DESCRIPTION
ADDRESS SETUP TIME TO WR SIGNAL ACTIVE
DATA SETUP TIME TO WR SIGNAL ACTIVE
ADDRESS HOLD TIME TO WR SIGNAL INACTIVE
DATA HOLD TIME TO WR SIGNAL INACTIVE
WR SIGNAL MINIMUM LOW TIME
WR SIGNAL MINIMUM HIGH TIME
MINIMUM WRITE TIME
T
WR
A<5:0> A1 A2 A3
T
ASU
T
AHD
T
WRHIGH
T
WRLOW
T
DHD
T
DSU
WR
00634-050
Figure 50. Parallel Port Write Timing Diagram
Table 9. Serial I/O Pin Requirements
Pin Number Mnemonic Serial I/O Description
1, 2, 3, 4, 5, 6, 7, 8 D [7:0] The parallel data pins are not active; tie these pins to VDD or GND.
14, 15, 16 A [5:3] The parallel address pins Pin A5, Pin A4, and Pin A3 are not active; tie these pins to VDD or GND.
17 A2/IO RESET I/O RESET.
18 A1/SDO SDO.
19 A0/SDIO SDIO.
20 I/O UD CLK Update Clock. Same functionality for serial mode as parallel mode.
21 WR/SCLK SCLK.
22 RDB/CS CS—Chip Select.
AD9852
Rev. D | Page 35 of 52
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a serial communication cycle with the
AD9852. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9852, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9852 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication
cycle. The Phase 1 instruction byte defines whether the
upcoming data transfer is read or write, and the register address
to be acted upon.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9852. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9852
and the system controller. The number of data bytes transferred
during Phase 2 of the communication cycle is a function of the
register address. The AD9852 internal serial I/O controller
expects every byte of the register being accessed to be
transferred. Table 10 describes how many bytes must be
transferred.
Table 10. Register Address vs. Data Bytes Transferred
Serial
Register
Address Register Name
Number
of Bytes
Transferred
0 Phase Offset Tuning Word Register 1 2
1 Phase Offset Tuning Word Register 2 2
2 Frequency Tuning Word 1 6
3 Frequency Tuning Word 2 6
4 Delta frequency register 6
5 Update clock rate register 4
6 Ramp rate clock register 3
7 Control register 4
8 Digital multiplier register 2
A Shaped on/off keying ramp rate
register
1
B Control DAC register 2
At the completion of a communication cycle, the AD9852 serial
port controller expects the next eight rising SCLK edges to be
the instruction byte of the next communication cycle. In
addition, an active high input on the I/O RESET pin immed-
iately terminates the current communication cycle. After I/O
RESET returns low, the AD9852 serial port controller requires
the next eight rising SCLK edges to be the instruction byte of
the next communication cycle.
All data input to the AD9852 is registered on the rising edge of
SCLK. All data is driven out of the AD9852 on the falling edge
of SCLK.
Figure 51 and Figure 52 are useful in understanding the general
operation of the AD9852 serial port.
INSTRUCTION
CYCLE DATA TRANSFER
INSTRUCTION
BYTE DATA BYTE 1 DATA BYTE 2 DATA BYTE 3
SDIO
CS
00634-051
Figure 51. Using SDIO as a Read/Write Transfer
INSTRUCTION
CYCLE DATA TRANSFER
INSTRUCTION
BYTE
SDIO
CS
DATA TRANSFER
DATA BYTE 1 DATA BYTE 2 DATA BYTE 3
SDO
00634-052
Figure 52. Using SDIO as an Input and SDO as an Output
INSTRUCTION BYTE
The instruction byte contains the following information:
MSB D6 D5 D4 D3 D2 D1 LSB
R/W X X X A3 A2 A1 A0
R/W
Bit 7 of the instruction byte determines whether a read or write
data transfer occurs following the instruction byte. Logic high
indicates that a read operation will occur. Logic 0 indicates that
a write operation will occur.
Bit 6, Bit 5, and Bit 4 of the instruction byte are dummy bits
(don’t care).
A3, A2, A1, A0
Bit 3, Bit 2, Bit 1, and Bit 0 of the instruction byte determine
which register is accessed during the data transfer portion of
the communication cycle (see Table 10 for register address
details).
AD9852
Rev. D | Page 36 of 52
SERIAL INTERFACE PORT PIN DESCRIPTIONS
Table 11.
Pin Description
SCLK Serial Clock (Pin 21). The serial clock pin is used to synchronize data to and from the AD9852 and to run the internal state
machines. SCLK maximum frequency is 10 MHz.
CS Chip Select (Pin 22). Active low input that allows more than one device on the same serial communication line. The SDO and
SDIO pins go to a high impedance state when this input is high. If driven high during a communication cycle, that cycle is
suspended until CS is reactivated low. Chip select can be tied low in systems that maintain control of SCLK.
SDIO Serial Data I/O (Pin 19). Data is always written into the AD9852 on this pin. However, this pin can be used as a bidirectional data
line. The configuration of this pin is controlled by Bit 0 of Register Address 20 hex. The default is Logic 0, which configures the
SDIO pin as bidirectional.
SDO Serial Data Out (Pin 18). Data is read from this pin for protocols that use separate lines for transmitting and receiving data.
In the case where the AD9852 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high
impedance state.
I/O RESET Synchronize I/O Port (Pin 17). Synchronizes the I/O port state machines without affecting the contents of the addressable
registers. An active high input on the I/O RESET pin causes the current communication cycle to terminate. After I/O RESET
returns low (Logic 0), another communication cycle may begin, starting with the instruction byte.
Notes on Serial Port Operation
The AD9852 serial port configuration bits reside in Bit 1 and
Bit 0 of Register Address 20 hex. The configuration changes
immediately upon a valid I/O update. For multibyte transfers,
writing this register can occur during the middle of a
communication cycle. Care must be taken to compensate for
this new configuration for the remainder of the current
communication cycle.
The system must maintain synchronization with the AD9852,
or the internal control logic is not able to recognize further
instructions. For example, if the system sends the instruction to
write a 2-byte register and then pulses the SCLK pin for a 3-byte
register (24 additional SCLK rising edges), communication
synchronization is lost. In this case, the first 16 SCLK rising
edges after the instruction cycle properly write the first two data
bytes into the AD9852, but the next eight rising SCLK edges are
interpreted as the next instruction byte, not the final byte of the
previous communication cycle.
In cases where synchronization is lost between the system and
the AD9852, the I/O RESET pin provides a means to re-establish
synchronization without reinitializing the entire chip. Asserting
the I/O RESET pin (active high) resets the AD9852 serial port
state machine, terminating the current I/O operation and putting
the device into a state where the next eight SCLK rising edges
are understood to be an instruction byte. The I/O RESET pin
must be deasserted (low) before the next instruction byte write
can begin. Any information written to the AD9852 registers
during a valid communication cycle prior to loss of synchro-
nization, remains intact.
MSB/LSB TRANSFERS
The AD9852 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by Bit 1 of Serial Bank 20 hex. When
this bit is set active high, the AD9852 serial port is in LSB-first
format. This bit defaults low, to the MSB-first format. The
instruction byte must be written in the format indicated by Bit 1
of Serial Register Bank 20 hex, that is, if the AD9852 is in LSB-
first mode, the instruction byte must be written from least
significant bit to most significant bit.
CS
SCLK
SDIO
T
PRE
T
DSU
T
SCLKPWH
T
SCLKPWL
T
SCLK
T
DHLD
SECOND BITFIRST BIT
SYMBOL
T
PRE
T
SCLK
T
DSU
T
SCLKPWH
T
SCLKPWL
T
DHLD
MIN
30ns
100ns
30ns
40ns
40ns
0ns
DEFINITION
CS SETUP TIME
PERIOD OF SERIAL DATA CLOCK
SERIAL DATA SETUP TIME
SERIAL DATA CLOCK PULSE WIDTH HIGH
SERIAL DATA CLOCK PULSE WIDTH LOW
SERIAL DATA HOLD TIME
00634-053
Figure 53. Timing Diagram for Data Write to AD9852
T
DV
FIRST BIT SECOND BIT
SDIO
SDO
S
CLK
CS
SYMBOL
T
DV
MAX
30ns DEFINITION
DATA VALID TIME
00634-054
Figure 54. Timing Diagram for Read from AD9852
AD9852
Rev. D | Page 37 of 52
CONTROL REGISTER DESCRIPTIONS
The control register is located at Address 1D hex to Address 20 hex, shown in the shaded portion of Table 8. It is composed of 32 bits.
Bit 31 is located at the top left position, and Bit 0 is located in the lower right position of the shaded table portion. The register has been
subdivided below to make it easier to locate the text associated with specific control categories.
Table 12.
Bit Description
CR [31:29] Open.
CR [28] The comparator power-down bit. When this bit is set to Logic 1, it indicates to the comparator that a power-down mode is
active. This bit is an output of the digital section and is an input to the analog section.
CR [27] Must always be written to Logic 0. Writing this bit to Logic 1 causes the AD9852 to stop working until a master reset is
applied.
CR [26] The control DAC power-down bit. When this bit is set to Logic 1, it indicates to the control DAC that power-down mode is
active.
CR [25] The full DAC power-down bit. When this bit is set to Logic 1, it indicates to both the cosine and control DACs as well as the
reference that a power-down mode is active.
CR [24] The digital power-down bit. When this bit is set to Logic 1, it indicates to the digital section that a power-down mode is
active. Within the digital section, the clocks are forced to dc, effectively powering down the digital section. The PLL still
accepts the REFCLK signal and continues to output the higher frequency.
CR [23] Reserved. Write to 0.
CR [22] The PLL range bit. The PLL range bit controls the VCO gain. The power-up state of the PLL range bit is Logic 1; a higher gain
is required for frequencies above 200 MHz.
CR [21] The bypass PLL bit, active high. When this bit is active, the PLL is powered down and the REFCLK input is used to drive the
system clock signal. The power-up state of the bypass PLL bit is Logic 1, PLL bypassed.
CR [20:16] The PLL multiplier factor. These bits are the REFCLK multiplication factor unless the bypass PLL bit is set. The PLL multiplier
valid range is from 4 to 20, inclusive.
CR [15] The Clear Accumulator 1 bit. This bit has a one-shot type of function. When this bit is written active (Logic 1), a Clear
Accumulator 1 signal is sent to the DDS logic, resetting the accumulator value to 0. The bit is then automatically reset, but
the buffer memory is not reset. This bit allows the user to create a sawtooth frequency sweep pattern easily with minimal
user intervention. This bit is intended for chirp mode only, but its function is still retained in other modes.
CR [14] The clear accumulator bit. When this bit is active high, it holds both the Accumulator 1 and Accumulator 2 values at 0 for as
long as the bit is active. This allows the DDS phase to be initialized via the I/O port.
CR [13] The triangle bit. When this bit is set, the AD9852 automatically performs a continuous frequency sweep from F1 to F2
frequencies and back. The effect is a triangular frequency sweep. When this bit is set, the operating mode must be set to
ramped FSK.
CR [12] Don’t care.
CR [11:9] The three bits that describe the five operating modes of the AD9852:
0x0 = single-tone mode
0x1= FSK mode
0x2 = ramped FSK mode
0x3 = chirp mode
0x4 = BPSK mode
CR [8] The internal update active bit. When this bit is set to Logic 1, the I/O UD CLK pin is an output and the AD9852 generates the
I/O UD signal. When this bit is set to Logic 0, external I/O update function is performed, and the I/O UD CLK pin is
configured as an input.
CR [7] Reserved. Write to 0.
CR [6] This is the inverse sinc filter BYPASS bit. When this bit is set, the data from the DDS block goes directly to the output
shaped-keying logic, and the clock for the inverse sinc filter is stopped. Default is clear, filter enabled.
CR [5] The shaped-keying enable bit. When this bit is set, the output ramping function is enabled and is performed in accordance
with the CR [4] bit requirements.
CR [4] The internal/external output shaped-keying control bit. When this bit is set to Logic 1, the shaped-keying factor is internally
generated and applied to the cosine DAC path. When this bit is cleared (default), the output shaped-keying function is externally
controlled by the user, and the shaped-keying factor is the value of the shaped key multiplier register. The two shaped key
multiplier registers also default low, so that the output is off at power-up until the device is programmed by the user.
CR [3:2] Reserved. Write to 0.
CR [1] The serial port MSB/LSB first bit. Defaults low, MSB first.
CR [0] The serial port SDO active bit. Defaults low, inactive.
AD9852
Rev. D | Page 38 of 52
SDIO D
7
I
7
SCLK
CS INSTRUCTION CYCLE DATA TRANSFER CYCLE
I
6
I
5
I
4
I
3
I
0
I
2
I
1
D
6
D
5
D
4
D
3
D
2
D
1
D
0
00634-055
Figure 55. Serial Port Write Timing Clock Stall Low
SDIO
D
O7
D
O6
D
O5
D
O4
D
O3
D
O2
D
O1
D
O0
SCLK
CS INSTRUCTION CYCLE
DON’T CARE
SDO
DATA TRANSFER CYCLE
I
7
I
6
I
5
I
4
I
3
I
0
I
2
I
1
00634-056
Figure 56. 3-Wire Serial Port Read Timing Clock Stall Low
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SDIO
SCLK
INSTRUCTION CYCLE DATA TRANSFER CYCLE
I
7
I
6
I
5
I
4
I
3
I
0
I
2
I
1
CS
00634-057
Figure 57. Serial Port Write Timing Clock Stall High
I
7
I
6
I
5
I
4
I
3
I
0
I
2
I
1
SDIO
SCLK
INSTRUCTION CYCLE DATA TRANSFER CYCLE
D
O7
D
O6
D
O5
D
O4
D
O3
D
O2
D
O1
D
O0
CS
00634-058
Figure 58. 2-Wire Serial Port Read Timing Clock Stall High
AD9852
Rev. D | Page 39 of 52
POWER DISSIPATION AND THERMAL CONSIDERATIONS
The AD9852 is a multifunctional, very high speed device that
targets a wide variety of synthesizer and agile clock applications.
The numerous innovative features contained in the device each
consume incremental power. If enabled in combination, the safe
thermal operating conditions of the device may be exceeded.
Careful analysis and consideration of power dissipation and
thermal management is a critical element in the successful
application of the AD9852 device.
The AD9852 device is specified to operate within the industrial
temperature range of –40°C to +85°C. This specification is con-
ditional, however, such that the absolute maximum junction
temperature of 150°C is not exceeded. At high operating tem-
peratures, extreme care must be taken when operating the device
to avoid exceeding the junction temperature, which could result
in a damaging thermal condition.
Many variables contribute to the operating junction
temperature within the device, including
1. Package style.
2. Selected mode of operation.
3. Internal system clock speed.
4. Supply voltage.
5. Ambient temperature.
The combination of these variables determines the junction
temperature within the AD9852 device for a given set of
operating conditions.
The AD9852 device is available in two package styles: a
thermally enhanced surface-mount package with an exposed
heat sink, and a nonthermally enhanced surface-mount
package. The thermal impedance of these packages is 16°C/W
and 38°C/W, respectively, measured under still-air conditions.
THERMAL IMPEDANCE
The thermal impedance of a package can be thought of as a
thermal resistor that exists between the semiconductor surface
and the ambient air. The thermal impedance of a package is
determined by the package material and its physical dimensions.
The dissipation of the heat from the package is directly depen-
dent on the ambient air conditions and the physical connection
made between the IC package and the PCB. Adequate dissipation
of power from the AD9852 relies upon all power and ground pins
of the device being soldered directly to a copper plane on a PCB.
In addition, the thermally enhanced package of the AD9852ASQ
contains a heat sink on the bottom that must be soldered to a
ground pad on the PCB surface. This pad must be connected to
a large copper plane, which, for convenience, can be the ground
plane. Sockets for either package style of the AD9852 device are
not recommended.
JUNCTION TEMPERATURE CONSIDERATIONS
The power dissipation (PDISS) of the AD9852 device in a given
application is determined by many operating conditions. Some
of the conditions have a direct relationship with PDISS, such as
supply voltage and clock speed, but others are less deterministic.
The total power dissipation within the device and its effect on
the junction temperature must be considered when using the
device. The junction temperature of the device is given by
Junction Temperature = (Thermal Impedance ×
Power Consumption) + Ambient Temperature
Given that the junction temperature should never exceed 150°C
for the AD9852 and that the ambient temperature can be 85°C,
the maximum power consumption is 1.7 W for the AD9852AST
and 4.1 W for the AD9852ASQ (thermally enhanced package).
Factors affecting the power dissipation are described is the
Supply Voltage section.
Supply Voltage
Because PDISS = V × I, the supply voltage obviously affects power
dissipation and junction temperature. Users should design for
3.3 V nominally; however, the device is guaranteed to meet
specifications over the full temperature range and the supply
voltage range of 3.135 V to 3.465 V.
Clock Speed
Clock speed directly and linearly influences the total power
dissipation of the device, and, therefore, the junction temperature.
As a rule, the user should select the lowest internal clock speed
possible to support a given application to minimize power
dissipation. Typically the usable frequency output bandwidth
from a DDS is limited to 40% of the clock rate to keep
reasonable requirements on the output low-pass filter. For the
typical DDS application, the system clock frequency should be
2.5 times the highest desired output frequency.
Mode of Operation
The selected mode of operation for the AD9852 has a great
influence on total power consumption. The AD9852 offers
many features and modes, each of which imposes an additional
power requirement. The collection of features contained in the
AD9852 targets a wide variety of applications, and the device
was designed under the assumption that only a few features
would be enabled for any given application. In fact, the user
must understand that enabling multiple features at higher clock
speeds can cause the maximum junction temperature of the die
to be exceeded. This can severely limit the long-term reliability
of the device. Figure 59 and Figure 60 show the power require-
ments associated with the individual features of the AD9852.
These charts should be used as a guide in determining how to
optimize the AD9852 for reliable operation in a specific
application.
AD9852
Rev. D | Page 40 of 52
As can be seen in Figure 60, the inverse sinc filter function
requires a significant amount of power. As an alternative
approach to maintaining flatness across the output bandwidth,
the digital multiplier function can be used to adjust the output
signal level at a dramatic savings in power consumption.
Careful planning and management when using this feature set
minimizes power dissipation and avoids exceeding junction
temperature requirements within the IC.
Figure 59 shows the supply current consumed by the AD9852
over a range of frequencies for two possible configurations. All
circuits enabled means the output scaling multiplier, the inverse
sinc filter, both DACs, and the on-board comparator are all
enabled. Basic configuration means the output scaling
multipliers, the inverse sinc filter, the control DAC, and the on-
board comparator are all disabled.
Figure 60 shows the approximate current consumed by each of
the four functions.
FREQUENCY (MHz)
1400
20
SUPPLY CURRENT (mA)
1200
1000
800
600
400
200
060 100 140 180 220 260 300
ALL CIRCUITS ENABLED
BASIC CONFIGURATION
00634-059
Figure 59. Current Consumption vs. Clock Frequency
FREQUENCY (MHz)
20 60 100 140 180 220 260 300
450
SUPPLY CURRENT (mA)
400
350
300
250
200
150
0
100
50
CONTROL DAC
500
INVERSE SINC FILTER
OUTPUT SCALING
MULTIPLIERS
COMPARATOR
00634-060
Figure 60. Current Consumption by Function vs. Clock Frequency
AD9852
Rev. D | Page 41 of 52
EVALUATION OF OPERATING CONDITIONS
The first step in applying the AD9852 is to select the internal
clock frequency. Clock frequency selections above 200 MHz
require the thermally enhanced package (AD9852ASQ); clock
frequency selections of 200 MHz and below can allow the use of
the standard plastic surface-mount package, but more
information is needed to make this determination.
The second step is to determine the maximum required oper-
ating temperature for the AD9852 in the given application.
Subtract this value from 150°C, which is the maximum junction
temperature allowed for the AD9852. For the extended indust-
rial temperature range, the maximum operating temperature is
85°C, which results in a difference of 65°C. This is the maxi-
mum temperature gradient the device can experience due to
power dissipation.
The third step is to divide this maximum temperature gradient
by the thermal impedance to arrive at the maximum power
dissipation allowed for the application. For this example, 65°C
divided by both versions of the AD9852 package’s thermal
impedances of 38°C/W and 16°C/W yields a total power
dissipation limit of 1.7 W and 4.1 W, respectively. This means
for a 3.3 V nominal power supply voltage, the current consumed
by the device under full operating conditions must not exceed
515 mA in the standard plastic package and 1242 mA in the
thermally enhanced package. The total set of enabled functions
and operating conditions of the AD9852 application must
support these current consumption limits.
Figure 59 and Figure 60 can be used to determine the suitability
of a given AD9852 application vs. power dissipation requirements.
These graphs assume that the AD9852 device is soldered to a
multilayer PCB according to the recommended best manufacturing
practices and procedures for the given package type. This ensures
that the specified thermal impedance specifications are achieved.
THERMALLY ENHANCED
PACKAGE MOUNTING GUIDELINES
This section gives general recommendations for mounting the
thermally enhanced exposed heat sink package (AD9852ASQ)
to printed circuit boards. The exceptional thermal character-
istics of this package depend entirely on proper mechanical
attachment.
Figure 61 depicts the package’s bottom view and the dimensions
of the exposed heat sink. A solid conduit of solder must be
established between this pad and the surface of the PCB.
C
O
U
N
T
R
Y
14mm
10mm
00634-061
Figure 61. Bottom View of Exposed Heat Sink
Figure 62 depicts a general PCB land pattern for such an
exposed heat sink device. Note that this pattern is for a 64-lead
device, not an 80-lead device, but the relative shapes and
dimensions still apply. In this land pattern, a solid copper plane
exists inside the individual lands for device leads. Note that the
solder mask opening is conservatively dimensioned to avoid any
assembly problems.
SOLDER MASK
OPENING
THERMAL LAND
00634-062
Figure 62. General PCB Land Pattern
AD9852
Rev. D | Page 42 of 52
The thermal land itself must be able to distribute heat to an
even larger copper plane, such as an internal ground plane.
Vias must be uniformly provided over the entire thermal pad to
connect to this internal plane. A proposed via pattern is shown
in Figure 63. Via holes should be small (12 mil, 0.3 mm), so
they can be plated and plugged. These provide the mechanical
conduit for heat transfer.
00634-063
Figure 63. Proposed Via Pattern
Finally, a proposed stencil design is shown in Figure 64 for
screen solder placement. If vias are not plugged, wicking occurs,
which displaces solders away from the exposed heat sink, and
the necessary mechanical bond is not established.
00634-064
Figure 64. Proposed Solder Placement
AD9852
Rev. D | Page 43 of 52
EVALUATION BOARD
An evaluation board is available that supports the AD9852 DDS
devices. This evaluation board consists of a PCB, software, and
documentation to facilitate bench analysis of the performance
of the AD9852 device. It is recommended that users of the
AD9852 familiarize themselves with the operation and
performance capabilities of the device with the evaluation
board. The evaluation board should also be used as a PCB
reference design to ensure optimum dynamic performance
from the device.
EVALUATION BOARD INSTRUCTIONS
The AD9852/AD9854 Rev. E evaluation board includes either
an AD9852ASQ or AD9854ASQ IC.
The ASQ package permits 300 MHz operation by virtue of its
thermally enhanced design. This package has a bottom-side
heat slug that must be soldered to the ground plane of the
PCB directly beneath the IC. In this manner, the evaluation
board PCB ground plane layer extracts heat from the AD9852
or AD9854 IC package. If device operation is limited to 200 MHz
and below, the AST package without a heat slug may be used in
customer installations over the full temperature range. The AST
package is less expensive than the ASQ package, and those costs
are reflected in the price of the IC.
Evaluation boards for both the AD9852 and AD9854 are
identical except for the installed IC.
To assist in proper placement of the pin-header shorting
jumpers, the instructions refer to direction (left, right, top,
bottom) as well as header pins to be shorted. Pin 1 for each
3-pin header has been marked on the PCB corresponding with
the schematic diagram. When following these instructions,
position the PCB so that the PCB text can be read from left to
right. The board is shipped with the pin headers configuring the
board as follows:
1. REFCLK for the AD9852 or AD9854 is configured as
differential. The differential clock signals are provided by
the MC100LVEL16D differential receiver.
2. Input clock for the MC100LVEL16D is single ended via
J25. This signal may be 3.3 V CMOS or a 2 V p-p sine wave
capable of driving 50 Ω (R13).
3. Both DAC outputs from the AD9852 or AD9854 are
routed through the two 120 MHz elliptical LP filters, and
their outputs are connected to J7 (Q or control DAC) and
J6 (I or cosine DAC).
4. The board is set up for software control via the printer port
connector.
5. The DAC’s output currents are configured for 10 mA.
GENERAL OPERATING INSTRUCTIONS
Load the CD software onto the PC’s hard disk. Connect a
printer cable from the PC to the AD9852 evaluation board
printer port connector labeled J11. The current software
(Version 1.72) supports Windows® 95 or better operating
systems.
Hardware Preparation
Using the schematic in conjunction with these instructions
helps acquaint the user with the electrical functioning of the
evaluation board.
Attach power wires to the connector labeled TB1 using the
screw-down terminals. This is a plastic connector that press-fits
over a 4-pin header soldered to the board. Table 13 shows
connections to each pin.
DUT = device under test.
Table 13. Power Requirements for DUT Pins
AVDD 3.3 V DVDD 3.3 V VCC 3.3 V Ground
All DUT
analog pins
All DUT
digital pins
All other
devices
All devices
Clock Input, J25
Attach REFCLK to the clock input, J25. This is actually a single-
ended input that is routed to the MC100LVEL16D for conversion
to differential PECL output. This is accomplished by attaching a
2 V p-p clock or sine wave source to J25. This is a 50 Ω impedance
point set by R13. The input signal is ac-coupled and then biased
to the center-switching threshold of the MC100LVEL16D. To
engage the differential clocking mode of the AD9852, Pin 2 and
Pin 3 (the bottom two pins) of W3 must be connected with a
shorting jumper.
The signal arriving at the AD9852 is called the reference clock.
If the user chooses to engage the on-chip PLL clock multiplier,
this signal is the reference clock for the PLL, and the multiplied
PLL output becomes the system clock. If the user chooses to
bypass the PLL clock multiplier, the reference clock that has
been supplied is directly operating the AD9852 and is,
therefore, the system clock.
Three-State Control
Three of the following control or switch headers must be
shorted to allow the provided software to control the evaluation
board via Printer Port Connector J11: W9, W11, W12, W13,
W14, and W15.
AD9852
Rev. D | Page 44 of 52
Programming
If a PC and ADI software are not used to program the AD9852,
Headers W9, W11, W12, W13, W14, and W15 should be
opened (shorting jumpers removed). This effectively detaches
the PC interface and allows J10 (the 40-pin header) and J1 to
assume control without bus contention. Input signals on J10
and J1 going to the AD9852 should be 3.3 V CMOS logic levels.
Low-Pass Filter Testing
The purpose of 2-pin headers, W7 and W10 (associated with J4
and J5), is to allow the two 50 Ω, 120 MHz filters to be tested
during PCB assembly without interference from other circuitry
attached to the filter inputs. Normally, a shorting jumper is attached
to each header to allow the DAC signals to be routed to the filters.
If the user wishes to test the filters, the shorting jumpers at W7
and W10 should be removed and 50 Ω test signals applied at J4
and J5 inputs to the 50 Ω elliptic filters. The user can refer to the
provided schematic (Figure 65 and Figure 66) and the following
sections to properly position the remaining shorting jumpers.
Observing the Unfiltered IOUT1 and the Unfiltered
IOUT2 DAC Signals
The unfiltered DAC outputs can be observed at J5 (the I or
cosine signal) and J4 (the Q or control DAC signal). The
procedure below simply routes the two 50 Ω terminated analog
DAC outputs to the SMB connectors and disconnects any other
circuitry. The raw DAC outputs may appear as a series of
quantized (stepped) output levels that may not resemble a sine
wave until they have been filtered. The default 10 mA output
current develops a 0.5 V p-p signal across the on-board
50 Ω termination. If your observation equipment offers
50 Ω inputs, the DAC develops only 0.25 V p-p due to the
double termination.
1. Install shorting jumpers at W7 and W10.
2. Remove shorting jumper at W16.
3. Remove shorting jumper from the W1 3-pin header.
4. Install shorting jumper on Pin 1 and Pin 2 (bottom two
pins) of the W4 3-pin header.
If using the AD9852 evaluation board, IOUT2, the control DAC
output is under user control through the serial or parallel ports.
The 12-bit, twos complement value(s) is/are written to the
control DAC register that sets the IOUT2 output to a static dc
level. Allowable hexadecimal values are 7FF (maximum) to 800
(minimum), with all 0s being midscale. Rapidly changing the
contents of the control DAC register (up to 100 MSPS) allows
IOUT2 to assume any programmable waveform.
Observing the Filtered IOUT1 and the Filtered IOUT2
The filtered I and Q (or control) DAC outputs may be observed
at J6 (the I signal) and J7 (the Q or control signal). This places
the 50 Ω (input and output Z) low-pass filters in the I and Q (or
control) DAC pathways to remove images and aliased harmonics
and other spurious signals above approximately 120 MHz.
These signals appear as nearly pure sine waves and 90° out of
phase with each other. These filters are designed with the
assumption that the system clock speed is at or near maximum
(300 MHz). If the system clock speed is much less than 300 MHz,
for example 200 MHz, it is possible, or inevitable, that unwanted
DAC products other than the fundamental signal are passed by
the low-pass filters.
If an AD9852 evaluation board is being used, any reference to
the Q signal should be interpreted to mean control DAC.
1. Install shorting jumpers at W7 and W10.
2. Install shorting jumper at W16.
3. Install shorting jumper on Pin 1 and Pin 2 (bottom two
pins) of the W1 3-pin header.
4. Install shorting jumper on Pin 1 and Pin 2 (bottom two
pins) of the W4 3-pin header.
5. Install shorting jumper on Pin 2 and Pin 3 (bottom two
pins) of the W2 and W8 3-pin headers.
Observing the Filtered IOUT1 and the Filtered IOUT1
The filtered I DAC outputs can be observed at J6 (the true
signal) and J7 (the complementary signal). This places the
120 MHz low-pass filters in the true and complementary
output paths of the I DAC to remove images and aliased
harmonics and other spurious signals above approximately
120 MHz. These signals appear as nearly pure sine waves and
180° out of phase with each other. If the system clock speed is
much less than 300 MHz, for example 200 MHz, it is possible,
or inevitable, that unwanted DAC products other than the
fundamental signal are passed by the low-pass filters.
1. Install shorting jumpers at W7 and W10.
2. Install shorting jumper at W16.
3. Install shorting jumper on Pin 2 and Pin 3 (top two pins)
of the W1 3-pin header.
4. Install shorting jumper on Pin 2 and Pin 3 (top two pins)
of the W4 3-pin header.
5. Install shorting jumpers on Pin 2 and Pin 3 (bottom two
pins) of the W2 and W8 3-pin headers.
Connecting the High Speed Comparator
To connect the high speed comparator to the DAC output
signals, either the quadrature filtered output configuration
(AD9854 only) or the complementary filtered output configuration
outlined above (both AD9854 and AD9852) can be chosen. Follow
Step 1 through Step 4 for either filtered configuration (see the
Observing the Filtered IOUT1 and the Filtered IOUT2 section
and the Observing the Filtered IOUT1 and the Filtered IOUT1B
section). Then install a shorting jumper on Pin 1 and Pin 2 (the
top two pins) of the W2 and W8 3-pin headers.
AD9852
Rev. D | Page 45 of 52
This additional step reroutes the filtered signals away from their
output connectors (J6 and J7) and to the 100 Ω configured
comparator inputs. This sets up the comparator for differential
input without control of the comparator output duty cycle. The
comparator output duty cycle should be close to 50% in this
configuration.
The user may elect to change RSET Resistor R2 from 3.9 kΩ to
1.95 kΩ to receive a more robust signal at the comparator
inputs. This decreases jitter and extends the comparator’s
operating range. This can be accomplished by installing a
shorting jumper at W6, which provides a second 3.9 kΩ chip
resistor (R20) in parallel with that provided by R2. This boosts
the DAC output current from 10 to 20 mA and doubles the
peak-to-peak output voltage developed across the loads.
Single-Ended Configuration
To connect the high speed comparator in a single-ended
configuration so that the duty cycle or pulse width can be
controlled, a dc threshold voltage must be present at one of the
comparator inputs. This voltage can be supplied using the
control DAC. A 12-bit, twos complement value is written to the
control DAC register that sets the IOUT2 output to a static dc
level. Allowable hexadecimal values are 7FF (maximum) to 800
(minimum), with all 0s being midscale. The IOUT1 channel
continues to output a user-programmable, filtered sine wave.
These two signals are routed to the comparator using the W2
and W8 3-pin header switches. Users must be in the configura-
tion described in the Observing the Filtered IOUT1 and the
Filtered IOUT2 section. Follow Step 1 through Step 4 in this
section, and then install the shorting jumper on Pin 1 and Pin 2
(top two pins) of the W2 and W8 3-pin header switches.
The user can elect to change RSET Resistor R2 from 3.9 kΩ to
1.95 kΩ to receive a more robust signal at the comparator inputs.
This decreases jitter and extends the comparator’s operating range.
The user can accomplish this by installing a shorting jumper at
W6, which provides a second 3.9 kΩ chip resistor (R20) in
parallel with that provided by R2.
USING THE PROVIDED SOFTWARE
The software is provided on a CD, along with a brief set of
instructions. Use the instructions in conjunction with the
AD9852 or AD9854 data sheet and the AD9852 or AD9854
evaluation board schematic.
The CD-ROM contains the following:
• The AD9852/AD9854 evaluation software
• AD9852 data sheet
• AD9852 evaluation board schematics
• AD9852 PCB layout
Several numerical entries, such as frequency and phase
information, require pressing ENTER to register this
information. For example, if a new frequency is input and
nothing happens when the Load button is clicked, it is probably
because ENTER was not pressed after inputting the new
information.
1. Typical operation of the AD9852/AD9854 evaluation
board begins with a master reset. After this reset, many of
the default register values are depicted in the software
control panel. The reset command sets the DDS output
amplitude to minimum and 0 Hz, 0 phase offset, as well as
other states that are listed in the Register Layout table
(Tabl e 8 for AD9852).
2. The next programming block should be the reference clock
and multiplier since this information is used to determine
the proper 48-bit frequency tuning words that are entered
and calculated later.
3. The output amplitude defaults to the 12-bit, straight binary
multiplier values of the I or cosine multiplier register of
000 hex, and no output (dc) should be seen from the DAC.
Set the multiplier amplitude in the Output Amplitude
window to a substantial value, such as FFF hex. The digital
multiplier can be bypassed by selecting the Output
Amplitude is always Full-Scale box, but experience has
shown that doing so does not result in the best spurious-
free dynamic range (SFDR). The best SFDR, as much as
11 dB better, is obtained by routing the signal through the
digital multiplier and reducing the multiplier amplitude.
For instance, FC0 hex produces less spurious signal
amplitude than FFF hex. If SFDR must be maximized, this
exploitable and repeatable phenomenon should be
investigated in the user’s application. This phenomenon is
more readily observed at higher output frequencies, where
good SFDR becomes more difficult to achieve.
4. Refer to this data sheet and the evaluation board schematic
(Figure 65 and Figure 66) to understand all the functions of
the AD9852 available to the user and to gain an understanding
of how the software responds to programming commands.
Applications assistance is available for the AD9852, the AD9852
evaluation board, and all other products of Analog Devices, Inc.
Please call 1-800-ANALOGD or visit www.analog.com/dds.
AD9852
Rev. D | Page 46 of 52
Table 14. AD9852/AD9854 Customer Evaluation Board (AD9852 PCB > U1 = AD9852ASQ, AD9854 PCB > U1 = AD9854ASQ)
Number Quantity REFDES Device Package Value Mfg. Part No.
1 3 C1, C2, C45 CAP 0805 0.01 μF
2 21 C7, C8, C9, C10, C11, C12, C13, C14,
C16, C17, C18, C19, C20, C22, C23,
C24, C26, C27, C28, C29, C44
CAP 0603 0.1 μF
3 2 C4, C37 CAP 1206 27 pF
4 2 C5, C38 CAP 1206 47 pF
5 3 C6, C21, C25 BCAPT TAJD 10 μF
6 2 C30, C39 CAP 1206 39 pF
7 2 C31, C40 CAP 1206 22 pF
8 2 C32, C41 CAP 1206 2.2 pF
9 2 C33, C42 CAP 1206 12 pF
10 2 C34, C43 CAP 1206 8.2 pF
11 9 J1, J2, J3, J4, J5, J6, J7, J25, J26 SMB STR-PC MNT ITT Industries
B51-351-000220
12 16 J8, J9, J11, J12, J13, J14, J15, J16, J17,
J18, J19, J20, J21, J22, J23, J24
W HOLE
13 1 J10 Dual-row header 40 pins SAMTEC
TSW-120-23-L-D
14 4 L1, L2, L3, L5 IND-COIL 1008CS 68 nH COILCRAFT 1008CS-
680XGBB
15 2 L4, L6 IND-COIL 1008CS 82 nH COILCRAFT 1008CS-
820XGBB
16 2 R2, R20 RES 1206 3.9 kΩ
17 2 R3, R7 RES 1206 25 Ω (24.9 Ω, 1%)
18 1 R4 RES 1206 1.3 kΩ
19 4 R1, R5, R6, R11, R12, R13 RES 1206 50 Ω (49.9 Ω, 1%)
20 1 R8 RES 1206 2 kΩ
21 2 R9, R10 RES 1206 100 Ω
22 4 R15, R16, R17, R18 RES 1206 10 kΩ
23 1 RP1 RES network SIP-10P 10 kΩ Bourns 4610X-101-
103
24 1 TB1 Terminal 4-position WIELAND
Block & pins 25.602.2453.0 block
Z5.530.3425.0 pins
25 1 U1 AD9852 or AD9854 80 LQFP AD9852ASQ or
AD9854ASQ
26 1 U2 74HC125 14 SO1C SN74HC125D
27 1 U3 MC100LVEL16D 8 SO1C MC100LVEL16D
28 4 U4, U5, U6, U7 74HC14 14 SO1C SN74HC14D
29 3 U8, U9, U10 74HC574 20 SO1C SN74HC574DW
30 1 J11 36-pin connector AMP 552742-1
31 6 W1, W2, W3, W4, W8, W17 3-pin jumper SAMTEC
32 10 W6, W7, W9, W10, W11, 2-pin jumper SAMTEC
W12, W13, W14, W15, W16
33 2 Self-tapping screw 4–40, Philips,
round head
34 4 Rubber Square 3M
Bumper Black SJ-5018SPBL
35 1 AD9852/AD9854 PCB GSO2669 Rev. E
36 2 R14, R19 0 Ω jumper 1206 0 Ω
37 4 Pin socket AMP 5-330808-6
38 1 Y1 (not supplied) XTAL COSC (not supplied)
AD9852
Rev. D | Page 47 of 52
RD/CS
D7
D6
D5
D4
D3
D2
D1
D0
DVDD1
DVDD2
DGND1
DGND2
NC
ADDR5
ADDR4
ADDR3
A2/IO RESET
A1/SDO
A0/SDIO
UPDCLK
U1
AD9852
TOP VIEW
(Not to Scale)
PLLVDD
PLLGND
NC4
NC3
RSET
DACBYPASS
AVDD2
AGND2
IOUT2
IOUT2
AVDD
IOUT1
IOUT1
AGND
GND2
COMPVDD
VINN
VINP
GND
COMPGND
PLLFLT
GND3
NC5
DIFFCLKEN
CLKVDD
CLKGND
GND4
REFCLK
SPSELECT
MRESET
OPTGND
DVDD6
DVDD7
DGND6
DGND7
DGND8
DGND9
DVDD8
DVDD9
COUTGND2
COUTGND
COUTVDD2
COUTVDD
VOUT
NC2
DACDGND2
DACDGND
DACDVDD2
DACDVDD
OSK
FSK/BPSK/HOLD
DGND5
DGND4
DVDD5
DVDD4
DVDD3
RD
DGND3
WR
J6
J8
J16
J17
J18
J19
J20
J21
J22
J24 J23
J14
J13
J12
J11 GND
J15
W6 R2
3.9kΩ
R20
3.9kΩ
AVDD
C45
0.01μF
R1
50Ω
J4
W7
W1 1
GND
GND AVDD
R3
25Ω
W10 W16
D7
D6
D5
D4
D3
D2
D1
D0
DVDD
DVDD
GND
GND
A5
A4
A3
A2/IO RESET
A1/SDO
A0/SDIO
I/O UD CLK
AVDD
AVDD
AVDD
DVDD
DVDD
DVDD
OSK
AVDD
AVDD
AVDD
AVDD
AVDD
DVDD
AVDD
GND
DVDD
W3
R4
1.3kΩ
C1
0.01μF
CLK8
CLK
PMODE
RESET
GND GND
DVDD
GND R13
50Ω
C2
0.01μF
OUT GND
NC3.3V
MC100LVEL16
L5
68nH
VEE
VBB
VCC
U3
Y1
D
D
Q
Q
DVDD
14
78
1
2
37
6
C25
10μF
C21
10μF
C24
0.1μFC23
0.1μFC22
0.1μFC27
0.1μFC8
0.1μFC44
0.1μF
GND
DVDD
J10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
UDCLK
WR
RD
PMODE
OSK
RESET
D7
D6
D5
D4
D3
D2
D0
D1
120MHz LOW-PASS FILTER
120MHz LOW-PASS FILTER
W4
R5
50Ω
W17
R8
2kΩ
1DVDD
R11
50Ω
R12
50Ω
R19
0Ω
R14
0Ω
CLKB
CLK
J3
GND
C37
27pF C38
47pF C39
39pF C40
22pF
W8
1
L1
68nH
L6
82nH
C41
2.2pF C42
12pF C43
8.2pF
C31
22pF
C30
39pF
C5
47pF
C4
27pF
L4
82nH L2
68nH
C32
2.2pF C33
12pF C34
8.2pF GND
J6
W2
1
GND
1R7
25Ω
R6
50Ω
FDATA
548
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND GND GND
GNDGNDGNDGND
GND
GND
GND
NC = NO CONNECT
L3
68nH
R9
100Ω
GND
R10
100Ω
GND
1
GND
GND
GND
GND
GND
GND
TB1
DVDD
AVDD
VCC
1
2
3
4
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
GND
GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
J26
GND
J1
GND
J5
GND GND
J6
GND
J25
C6
10μFC7
0.1μFC29
0.1μFC9
0.1μFC10
0.1μFC11
0.1μFC13
0.1μF
GND
AVDD
C20
0.1μFC19
0.1μFC18
0.1μFC14
0.1μFC26
0.1μFC28
0.1μF
GND
VCC
C12
0.1μF
C17
0.1μFC16
0.1μF
J2
GND
WR/SCLK
REFCLK
00634-065
Figure 65. Evaluation Board Schematic
AD9852
Rev. D | Page 48 of 52
9
8
7
6
5
4
3
2
12
13
14
15
16
17
18
19
8D
1D
GND: 10
11
1
EN
74HC574
C1 VCC: 20
D0
D1
D2
D3
D4
D5
D6
D7
U8
9
8
7
6
5
4
3
2
12
13
14
15
16
17
18
19
8D
1D
11
1
EN
74HC574
C1
U9
1
3
5
9
11
13
7
74HC14
14
VCC GND
2
4
6
8
10
12
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
GNDVCC
U5
4
6
8
3
5
9
2
7
1
J11
36-PIN
CONNECTOR
GND:[19:30]
11
13
10
12
14
A0
C0
A1
A2
A3
A4
A5
A6
A7
B6
B7
B5
B4
C1
C2
B3
C3
VCC
R15
10kΩ
R16
10kΩ
R17
10kΩ
GND: 10
VCC: 20
9
8
7
6
5
4
3
2
12
13
14
15
16
17
18
19
8D
1D
11
1
EN
74HC574
C1
U10 VCC: 20
ADDR5
ADDR4
ADDR3
ADDR2
VCC
GND: 10
WR
RD
RESET
UDCLK
PMODE
ORAMP
FDATA
74HC125
GND
1G
1A
1Y
2G
2A
2Y
VCC
4G
4A
4Y
3G
3A
3Y
U2
GND
1
2
3
4
5
6
7
13
12
11
10
9
8
14
VCC
W11
ADDR1
ADDR0 W14
W12
W13
W9
VCC
R18
10kΩW15
VCC
VCC RP1
10kΩ
1359
246810
7
31
32
36
VCC
VCC
VCC
GND
1
3
5
9
11
13
7
74HC14
14
VCC GND
2
4
6
8
10
12
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
GNDVCC
U6
1
3
5
9
11
13
7
74HC14
14
VCC GND
2
4
6
8
10
12
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
GNDVCC
U4
VCC
VCC
1
3
5
9
11
13
7
74HC14
14
VCC GND
2
4
6
8
10
12
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
GNDVCC
U7
00634-066
Figure 66. Evaluation Board Schematic
AD9852
Rev. D | Page 49 of 52
00634-067
Figure 67. Assembly Drawing
00634-068
Figure 68. Top Routing Layer, Layer 1
AD9852
Rev. D | Page 50 of 52
00634-070
Figure 69. Ground Plane Layer, Layer 2
00634-069
Figure 70. Power Plane Layer, Layer 3
AD9852
Rev. D | Page 51 of 52
00634-071
Figure 71. Bottom Routing Layer, Layer 4
AD9852
Rev. D | Page 52 of 52
OUTLINE DIMENSIONS
COMP LIANT TO JEDE C S T ANDARDS M S-026-BEC- HD
0.65
BSC 0.38
0.32
0.22
16.00
BSC SQ
61 80 1
21 20
40
41
60
14.00
BSC S Q
1.60
MAX
VIEW A
SEATING
PLANE
0.75
0.60
0.45
0.15
0.05 0.10
COPLANARITY
1.45
1.40
1.35
7°
0°
0.20
0.09
VIEW A
ROT ATED 90° CCW
6180
1
21
20 40 41
60
TOP VIEW
(PINS DOWN)
13°
12°
11°
PIN 1
EXPOSED
HEAT S INK
(CENTERED)
BOTTO M VIEW
(PINS UP)
4.45
4.30 ( 4 P LCS)
4.15
4.05
3.90 ( 4 P LCS)
3.75
10.15
10.00 S Q
9.85
121905-0
Figure 72. 80-Lead Low Profile Quad Flat Package, Edquad [LQFP_ED]
(SQ-80-2)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MS-026-BEC
1.45
1.40
1.35
0.15
0.05
0.20
0.09
0.10 MAX
COPLANARITY
VIEW A
ROTATED 90° CCW
SEATING
PLANE
7°
3.5°
0°
61 60
180
20 41
21 40
VIEW A
1.60
MAX
0.75
0.60
0.45
16.20
16.00 SQ
15.80
14.20
14.00 S
Q
13.80
0.65
BSC
LEAD PITCH
0.38
0.32
0.22
TOP VIEW
(PINS DOWN)
PIN 1
Figure 73. 80-Lead Low Profile Quad Flat Package [LQFP]
(ST-80-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9852ASQ –40°C to +85°C 80-Lead Low Profile Quad Flat Package, Edquad [LQFP_ED] SQ-80-2
AD9852ASQZ1–40°C to +85°C 80-Lead Low Profile Quad Flat Package, Edquad [LQFP_ED] SQ-80-2
AD9852AST –40°C to +85°C 80-Lead Low Profile Quad Flat Package [LQFP] ST-80-2
AD9852ASTZ1–40°C to +85°C 80-Lead Low Profile Quad Flat Package [LQFP] ST-80-2
AD9852/PCB Evaluation Board
1 Z = Pb-free part.
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registered trademarks are the property of their respective owners.
C00634–0–12/05(D)
