I|/CATALYST Preliminary SEMICQAONDUCTEAR CAT28LV65 64K-Bit CMOS E?PROM FEATURES B 3.0V to 3.6V Supply @ CMOS and TTL Compatible /O m@ Read Access Times: w Automatic Page Write Operation: 250/300/350ns - 1 to 32 Bytes in 5ms m Low Power CMOS Dissipation: ~ Page Load Timer - Active: 8 mA Max. @ End of Write Detection: Standby: 100 LA Max. Toggle Bit &@ Simple Write Operation: - DATA Polling ~On-Chip Address and Data Latches ~RDY Self-Timed Write Cycle with Auto-Clear @ Hardware and Software Write Protection @ Fast Write Cycle Time: @ 100,000 ProgranvErase Cycles - 5ms Max. mw 100 Year Data Retention @ Commercial and Industrial Temperature Ranges DESCRIPTION The CAT28LV65 is a low voltage, low power, CMOS CAT28LV65 features hardware and software write EPROM organized as 8K x 8-bits. It requires a simple protection. interface for in-system programming. On-chip address . . , and data latches, self-timed write cycle with auto-clear The CAT28LV65 is manufactured using Catalyst's ad- and Vcc power up/down write protection eliminate addi- vanced CMOS floating gate technology. Itis designed to tional timing and protection hardware. DATA Polling endure 100,000 program/erase cycles and has a data RDY/BUSY and Toggle status bit signal the start and retention of 100 years. The device is available in JEDEC end of the self-timed write cycle. Additionally, the approved 28-pin DIP, TSOP and SOIC or 32-pin PLCC and TSOP packages. BLOCK DIAGRAM ADDR. BUFFER ROW B,192x8 AsA - E2PROM BAY2 DECODER & LATCHES PRON INAOVERTENT HIGH VOLTAGE ! Yoo WRITE GENERATOR soe Age PROTECTION : ce hoy OE _____-| CONTROL WE LOGIC 71 t VO BUFFERS DATA POLLING, TIMER j| ADY/BUSY & 1 TOGGLE BIT VOg-VO7 ADDR. BUFFER Ag-Ag & LATCHES COLUMN DECODER RDY/BUSY ~ 2BLV65 FO! 1986 by Catalyst Semiconductor, Inc Characteristics subject to change without notice 8-61CAT28LV65 Preliminary PIN CONFIGURATION PIN FUNCTIONS DIP Package (P) SOIC Package (J, K) Pin Name Function Rovieusy ~ 28 B vos ROY@USY Cfo 28 LY Voc Ao~Ai2 Address Inputs AC 3 26 Fine Ai2C{2 27 | We VvOo-V/O7 Data Inputs/Outputs 7 A7(13 26 NC = 4644 25 [1 Ag AgC]4 25 0 Ag CE Chip Enable AsC]5 24 (1 Ag A s(15 24123 Ag md 6 23f Ant Aa J 6 23 An OE Output Enable AgsO}7 22 AgC]7 22 GE WE Write Enable Ag] 8 21 I Ato A2 C4 8 21 Ato A,C)9 20 [CE avcis 20 ce Voc 3.0 to 3.6 V Supply AgX} 10 19 [) WO7 WOgt] 11 18 E vO, Ag C4 10 19 F) VO7 Vss Ground o 6 VOpo CJ 1t 18 [9 vOg VO, C0} 12 17 9 5 WO, 12 17 [4 Ws NC No Connect VO2T 13 16 PF WO4 W213 16 F WO, RDY/BUSY| Ready/BUSY Stat Vggf] 14 15 FP) 03 vss C1 1415 9 03 eady: atus PLCC Package (N) [3 TSOP Top View (8mm x 14mm) (114) fo TSOP Top View (8mm x 20mm) (T) Ny g a oO 32 Oo qqrZ2s|l5 Zz Ag C1410 32 Fr Ag Ay C42 31 PE Ay 4 3 2 1 323130 Ag C113 30 FD As Ag 5 295 Ag Og C44 29 FI Ag A 6 28 A VOy 15 28 FD Az 5 9 VWOo 416 27 FE Ayo Aa] 7 2700 Ant NC or7 26 fr RDY/BUSY AgC] 8 2617) NC Vss 448 25 Fr NC AoC] 9 TOP VIEW 25(9 OE NC C119 24FX Voc Ay F Aro VO3 4410 23 FI NC Ag 5 ce VO4 [44 11 22 3 WE NC Fi VOx or] 12 21-7 NC O7 Og 4 13 20 5 Ag VO [} Og VO7 1 14 19 E35 Ag CE C44 15 18 FE Aq Aio [1116 17 FT OE S8B2838 28LV65 F02 28LV65 FOS TSOP Top View (8mm x 13.4mm) (T13) OF Hrq10 28 A Aig Ady coy2 27 FS Ce Ag (143 26 Fr i Ag 4 25 E39 0g ne cos 245 Ws WE C16 23 3 WO, Vee 7 22 F310, RADY/BUSY 48 21 [73 GND Ayo C49 20 3 0, A7 (410 19 Fr 0, Ag Gott 18 FI WO Ag O12 17 Fr Ay Ay o413 16 A, Ag 414 15 FT Ay 28LV65 FO4 8-62Preliminary CAT28LV65 MODE SELECTION Mode CE WE GE vo Power Read L L Dout ACTIVE Byte Write (WE Controlled) L VS H Din ACTIVE Byte Write (CE Controlled) VS H Din ACTIVE Standby, and Write Inhibit H X High-Z STANDBY Read and Write Inhibit Xx H High-Z ACTIVE CAPACITANCE Ta = 25C, f = 1.0 MHz Symbol Test Max. Units Conditions Cro!) Input/Output Capacitance pF Vvo = OV Cin?) Input Capacitance pF Vin = OV ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias.................. 55C to +125C Storage Temperature ...............008 65C to +150C Voltage on Any Pin with Respect to Ground) ........... -2.0V to +Vcc + 2.0V Vcc with Respect to Ground .............. 2.0V to +7.0V Package Power Dissipation Capability (Ta = 25C) ....cccceeetereees 1.0W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current ooo. 100 mA RELIABILITY CHARACTERISTICS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specifica- tion is not implied. Exposure to any absolute maximum rating for extended periods may affect device perfor- mance and reliability. Symbol Parameter Min. Max. Units Test Method Nenp) Endurance 104 or 105 Cycles/Byte MIL-STD-883, Test Method 1033 Tor) Data Retention 100 Years MIL-STD-883, Test Method 1008 Vzap) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 IeTHO4) | Lateh-Up 100 mA JEDEC Standard 17 Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of lass than 20 ns. Maximum DC valtage on output pins is Vcc +0.5V, which may overshoot to Vcc +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to Voc +1V. 8-63CAT28LV65 Preliminary D.C. OPERATING CHARACTERISTICS Voc = 3.0V to 3.6V, unless otherwise specified. Limits Symbol Parameter Min. | Typ. Max. [Units Test Conditions lec Vcc Current (Operating, TTL) 8 mA CE = OE = Vit, f = 1/tac min, All /Os Open Isac!) Voc Current (Standby, CMOS) 100 yA | CE=Vune, All /Os Open hu Input Leakage Current -1 1 HA Vin = GND to Voc ILo Output Leakage Current -5 5 HA Vout = GND to Vcc, CE =Vin Vin) High Level Input Voltage 2 Voc +0.3] V ViL Low Level Input Voitage -0.3 0.6 Vv Vou High Level Output Voltage 2 Vv lon = -100nA VoL Low Level Output Voltage 0.3 Vv lo. = 1.0mMA Vwi Write Inhibit Voltage 2 Vv Note: (1) Vine = Voc -0.3V to Voc +0.3V. A.C. CHARACTERISTICS, Read Cycle Voc = 3.0V to 3.6V, unless otherwise specified. 28LV65-25 28LV65-30 28LV65-35 Symbol Parameter Min. Max. | Min. Max. | Min. Max. | Units tac Read Cycle Time 250 300 350 ns tce CE Access Time 250 300 350 ns taa Address Access Time 250 300 350 ns toe OE Access Time 100 150 150 ns tz) CE Low to Active Output 0 ns torz'") OE Low to Active Output 0) ns tHz'(2) | CE High to High-Z Output 55 60 60 ns tonz(2) | GE High to High-Z Output 55 60 60 ns ton!) Output Hold from Address Change 0 0 0 ns Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.Preliminary CAT28LV65 Figure 1. A.C. Testing Input/Output Waveform() Vee - 0.3V a0V INPUT PULSE LEVELS xX REFERENCE POINTS 0.0V 0.6V Note: . . FHD FO3 (1) Input rise and fall timas (10% and 90%) < 10 ns. 5096 Figure 2. A.C. Testing Load Circuit (example) Voc 1.8K Davi Device OUTPUT Test 19K T C, = 100 pF CL INCLUDES JIG CAPACITANCE 5096 FHOD Fo4 A.C. CHARACTERISTICS, Write Cycle Vee = 3.0V to 3.6V, unless otherwise specified. 28LV65-25 28LV65-30 28LV65-35 Symbol Parameter Min. Max. | Min. Max. | Min. Max. | Units twe Write Cycle Time 5 5 5 ms tas Address Setup Time 0 0 0 ns taH Address Hold Time 100 100 100 ns tcs CE Setup Time 0 0 0 ns tcn CE Hold Time 0 0 0 ns tewl2) CE Pulse Time 150 150 150 ns toes OE Setup Time 10 10 10 ns toeH OE Hold Time 10 10 10 ns twp(?) WE Pulse Width 150 150 150 ns tos Data Setup Time 100 100 100 ns tou Data Hold Time 0 0 0 ns tinct) Write Inhibit Period After Power-up 5 10 5 10 5 10 ms tarc(N) Byte Load Cycle Time 0.1 100 | 0.1 100 | 0.1 100 us trB WE Low to RDY/BUSY Low 220 220 220 ns Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Awrite pulse of less than 20ns duration will not initiate a write cycle. (3) A timer of duration tg_c max. begins with every LOW to HIGH transition of WE. {f allowed to time out, a page or byte write will begin; however a transition from HIGH to LOW within taic max. stops the timer. 8-65CAT28LV65 Preliminary DEVICE OPERATION Read Data stored in the CAT28LV65 is transferred to the data bus when WE is held high, and both GE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architec- ture can be used to eliminate bus contention in a system environment. Byte Write Awrite cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 5 ms. Figure 3. Read Cycle + trac. _ >} ADDRESS x x jg_- to __>| eT j toE > _ a OE \ }| VIH WE {jt We betOHZ> bona = DATA OUT iene h DATA VALID DATA VALID tAA Figure 4. Byte Write Cycle [WE Controlled] x tas <+1#\ taH tcs ADDRESS AXKX bag KKK h- 'CH 7 | 7 LIM TM WE he-taB HIGH-Z RDY/BUSY My HIGH-Z +t tBLC _>] HIGH-Z DATA OUT DATA IN DATA VALID XKXXEXEKE KKK 28LV65 FOO 8-66Preliminary CAT28LV65 Page Write The page write mode of the CAT28LV65 (essentially an extended BYTE WRITE mode) allows from 1 to 32 bytes of data to be programmed within a single E7PROM write cycle. This effectively reduces the byte-write time by a factor of 32. Following aninitial WRITE operation (WE pulsed low, for twe, and then high) the page write mode can begin by issuing sequential WE pulses, which load the address and data bytes into a 32 byte temporary buffer. The page address where data is to be written, specified by bits As to Aig, is latched on the last falling edge of WE. Each byte within the page is defined by address bits Ao to Ag (which can be loaded in any order) during the first and subsequent write cycles. Each successive byte load cycle must begin within tatc max of the rising edge of the preceding WE pulse. TI here is no page write window limitation as long as WE is pulsed low within tic max. Upon completion of the page write sequence, WE must stay high a minimum of taic max for the internal auto- matic program cycle to commence. This programming cycle consists of an erase cycle, which erases any data that existed in each addressed cell, and a write cycle, which writes new data back into the cell. A page write will only write data to the locations that were addressed and will not rewrite the entire page. Figure 5. Byte Write Cycle [CE Controlled] ADDRESS ROY/BUSY DATA OUT DATA IN os DATA VALID Figure 6. Page Mode Write Cycle OE SELLS I twp tBLC J \S WS ADDRESS XxX x Xx , lL two LAST BYTE BYTEO BYTE1 BYTE 2 BYTE n BYTE n+1 BYTE n+2 5096 FHD F10 8-67CAT28LV65 Preliminary DATA Polling BATA polling is provided to indicate the completion of write cycle. Once a byte write or page write cycle is initiated, attempting to read the iast byte written will output the complement of that data on I/O7 (I/Oo~-V/Os are indeterminate) until the programming cycle is com- plete. Upon completion of the self-timed write cycle, all \/Os will output true data during a read cycle. Toggle Bit In addition to the DATA Polling feature, the device offers an additional method for determining the completion of a write cycle. White a write cycle is in progress, reading data from the device will result in |/Og toggling between one and zero. However, once the write is complete, I/Og stops toggling and valid data can be read from the device. Ready/BUSY (RDY/BUSY) The RDY/BUSY pin is an open drain output which indicates device status during programming. Itis pulled low during the write cycle and released at the end of programming. Several devices may be OR-tied to the same RDY/BUSY line. Figure 7. DATA Polling VF VS VS X_ NY VWO7 lOEH Ft LL tog = a twe Dout = X 5{ Dour = x 5094 FHD Fit Figure 8. Toggle Bit NY toEH _ VOg __ Note: (1) Beginning and ending state of I/Og is indeterminate. 7 rng (1) ; f * two \ fay { VS Loe 28LV65 F12 8-68Preliminary HARDWARE DATA PROTECTION The following is a list of hardware data protection fea- tures that are incorporated into the CAT28LV65. (1) Vec sense provides for write protection when Vcc falls below 2.0V min. (2) A power on delay mechanism, tinit (see AC charac- teristics), provides a 5 to 10 ms delay before a write sequence, after Vcc has reached 2.40V min. (3) Write inhibit is activated by holding any one of OE low, CE high or WE high. CAT28LV65 (4) Noise pulses of fess than 20 ns on the WE or CE inputs will not result in a write cycle. SOFTWARE DATA PROTECTION The CAT28LV65 features a software controlled data protection scheme which, once enabled, requires a data algorithm to be issued to the device before a write can be performed. The device is shipped from Catalyst with the software protection NOT ENABLED (the CAT28LV65 is in the standard operating mode). Figure 9. Write Sequence for Activating Software Data Protection WRITE DATA: AA ADDRESS: 1555 WRITE DATA: 55 ADDRESS: OAAA q WRITE DATA: AQ ADDRESS: 1555 SOFTWARE DATA (1) PROTECTION ACTIVATED WRITE DATA: XX TO ANY ADDRESS WRITE LAST BYTE TO LAST ADDRESS 5094 FHD FOB Note: Figure 10. Write Sequence for Deactivating Software Data Protection WRITE DATA: AA ADORESS: 1555 WRITE DATA: 55 ADDRESS: OAAA WRITE DATA: 80 ADDRESS: 1555 WRITE DATA: AA ADORESS: 1555 WRITE DATA: 55 ADDRESS: OAAA WRITE DATA: 20 ADDRESS: 1555 5094 FHD FOS (1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within tac Max., after SDP activation. 8-698 CAT28LV65 Preliminary To activate the software data protection, the device must be sent three write commands to specific addresses with specific data (Figure 9). This sequence of commands (along with subsequent writes) must adhere to the page write timing specifications (Figure 11). Once this is done, all subsequent byte or page writes to the device must be preceded by this same set of write commands. The data protection mechanism is activated until a deactivate sequence is issued regardless of power on/off transi- tions. This gives the user added inadvertent write pro- tection on power-up in addition to the hardware protec- tion provided. To allow the user the ability to program the device with an E2PROM programmer (or for testing purposes) there is a software command sequence for deactivating the data protection. The six step algorithm (Figure 10) will reset the internal protection circuitry, and the device will return to standard operating mode (Figure 12 provides reset timing). After the sixth byte of this reset sequence has been issued, standard byte or page writing can commence. Figure 11. Software Data Protection Timing DATA AA 55 ADDRESS 1555 OAAA CE WRITES ENABLED . + | WE $094 FHD F13 Figure 12. Resetting Software Data Protection Timing DATA AA 55 80 AA 55 20 twc - SDP ADDRESS 1555 OAAA 1555 1555 OAAA 1555 RESET CE DEVICE UNPROTECTED _ 4 L_ WE 5094 FHD F14 ORDERING INFORMATION [Prefix | Device # | Suffix | CAT 28LV65 -25 TE7 Optional Endurance Temperature Range Tape & Reel Company Blank = 10,000 Cycle Blank = Commercial (0C to +70C) TE?: 500/Reel { H = 100,000 Cycle | = Industrial (-40C to +85C) TE13: 2000/Reel Product Packa Speed Number P: PDI 25: 250ns J: SOIC (JEDEC) 30: 300ns K: SOIC (EIAJ) 35: 350ns N: PLCC T: TSOP (8mmx20mm) T13: TSOP (86mmx13.4mm) 714: TSOP (8mmx14mm) 2BLV65 F17 Notes: (1) The device used in the above example is a CAT28LV65HNI-25TE7 (100,000 Cycle Endurance, PLCC, Industrial temperature, 250 ns Access Time, Tape & Reel). 8-70