AVG Semiconductors Technical Data Octal 3-State Noninverting Transparent Latch Pinouts for the HCS73A and 'HCT573A are identical to the LS573. Both devices are similar in function to the 'HC373A but have the Data inputs on the opposite side of the pack- age from the outputs to facilitate PC board layout. The Output Enable input does not affect the state of the latches, but when the Output Enable is high, all device out- puts are forced to the high-impedence state. Thus, data may be latched even when the outputs are not enabled. * Output Drive Capability: 15 LSTTL Loads + Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2to6 V Low Input Current: 1 WA = DC, AC parameters guaranteed from -55C to 125C DV74HC573A DV74HCT573A N Suffix | Plastic DIP AVG-005 Case TRUTH TABLE (Each Flip-Flop) NONINVERTING Inputs Output ouieuls PIN ASSIGNMENT len eaten a tL | H |H| H OUTPUT ENABLE []1 @ 20/1 Yee L HSL L po [2 i9/ | oo L L X | no change lL J H x x Z or [3 18/ ] a1 X = Don't Care PIN 20 = Voc bz [4 17/] @2 H=High Logic Level OUTPUT PIN 10 = GND 3 Ts i6[] 03 L = Low Logic Level ENABLE = High Impedence b4 Tle6 15[] 4 vs LI? 14, ] 95 06 [|e 13] 06 07 [jo 12[] a7 GND [10 11() LATCH ENABLE ABSOLUTE MAXIMUM RATINGS Maximum ratings are those values beyond which damage to the device may occur. __Symbol | Parameter Value Unit Veo DC Supply Voltage (Referenced to GND) 0.5 to +7.0 Vv Vin DC Input Voltage (Referenced to GND) - 1.5 to Veco +1.5 v Vour DC Output Voltage (Referenced to GND) _ - 0.5 to Vor +0.5 Vv lin DC Input Current, per Pin +20 _ mA lour DC Output Sink/Source Current, per Pin +35 mA lec DC VCC or GND Current per Output Pin +75 mA Pp Power Dissipation in Still Air Plastic DIP 750 mW SOP Package 500 Tstg Storage Temperature 65to +150 | 6% | TL Lead Temperature, 1 mm from Case for 10 Seconds 260 % | Plastic DIP or SOP Package __| DV74HC573A, DV74HCTSTIA 5-198 1-800-AVG-SEMIGUARANTEED OPERATING CONDITIONS _ _ Symbol Parameter Min Max Unit Vec | DC Supply Voltage (Referenced to GND) 2.0 6.0 Vv Vin, Vout | DC Input Voltage, Output Voltage (Referenced to GND) 0 Vee Vv Ta _| Ambient Temperature -55 +125 C tr, ty Input Rise and Fall Time: HC: Vec=2.0V 0 1000 ns HCT: Voec=5.5V/ HC: Vec=4.5V 0 500 HC: Vec=6.0V 0 400 HC 573A Dc ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Vec Guaran Lim Unit (V) | 25C to | <85C | < 125C 55C Vin Minimum High Level Vour = Vec0.1 V 2.0 1.50 1.50 1.50 V Input Voltage Nour! < 20 pA 4.5 315 | 3.15 3.15 6.0 4.20 4.20 4.20 Vin Maximum Low Level Vout =0.1V 2.0 0.50 0.50 0.50 V Input Voltage llourl < 20 pA 45 1.35 1.35 1.35 6.0 1.80 1.80 1.80 Vou | Minimum High Level Vin = Vie 2.0 1.90 1.90 1.90 V Output Voltage lout! <= 20 WA 4.5 4.40 4.40 4.40 6.0 5.90 5.90 5.90 Mir = Her llourl <= 6.0 mA 4.5 3.98 3.64 3.70 llourl < 7.8 mA 6.0 5.48 5.34 5.20 V Vou. Maaimum Low Level VIN = Va. 2.0 0.70 0.10 0.10 y Output Voltage lloum = 20 pA 4.5 0.10 0.10 0.10 6.0 0.10 0.10 0.10 Vin = Vin llour! < 6.0 mA 4.5 0.26 0.33 0.40 V llourl < 7.8 mA 6.0 0.26 0.33 0.40 lina Maximum Input Leakage Current Vin=Viec or GND 6.0 40.1 +1.00 1.00 pA loz Maximum 3-State Current Vin=Vit or Vin 6.0 -0.5 -.0 -10.0 mA (Output in High impedence State) | Vout=Vec or GND lec Maximum Quiescent Supply Vin = Veco or GND 6.0 4 40 160 pA Current lout = 0 wA AC CHARACTERISTICS over full operating conditions (CL = 50 pF, Input t; = t}= 6 ns) Symbol Parameter Vee Guaranteed Limits Unit (v) +25C | < 85C |< 125C to -55C teLH, Maximum Propogation Delay, Input D to Q 2.0 150 190 225 ns TeHL 4.5 30 38 45 6.0 26 33 38 tPLH, Maximum Propogation Delay Time, 2.0 160 200 240 ns PHL Latch Enable to Q 4.5 32 40 48 6.0 27 34 41 IpLz, Maximum Propogation Delay Time, 2.0 150 190 225 ns teHz Output Disable to OQ 4.5 30 38 45 6.0 26 33 38 tpzL, Maximum Propogation Delay Time, 2.0 150 190 225 ns {PZH Output Enable to Q 4.5 30 38 45 6.0 26 33 38 1-800-AVG-SEMI 3+ 199 DV74HC573A, DV74HCTS73A Zs573 symbol Parameter Vee Guaranteed Limits |_-Unit | (v) 425C | <85C < 125C | to -55C | trum, | Maximum Output Transition Time, any Output 20 | 60 75 9 | As |; tH 4.5 12 15 18 6.0 10 13 16 Cin Maximum Input Capacitance 10 10 10 pF _ Cour | Maximum Three-State Output Capacitance 15 15 15 pF Output in High-Impedance State) Power Dissipation Capacitance (Per Butfer) Typical @ 25C, Voc = 5.0 V / Cpp | Used to determine the no-load dynamic power consupmption: 23 pF Po = Ceo Veet + lec Veo TIMING REQUIREMENTS (C, = 50 pF, Input t;= t= 6.0 ns) | Symbol Parameter Vee Guaranteed Limits Unit | ) | ascto-ssc |< 85C < 128C Min Max Min Max Min Max leu Minimum Setup Time, 2.0 50 65 75 ns Input D to Latch Enable 4.5 10 13 16 6.0 9 11 13 th Minimum Hold Time, 2.0 5 5 5 ns Latch Enable to Input D 4.5 5 5 5 6.0 5 5 5 tw Minimum Pulse Width, 2.0 75 95 110 ns Latch Enable 4.5 15 19 22 6.0 13 16 19 HCT 573A DC ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Vec Guaranteed Limits Unit (V) | 425 | <85C |.<125C . 5C Vin Minimum High Level Vout = 0.1V 4.5 2.0 2.0 2.0 V Input Voltage or Voc = 0.1 5.5 2.0 2.0 2.0 llourl = $20 uA Vir Maximum Low Level Vour =0.1V 45 0.8 0.8 0.8 V Input Voltage orVece-O0.1V 5.5 0.8 0.8 0.8 Mout = 20 vA Vou | Minimum High Level Vin = Vi or View 4.5 4.4 4.4 44 V Output Voltage Nour! < 20 wA 55 | 54 5.4 5.4 Vin = Va or Vin llourl = 6 mA 45 | 3.98 3.84 3.7 V Vo. | MaximumLow Level Vin = Vic or Vow 45 0.1 0.1 0.1 Vv Output Voltage Hour! < 20 pA 5.5 0.1 0.1 0.1 Vin = Viv or Ving llourl <6 mA 4.5 0.26 0.33 0.4 Vv ln | Maximum Input Leakage Current | Vout=Vec or GND 5.5 +0.1 +1.0 +1.0 A loz | Maximum 3-State Current ViN=Vic or View 5.5 +0.5 +5.0 +10.0 | pA |__| (Output in High Impedance State) | Vour=Vec or GND Icc | Maximum Quiescent Vin = Vee or GND 5.5 4.0 40,0 160 uA Supply Current LouT = O pA Alce | Additional Quiescent Vin=2.4V, Any One Input >-5C 25C to Supply Current Vin=Voc or GND, Other Inputs 125C lour=OnA 5.5 2.9 24 | mA | DVT4HC573A, OVT4HCTST3A 5-200 1-800-AVG-SEMIAC CHARACTERISTICS (C._ = 50pF, Input t= tr= 6.0 ns) Symbol Parameter Guaranteed Limits | Unit 25C | < a5C <125C to- 55C _ a tIpLH, | Maximum Propogation Delay 30 38 45 ns tpH. | Input D to Output O - tet, | Maximum Propogation Delay Time, 30 38 45 ns tPHL Latch Enable to Q tPLz, Maximum Propogation Delay Time, 28 35 42 ns texz | Output Disable to O tpzL, | Maximum Propogation Delay Time, 28 35 42 ns tPzH Output Enable to tun, | Maximum Output Transition Time, any Output 12 15 16 ns tTHL Ciw | Maximum Input Capacitance 10 10 10 | op Cout | Maximum Three-State Output Capacitance 15 15 15 pF | (Output in High -impedance State) Power Dissipation Capacitance (Per Enabled Output) Typical @ 25C, Vec =5.0 V Cpep | Used to determine the no-load dynamic power consupmption: 48 pF Pp = Cep Voc*f + loc Vec TIMING REQUIREMENTS (Vcc = 5.0 V 10%, Input tr = t} = 6.0 ns. Symbol Parameter Guaranteed Limits Unit 25C to 55C <= 85C < 125C Min Max Min Max | Min | Max ty Minimum Setup Time, 10 13.0 15.0 ns Input D to Latch Enable th Minimum Hold Time, 5.0 5.0 | .0 ns Latch Enable to Input D tw Minimum Pulse Width, Latch Enable 15 19.0 | 22.0 ns SWITCHING WAVEFORMS input and Output Threshold Voltage: VT=50% Veco for HC; 1.3V for HOT VH=Vee for HC, 3V for HCT VH Latch WH Enoble GND ta WH GND High Impedance 7 'o4 Veo TI Vou rr Y aw Nikos Vee High impedance 1-800-AVG-SEMI 5-201 DV74HC573A, DV7T4HCTS734 ELS