ACT8937 (R) Rev 0, 21-Sep-10 Advanced PMU for Samsung S5PC100, S5PC110 and S5PV210 Processors FEATURES GENERAL DESCRIPTION * Optimized for Samsung S5PC100, S5PC110 and The ACT8937 is a complete, cost effective, highlyefficient ActivePMUTM power management solution, optimized for the unique power, voltagesequencing, and control requirements of the Samsung S5PC100, S5PC110 and S5PV210 processors. S5PV210 Processors * * * * * * * Three Step-Down DC/DC Converters Four Low-Dropout Linear Regulators Integrated ActivePathTM Charger I2CTM Serial Interface Advanced Enable/Disable Sequencing Controller Minimal External Components Tiny 5x5mm TQFN55-40 Package - 0.75mm Package Height - Pb-Free and RoHS Compliant This device features three step-down DC/DC converters and four low-noise, low-dropout linear regulators, along with a complete battery charging solution featuring the advanced ActivePathTM system-power selection function. The three DC/DC converters utilize a highefficiency, fixed-frequency (2MHz), current-mode PWM control architecture that requires a minimum number of external components. Two DC/DCs are capable of supplying up to 1100mA of output current, while the third supports up to 1200mA. All four low-dropout linear regulators are highperformance, low-noise, regulators that supply up to 150mA, 150mA, 250mA, and 250mA, respectively. The ACT8937 is available in a compact, Pb-Free and RoHS-compliant TQFN55-40 package. TYPICAL APPLICATION DIAGRAM Innovative PowerTM Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. -1- www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 TABLE OF CONTENTS General Information ..................................................................................................................................... p. 01 Functional Block Diagram ............................................................................................................................ p. 03 Ordering Information .................................................................................................................................... p. 04 Pin Configuration ......................................................................................................................................... p. 04 Pin Descriptions ........................................................................................................................................... p. 05 Absolute Maximum Ratings ......................................................................................................................... p. 07 I2C Interface Electrical Characteristics ........................................................................................................ p. 08 Global Register Map .................................................................................................................................... p. 09 Register and Bit Descriptions ...................................................................................................................... p. 10 System Control Electrical Characteristics.................................................................................................... p. 15 Step-Down DC/DC Electrical Characteristics .............................................................................................. p. 16 Low-Noise LDO Electrical Characteristics ................................................................................................... p. 17 ActivePathTM Charger Electrical Characteristics.......................................................................................... p. 18 Typical Performance Characteristics ........................................................................................................... p. 20 System control information .......................................................................................................................... p. 27 Interfacing with the Samsung S5PV210 ..........................................................................................p. 27 Control Signals ................................................................................................................................. p. 28 Push-Button Control ......................................................................................................................... p. 29 Control Sequences ........................................................................................................................... p. 29 Functional Description ................................................................................................................................. p. 32 I2C Interface ..................................................................................................................................... p. 32 Housekeeping Functions.................................................................................................................. p. 32 Step-Down DC/DC Regulators .................................................................................................................... p. 33 General Description.......................................................................................................................... p. 33 100% Duty Cycle Operation ............................................................................................................. p. 33 Synchronous Rectification ................................................................................................................ p. 33 Soft-Start .......................................................................................................................................... p. 33 Compensation .................................................................................................................................. p. 33 Configuration Options....................................................................................................................... p. 33 OK[ ] and Output Fault Interrupt ....................................................................................................... p. 34 PCB Layout Considerations ............................................................................................................. p. 34 Low-Noise, Low-Dropout Linear Regulators................................................................................................ p. 35 General Description.......................................................................................................................... p. 35 Output Current Limit ......................................................................................................................... p. 35 Compensation .................................................................................................................................. p. 35 Configuration Options....................................................................................................................... p. 35 OK[ ] and Output Fault Interrupt ....................................................................................................... p. 35 PCB Layout Considerations ............................................................................................................. p. 35 ActivePathTM Charger .................................................................................................................................. p. 37 General Description.......................................................................................................................... p. 37 ActivePath Architecture .................................................................................................................... p. 37 System Configuration Optimization .................................................................................................. p. 37 Input Protection ................................................................................................................................ p. 37 Battery Management ........................................................................................................................ p. 37 Charge Current Programming .......................................................................................................... p. 38 Charge-Control State Machine ......................................................................................................... p. 40 Thermal Regulation .......................................................................................................................... p. 41 Charge Safety Timers ...................................................................................................................... p. 41 Charge Status Indicator.................................................................................................................... p. 41 Reverse-Current Protection ............................................................................................................. p. 41 Battery Temperature Monitoring ...................................................................................................... p. 41 TQFN55-40 Package Outline and Dimensions ........................................................................................... p. 43 Innovative PowerTM Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. -2- www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 FUNCTIONAL BLOCK DIAGRAM Active-Semi Innovative PowerTM Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. -3- www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 ORDERING INFORMATION PART NUMBER VOUT1 VOUT2/VSTBY2 VOUT3/VSTBY3 VOUT4 VOUT5 VOUT6 VOUT7 PROCESSOR ACT8937QJ2PQ-T 3.3V 1.3V/1.2V 1.35V/1.2V 1.2V 1.2V 1.2V 3.3V S5PC100 ACT8937QJ21C-T 3.3V 1.1V/1.1V 1.25V/1.25V 1.1V 1.1V 1.1V 3.3V S5PC110 S5PV210 ACT8937QJ206-T 1.8V 1.1V/1.1V 1.25V/1.25V 1.1V 1.1V 1.1V 3.3V S5PC110 S5PV210 : All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means semiconductor products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards. : Standard product options are identified in this table. Contact factory for custom options. Minimum order quantity is 12,000 units. : To select VSTBYx as a output regulation voltage of REGx. Drive VSEL to a logic high. The VSTBYx can be set by software via I2C interface, refer to appropriate sections of this datasheet for VSTBYx setting. : ACT8937QJ2PQ-T is optimized for S5PC100, ACT8937QJ21C-T and ACT8937QJ206-T are optimized for S5PC110 and S5PV210. ACT8937QJ_ _ _-T Active-Semi Product Number Package Code Pin Count Option Code Tape and Reel PIN CONFIGURATION VSYS CHGIN VSYS OUT2 VP2 SW2 GP12 SW1 VP1 NC TOP VIEW REFBP BAT OUT1 BAT GA nSTAT OUT4 SDA Active-Semi OUT5 INL SCL VSEL ACT8937 OUT7 TH OUT6 ISET nPBIN CHGLEV EP LBI nLBO PWREN OUT3 VP3 SW3 GP3 nPBSTAT nIRQ ACIN nRSTO PWRHLD Thin - QFN (TQFN55-40) Innovative PowerTM Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. -4- www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 PIN DESCRIPTIONS PIN NAME DESCRIPTION 1 REFBP 2 OUT1 3 GA 4 OUT4 Output Voltage for REG4. Capable of delivering up to 150mA of output current. Connect a 1.5F ceramic capacitor from OUT4 to GA. The output is discharged to GA with 1.5k when disabled. 5 OUT5 Output Voltage for REG5. Capable of delivering up to 150mA of output current. Connect a 1.5F ceramic capacitor from OUT5 to GA. The output is discharged to GA with 1.5k when disabled. 6 INL 7 OUT7 Output Voltage for REG7. Capable of delivering up to 250mA of output current. Connect a 2.2F ceramic capacitor from OUT7 to GA. The output is discharged to GA with 1.5k when disabled. 8 OUT6 Output Voltage for REG6. Capable of delivering up to 250mA of output current. Connect a 2.2F ceramic capacitor from OUT6 to GA. The output is discharged to GA with 1.5k when disabled. 9 nPBIN Master Enable Input. Drive nPBIN to GA through a 50k resistor to enable the IC, drive nPBIN directly to GA to assert a manual reset condition. Refer to the nPBIN Input section for more information. nPBIN is internally pulled up to VSYS through a 35k resistor. 10 PWRHLD Power Hold Input. Refer to the Control Sequences section for more information. 11 nRSTO Active Low Reset Output. See the nRSTO Output section for more information. 12 nIRQ 13 nPBSTAT 14 GP3 Power Ground for REG3. Connect GA, GP12, and GP3 together at a single point as close to the IC as possible. 15 SW3 Switching Node Output for REG3. Connect this pin to the switching end of the inductor. 16 VP3 Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close as possible to the IC. 17 OUT3 Output Feedback Sense for REG3. Connect this pin directly to the output node to connect the internal feedback network to the output voltage. 18 PWREN 19 nLBO 20 LBI 21 ACIN 22 CHGLEV Charge Current Selecting Input. See the Charge Current Programming section for more information. 23 ISET Charge Current Set. Program the maximum charge current by connecting a resistor (RISET) between ISET and GA. See the Charge Current Programming section for more information. 24 TH Reference Bypass. Connect a 0.047F ceramic capacitor from REFBP to GA. This pin is discharged to GA in shutdown. Output Feedback Sense for REG1. Connect this pin directly to the output node to connect the internal feedback network to the output voltage. Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP12 and GP3 together at a single point as close to the IC as possible. Power Input for REG4, REG5, REG6, and REG7. Bypass to GA with a high quality ceramic capacitor placed as close as possible to the IC. Open-Drain Interrupt Output. nIRQ asserts any time an unmasked fault condition exists or a charger interrupt occurs. See the nIRQ Output section for more information. Active-Low Open-Drain Push-Button Status Output. nPBSTAT is asserted low whenever the nPBIN is pushed, and is high-Z otherwise. See the nPBSTAT Output section for more information. Power Enable Input. Refer to the Control Sequences section for more information. Low Battery Indicator Output. nLBO is asserted low whenever the voltage at LBI is lower than 1.2V, and is high-Z otherwise. See the Precision Voltage Detector section for more information. Low Battery Input. The input voltage will be compared to 1.2V and output of this comparison drives nLBO. See the Precision Voltage Detector section for more information. AC Input Supply Detection. See the Charge Current Programming section for more information. Temperature Sensing Input. Connect to battery thermistor. TH is pulled up with a 102A current internally. See the Battery Temperature Monitoring section for more information. Innovative PowerTM Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. -5- www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 PIN DESCRIPTIONS CONT'D PIN NAME DESCRIPTION 25 VSEL Step-Down DC/DCs Output Voltage Selection. Drive to logic low to select default output voltage. Drive to logic high to select secondary output voltage. See the Output Voltage Programming section for more information. 26 SCL Clock Input for I2C Serial Interface. 27 SDA Data Input for I2C Serial Interface. Data is read on the rising edge of SCL. 28 nSTAT 29, 30 BAT 31, 32 VSYS System Output Pin. Bypass to GA with a 10F or larger ceramic capacitor. 33 CHGIN Power Input for the Battery Charger. Bypass CHGIN to GA with a capacitor placed as close to the IC as possible. The battery charger is automatically enabled when a valid voltage is present on CHGIN . 34 OUT2 Output Feedback Sense for REG2. Connect this pin directly to the output node to connect the internal feedback network to the output voltage. 35 VP2 Power Input for REG2. Bypass to GP12 with a high quality ceramic capacitor placed as close as possible to the IC. 36 SW2 Switching Node Output for REG2. Connect this pin to the switching end of the inductor. 37 GP12 Power Ground for REG1 and REG2. Connect GA, GP12 and GP3 together at a single point as close to the IC as possible. 38 SW1 Switching Node Output for REG1. Connect this pin to the switching end of the inductor. 39 VP1 Power Input for REG1. Bypass to GP12 with a high quality ceramic capacitor placed as close as possible to the IC. 40 NC No Connect. Not internally connected. EP EP Exposed Pad. Must be soldered to ground on PCB. Active-Low Open-Drain Charger Status Output. nSTAT has a 8mA (typ) current limit, allowing it to directly drive an indicator LED without additional external components. See the Charge Status Indicator section for more information. Battery Charger Output. Connect this pin directly to the battery anode (+ terminal) Innovative PowerTM Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. -6- www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 ABSOLUTE MAXIMUM RATINGS PARAMETER VALUE UNIT VP1, VP2 to GP12 VP3 to GP3 -0.3 to +6 V BAT, VSYS, INL to GA -0.3 to +6 V CHGIN to GA t < 1ms and duty cycle <1% Steady State -0.3 to +18 -0.3 to +14 V V SW1, OUT1 to GP12 -0.3 to (VVP1 + 0.3) V SW2, OUT2 to GP12 -0.3 to (VVP2 + 0.3) V SW3, OUT3 to GP3 -0.3 to (VVP3 + 0.3) V -0.3 to +6 V -0.3 to (VINL + 0.3) V -0.3 to +0.3 V Operating Ambient Temperature -40 to 85 C Maximum Junction Temperature 125 C Maximum Power Dissipation TQFN55-40 (Thermal Resistance JA = 30oC/W) 2.7 W -65 to 150 C 300 C nPBIN, ACIN, CHGLEV, ISET, TH, nSTAT, SCL, SDA, REFBP, PWRHLD, PWREN, VSEL, nLBO, LBI, nPBSTAT, nIRQ, nRSTO to GA OUT4, OUT5, OUT6, OUT7 to GA GP12, GP3 to GA Storage Temperature Lead Temperature (Soldering, 10 sec) : Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may affect device reliability. Innovative PowerTM Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. -7- www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 I2C INTERFACE ELECTRICAL CHARACTERISTICS (VVSYS = 3.6V, TA = 25C, unless otherwise specified.) PARAMETER TEST CONDITIONS MIN SCL, SDA Input Low VVSYS = 3.1V to 5.5V, TA = -40C to 85C SCL, SDA Input High VVSYS = 3.1V to 5.5V, TA = -40C to 85C TYP UNIT 0.35 V 1.55 V SDA Leakage Current SCL Leakage Current 8 SDA Output Low MAX IOL = 5mA 1 A 18 A 0.35 V SCL Clock Period, tSCL 1.5 s SDA Data Setup Time, tSU 100 ns SDA Data Hold Time, tHD 300 ns Start Setup Time, tST For Start Condition 100 ns Stop Setup Time, tSP For Stop Condition 100 ns Figure 1: I2C Compatible Serial Bus Timing tSCL SCL tST tHD tSU tSP SDA Start condition Innovative PowerTM Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. Stop condition -8- www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 GLOBAL REGISTER MAP BITS OUTPUT ADDRESS SYS 0x00 SYS 0x01 REG1 REG1 REG1 REG2 REG2 REG2 REG3 REG3 REG3 REG4 REG4 REG5 REG5 REG6 REG6 REG7 0x20 0x21 0x22 0x30 0x31 0x32 0x40 0x41 0x42 0x50 0x51 0x54 0x55 0x60 0x61 0x64 REG7 0x65 APCH 0x70 APCH APCH APCH APCH 0x71 0x78 0x79 0x7A D7 NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME DEFAULT NAME TRST D6 D5 D4 D3 nSYSMODE nSYSLEVMSK nSYSSTAT D2 SYSLEV[3] D1 SYSLEV[2] SYSLEV[1] D0 SYSLEV[0] 0 1 0 R 0 1 1 1 Reserved Reserved Reserved Reserved SCRATCH SCRATCH SCRATCH SCRATCH 0 0 0 0 0 0 0 0 Reserved Reserved VSET1[5] VSET1[4] VSET1[3] VSET1[2] VSET1[1] VSET1[0] 0 0 1 1 1 0 0 1 Reserved Reserved VSET2[5] VSET2[4] VSET2[3] VSET2[2] VSET2[1] VSET2[0] 0 0 1 1 1 0 0 1 ON PHASE MODE DELAY[2]2 DELAY[1]2 DELAY[0]2 nFLTMSK OK 0 0 0 0 1 1 0 R Reserved Reserved VSET1[5] VSET1[4] VSET1[3] VSET1[2] VSET1[1] VSET1[0] 0 0 0 1 0 1 0 0 Reserved Reserved VSET2[5] VSET2[4] VSET2[3] VSET2[2] VSET2[1] VSET2[0] 0 0 0 1 0 1 0 0 ON PHASE MODE DELAY[2]2 DELAY[1]2 DELAY[0]2 nFLTMSK OK 0 0 0 0 1 1 0 R Reserved Reserved VSET1[5] VSET1[4] VSET1[3] VSET1[2] VSET1[1] VSET1[0] 0 0 0 1 1 0 0 1 Reserved Reserved VSET2[5] VSET2[4] VSET2[3] VSET2[2] VSET2[1] VSET2[0] 0 0 0 1 1 0 0 1 ON PWRSTAT MODE DELAY[2]2 DELAY[1]2 DELAY[0]2 nFLTMSK OK 0 0 0 0 1 1 0 R Reserved Reserved VSET[5] VSET[4] VSET[3] VSET[2] VSET[1] VSET[0] 0 0 0 1 0 1 0 0 nFLTMSK OK 2 2 2 ON DIS LOWIQ 0 1 0 0 1 1 0 R Reserved Reserved VSET[5] VSET[4] VSET[3] VSET[2] VSET[1] VSET[0] DELAY[2] DELAY[1] DELAY[0] 0 0 0 1 0 1 0 0 ON DIS LOWIQ DELAY[2]2 DELAY[1]2 DELAY[0]2 nFLTMSK OK 0 1 0 0 0 0 0 R Reserved Reserved VSET[5] VSET[4] VSET[3] VSET[2] VSET[1] VSET[0] 0 0 0 1 0 1 0 0 ON DIS LOWIQ DELAY[2]2 DELAY[1]2 DELAY[0]2 nFLTMSK OK 0 1 0 0 1 1 0 R Reserved Reserved VSET[5] VSET[4] VSET[3] VSET[2] VSET[1] VSET[0] 0 0 1 1 1 0 0 1 ON DIS LOWIQ DELAY[2]2 DELAY[1]2 DELAY[0]2 nFLTMSK OK 0 1 0 1 0 0 0 R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 1 0 1 0 0 0 SUSCHG Reserved TOTTIMO[1] 0 0 TIMRSTAT TEMPSTAT TOTTIMO[0] PRETIMO[1] PRETIMO[0] OVPSET[1] 0 OVPSET[0] 1 0 1 0 0 0 INSTAT CHGSTAT TIMRDAT TEMPDAT INDAT CHGDAT 0 0 0 0 R R R R TIMRTOT TEMPIN INCON CHGEOCIN TIMRPRE TEMPOUT INDIS CHGEOCOUT 0 0 0 0 0 0 0 0 Reserved Reserved CSTATE[0] CSTATE[1] Reserved Reserved ACINSTAT Reserved 0 R R R R R R 0 DEFAULT : Default values of ACT8937QJ21C-T. 2: Regulator turn-on delay bits. Automatically cleared to default values when the input power is removed or falls below the system UVLO. Innovative PowerTM Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. -9- www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 REGISTER AND BIT DESCRIPTIONS Table 1: Global Register Map OUTPUT ADDRESS BIT NAME ACCESS DESCRIPTION SYS 0x00 [7] TRST R/W Reset Timer Setting. Defines the reset timeout threshold. See nRSTO Output section for more information. SYS 0x00 [6] nSYSMODE R/W SYSLEV Mode Select. Defines the response to the SYSLEV voltage detector, 1: Generate an interrupt when VSYS falls below the programmed SYSLEV threshold, 0: automatic shutdown when VSYS falls below the programmed SYSLEV threshold. SYS 0x00 [5] nSYSLEVMSK R/W System Voltage Level Interrupt Mask. Disabled interrupt by default, set to 1 to enable this interrupt. See the Programmable System Voltage Monitor section for more information SYS 0x00 [4] nSYSSTAT R System Voltage Status. Value is 1 when VSYS is higher than the SYSLEV voltage threshold, value is 0 when VSYS is lower than the system voltage detection threshold. SYS 0x00 [3:0] SYSLEV R/W System Voltage Detect Threshold. Defines the SYSLEV voltage threshold. See the Programmable System Voltage Monitor section for more information. SYS 0x01 [7:4] - R/W Reserved. SYS 0x01 [3:0] SCRATCH R/W Scratchpad Bits. Non-functional bits, maybe be used by user to store system status information. Volatile bits, which are cleared upon system shutdown. REG1 0x20 [7:6] - R REG1 0x20 [5:0] VSET1 R/W REG1 0x21 [7:6] - R REG1 0x21 [5:0] VSET2 R/W Secondary Output Voltage Selection. Valid when VSEL is driven high. See the Output Voltage Programming section for more information. REG1 0x22 [7] ON R/W Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. REG1 0x22 [6] PHASE R/W Regulator Phase Control. Set bit to 1 for regulator to operate 180 out of phase with the oscillator, clear bit to 0 for regulator to operate in phase with the oscillator. REG1 0x22 [5] MODE R/W Regulator Mode Select. Set bit to 1 for fixed-frequency PWM under all load conditions, clear bit to 0 to transit to power-savings mode under light-load conditions. REG1 0x22 [4:2] DELAY R/W Regulator Turn-On Delay Control. See the REG1, REG2, REG3 Turn-on Delay section for more information. REG1 0x22 [1] nFLTMSK R/W Regulator Fault Mask Control. Set bit to 1 enable to faultinterrupts, clear bit to 0 to disable fault-interrupts. REG1 0x22 [0] OK R Regulator Power-OK Status. Value is 1 when output voltage exceeds the power-OK threshold, value is 0 otherwise. REG2 0x30 [7:6] - R Reserved. REG2 0x30 [5:0] VSET1 R/W REG2 0x31 [7:6] - R Reserved. Primary Output Voltage Selection. Valid when VSEL is driven low. See the Output Voltage Programming section for more information. Reserved. Primary Output Voltage Selection. Valid when VSEL is driven low. See the Output Voltage Programming section for more information. Reserved. Innovative PowerTM - 10 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 REGISTER AND BIT DESCRIPTIONS CONT'D OUTPUT ADDRESS BIT NAME ACCESS DESCRIPTION REG2 0x31 [5:0] VSET2 R/W Secondary Output Voltage Selection. Valid when VSEL is driven high. See the Output Voltage Programming section for more information. REG2 0x32 [7] ON R/W Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. REG2 0x32 [6] PHASE R/W Regulator Phase Control. Set bit to 1 for regulator to operate 180 out of phase with the oscillator, clear bit to 0 for regulator to operate in phase with the oscillator. REG2 0x32 [5] MODE R/W Regulator Mode Select. Set bit to 1 for fixed-frequency PWM under all load conditions, clear bit to 0 to transit to powersavings mode under light-load conditions. REG2 0x32 [4:2] DELAY R/W Regulator Turn-On Delay Control. See the REG1, REG2, REG3 Turn-on Delay section for more information. REG2 0x32 [1] nFLTMSK R/W Regulator Fault Mask Control. Set bit to 1 enable to faultinterrupts, clear bit to 0 to disable fault-interrupts. REG2 0x32 [0] OK R Regulator Power-OK Status. Value is 1 when output voltage exceeds the power-OK threshold, value is 0 otherwise. REG3 0x40 [7:6] - R Reserved. REG3 0x40 [5:0] VSET1 R/W REG3 0x41 [7:6] - R REG3 0x41 [5:0] VSET2 R/W Secondary Output Voltage Selection. Valid when VSEL is driven high. See the Output Voltage Programming section for more information. REG3 0x42 [7] ON R/W Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. REG3 0x42 [6] PWRSTAT R/W Configures regulator behavior with respect to the nPBIN input. Set bit to 0 to enable regulator when nPBIN is asserted. REG3 0x42 [5] MODE R/W Regulator Mode Select. Set bit to 1 for fixed-frequency PWM under all load conditions, clear bit to 0 to transit to powersavings mode under light-load conditions. REG3 0x42 [4:2] DELAY R/W Regulator Turn-On Delay Control. See the REG1, REG2, REG3 Turn-on Delay section for more information. REG3 0x42 [1] nFLTMSK R/W Regulator Fault Mask Control. Set bit to 1 enable to faultinterrupts, clear bit to 0 to disable fault-interrupts. REG3 0x42 [0] OK R REG4 0x50 [7:6] - R Primary Output Voltage Selection. Valid when VSEL is driven low. See the Output Voltage Programming section for more information. Reserved. Regulator Power-OK Status. Value is 1 when output voltage exceeds the power-OK threshold, value is 0 otherwise. Reserved. REG4 0x50 [5:0] VSET R/W Output Voltage Selection. See the Output Voltage Programming section for more information. REG4 0x51 [7] ON R/W Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. REG4 0x51 [6] DIS R/W Output Discharge Control. When activated, discharges LDO output to GA through 1.5k when in shutdown. Set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. REG4 0x51 [5] LOWIQ R/W LDO Low-IQ Mode Control. Set bit to 1 for low-power operating mode, clear bit to 0 for normal mode. REG4 0x51 [4:2] DELAY R/W Regulator Turn-On Delay Control. See the REG4, REG5, REG6, REG7 Turn-on Delay section for more information. REG4 0x51 [1] nFLTMSK R/W Regulator Fault Mask Control. Set bit to 1 enable to faultinterrupts, clear bit to 0 to disable fault-interrupts. Innovative PowerTM - 11 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 REGISTER AND BIT DESCRIPTIONS CONT'D OUTPUT ADDRESS BIT NAME ACCESS REG4 0x51 [0] OK R REG5 0x54 [7:6] - R DESCRIPTION Regulator Power-OK Status. Value is 1 when output voltage exceeds the power-OK threshold, value is 0 otherwise. Reserved. REG5 0x54 [5:0] VSET R/W Output Voltage Selection. See the Output Voltage Programming section for more information. REG5 0x55 [7] ON R/W Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. REG5 0x55 [6] DIS R/W Output Discharge Control. When activated, discharges LDO output to GA through 1.5k when in shutdown. Set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. REG5 0x55 [5] LOWIQ R/W LDO Low-IQ Mode Control. Set bit to 1 for low-power operating mode, clear bit to 0 for normal mode. REG5 0x55 [4:2] DELAY R/W Regulator Turn-On Delay Control. See the REG4, REG5, REG6 , REG7 Turn-on Delay section for more information. REG5 0x55 [1] nFLTMSK R/W Regulator Fault Mask Control. Set bit to 1 enable to faultinterrupts, clear bit to 0 to disable fault-interrupts. REG5 0x55 [0] OK R REG6 0x60 [7:6] - R Regulator Power-OK Status. Value is 1 when output voltage exceeds the power-OK threshold, value is 0 otherwise. Reserved. REG6 0x60 [5:0] VSET R/W Output Voltage Selection. See the Output Voltage Programming section for more information. REG6 0x61 [7] ON R/W Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. REG6 0x61 [6] DIS R/W Output Discharge Control. When activated, discharges LDO output to GA through 1.5k when in shutdown. Set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. REG6 0x61 [5] LOWIQ R/W LDO Low-IQ Mode Control. Set bit to 1 for low-power operating mode, clear bit to 0 for normal mode. REG6 0x61 [4:2] DELAY R/W Regulator Turn-On Delay Control. See the REG4, REG5, REG6, REG7 Turn-on Delay section for more information. REG6 0x61 [1] nFLTMSK R/W Regulator Fault Mask Control. Set bit to 1 enable to faultinterrupts, clear bit to 0 to disable fault-interrupts. REG6 0x61 [0] OK R Regulator Power-OK Status. Value is 1 when output voltage exceeds the power-OK threshold, value is 0 otherwise. REG7 0x64 [7:6] - R Reserved. REG7 0x64 [5:0] VSET R/W Output Voltage Selection. See the Output Voltage Programming section for more information. REG7 0x65 [7] ON R/W Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. REG7 0x65 [6] DIS R/W Output Discharge Control. When activated, discharges LDO output to GA through 1.5k when in shutdown. Set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. REG7 0x65 [5] LOWIQ R/W LDO Low-IQ Mode Control. Set bit to 1 for low-power operating mode, clear bit to 0 for normal mode. REG7 0x65 [4:2] DELAY R/W Regulator Turn-On Delay Control. See the REG4, REG5, REG6, REG7 Turn-on Delay section for more information. REG7 0x65 [1] nFLTMSK R/W Regulator Fault Mask Control. Set bit to 1 enable to faultinterrupts, clear bit to 0 to disable fault-interrupts. Innovative PowerTM - 12 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 REGISTER AND BIT DESCRIPTIONS CONT'D OUTPUT ADDRESS BIT NAME ACCESS DESCRIPTION Regulator Power-OK Status. Value is 1 when output voltage exceeds the power-OK threshold, value is 0 otherwise. REG7 0x65 [0] OK R APCH 0x70 [7:0] - R/W Reserved. APCH 0x71 [7] SUSCHG R/W Charge Suspend Control Input. Set bit to 1 to suspend charging, clear bit to 0 to allow charging to resume. APCH 0x71 [6] - R/W Reserved. APCH 0x71 [5:4] TOTTIMO R/W Total Charge Timeout Selection. See the Charge Safety Timers section for more information. APCH 0x71 [3:2] PRETIMO R/W Precondition Charge Timeout Selection. See the Charge Safety Timers section for more information. APCH 0x71 [1:0] OVPSET R/W Input Over-Voltage Protection Threshold Selection. See the Input Over-Voltage Protection section for more information. APCH 0x78 [7] TIMRSTAT R/W Charge Timeout Interrupt Status. See the Charge Safety Timers section for more information. APCH 0x78 [6] TEMPSTAT R/W Temperature Interrupt Status. See the Battery Temperature Monitoring section for more information. APCH 0x78 [5] INSTAT R/W Input Voltage Interrupt Status. See the Charge Current Programming section for more information. APCH 0x78 [4] CHGSTAT R/W Charge State Interrupt Status. See the State Machine Interrupts section for more information. APCH 0x78 [3] TIMRDAT R Charge Timer Interrupt Status. Value is 1 when precondition timeout or total charge timeout fault occurs. Value is 0 in other case. APCH 0x78 [2] TEMPDAT R Temperature Status. Value is 1 when battery temperature is outside of valid range. Value is 0 when battery temperature is inside of valid range. APCH 0x78 [1] INDAT R Input Voltage Status. Value is 1 when a valid input at CHGIN is present. Value is 0 when a valid input at CHGIN is not present. APCH 0x78 [0] CHGDAT R Charge State Status. Value is 1 when in END-OF-CHARGE State. Value is 0 when in other state. APCH 0x79 [7] TIMRTOT R/W Charge Timer Interrupt Control. See the Charge Safety Timers section for more information. APCH 0x79 [6] TEMPIN R/W Temperature Interrupt Control. See the Battery Temperature Monitoring section for more information. APCH 0x79 [5] INCON R/W Input Voltage Interrupt Control. See the Charge Current Programming section for more information. APCH 0x79 [4] CHGEOCIN R/W Charge State Interrupt Control. See the State Machine Interrupts section for more information. APCH 0x79 [3] TIMRPRE R/W Charge Timer Interrupt Control. See the Charge Safety Timers section for more information. APCH 0x79 [2] TEMPOUT R/W Temperature Interrupt Control. See the Battery Temperature Monitoring section for more information. APCH 0x79 [1] INDIS R/W Input Voltage Interrupt Control. See the Charge Current Programming section for more information. APCH 0x79 [0] CHGEOCOUT R/W Charge State Interrupt Control. See the State Machine Interrupts section for more information. APCH 0x7A [7:6] - R Reserved. Innovative PowerTM - 13 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 REGISTER AND BIT DESCRIPTIONS CONT'D OUTPUT ADDRESS BIT NAME ACCESS DESCRIPTION APCH 0x7A [5:4] CSTATE R Charge State. Values indicate the current charging state. See the State Machine Interrupts section for more information. APCH 0x7A [3:2] - R Reserved. APCH 0x7A [1] ACINSTAT R ACIN Status. Indicates the state of the ACIN input, typically in order to identify the type of input supply connected. Value is 1 when ACIN is above the 1.2V precision threshold, value is 0 when ACIN is below this threshold. APCH 0x7A [0] - R Reserved. Innovative PowerTM - 14 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 SYSTEM CONTROL ELECTRICAL CHARACTERISTICS (VVSYS = 3.6V, TA = 25C, unless otherwise specified.) PARAMETER TEST CONDITIONS Input Voltage Range MIN TYP 2.7 UVLO Threshold Voltage VSYS Rising UVLO Hysteresis VSYS Falling 200 REG1 and REG5 Enabled. REG2, REG3, REG4, REG6 and REG7 Disabled 190 REG1, REG2, REG3, REG4 and REG5 Enabled. REG6 and REG7 Disabled 340 REG1, REG2, REG3, REG4, REG5, REG6 and REG7 Enabled 420 Supply Current Shutdown Supply Current 2.45 All Regulators Disabled Oscillator Frequency Logic High Input Voltage 2.2 1.8 UNIT 5.5 V 2.65 V mV A 8 18 A 2 2.2 MHz 1.4 1 V Logic Low Input Voltage Leakage Current VnIRQ = VnRSTO = 4.2V LBI Threshold Voltage VBAT Falling LBI Hysteresis Threshold VBAT Rising Low Level Output Voltage2 ISINK = 5mA nRSTO Delay Thermal Shutdown Temperature MAX Temperature rising Thermal Shutdown Hysteresis 1.03 1.2 0.4 V 1 A 1.31 V 200 mV 0.35 V 260 ms 160 C 20 C : PWRHLD, PWREN, VSEL are logic inputs 2: nLBO, nPBSTAT, nIRQ, nRSTO are open drain outputs 3: Typical value shown. Actual value may vary from 227.9ms to 291.2ms. Innovative PowerTM - 15 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS (VVP1 = VVP2 = VVP3 = 3.6V, TA = 25C, unless otherwise specified.) PARAMETER CONDITIONS Operating Voltage Range MIN TYP 2.7 5.5 V 2.7 V Input Voltage Rising UVLO Hysteresis Input Voltage Falling 100 Quiescent Supply Current Regulator Enabled 65 90 A Shutdown Current VVP = 5.5V, Regulator Disabled 0 1 A mV VOUT 1.2V, IOUT = 10mA -1% VNOM 1% VOUT < 1.2V, IOUT = 10mA -2% VNOM 2% Line Regulation VVP = Max(VNOM1 +1, 3.2V) to 5.5V Load Regulation IOUT = 10mA to IMAX Power Good Threshold Power Good Hysteresis Oscillator Frequency 2.6 UNIT UVLO Threshold Output Voltage Accuracy 2.5 MAX V 0.15 %/V 0.0017 %/mA VOUT Rising 93 %VNOM VOUT Falling 2 %VNOM 2 VOUT 20% of VNOM 1.8 VOUT = 0V 2 2.2 MHz 500 kHz Soft-Start Period 400 s Minimum On-Time 75 ns REG1 Maximum Output Current 1.1 Current Limit 1.55 A 1.80 2.05 A PMOS On-Resistance ISW1 = -100mA 0.16 NMOS On-Resistance ISW1 = 100mA 0.16 SW1 Leakage Current VVP1 = 5.5V, VSW1 = 0 or 5.5V 0 1 A REG2 Maximum Output Current 1.1 Current Limit 1.55 PMOS On-Resistance A 1.80 ISW2 = -100mA 0.16 NMOS On-Resistance ISW2 = 100mA 0.16 SW2 Leakage Current VVP2 = 5.5V, VSW2 = 0 or 5.5V 0 2.05 A 1 A REG3 Maximum Output Current 1.2 Current Limit 1.55 A 1.80 2.05 A PMOS On-Resistance ISW3 = -100mA 0.16 NMOS On-Resistance ISW3 = 100mA 0.16 SW3 Leakage Current VVP3 = 5.5V, VSW3 = 0 or 5.5V 0 1 A : VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section. 2: IMAX Maximum Output Current. Innovative PowerTM - 16 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 LOW-NOISE LDO ELECTRICAL CHARACTERISTICS (VINL = 3.6V, COUT4 = COUT5 = 1.5F, COUT6 = COUT7 = 2.2F, LOWIQ[ ] = [0], TA = 25C, unless otherwise specified.) PARAMETER TEST CONDITIONS Operating Voltage Range Output Voltage Accuracy Line Regulation Load Regulation Power Supply Rejection Ratio Supply Current per Output MIN TYP MAX UNIT 5.5 V 2.5 VOUT 1.2V, TA = 25C, IOUT = 10mA -1% VNOM 2% VOUT < 1.2V, TA = 25C, IOUT = 10mA -2% VNOM 4% VINL = Max(VOUT + 0.5V, 3.6V) to 5.5V LOWIQ[ ] = [0] 0.05 VINL = Max(VOUT + 0.5V, 3.6V) to 5.5V LOWIQ[ ] = [1] 0.5 IOUT = 1mA to IMAX2 0.08 V mV/V V/A f = 1kHz, IOUT = 20mA, VOUT =1.2V 75 f = 10kHz, IOUT = 20mA, VOUT =1.2V 65 Regulator Enabled, LOWIQ[ ] = [0] 37 60 Regulator Enabled, LOWIQ[ ] = [1] 31 52 Regulator Disabled 0 1 dB A Soft-Start Period VOUT = 2.9V 140 s Power Good Threshold VOUT Rising 89 % Power Good Hysteresis VOUT Falling 3 % Output Noise IOUT = 20mA, f = 10Hz to 100kHz, VOUT = 1.2V 50 VRMS Discharge Resistance LDO Disabled, DIS[ ] = 1 1.5 k IOUT = 80mA, VOUT > 3.1V 90 REG4 Dropout Voltage Maximum Output Current Current Limit VOUT = 95% of regulation voltage Stable COUT4 Range 180 mV 150 mA 200 mA 1.5 20 F 280 mV REG5 Dropout Voltage IOUT = 80mA, VOUT > 3.1V Maximum Output Current Current Limit VOUT = 95% of regulation voltage Stable COUT5 Range 140 150 mA 200 mA 1.5 20 F 180 mV REG6 Dropout Voltage IOUT = 120mA, VOUT > 3.1V Maximum Output Current Current Limit VOUT = 95% of regulation voltage Stable COUT6 Range 90 250 mA 300 mA 2.2 20 F 280 mV REG7 Dropout Voltage IOUT = 120mA, VOUT > 3.1V Maximum Output Current Current Limit 140 250 VOUT = 95% of regulation voltage Stable COUT7 Range mA 300 mA 2.2 20 F : VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section. 2: IMAX Maximum Output Current. 3: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the regulation voltage (for 3.1V output voltage or higher). Innovative PowerTM - 17 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 ActivePathTM CHARGER ELECTRICAL CHARACTERISTICS (VCHGIN = 5.0V, TA = 25C, unless otherwise specified.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 6.0 V 3.9 V ActivePath CHGIN Operating Voltage Range 4.35 CHGIN UVLO Threshold CHGIN Voltage Rising CHGIN UVLO Hysteresis CHGIN Voltage Falling CHGIN OVP Threshold CHGIN Voltage Rising CHGIN OVP Hysteresis CHGIN Voltage Falling 0.4 VCHGIN < VUVLO 35 70 A VCHGIN < VBAT + 50mV, VCHGIN > VUVLO 100 200 A VCHGIN > VBAT + 150mV, VCHGIN > VUVLO Charger disabled, IVSYS = 0mA 1.3 2.0 mA IVSYS = 100mA 0.3 A CHGIN Supply Current CHGIN to VSYS On-Resistance CHGIN to VSYS Current Limit 3.1 3.5 0.5 6.0 6.6 V 7.2 V V ACIN = VSYS 1.5 2 ACIN = GA, CHGLEV = GA 80 90 100 ACIN = GA, CHGLEV = VSYS 400 450 500 IVSYS = 10mA 4.45 4.6 4.8 V 4 8 12 mA 1 A mA VSYS REGULATION VSYS Regulated Voltage nSTAT OUTPUT nSTAT Sink current VnSTAT = 2V nSTAT Leakage Current VnSTAT = 4.2V ACIN AND CHGLEV INPUTS CHGLEV Logic High Input Voltage 1.4 V CHGLEV Logic Low Input Voltage CHGLEV Leakage Current VCHGLEV = 4.2V ACIN Voltage Thresholds ACIN voltage rising ACIN Hysteresis voltage threshold ACIN voltage falling ACIN Leakage Current VACIN = 4.2V 1.03 1.2 0.4 V 1 A 1.31 V 200 mV 1 A TH INPUT TH Pull-Up Current VCHGIN > VBAT + 100mV, Hysteresis = 50mV 91 102 110 A VTH Upper Temperature Voltage Threshold (VTHH) Hot Detect NTC Thermistor 2.44 2.51 2.58 V VTH Lower Temperature Voltage Threshold (VTHL) Cold Detect NTC Thermistor 0.47 0.50 0.53 V VTH Hysteresis Upper and Lower Thresholds Innovative PowerTM - 18 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. 30 mV www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 ActivePathTM CHARGER ELECTRICAL CHARACTERISTICS CONT'D (VCHGIN = 5.0V, TA = 25C, unless otherwise specified.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CHARGER BAT Reverse Leakage Current VCHGIN = 0V, VBAT = 4.2V, IVSYS = 0mA BAT to VSYS On-Resistance ISET Pin Voltage Charge Termination Voltage Charge Current Precondition Charge Current A 70 m Fast Charge 1.2 Precondition 0.13 V TA = -20C to 70C 4.179 4.2 4.221 TA = -40C to 85C 4.170 4.2 4.230 ACIN = VSYS, CHGLEV = VSYS -10% ICHG1 +10% ACIN = VSYS, CHGLEV = GA -10% ICHG/5 +10% ACIN = GA, CHGLEV = VSYS 400 450 500 ACIN = GA, CHGLEV = GA 80 90 100 VBAT = 3.8V RISET = 6.8K VBAT = 2.7V RISET = 6.8K ACIN = VSYS, CHGLEV = VSYS 10% ICHG ACIN = VSYS, CHGLEV = GA 10% ICHG ACIN = GA, CHGLEV = VSYS 45 ACIN = GA, CHGLEV = GA 45 Precondition Threshold Voltage VBAT Voltage Rising Precondition Threshold Hysteresis VBAT Voltage Falling END-OF-CHARGE Current Threshold 8 VBAT = 4.15V 2.75 2.85 10% ICHG ACIN = VSYS, CHGLEV = GA 10% ICHG ACIN = GA, CHGLEV = VSYS 45 ACIN = GA, CHGLEV = GA 45 mA mA 3.0 150 ACIN = VSYS, CHGLEV = VSYS V V mV mA Charge Restart Threshold VVSYS - VBAT, VBAT Falling Precondition Safety Timer PRETIMO[ ] = 10 80 min Total Safety Timer TOTTIMO[ ] = 10 5 hr 100 C Thermal Regulation Threshold 190 205 220 V : RISET (k) = 2336 x (1V/ICHG (mA)) - 0.205 Innovative PowerTM - 19 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 TYPICAL PERFORMANCE CHARACTERISTICS (VVSYS = 3.6V, TA = 25C, unless otherwise specified.) Frequency vs. Temperature VREF vs. Temperature 0 -0.42 2 Frequency (%) VREF (%) 0.42 2.5 -20 0 20 40 60 80 100 1.5 1 0.5 0 -0.5 Typical VREF=1.2V -0.84 -40 ACT8937-002 ACT8937-001 0.84 Typical Oscillator Frequency=2MHz -1 -40 120 -20 0 20 40 60 80 85 Temperature (C) Temperature (C) PWREN Sequence PWRHLD holding OUT1 & OUT5 after nPBIN is released CH2 ACT8937-004 ACT8937-003 CH1 CH1 CH2 CH3 CH3 CH4 CH5 CH4 CH6 CH1: VPWREN, 5V/div CH2: VOUT2, 1V/div CH3: VOUT3, 1V/div CH4: VOUT4, 1V/div CH5: VOUT6, 1V/div CH6: VOUT7, 2V/div TIME: 4ms/div CH1: VnPBIN, 2V/div CH2: VOUT5, 1V/div CH3: VOUT1, 2V/div CH4: VPWRHLD, 2V/div TIME: 100ms/div nPBIN Startup Sequence nPBIN Startup Sequence CH2 CH3 ACT8937-006 ACT8937-005 CH1 CH1 CH2 CH3 CH4 CH4 CH5 CH5 CH6 CH1: VnPBIN, 5V/div CH2: VOUT5, 1V/div CH3: VOUT2, 1V/div CH4: VOUT1, 2V/div CH5: VOUT6, 1V/div CH6: VOUT7, 2V/div TIME: 4ms/div Innovative PowerTM - 20 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. CH1: VnPBIN, 5V/div CH2: VOUT5, 1V/div CH3: VOUT2, 1V/div CH4: VOUT3, 1V/div CH5: VOUT4, 1V/div TIME: 2ms/div www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 TYPICAL PERFORMANCE CHARACTERISTICS CONT'D (TA = 25C, unless otherwise specified.) Push-Button Response (First Power-Up) Manual Reset Response ACT8937-008 ACT8937-007 CH1 CH1 CH2 CH2 CH3 CH3 CH1: VnPBIN, 2V/div CH2: VnPBSTAT, 2V/div CH3: VnRSTO, 2V/div TIME: 100ms/div CH1: VnPBIN, 2V/div CH2: VnPBSTAT, 2V/div CH3:VnRSTO , 2V/div TIME: 100ms/div nPBIN Resistor = 50k REG1 Efficiency vs. Output Current Efficiency (%) 80 VIN = 4.2V VIN = 3.6V VOUT = 1.2V VIN = 3.6V 80 Efficiency (%) VIN = 5.0V 100 ACT8937-010 VOUT = 3.3V REG2 Efficiency vs. Output Current ACT8937-009 100 nPBIN Resistor = 0 60 40 VIN = 5.0V VIN = 4.2V 60 40 20 20 0 0 1 10 100 10 1 1000 100 1000 Output Current (mA) Output Current (mA) REG3 Efficiency vs. Output Current VOUT = 1.35V ACT8937-011 100 VIN = 3.6V Efficiency (%) 80 VIN = 5.0V VIN = 4.2V 60 40 20 0 1 10 100 1000 Output Current (mA) Innovative PowerTM - 21 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 TYPICAL PERFORMANCE CHARACTERISTICS CONT'D (TA = 25C, unless otherwise specified.) REG1 Output Voltage vs. Temperature 3.298 3.294 3.290 -40 -20 0 20 40 60 80 100 VOUT2 = 1.3V ILOAD = 100mA 1.306 Output Voltage (V) 3.302 1.310 1.302 1.298 1.294 1.290 -40 120 -20 0 40 60 80 100 120 REG1, 2, 3 MOSFET Resistance REG3 Output Voltage vs. Temperature 1.348 ILOAD = 100mA 300 250 RDSON (m) 1.352 ACT8937-015 350 ACT8937-014 VOUT3 = 1.35V ILOAD = 100mA 1.356 Output Voltage (V) 20 Temperature (C) Temperature (C) 1.360 ACT8937-013 VOUT1 = 3.3V ILOAD = 100mA 3.306 Output Voltage (V) REG2 Output Voltage vs. Temperature ACT8937-012 3.310 200 PMOS NMOS 150 100 1.344 1.340 -40 50 0 -20 0 20 40 60 80 100 120 Temperature (C) Innovative PowerTM - 22 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. 3.0 3.5 4.0 4.5 5.0 5.5 Input Voltage (V) www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 TYPICAL PERFORMANCE CHARACTERISTICS CONT'D (TA = 25C, unless otherwise specified.) Output Voltage vs. Output Current Output Voltage vs. Output Current 3.30 3.10 2.90 2.70 2.50 1.70 Output Voltage (V) Output Voltage (V) REG7 1.90 ACT8937-017 3.50 ACT8937-016 3.70 1.50 REG6 1.30 1.10 0.90 0.70 0.50 2.30 0.30 2.10 50 0 100 150 200 250 0 300 50 Output Current (mA) Output Voltage vs. Output Current 250 REG4, REG5 1.180 1.140 160 140 Dropout Voltage (mV) Output Voltage (V) 200 120 100 REG4 80 60 40 20 VIN = 3.3V 0 1.100 0 20 40 60 80 100 120 140 160 0 20 Output Current (mA) 60 80 100 120 140 160 Dropout Voltage vs. Output Current REG5 100 50 VIN = 3.3V 160 Dropout Voltage (mV) 200 180 ACT8937-021 ACT8937-020 250 0 40 Output Current (mA) Dropout Voltage vs. Output Current 150 300 ACT8937-019 ACT8937-018 1.260 Dropout Voltage (mV) 150 Dropout Voltage vs. Output Current 1.300 1.220 100 Output Current (mA) 140 REG6 120 100 80 60 40 20 VIN = 3.3V 0 0 20 40 60 80 100 120 140 160 Output Current (mA) Innovative PowerTM - 23 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. 0 50 100 150 200 250 300 Output Current (mA) www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 TYPICAL PERFORMANCE CHARACTERISTICS CONT'D (TA = 25C, unless otherwise specified.) Dropout Voltage vs. Output Current Output Voltage vs. Temperature REG7 200 150 100 50 3.00 2.50 2.00 1.50 REG4, REG5, REG6 1.00 0.50 VIN = 3.3V 0 0 0 50 100 150 200 250 300 -40 -20 0 20 40 60 80 Output Current (mA) Temperature (C) Region of Stable COUT ESR vs. Output Current LDO Output Voltage Noise 100 120 ACT8937-025 ACT8937-024 1 ESR () REG7 3.50 Output Voltage (V) Dropout Voltage (mV) 250 4.00 ACT8937-023 ACT8937-022 300 CH1 0.1 Stable ESR 0.01 0 50 100 150 200 250 CH1: VOUTx, 200V/div (AC COUPLED) TIME: 200ms/div Output Current (mA) Innovative PowerTM - 24 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 TYPICAL PERFORMANCE CHARACTERISTICS CONT'D (TA = 25C, unless otherwise specified.) VSYS Voltage vs. CHGIN Voltage VSYS Voltage vs. VSYS Current 4.0 ACIN/CHGLEV = 01 ACIN/CHGLEV = 11 3.0 2.0 5.0 VSYS Voltage (V) VSYS Voltage (V) 5.0 5.2 ACT8937-027 ACT8937-026 6.0 4.8 VSYS = 4.6V 4.6 4.4 4.2 1.0 4.0 0 0 500 1000 1500 2000 2 0 2500 4 70 60 50 40 30 VCHGIN = 5V ACIN = 0 CHGLEV = 0 90mA USB 0 0.0 Charger Current (mA) 1.5 2.0 2.5 3.0 3.5 4.0 350 300 250 200 150 VBAT Falling VBAT Rising 100 0 0.0 4.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Battery Voltage (V) Battery Voltage (V) Charger Current vs. Battery Voltage DCCC and Battery Supplement Modes RISET = 2.4k VCHGIN = 5V ACIN/CHGLEV = 11 800 4.5 ACT8937-031 1000 1.0 CHGLEV = 1 400 450mA USB 50 ACT8937-030 1200 0.5 VCHGIN = 5V 450 ACIN = 0 Charger Current (mA) Charger Current (mA) 80 500 ACT8937-029 ACT8937-028 90 VBAT Falling VBAT Rising 10 Charger Current vs. Battery Voltage Charger Current vs. Battery Voltage 100 10 8 CHGIN Voltage (V) VSYS Current (mA) 20 6 CH4 CH3 600 CH2 VBAT = 3.5V VVSYS = 4.6V IVSYS = 0-1.8A ICHARGE = 1000mA VCHGIN = 5.1V-3A 400 VBAT Falling VBAT Rising 200 CH1 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Battery Voltage (V) Innovative PowerTM - 25 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. CH1: IVSYS, 1.00A/div CH2: IBAT, 1.00A/div CH3: VBAT, 1.00V/div CH4: VVSYS, 1V/div TIME: 200ms/div www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 TYPICAL PERFORMANCE CHARACTERISTICS CONT'D (TA = 25C, unless otherwise specified.) VAC Applied VAC Removed CH3 ACT8937-033 ACT8937-032 CH4 CH4 CH3 CH2 CH2 CH1 CH1 CH1: VBAT, 1V/div CH2: IBAT, 400mA/div CH3: VVSYS, 2V/div CH4: VCHGIN, 5V/div TIME: 40ms/div VCHGIN = 5V VBAT = 3.5V RVSYS = 100 ACIN/CHGLEV = 01 CH1: IBAT, 200mA/div CH2: VBAT, 1V/div CH3: VVSYS, 2V/div CH4: VCHGIN, 5V/div TIME: 100ms/div VAC Applied VAC Removed CH3 ACT8937-035 ACT8937-034 CH4 VCHGIN = 5V VBAT = 3.5V RVSYS = 100 ACIN/CHGLEV = 01 CH4 CH3 CH2 CH2 CH1 CH1 CH1: IBAT, 1A/div CH2: VBAT, 2V/div CH3: VVSYS, 2V/div CH4: VCHGIN, 5V/div TIME: 40ms/div VCHGIN = 5V VBAT = 3.97V RVSYS = 47 ACIN/CHGLEV = 11 Innovative PowerTM - 26 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. CH1: IBAT, 1A/div CH2: VVSYS, 2V/div CH3: VBAT, 2V/div CH4: VCHGIN, 5V/div TIME: 40ms/div VCHGIN = 5V VBAT = 3.97V RVSYS = 47 ACIN/CHGLEV = 11 www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 SYSTEM CONTROL INFORMATION Interfacing with the Samsung S5PC100, S5PC110 and S5PV210 Processors The ACT8937 is optimized for use in applications using the S5PC100, S5PC110 and S5PV210 processors, supporting both the power domains as well as the signal interface for these processors. The following paragraphs describe how to design ACT8937 with S5PV210 Processor, but the design guidelines are directly applicable to S5PC100 and S5PC110 as well. While the ACT8937 supports many possible configurations for powering these processors, one of the most common configurations is detailed in this datasheet. In general, this document refers to the ACT8937 pin names and functions. However, in cases where the description of interconnections between these devices benefits by doing so, both the ACT8937 pin names and the Samsung processor pin names are provided. When this is done, the S5PV210 pin names are located after the ACT8937 pin names, and are italicized and located inside parentheses. For example, PWREN (XPWRRGTON) refers to the logic signal applied to the ACT8937's PWREN input, identifying that it is driven from the S5PV210's XPWRRGTON output. Likewise, OUT1 (VDD_IO) refers to ACT8937's OUT1 pin, identifying that it is connected to the S5PV210's VDD_IO power domain. Table 2: ACT8937 and Samsung S5PV210 Power Domains POWER DOMAIN ACT8937 CHANNEL TYPE DEFAULT VOLTAGE CURRENT CAPABILITY VDD_IO REG1 DC/DC 3.3V 1100mA VDD_INT REG2 DC/DC 1.1V/1.V 1100mA VDD_ARM REG3 DC/DC 1.25V/1.25V 1200mA VDD_xPLL REG4 LDO 1.1V 150mA VDD_Alive REG5 LDO 1.1V 150mA VDD_UOTG_D REG6 LDO 1.1V 250mA VDD_UOTG_A REG7 LDO 3.3V 250mA Table 3: ACT8937 and Samsung S5PV210Power Modes POWER MODE CONTROL STATE POWER DOMAIN STATE QUIESCENT CURRENT ALL ON PWRHLD is asserted, PWREN is asserted REG1, REG2, REG3, REG4, REG5, REG6 and REG7 are all on 420A NORMAL PWRHLD is asserted, PWREN is asserted, REG6 and REG7 are disabled after system boots up. REG1, REG2, REG3, REG4 and REG5 are on. REG6 and REG7 are off 340A SLEEP ALL OFF PWRHLD is asserted, PWREN is de-asserted, REG1 and REG5 are on. REG2, REG3, REG6 and REG7 are disabled as default REG4, REG6 and REG7 are off PWRHLD is de-asserted, PWREN is deasserted REG1, REG2, REG3, REG4, REG5, REG6 and REG7 are all off Innovative PowerTM - 27 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. 190A <18A www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 Table 4: ACT8937 and Samsung S5PV210 Signal Interface ACT8937 DIRECTION SAMSUNG S5V210 PWREN XPWRRGTON SCL Xi2cSCL[0] SDA Xi2cSDA[0] VSEL DVS_GPIO nRSTO XnRESET nIRQ XEINT0 nPBSTAT XEINT1 nLBO XnBATF PWRHLD Power hold GPIO 1: Optional connection for DVS control. 2, : Typical connections shown, actual connections may vary. : Optional connection for power hold control. Table 5: Control Pins PIN NAME OUTPUT nPBIN REG1, REG2, REG3, REG4, REG5, REG6, REG7 PWRHLD REG1, REG5 PWREN REG2, REG3, REG4, REG6, REG7 Control Signals nPBSTAT Output Enable Inputs The ACT8937 features a variety of control inputs, which are used to enable and disable outputs depending upon the desired mode of operation. PWREN, PWRHLD are logic inputs, while nPBIN is a unique, multi-function input. Refer to Table 5 for a description of which channels are controlled by each input. nPBIN Multi-Function Input ACT8937 features the nPBIN multi-function pin, which combines system enable/disable control with a hardware reset function. Select either of the two pin functions by asserting this pin, either through a direct connection to GA, or through a 50k resistor to GA, as shown in Figure 2. nPBSTAT is an open-drain output that reflects the state of the nPBIN input; nPBSTAT is asserted low whenever nPBIN is asserted, and is high-Z otherwise. This output is typically used as an interrupt signal to the processor, to initiate a software-programmable routine such as operating mode selection or to open a menu. Connect nPBSTAT to an appropriate supply voltage (typically OUT1) through a 10k or greater resistor. Figure 2: nPBIN Input Manual Reset Function The second major function of the nPBIN input is to provide a manual-reset input for the processor. To manually-reset the processor, drive nPBIN directly to GA through a low impedance (less than 2.5k). When this occurs, nRSTO immediately asserts low, then remains asserted low until the nPBIN input is de-asserted and the reset timeout period expires. Innovative PowerTM - 28 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 nRSTO Output Control Sequences nRSTO is an open-drain output which asserts low upon startup or when manual reset is asserted via the nPBIN input. When asserted on startup, nRSTO remains low until reset timeout period expires after OUT5 reaches its power-OK threshold. When asserted due to manual-reset, nRSTO immediately asserts low, then remains asserted low until the nPBIN input is de-asserted and the reset timeout period expires. The ACT8937 features a variety of control sequences that are optimized for supporting system enable and disable, as well as SLEEP mode of the Samsung S5PC100, S5PC110 and S5PV210 processors. Connect a 10k or greater pull-up resistor from nRSTO to an appropriate voltage supply (typically OUT1). 1) nPBIN is asserted low via 50K resistance, or nIRQ Output nIRQ is an open-drain output that asserts low any time an interrupt is generated. Connect a 10k or greater pull-up resistor from nIRQ to an appropriate voltage supply. nIRQ is typically used to drive the interrupt input of the system processor. Many of the ACT8937's functions support interruptgeneration as a result of various conditions. These are typically masked by default, but may be unmasked via the I2C interface. For more information about the available fault conditions, refer to the appropriate sections of this datasheet. Note that under some conditions a false interrupt may be generated upon initial startup. For this reason, it is recommended that the interrupt service routine check and validate nSYSLEVMSK[-] and nFLTMSK[-] bits before processing an interrupt generated by these bits. These interrupts may be validated by nSYSSTAT[-], OK[-] bits. Push-Button Control The ACT8937 is designed to initiate a system enable sequence when the nPBIN multi-function input is asserted. Once this occurs, a power-on sequence commences, as described below. The power-on sequence must complete and the microprocessor must take control (by asserting PWREN or PWRHLD) before nPBIN is de-asserted. If the microprocessor is unable to complete its power-up routine successfully before the user lets the push-button go off, the ACT8937 automatically shuts the system down. This provides protection against accidental or momentary assertions of the push-button. If desired, longer "push-and-hold" times can be easily implemented by simply adding an additional time delay before asserting PWREN or PWRHLD. Enabling/Disabling Sequence A typical enable sequence is initiated whenever the following conditions occurs: 2) A valid input voltage is present at CHGIN . The enable sequence begins by enabling REG5. When REG5 reaches its power-OK threshold, nRSTO is asserted low, resetting the microprocessor. REG2, REG3 and REG4 are enabled after REG5 reaches its power-OK threshold for 8ms2. When REG2 reaches its powerOK threshold for 8ms2, REG1 and REG6 are enabled. When REG2 reaches its power-OK threshold for 16ms2, REG7 is enabled. If REG5 is above its power-OK threshold when the reset timer expires, nRSTO is de-asserted, allowing the microprocessor to begin its boot sequence. During the boot sequence, the microprocessor must assert PWRHLD, holding REG1 and REG5, and assert PWREN(XPWRRGTON), holding REG2, REG3, REG4, REG6 and REG7 to ensure that the system remains powered after nPBIN is released. REG6 and REG7 can also be enabled/disabled via I2C after microprocessor completes its boot sequence. Once the power-up routine is completed, the system remains enabled after the push-button is released as long as either PWRHLD or PWREN are asserted high. If the processor does not assert PWRHLD before the user releases the push-button, the boot-up sequence is terminated and all regulators are disabled. This provides protection against "false-enable", when the pushbutton is accidentally depressed, and also ensures that the system remains enabled only if the processor successfully completes the boot-up sequence. To disable REG6 (or REG7) via I2C after the power-up, the software needs to set register bit REG6.ON[ ] (or REG7.ON[ ]) to "1" first, then set it back to "0" to turn off the regulator. As with the enable sequence, a typical disable sequence is initiated when the user presses the push-button, which interrupts the processor via the nPBSTAT output. The actual disable sequence is completely software-controlled, but typically : Applicable only for ACT8937QJ2XX. 2: Typical value shown, actual delay time may vary from (T-1ms) x 88% to T x 112%, where T is the typical delay time setting. Innovative PowerTM - 29 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 involved initiating various "clean-up" processes before the processor finally de-asserts PWRHLD, which disables REG1 and REG5 after push-button is released. Since the processor loses power of VDD_IO and VDD_Alive, it automatically de-asserts PWREN (XPWRRGTON), and hence shuts the system down by disabling REG2, REG3, REG4, REG6 and REG7. SLEEP Mode Sequence The ACT8937 supports Samsung S5PC100, S5PC110 and S5PV210 processors' SLEEP mode operation. Once a successful power-up routine has been completed, SLEEP mode may be initiated through a variety of software-controlled mechanisms. SLEEP mode is typically initiated when the user presses the push-button during normal operation. Pressing the push-button asserts the nPBIN input, which asserts the nPBSTAT output, which interrupts the processor. In response to this interrupt the processor should de-assert PWREN(XPWRRGTON), disabling REG2, REG3, REG4, REG6 and REG7. PWRHLD should remain asserted during SLEEP mode so that REG1 and REG5 remain enabled. Waking up from SLEEP mode is typically initiated when the user presses the push-button again, which enables REG2, REG3, REG4, REG6 and REG7 and asserts nPBSTAT. Processors should respond by asserting PWREN(XPWRRGTON), which holds REG2, REG3, REG4, REG6 and REG7 so that normal operation may resume. An external interrupt , for instance a charger interrupt or a RTC interrupt, can also initiate a wake up sequence. When an external interrupt is sent to the processor, the processor should response by getting itself ready to wake up from SLEEP mode first, then assert PWREN(XPWRRGTON), which enables REG2, REG3, REG4, REG6 and REG7 so that the normal operation may resume. Figure 3: Enable/Disable Sequence : Applicable only for ACT8937QJ2XX. Innovative PowerTM - 30 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. (R) ACT8937 Rev 0, 21-Sep-10 Figure 4: Sleep Mode and Wake up Sequence (from Push Button) Figure 5: Sleep Mode and Wake up Sequence (from External Interrupt) : Applicable only for ACT8937QJ2XX. Innovative PowerTM - 31 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 FUNCTIONAL DESCRIPTION I2C Interface 2 The ACT8937 features an I C interface that allows advanced programming capability to enhance overall system performance. To ensure compatibility with a wide range of system processors, the I2C interface supports clock speeds of up to 400kHz ("Fast-Mode" operation) and uses standard I2C commands. I2C write-byte commands are used to program the ACT8937, and I2C read-byte commands are used to read the ACT8937's internal registers. The ACT8937 always operates as a slave device, and is addressed using a 7-bit slave address followed by an eighth bit, which indicates whether the transaction is a readoperation or a write-operation, [1011011x]. SDA is a bi-directional data line and SCL is a clock input. The master device initiates a transaction by issuing a START condition, defined by SDA transitioning from high to low while SCL is high. Data is transferred in 8-bit packets, beginning with the MSB, and is clocked-in on the rising edge of SCL. Each packet of data is followed by an "Acknowledge" (ACK) bit, used to confirm that the data was transmitted successfully. For more information regarding the I2C 2-wire serial interface, go to the NXP website: http://www.nxp.com. Housekeeping Functions Programmable System Voltage Monitor The ACT8937 features a programmable systemvoltage monitor, which monitors the voltage at VSYS and compares it to a programmable threshold voltage. The programmable voltage threshold is programmed by SYSLEV[3:0], as shown in Table 6. The nSYSSTAT[-] bit reflects the output of an internal voltage comparator that monitors VSYS relative to the SYSLEV[-] voltage threshold, the value of nSYSTAT[-] = 1 when VSYS is higher than the SYSLEV[-] voltage threshold, and nSYSTAT[-] = 0 when VSYS is lower than the SYSLEV[-] voltage threshold. Note that the SYSLEV[-] voltage threshold is defined for falling voltages, and that the comparator produces about 200mV of hysteresis at VSYS. As a result, once VSYS falls below the SYSLEV threshold, its voltage must increase by more than about 200mV to clear that condition. The ACT8937 responds in one of two ways when the voltage at VSYS falls below the SYSLEV[-] voltage threshold: 1) If nSYSMODE[-] = 1 (default case), when VSYS falls below the programmable threshold the ACT8937 asserts nIRQ, providing a software "undervoltage alarm". The response to this interrupt is controlled by the CPU, but will typically initiate a controlled shutdown sequence either or alert the user that the battery is low. In this case the interrupt is cleared when nSYSSTAT[-] is read via I2C. 2) If nSYSMODE[-] = 0, when VSYS falls below the programmable threshold the ACT8937 shuts down, immediately disabling all regulators. This option is useful for implementing a programmable "undervoltage lockout" function that forces the system off when the battery voltage falls below the SYSLEV threshold voltage. Since this option does not support a controlled shutdown sequence, it is generally used as a "fail-safe" to shut the system down when the battery voltage is too low. Table 6: SYSLEV Falling Threshold SYSLEV[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Precision Voltage Detector The LBI input connects to one input of a precision voltage comparator, which can be used to monitor a system voltage such as the battery voltage. An external resistive-divider network can be used to set voltage monitoring thresholds, as shown in Functional Block Diagram. The output of the comparator is present at the nLBO open-drain output. Thermal Shutdown The ACT8937 integrates thermal shutdown protection circuitry to prevent damage resulting from excessive thermal stress, as may be encountered under fault conditions. This circuitry disables all regulators if the ACT8937 die temperature exceeds 160C, and prevents the regulators from being enabled until the IC temperature drops by 20C (typ). Innovative PowerTM - 32 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. SYSLEV Falling Threshold (Hysteresis = 200mV) 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 STEP-DOWN DC/DC REGULATORS General Description The ACT8937 features three synchronous, fixedfrequency, current-mode PWM step down converters that achieve peak efficiencies of up to 97%. REG1 and REG2 are capable of supplying up to 1100mA of output current, while REG3 supports up to 1200mA. These regulators operate with a fixed frequency of 2MHz, minimizing noise in sensitive applications and allowing the use of small external components. 100% Duty Cycle Operation Each regulator is capable of operating at up to 100% duty cycle. During 100% duty-cycle operation, the high-side power MOSFET is held on continuously, providing a direct connection from the input to the output (through the inductor), ensuring the lowest possible dropout voltage in battery powered applications. Synchronous Rectification REG1, REG2, and REG3 each feature integrated nchannel synchronous rectifiers, maximizing efficiency and minimizing the total solution size and cost by eliminating the need for external rectifiers. Soft-Start When enabled, each output voltages tracks an internal 400s soft-start ramp, minimizing input current during startup and allowing each regulator to power up in a smooth, monotonic manner that is independent of output load conditions. Compensation Each buck regulator utilizes current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over its full operating range. No compensation design is required; simply follow a few simple guidelines described below when choosing external components. Input Capacitor Selection The input capacitor reduces peak currents and noise induced upon the voltage source. A 4.7F ceramic capacitor is recommended for each regulator in most applications. Output Capacitor Selection For most applications, 22F ceramic output capacitors are recommended for REG1, REG2 and REG3. must be taken during the design process to ensure stable operation over the full operating voltage and temperature range. Ceramic capacitors are available in a variety of dielectrics, each of which exhibits different characteristics that can greatly affect performance over their temperature and voltage ranges. Two of the most common dielectrics are Y5V and X5R. Whereas Y5V dielectrics are inexpensive and can provide high capacitance in small packages, their capacitance varies greatly over their voltage and temperature ranges and are not recommended for DC/DC applications. X5R and X7R dielectrics are more suitable for output capacitor applications, as their characteristics are more stable over their operating ranges, and are highly recommended. Inductor Selection REG1, REG2, and REG3 utilize current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating range. These devices were optimized for operation with 2.2H inductors, although inductors in the 1.5H to 3.3H range can be used. Choose an inductor with a low DC-resistance, and avoid inductor saturation by choosing inductors with DC ratings that exceed the maximum output current by at least 30%. Configuration Options Output Voltage Programming By default, each regulator powers up and regulates to its default output voltage. Output voltage is selectable by setting VSEL pin that when VSEL is low, output voltage is programmed by VSET1[-] bits, and when VSEL is high, output voltage is programmed by VSET2[-] bits. However, once the system is enabled, each regulator's output voltage may be independently programmed to a different value, typically in order to minimize the power consumption of the microprocessor during some operating modes. Program the output voltages via the I2C serial interface by writing to the regulator's VSET1[-] register if VSEL is low or VSET2[-] register if VSEL is high as shown in Table 8. Enable / Disable Control During normal operation, each buck may be enabled or disabled via the I2C interface by writing to that regulator's ON[ ] bit. To enable the regulator set ON[ ] to 1, to disable the regulator clear ON[ ] to 0. Despite the advantages of ceramic capacitors, care Innovative PowerTM - 33 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 REG1, REG2, REG3 Turn-on Delay Each of REG1, REG2 and REG3 features a programmable Turn-on Delay which help ensure a reliable qualification. This delay is programmed by DELAY[2:0], as shown in Table 7. Table 7: REGx/DELAY[ ] Turn-On Delay DELAY[2] DELAY[1] DELAY[0] TURN-ON DELAY 0 0 0 0 ms 0 0 1 2 ms 0 1 0 4 ms interface. If an output voltage is lower than the powerOK threshold, typically 7% below the programmed regulation voltage, that regulator's OK[ ] bit will be 0. If a DC/DC's nFLTMSK[-] bit is set to 1, the ACT8937 will interrupt the processor if that DC/DC's output voltage falls below the power-OK threshold. In this case, nIRQ will assert low and remain asserted until the OK[ ] bit has been read via I2C. PCB Layout Considerations High switching frequencies and large peak currents make PC board layout an important part of step-down DC/DC converter design. A good design minimizes excessive EMI on the feedback paths and voltage gradients in the ground plane, both of which can result in instability or regulation errors. 0 1 1 8 ms 1 0 0 16 ms 1 0 1 32 ms 1 1 0 64 ms 1 1 1 128 ms Operating Mode By default, REG1, REG2, and REG3 each operate in fixed-frequency PWM mode at medium to heavy loads, while automatically transitioning to a proprietary power-saving mode at light loads in order to maximize standby battery life. In applications where low noise is critical, force fixed-frequency PWM operation across the entire load current range, at the expense of light-load efficiency, by setting the MODE[ ] bit to 1. OK[ ] and Output Fault Interrupt Each DC/DC features a power-OK status bit that can be read by the system microprocessor via the I2C Step-down DC/DCs exhibit discontinuous input current, so the input capacitors should be placed as close as possible to the IC, and avoiding the use of via if possible. The inductor, input filter capacitor, and output filter capacitor should be connected as close together as possible, with short, direct, and wide traces. The ground nodes for each regulator's power loop should be connected at a single point in a starground configuration, and this point should be connected to the backside ground plane with multiple via. The output node for each regulator should be connected to its corresponding OUTx pin through the shortest possible route, while keeping sufficient distance from switching nodes to prevent noise injection. Finally, the exposed pad should be directly connected to the backside ground plane using multiple via to achieve low electrical and thermal resistance. Table 8: REGx/VSET[ ] Output Voltage Setting REGx/VSET[2:0] REGx/VSET[5:3] 000 001 010 011 100 101 110 111 000 0.600 0.800 1.000 1.200 1.600 2.000 2.400 3.200 001 0.625 0.825 1.025 1.250 1.650 2.050 2.500 3.300 010 0.650 0.850 1.050 1.300 1.700 2.100 2.600 3.400 011 0.675 0.875 1.075 1.350 1.750 2.150 2.700 3.500 100 0.700 0.900 1.100 1.400 1.800 2.200 2.800 3.600 101 0.725 0.925 1.125 1.450 1.850 2.250 2.900 3.700 110 0.750 0.950 1.150 1.500 1.900 2.300 3.000 3.800 111 0.775 0.975 1.175 1.550 1.950 2.350 3.100 3.900 Innovative PowerTM - 34 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 LOW-NOISE, LOW-DROPOUT LINEAR REGULATORS General Description REG4, REG5, REG6, and REG7 are low-noise, low-dropout linear regulators (LDOs) that supply up to 150mA, 150mA, 250mA, and 250mA, respectively. Each LDO has been optimized to achieve low noise and high-PSRR, achieving more than 65dB PSRR at frequencies up to 10kHz. to that LDO's ON[ ] bit. To enable the LDO set ON[ ] to 1, to disable the LDO clear ON[ ] to 0. REG4, REG5, REG6, REG7 Turn-on Delay Each of REG4, REG5, REG6 and REG7 features a programmable Turn-on Delay which help ensure a reliable qualification. This delay is programmed by DELAY[2:0], as shown in Table 7. Output Current Limit Each LDO contains current-limit circuitry featuring a current-limit fold-back function. During normal and moderate overload conditions, the regulators can support more than their rated output currents. During extreme overload conditions, however, the current limit is reduced by approximately 30%, reducing power dissipation within the IC. Output Discharge Each of the ACT8937's LDOs features an optional output discharge function, which discharges the output to ground through a 1.5k resistance when the LDO is disabled. This feature may be enabled or disabled by setting DIS[-] via; set DIS[-] to 1 to enable this function, clear DIS[-] to 0 to disable it. Low-Power Mode Compensation The LDOs are internally compensated and require very little design effort, simply select input and output capacitors according to the guidelines below. Input Capacitor Selection Each LDO requires a small ceramic input capacitor to supply current to support fast transients at the input of the LDO. Bypassing each INL pin to GA with 1F. High quality ceramic capacitors such as X7R and X5R dielectric types are strongly recommended. Output Capacitor Selection Each LDO requires a small ceramic output capacitor for stability. Capacitance value is 1.5F for REG4 and REG5, 2.2F for REG6 and REG7. For best performance, each output capacitor should be connected directly between the output and GA pins, as close to the output as possible, and with a short, direct connection. High quality ceramic capacitors such as X7R and X5R dielectric types are strongly recommended. Configuration Options Output Voltage Programming By default, each LDO powers up and regulates to its default output voltage. Once the system is enabled, each output voltage may be independently programmed to a different value by writing to the regulator's VSET[-] register via the I2C serial interface as shown in Table 8. Enable / Disable Control During normal operation, each LDO may be enabled or disabled via the I2C interface by writing Each of ACT8937's LDOs features a LOWIQ[-] bit which, when set to 1, reduces the LDO's quiescent current by about 16%, saving power and extending battery lifetime. OK[ ] and Output Fault Interrupt Each LDO features a power-OK status bit that be read by the system microprocessor via interface. If an output voltage is lower than power-OK threshold, typically 11% below programmed regulation voltage, the value of regulator's OK[-] bit will be 0. If a LDO's nFLTMSK[-] bit is set to 1, the ACT8937 will interrupt the processor if that LDO's output voltage falls below the power-OK threshold. In this case, nIRQ will assert low and remain asserted until the OK[-] bit has been read via I2C. PCB Layout Considerations PCB Layout Considerations The ACT8937's LDOs provide good DC, AC, and noise performance over a wide range of operating conditions, and are relatively insensitive to layout considerations. When designing a PCB, however, careful layout is necessary to prevent other circuitry from degrading LDO performance. A good design places input and output capacitors as close to the LDO inputs and output as possible, and utilizes a star-ground configuration for all regulators to prevent noise-coupling through ground. Output traces should be routed to avoid close proximity to noisy nodes, particularly the SW nodes of the DC/DCs. REFBP is a filtered reference noise, and internally Innovative PowerTM - 35 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. can the the the that www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. (R) ACT8937 Rev 0, 21-Sep-10 has a direct connection to the linear regulator controller. Any noise injected onto REFBP will directly affect the outputs of the linear regulators, and therefore special care should be taken to ensure that no noise is injected to the outputs via REFBP. As with the LDO output capacitors, the REFBP bypass capacitor should be placed as close to the IC as possible, with short, direct connections to the star-ground. Avoid the use of via whenever possible. Noisy nodes, such as from the DC/DCs, should be routed as far away from REFBP as possible. Innovative PowerTM - 36 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 ActivePathTM CHARGER General Description The ACT8937 features an advanced battery charger that incorporates the patent-pending ActivePath architecture for system power selection. This combination of circuits provides a complete, advanced battery-management system that automatically selects the best available input supply, manages charge current to ensure system power availability, and provides a complete, highaccuracy (0.5%), thermally regulated, full-featured single-cell linear Li+ charger that can withstand input voltages of up to 12V. In an input over-voltage condition this circuit limits VSYS to 4.6V, protecting any circuitry connected to VSYS from the over-voltage condition, which may exceed this circuitry's voltage capability. This circuit is capable of withstanding input voltages of up to 12V. Table 9: Input Over-Voltage Protection Setting OVPSET[1] OVPSET[0] OVP THRESHOLD 0 0 6.6V 0 1 7.0V ActivePath Architecture 1 0 7.5V The ActivePath architecture important functions: 1 1 8.0V performs three 1) System Configuration Optimization 2) Input Protection 3) Battery-Management System Configuration Optimization The ActivePath circuitry monitors the state of the input supply, the battery, and the system, and automatically reconfigures itself to optimize the power system. If a valid input supply is present, ActivePath powers the system from the input while charging the battery in parallel. This allows the battery to charge as quickly as possible, while supplying the system. If a valid input supply is not present, ActivePath powers the system from the battery. Finally, if the input is present and the system current requirement exceeds the capability of the input supply, ActivePath allows system power to be drawn from both the battery and the input supply. Input Protection Input Over-Voltage Protection The ActivePath circuitry features input over-voltage protection circuitry. This circuitry disables charging when the input voltage exceeds the voltage set by OVPSET[-] as shown in Table 9, but stands off the input voltage in order to protect the system. Note that the adjustable OVP threshold is intended to provide the charge cycle with adjustable immunity against upward voltage transients on the input, and is not intended to allow continuous charging with input voltages above the charger's normal operating voltage range. Independent of the OVPSET[-] setting, the charge cycle is not allowed to continue until the input voltage falls back into the charger's normal operating voltage range (i.e. below 6.0V). Input Supply Overload Protection The ActivePath circuitry monitors and limits the total current drawn from the input supply to a value set by the ACIN and CHGLEV inputs, as well as the resistor connected to ISET. Drive ACIN to a logiclow for "USB Mode", which limits the current to either 100mA, when CHGLEV is driven to a logiclow, or 500mA, when CHGLEV is driven to a logichigh. Drive ACIN to a logic-high for "AC-Mode", which limits the input current to 2A, typically. Input Under Voltage Lockout If the input voltage applied to CHGIN falls below 3.5V (typ), an input under-voltage condition is detected and the charger is disabled. Once an input under-voltage condition is detected, a new charge cycle will initiate when the input exceeds the undervoltage threshold by at least 500mV. Battery Management The ACT8937 features a full-featured, intelligent charger for Lithium-based cells, and was designed specifically to provide a complete charging solution with minimum system design effort. The core of the charger is a CC/CV (ConstantCurrent/Constant-Voltage), linear-mode charge controller. This controller incorporates current and voltage sense circuitry, an internal 70m power MOSFET, thermal-regulation circuitry, a fullfeatured state-machine that implements charge control and safety features, and circuitry that eliminates the reverse blocking diode required by conventional charger designs. The charge termination voltage is highly accurate (0.5%), and features a selection of charge safety timeout periods that protect the system from operation with damaged cells. Other features Innovative PowerTM - 37 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 include pin-programmable fast-charge current and one current-limited nSTAT output that can directly drive LED indicator or provide a logic-level status signal to the host microprocessor. Dynamic Charge Current Control (DCCC) The ACT8937's ActivePath charger features dynamic charge current control (DCCC) circuitry, which acts to ensure that the system remains powered while operating within the maximum output capability of the power adapter. The DCCC circuitry continuously monitors VSYS, and if the voltage at VSYS drops by more than 200mV, the DCCC circuitry automatically reduces charge current in order to prevent VSYS from continuing to drop. Charge Current Programming The ACT8937's ActivePath charger features a flexible charge current-programming scheme that combines the convenience of internal charge current programming with the flexibility of resistor based charge current programming. Current limits and charge current programming are managed as a function of the ACIN and CHGLEV pins, in combination with RISET, the resistance connected to the ISET pin. ACIN is a logic input that configures the current-limit of ActivePath's linear regulator as well as that of the battery charger. ACIN features a precise 1.2V logic threshold, so that the input voltage detection threshold may be adjusted with a simple resistive voltage divider. This input also allows a simple, lowcost dual-input charger switch to be implemented with just a few, low-cost components. When the voltage at ACIN is above the 1.2V threshold, the charger operates in "AC-Mode" with a charge current programmed by RISET, and the RISET is given by: RISET (k) = 2336 x (1V/ICHG (mA)) - 0.205 With a given RISET then charge current will reduce 5 times when CHGLEV is driven low. When ACIN is below the 1.2V threshold, the charger operates in "USB-Mode", with a maximum charge current defined by the CHGLEV input; 500mA, if CHGLEV is driven to a logic-high, or 100mA, if CHGLEV is driven to a logic-low. The ACT8937's charge summarized in Table 10. current settings are Note that the actual charge current may be limited to a current lower than the programmed fast charge current due to the ACT8937's internal thermal regulation loop. See the Thermal Regulation section for more information. In order to ease input supply detection and eliminate the size and cost of external detection circuitry, the charger has the ability to generate interrupts based upon the status of the input supply. This function is capable of generating an interrupt when the input is connected, disconnected, or both. An interrupt is generated any time the input supply is connected when INSTAT[ ] bit is set to 1 and the INCON[-] bit is set to 1, and an interrupt is generated any time the input supply is disconnected when INSTAT[ ] bit is set to 1 and the INDIS[ ] bit is set to 1. The status of the input may be read at any time by reading the INDAT[-] bit, where a value of 1 indicates that the valid input (V CHGIN UVLO<VCHGIN<VOVP) is present, and a value of 0 indicates that a valid input is not present. Reading the INSTAT[-] bit indicates when the input has generated an interrupt; this bit will normally return a value of 0, but will return value of 1 when an input interrupt has been generated then the interrupt is automatically cleared to 0 upon reading. When responding to an Input Status Interrupt, it is often useful to know the state of the ACIN input. For example, in a dual-input charger application knowing the state of the ACIN input can identify which type of input supply has been connected. The state of the ACIN input can be read at any time by reading the ACINSTAT[-] bit, where a value of 1 indicates that the voltage at ACIN is above the 1.2V threshold (indicating that a wall-cube has been attached), and a value of 0 indicates that the voltage is below this threshold (indicating that ACIN input is not valid and USB supply input is selected). Table 10: ACIN and CHGLEV Inputs ACIN CHGLEV CHARGE CURRENT (mA) PRECONDITION CHARGE CURRENT (mA) 0 0 90mA 45mA 0 1 450mA 45mA 1 0 ICHG/5 10% x ICHG 1 1 ICHG 10% x ICHG Innovative PowerTM - 38 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 Figure 6: Typical Li+ charge profile and ACT8937 charge states A: PRECONDITION State B: FAST-CHARGE State C: TOP-OFF State D: END-OF-CHARGE State Figure 7: Charger State Diagram TEMP NOT OK ANY STATE (VCHGIN < VBAT) OR (VCHGIN < VCHGIN UVLO) OR (VCHGIN > VOVP) OR (SUSCHG[ ] = 1) SUSPEND TEMP-FAULT (VCHGIN > VBAT) AND (VCHGIN > VCHGIN UVLO) AND (VCHGIN < VOVP) AND (SUSCHG[ ] = 0) TEMP OK PRECONDITION TIMEOUT-FAULT PRECONDITION Timeout Total Timeout (VBAT > 2.85V) AND (TQUAL = 32ms) FAST-CHARGE (VBAT = VTERM ) AND (TQUAL = 32ms) (VBAT < VTERM - 205mV ) AND (TQUAL = 32ms) TOP-OFF (IBAT < 10% x ICHG) OR (Total Time-out) AND (TQUAL = 32ms) END-OF-CHARGE Innovative PowerTM - 39 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 Charge-Control State Machine PRECONDITION State A new charging cycle begins with the PRECONDITION state, and operation continues in this state until VBAT exceeds the Precondition Threshold Voltage. When operating in PRECONDITION state, the cell is charged at 10% of the programmed maximum fast-charge constant current, ICHG[-]. Once VBAT reaches the Precondition Threshold Voltage, the state machine jumps to the FASTCHARGE state. If VBAT does not reach the Precondition Threshold Voltage before the Precondition Timeout period expires, then the state machine jumps to the TIMEOUT-FAULT state in order to prevent charging a damaged cell. See the Charge Safety Timers section for more information. FAST-CHARGE State In the FAST-CHARGE state, the charger operates in constant-current (CC) mode and regulates the charge current to the current set by RISET . Charging continues in CC mode until VBAT reaches the charge termination voltage (VTERM), at which point the statemachine jumps to the TOP-OFF state. If VBAT does not reach VTERM before the total time out period expires then the state-machine will jump to the "EOC" state and will re-initiate a new charge cycle after 32ms "relax". See the Current Limits and Charge Current Programming sections for more information about setting the maximum charge current. TOP-OFF State In the TOP-OFF state, the cell charges in constantvoltage (CV) mode. In CV mode operation, the charger regulates its output voltage to the 4.20V charge termination voltage, and the charge current is naturally reduced as the cell approaches full charge. Charging continues until the charge current drops to END-OF-CHARGE current threshold, at which point the state machine jumps to the ENDOF-CHARGE (EOC) state. If the state-machine does not jump out of the TOPOFF state before the Total-Charge Timeout period expires, the state machine jumps to the EOC state and will re-initiate a new charge cycle if VBAT falls below termination voltage 205mV (typ). For more information about the charge safety timers, see the Charging Safety Times section. END-OF-CHARGE (EOC) State presents a high-impedance to the battery, minimizing battery current drain and allowing the cell to "relax". The charger continues to monitor the cell voltage, and re-initiates a charging sequence if the cell voltage drops to 205mV (typ) below the charge termination voltage. SUSPEND State The state-machine jumps to the SUSPEND state any time the battery is removed, and any time the input voltage falls below either the UVLO threshold or exceeds the OVP threshold. Once none of these conditions are present, a new charge cycle initiates. A charging cycle may also be suspended manually by setting the SUSPEND[ ] bit. In this case, initiate a new charging sequence by clearing SUSPEND[ ] to 0. State Machine Interrupts The charger features the ability to generate interrupts when the charger state machine transitions, based upon the status of the CHG_ bits. An interrupt may be generated when the state machine transitions to END-OF-CHARGE (EOC) state by setting the CHGEOCIN[ ] bit to 1 and CHGSTAT[ ] bit to 1. An interrupt may be generated when machine transitions get out ENDOF-CHARGE (EOC) state by setting the CHGEOCOUT[ ] bit to 1 and CHGSTAT[ ] bit to 1. The status of the charge state machine may be read at any time by reading the CHGDAT[-] bit, where a value of 0 indicates no interrupt generated, and a value of 1 indicates interrupt generated. Reading the CHGSTAT[-] bit indicates when a state machine transition has generated an interrupt; this bit will normally return a value of 0, but will return value of 1 when a state transition occurs then the interrupt is automatically cleared to 0 upon reading. For additional information about the charge cycle, CSTATE[1:0] may be read at any time via I2C to determine the current charging state. Table 11: Charging Status Indication CSTATE[1] CSTATE[0] STATE MACHINE STATUS 0 0 PRECONDITION State 0 1 FAST-CHARGE State 1 0 TOP-OFF State 1 1 END-OF-CHARGE State In the END-OF-CHARGE (EOC) state, the charger Innovative PowerTM - 40 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 Thermal Regulation Table 13: The charger features an internal thermal regulation loop that monitors die temperature and reduces charging current as needed to ensure that the die temperature does not exceed the thermal regulation threshold of 110C. This feature protects against excessive junction temperature and makes the device more accommodating to aggressive thermal designs. Note, however, that attention to good thermal designs is required to achieve the fastest possible charge time by maximizing charge current. Total Safety Timer Setting Charge Safety Timers Charge Status Indicator The charger features programmable charge safety timers which help ensure a safe charge by detecting potentially damaged cells. These timers are programmable via the PRETIMO[1:0] and TOTTIMO[1:0] bits, as shown in Table 12 and Table 13. Note that in order to account for reduced charge current resulting from DCCC operation, the charge timeout periods are extended proportionally to the reduction in charge current. As a result, the actual safety period may exceed the nominal timer period. The charger provides a charge-status indicator output, nSTAT. nSTAT is an open-drain output which sinks current when the charger is in an active-charging state, and is high-Z otherwise. nSTAT features an internal 8mA current limit, and is capable of directly driving a LED without the need of a current-limiting resistor or other external circuitry. To drive an LED, simply connect the LED between nSTAT pin and an appropriate supply, such as VSYS. For a logic-level charge status indication, simply connect a resistor from nSTAT to an appropriate voltage supply. The charger features the ability to generate interrupts based upon the status of the charge timers, based upon the status of the TIMR_ bits. Generate interrupts when the Precondition Timer expires by setting the TIMRPRE[ ] bit to 1 and TIMRSTAT[ ] bit to 1, generate interrupts when the Total-Charge Timer expires by setting the TIMRTOT[ ] bit to 1 and TIMRSTAT[ ] bit to 1. The status of the charge timers may be read at any time by reading the TIMRDAT[ ] bit, where a value of 0 indicates that neither charge timer has expired, and a value of 1 indicates that one of the charge timers has expired. Reading the TIMRSTAT[-] bit indicates when a charge timers has generated an interrupt; this bit will normally return a value of 0, but will return value of 1 when a charge-timer interrupt has been generated then the interrupt is automatically cleared to 0 upon reading. Table 12: PRECONDITION Safety Timer Setting PRETIMO[1] PRETIMO[0] PRECONDITION TIMEOUT PERIOD 0 0 40 mins 0 1 60 mins 1 0 80 mins 1 1 Disabled TOTTIMO[1] TOTTIMO[0] TOTAL TIMEOUT PERIOD 0 0 3 hrs 0 1 4 hrs 1 0 5 hrs 1 1 Disabled Table 14: Charging Status Indication STATE nSTAT PRECONDITION Active FAST-CHARGE Active TOP-OFF Active END-OF-CHARGE High-Z SUSPEND High-Z TEMPERATURE FAULT High-Z TIMEOUT-FAULT High-Z Reverse-Current Protection The charger includes internal reverse-current protection circuitry that eliminates the need for blocking diodes, reducing solution size and cost as well as dropout voltage relative to conventional battery chargers. When the voltage at CHGIN falls below VBAT, the charger automatically reconfigures its power switch to minimize current drawn from the battery. Battery Temperature Monitoring In a typical application, the TH pin is connected to the battery pack's thermistor input, as shown in Innovative PowerTM - 41 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 Figure 8. The charger continuously monitors the temperature of the battery pack by injecting a 102A (typ) current into the thermistor (via the TH pin) and sensing the voltage at TH. The voltage at TH is continuously monitored, and charging is suspended if the voltage at TH exceeds either of the internal VTHH and VTHL thresholds of 0.5V and 2.51V, respectively. Figure 8: Simple Configuration The net resistance (from TH to GA) required to cross the thresholds are given by: 102A x RNOM x kHOT = 0.5V RNOM x kHOT 5k 102A x RNOM x kCOLD = 2.51V RNOM x kCOLD 25k where RNOM is the nominal thermistor resistance at room temperature, and kHOT and kCOLD represent the ratios of the thermistor's resistance at the desired hot and cold thresholds, respectively, to the resistance at 25C. In order to ease detecting the status of the battery temperature, the charger features the ability to generate interrupts based upon the status of the battery temperature. Generate an interrupt when battery temperature goes out of the valid temperature range by setting the TEMPOUT[ ] bit to 1 and TEMPSTAT[ ] bit to 1. Generated an interrupt when battery temperature returns to the valid range by setting the TEMPIN[ ] bit to 1 and TEMPSTAT[ ] bit to 1. The status of the battery temperature may be read at any time by reading the TEMPDAT[-] bit, where a value of 1 indicates that battery temperature is within the valid range, and a value of 0 indicates that battery temperature has exceeded either of the thresholds. Reading the TEMPSTAT[-] bit indicates when the battery temperature has generated an interrupt; this bit will normally return a value of 0, but will return value of 1 when a cell-temperature interrupt has been generated then the interrupt is automatically cleared to 0 upon reading. Innovative PowerTM - 42 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. ACT8937 (R) Rev 0, 21-Sep-10 TQFN55-40 PACKAGE OUTLINE AND DIMENSIONS SYMBOL A A1 DIMENSION IN MILLIMETERS DIMENSION IN INCHES MIN MAX MIN MAX 0.700 0.800 0.028 0.031 0.200 REF 0.008 REF A2 0.000 0.050 0.000 0.002 b 0.150 0.250 0.006 0.010 D 4.900 5.100 0.193 0.201 E 4.900 5.100 0.193 0.201 D2 3.450 3.750 0.136 0.148 E2 3.450 3.750 0.136 0.148 e L R 0.400 BSC 0.300 0.500 0.300 0.016 BSC 0.012 0.020 0.012 Active-Semi, Inc. reserves the right to modify the circuitry or specifications without notice. Users should evaluate each product to make sure that it is suitable for their applications. Active-Semi products are not intended or authorized for use as critical components in life-support devices or systems. Active-Semi, Inc. does not assume any liability arising out of the use of any product or circuit described in this datasheet, nor does it convey any patent license. Active-Semi and its logo are trademarks of Active-Semi, Inc. For more information on this and other products, contact sales@active-semi.com or visit http://www.active-semi.com. (R) is a registered trademark of Active-Semi. Innovative PowerTM - 43 Active-Semi ProprietaryFor Authorized Recipients and Customers ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of NXP. www.active-semi.com Copyright (c) 2010 Active-Semi, Inc. Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Active-Semi: ACT8937QJ21C-T