SLLS037C − MARCH 1988 − REVISED JANUARY 2006
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DProgrammable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (216 −1) and Generates an Internal 16×
Clock
DFull Double Buffering Eliminates the Need
for Precise Synchronization
DStandard Asynchronous Communication
Bits (Start, Stop, and Parity) Added or
Deleted to or From the Serial Data Stream
DIndependent Receiver Clock Input
DTransmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled
DFully Programmable Serial Interface
Characteristics:
− 5-, 6-, 7-, or 8-Bit Characters
− Even-, Odd-, or No-Parity Bit Generation
and Detection
− 1-, 1 1/2-, or 2-Stop Bit Generation
− Baud Generation (dc to 256 Kbit/s)
DFalse Start Bit Detection
DComplete Status Reporting Capabilities
D3-State TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
DLine Break Generation and Detection
DInternal Diagnostic Capabilities:
− Loopback Controls for Communications
Link Fault Isolation
− Break, Parity, Overrun, Framing Error
Simulation
DFully Prioritized Interrupt System Controls
DModem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
DEasily Interfaces to Most Popular
Microprocessors
DFaster Plug-In Replacement for National
Semiconductor NS16C450
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
D0
D1
D2
D3
D4
D5
D6
D7
RCLK
SIN
SOUT
CS0
CS1
CS2
BAUDOUT
XTAL1
XTAL2
DOSTR
DOSTR
VSS
VCC
RI
DCD
DSR
CTS
MR
OUT1
DTR
RTS
OUT2
INTRPT
NC
A0
A1
A2
ADS
CSOUT
DDIS
DISTR
DISTR
N PACKAGE
(TOP VIEW)
MR
OUT1
DTR
RTS
OUT2
NC
INTRPT
NC
A0
A1
A2
39
38
37
36
35
34
33
32
31
30
29
1819
7
8
9
10
11
12
13
14
15
16
17
D5
D6
D7
RCLK
SIN
NC
SOUT
CS0
CS1
CS2
BAUDOUT 20 21 22 23
FN PACKAGE
(TOP VIEW)
RI
DCD
DSR
CTS
54 321644
D4
D3
D2
D1
D0
NC
DISTR
DDIS
CSOUT
ADS
XTAL1
XTAL2
DOSTR
DOSTR
NC
DISTR
42 41 4043
24 25 26 27 28
NC − No internal connection
VCC
VSS
NOTE: 40-pin DIP (N package) will be obsoleted as of 7/30/2006. Please
contact your local distributor or TI Sales Office for more information.
!" #!$% &"'
&! #" #" (" " ") !"
&& *+' &! #", &" ""%+ %!&"
", %% #""'
Copyright 1988 − 2006, Texas Instruments Incorporated
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description
The TL16C450 is a CMOS version of an asynchronous communications element (ACE). It typically functions
in a microcomputer system as a serial input/output interface.
The TL16C450 performs serial-to-parallel conversion on data received from a peripheral device or modem and
parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of the
ACE at any point in the ACE’s operation. Reported status information includes the type of transfer operation
in progress, the status of the operation, and any error conditions encountered.
The TL16C450 ACE includes a programmable, on-board, baud rate generator. This generator is capable of
dividing a re f e r e n c e clock i n p u t b y d i v i s o r s f r o m 1 t o ( 2 16 −1) and producing a 16×clock for driving the internal
transmitter logic. Provisions are included to use this 16×clock to drive the receiver logic. Also included in the
ACE is a complete modem control capability and a processor interrupt system that may be software tailored
to the user’s requirements to minimize the computing required to handle the communications link.
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
block diagram
Receiver
Buffer
Register
Line
Control
Register
Divisor
Latch (LS)
36
40
37
41
42
43
38
35
13
17
10
11
31
30
29
14
15
16
28
39
25
24
21
20
26
27
18
19
2 − 9
33
A0
A1
A2
CS0
CS1
CS2
ADS
MR
DISTR
DISTR
DOSTR
DOSTR
CSOUT
XTAL1
XTAL2
D7−D0
DDIS
RTS
CTS
DTR
DSR
DCD
RI
OUT1
OUT2
SOUT
BAUDOUT
RCLK
SIN
INTRPT
VCC
VSS
44
22
Divisor
Latch (MS)
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Modem
Status
Register
Interrupt
Enable
Register
Interrupt
I/O
Register
Interrupt
Control
Logic
Baud
Generator
Receiver
Shift
Register
Receiver
Timing and
Control
Data
Bus
Buffer
Internal
Data Bus
Transmitter
Timing and
Control
Transmitter
Shift
Register
Modem
Control
Logic
Power
Supply
Select
and
Control
Logic
Terminal numbers shown are for the FN package.
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.†
I/O
DESCRIPTION
A0
A1
A2
31
30
29
I Register select. A0, A1, and A2 are three inputs used during read and write operations to select the ACE register
to read from or write to. Refer to Table 1 for register addresses, also refer to the address strobe (ADS) signal
description.
ADS 28 I Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select signals
(CS0, CS1, CS2) drive the internal select logic directly; when high, the register select and chip select signals are
held in the state they were in when the low-to-high transition of ADS occurred.
BAUDOUT 17 O Baud out. BAUDOUT is a16×clock signal for the transmitter section of the ACE. The clock rate is established
by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches.
BAUDOUT may also be used for the receiver section by tying this output to the RCLK input.
CS0
CS1
CS2
14
15
16
IChip select. When CSx is active (high, high, and low respectively), the ACE is selected. Refer to the ADS signal
description.
CSOUT 27 O Chip select out. When CSOUT is high, it indicates that the ACE has been selected by the chip select inputs (CS0,
CS1, and CS2). CSOUT is low when the chip is deselected.
CTS 40 I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem
status register. Bit 0 (DCTS) of the modem status register indicates that this signal has changed states since the
last read from the modem status register. If the modem status interrupt is enabled when CTS changes state, an
interrupt is generated.
D0 − D7 2 − 9 I/O Data bus. D0 − D7 are 3-state data lines that provide a bidirectional path for data, control, and status information
between the ACE and the CPU.
DCD 42 I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the
modem status register. Bit 3 (DDCD) of the modem status register indicates that this signal has changed states
since the last read from the modem status register. If the modem status interrupt is enabled when the DCD
changes state, an interrupt is generated.
DDIS 26 O Driver disable. DDIS is active (high) when the CPU is not reading data. When active, this output can disable an
external transceiver.
DISTR
DISTR 25
24 IData input strobes. When either DISTR or DISTR is active (high or low respectively) while the ACE is selected,
the CPU is allowed to read status information or data from a selected ACE register. Only one of these inputs is
required for the transfer of data during a read operation. The other input should be tied in its inactive state (i.e.,
DISTR tied low or DISTR tied high).
DOSTR
DOSTR 21
20 IData output strobes. When either DOSTR or DOSTR is active (high or low respectively), while the ACE is
selected, the CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs
is required to transfer data during a write operation. The other input should be tied in its inactive state (i.e., DOSTR
tied low or DOSTR tied high).
DSR 41 I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem
status register. Bit 1 (DDSR) of the modem status register indicates that this signal has changed state since the
last read from the modem status register. If the modem status interrupt is enabled when the DSR changes state,
an interrupt is generated.
DTR 37 O Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish
communication. D T R is placed in the active state by setting the DTR bit of the modem control register to a high
level. DTR is placed in the inactive state either as a result of a master reset or during loop mode operation or
clearing bit 0 (DTR) of the modem control register.
INTRPT 33 O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. The four
conditions that cause an interrupt are: a receiver error, received data is available, the transmitter holding register
is empty, or an enabled modem status interrupt. The INTRPT output is reset (inactivated) either when the interrupt
is serviced or as a result of a master reset.
MR 39 I Master reset. When active (high), MR clears most ACE registers and sets the state of various output signals.
Refer to Table 2 for ACE reset functions.
†Terminal numbers shown are for the FN package.
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME NO.†
I/O
DESCRIPTION
OUT1
OUT2 38
35 OOutputs 1 and 2. OUT1 and OUT2 are user-designated output terminals that are set to their active states by
setting their respective modem control register bits (OUT1 and OUT2) high. OUT1 and OUT2 are set to their
inactive (high) states as a result of master reset or during loop mode operations or by clearing bit 2 (OUT1) or
bit 3 (OUT2) of the MCR.
RCLK 10 I Receiver clock. RCLK is the 16×baud rate clock for the receiver section of the ACE.
RI 43 I Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status
register. Bit 2 (TERI) of the modem status register indicates that the RI input has transitioned from a low to a high
state since the last read from the modem status register. If the modem status interrupt is enabled when this
transition occurs, an interrupt is generated.
RTS 36 O Request to send. When active, RTS informs the modem or data set that the ACE is ready to transmit data. RTS
is set to its active state by setting the RTS modem control register bit and is set to its inactive (high) state either
as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR.
SIN 11 ISerial input. SIN is the serial data input from a connected communications device.
SOUT 13 O Serial output. SOUT is the composite serial data output to a connected communication device. SOUT is set to
the marking (set) state as a result of MR.
VCC 44 5-V supply voltage
VSS 22 Supply common
XTAL1
XTAL2 18
19 I/O External clock. XTAL1 and XTAL2 connect the ACE to the main timing reference (clock or crystal).
†Terminal numbers shown are for the FN package.
absolute maximum ratings over free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range at any input, VI −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation at (or below) 70°C free-air temperature: FN package 1100 mW. . . . . . .
N package‡ 800 mW. . . . . . . .
Operating free-air temperature range, TA 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 10 seconds, TC: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package‡ 260°C. . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡The N package in Not Recommended for New Designs.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
High-level input voltage, VIH 2 VCC V
Low-level input voltage, VIL −0.5 0.8 V
Operating free-air temperature, TA0 70 °C
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VOH‡HIgh-level output voltage IOH = −1 mA 2.4 V
VOL‡Low-level output voltage IOL = 1.6 mA 0.4 V
IIkg
Input leakage current
VCC = 5.25 V, VSS = 0,
±10
A
IIkg Input leakage current
VCC = 5.25 V, VSS = 0,
VI = 0 to 5.25 V, All other terminals floating ±1
0
µA
IOZ
High-impedance output current
VCC = 5.25 V, VSS = 0,
VO = 0 V to 5.25 V,
±20
A
IOZ High-impedance output current
V
O
= 0 V to 5.25 V,
Chip selected, write mode,or chip deselected ±2
0
µA
VCC = 5.25 V, TA = 25
°
C,
ICC
Supply current
VCC = 5.25 V, TA = 25 C,
SIN, DSR, DCD, CTS, and RI at 2 V,
10
mA
ICC Supply current
SIN, DSR, DCD, CTS, and RI at 2 V,
All other inputs at 0.8 V, Baud rate = 50 kbits/s, 10 mA
CC
All other inputs at 0.8 V, Baud rate = 50 kbits/s,
XTAL1 at 4 MHz, No load on outputs
CXTAL1 Clock input capacitance
V = 0, V = 0,
15 20 pF
CXTAL2 Clock output capacitance VCC = 0, VSS = 0,
f = 1 MHz, TA = 25°C,
20 30 pF
CiInput capacitance
CC SS
f = 1 MHz, T
A
= 25
°
C,
All other terminals grounded
6 10 pF
CoOutput capacitance
All other terminals grounded
10 20 pF
†All typical values are at VCC = 5 V, TA = 25°C.
‡These parameters apply for all outputs except XTAL2.
system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER FIGURE MIN MAX UNIT
tcR Cycle time, read (tw7 + td8 + td9) 175 ns
tcW Cycle time, write (tw6 + td5 + td6) 175 ns
tw5 Pulse duration, ADS low 2,3 15 ns
tw6 Pulse duration, write strobe 2 80 ns
tw7 Pulse duration, read strobe 3 80 ns
twMR Pulse duration, master reset 1000 ns
tsu1 Setup time, address valid before ADS↑2,3 15 ns
tsu2 Setup time, CS valid before ADS↑2,3 15 ns
tsu3 Setup time, data valid before WR1↓ or WR2↑2 15 ns
th1 Hold time, address low after ADS↑2,3 0 ns
th2 Hold time, CS valid after ADS↑2,3 0 ns
th3 Hold time, CS valid after WR1↑ or WR2↓2 20 ns
th4§Hold time, address valid after WR1↑or WR2↓2 20 ns
th5 Hold time, data valid after WR1↑ or WR2↓2 15 ns
th6 Hold time, CS valid after RD1↑ or RD2↓3 20 ns
th7§Hold time, address valid after RD1↑ or RD2↓3 20 ns
td4§Delay time, CS valid before WR1↓ or WR2↑2 15 ns
td5§Delay time, address valid before WR1↓ or WR2↑2 15 ns
td6 Delay time, write cycle, WR1↑ or WR2↓to ADS↓2 80 ns
td7§Delay time, CS valid to RD1↓ or RD2↑3 15 ns
td8§Delay time, address valid to RD1↓ or RD2↑3 15 ns
td9 Delay time, read cycle, RD1↑or RD2↓to ADS↓3 80 ns
§Only applies when ADS is low.
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
system switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT
tw1 Pulse duration, clock high 1f = 9 MHz maximum 50 ns
tw2 Pulse duration, clock low 1f = 9 MHz maximum 50 ns
td3 Delay time, select to CS output 2,3†CL = 100 pF 70 ns
td10 Delay time, RD1↓ or RD2↑to data valid 3 CL = 100 pF 60 ns
td11 Delay time, RD1↑ or RD2↓to floating data 3 CL = 100 pF 0 60 ns
tdis(R) Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓ 3 CL = 100 pF 60 ns
†Only applies when ADS is low.
baud generator switching characteristics over recommended ranges of supply voltage and
operating free-air temperature
PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT
tw3
Pulse duration, BAUDOUT low
1
f = 6.25 MHz, CLK
÷
1,
80
ns
tw3
Pulse duration, BAUDOUT low
1
f = 6.25 MHz, CLK ÷1,
CL = 100 pF 80 ns
tw4
Pulse duration, BAUDOUT high
1
f = 6.25 MHz, CLK
÷
1,
80
ns
tw4
Pulse duration, BAUDOUT high
1
f = 6.25 MHz, CLK ÷
1,
CL = 100 pF 80 ns
td1 Delay time, XIN↑ to BAUDOUT↑1 CL = 100 pF 125 ns
td2 Delay time, XIN↑↓ to BAUDOUT↓1 CL = 100 pF 125 ns
receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT
td12 Delay time, RCLK to sample clock 4 100 ns
td13
Delay time, stop to set RCV error interrupt or read
RDR to LSI interrupt or stop to
4
1
1
RCLK
td13
RDR to LSI interrupt or stop to
RXRDY↓4 1 1
RCLK
cycles
td14 Delay time, read RBR/LSR to reset interrupt 4 CL = 100 pF 140 ns
transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT
td15
Delay time, INTRPT to transmit start
5
8
24
baudout
td15 Delay time, INTRPT to transmit start 5 8 24
baudout
cycles
td16
Delay time, start to interrupt
5
8
8
baudout
td16 Delay time, start to interrupt 5 8 8
baudout
cycles
td17 Delay time, WR THR to reset interrupt 5 CL = 100 pF 140 ns
td18
Delay time, initial write to interrupt (THRE)
5
16
32
baudout
td18 Delay time, initial write to interrupt (THRE) 5 16 32
baudout
cycles
td19 Delay time, read IIR to reset interrupt (THRE) 5 CL = 100 pF 140 ns
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature
PARAMETER FIGURE TEST CONDITIONS MIN MAX UNIT
td20 Delay time, WR MCR to output 6 CL = 100 pF 100 ns
td21 Delay time, modem interrupt to set interrupt 6 CL = 100 pF 170 ns
td22 Delay time, RD MSR to reset interrupt 6 CL = 100 pF 140 ns
PARAMETER MEASUREMENT INFORMATION
(N-2) XTAL1
Cycles
2XTAL1
Cycles
tw1
tw2
2 V
0.8 V
N
td2
td1
td1 td2
tw3 tw4
RCLK
(9 MHz Max)
XTAL1
BAUDOUT
(1/1)
BAUDOUT
(1/2)
BAUDOUT
(1/3)
BAUDOUT
(1/N)
(N>3)
90% 90% 10%
Figure 1. Baud Generator Timing Waveforms
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Valid Data
tw5
tsu1
tsu2
tsu3
th1
th2
th3
th4†
th5
td3 td3
td4†
td5†td6
tw6
Active
Valid†
Valid
Valid Valid†
ADS
A0−A2
CS0, CS1, CS2
CSOUT
DOSTR,
D0−D7
DOSTR
10% 10%
10% 10%
10% 10%
90%
90% 90%
90% 90%
90% 90%
90%90%
10%
†Applicable only when ADS is tied low.
Figure 2. Write Cycle Timing Waveforms
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Valid Data
tw5
tsu1
tsu2
td10
th1
th2
th6
th7†
td11
td3†td3†
td7†
td8†td9
tw7
Active
Valid†
Valid
Valid Valid†
ADS
A0−A2
CS0, CS1, CS2
CSOUT
DISTR,
D0−D7
DISTR
DDIS
tdis(R) tdis(R)
90%
90% 90%
90% 90%
90%90%
90%
10% 10%
10%10%
10%10%
10% 10%
50%
10%
50%
10% 10%
†Applicable only when ADS is tied low.
Figure 3. Read Cycle Timing Waveforms
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
RCLK
Active
td12
8 CLKs
Start Data Bits 5−8 Parity Stop
td13
td14
SAMPLE
CLOCK
SIN
SAMPLE
CLOCK
INTRPT
(RDR/LSI)
DISTR, DISTR
(RD RBR/LSR)
90%
90%
10%
Figure 4. Receiver Timing Waveforms
INTRPT
(THRE)
Start Data Bits Parity Stop
td15
SOUT
DOSTR
DISTR (RD IIR)
td16
td19
td17
td18
td17
Start
(WR THR)
50%
50% 90%90%
90% 90%90%
10%
10% 50%
90%
Figure 5. Transmitter Timing Waveforms
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
INTRPT
(MODEM)
DOSTR (WR MCR)
RI
DISTR (RD MSR)
td20
CTS, DSR, DCD
td20
td21
td22
td21
RTS, DTR
OUT 1, OUT 2
90% 90%
90%
10% 10%
10%
50% 50%
50%
90%
Figure 6. Modem Control Timing Waveforms
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
SOUT
D7−D0
DISTR
DOSTR
INTRPT
MR
A0
A1
A2
ADS
DOSTR
DISTR
CS2
CS1
CS0
D7−D0
MEMR or I/OR
MEMW or I/ON
INTR
RESET
A0
A1
A2
CS
SIN
RTS
DTR
DSR
DCD
CTS
RI
TL16C450
(ACE)
XTAL1
XTAL2
BAUDOUT
RCLK
EIA 232-D
Drivers
and
Receivers
L
H
3.072
MHz
C
P
U
B
u
s
Figure 7. Basic TL16C450 Configuration
Microcomputer
System
TL16C450
(ACE)
Receiver
Disable DOSTR
D7−D0
DDIS
Driver
Disable
8-Bit
Bus Transceiver
WR
Data BusData Bus
Figure 8. Typical Interface for a High-Capacity Data Bus
SLLS037C − MARCH 1988 − REVISED JANUARY 2006
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
XTAL1
CS0
CS1
CS2
ADS
MR
A0−A2
D0−D7
DOSTR
DISTR
XTAL2
BAUDOUT
RCLK
TL16C450
DTR
RTS
OUT1
OUT2
RI
DCD
DSR
CTS
SOUT
SIN
INTRPT
CSOUT
DDIS
NC
DOSTR
DISTR
20
1
8
6
5
2
3
7
1
A16−A23 A16−A23
AD0−
AD7
Buffer
Address
Decoder
CPU
ADS
RSI/ABT
AD0−AD15
PHI2PHI1
PHI2PHI1 RSTOADS
RO
WR
TCU
AD0−AD15
GND
(VSS) 5 V
(VCC)
Alternate
Xtal Control
5 V
EIA-232-D
Connector
Figure 9. Typical TL16C450 Connection to a CPU
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PRINCIPLES OF OPERATION
Table 1. Register Selection
DLAB†A2 A1 A0 REGISTER
0 L L L Receiver buffer (read), transmitter holding register (write)
0 L L H Interrupt enable
X L H L Interrupt identification (read only)
X L H H Line control
X H L L Modem control
X H L H Line status
X H H L Modem status
X H H H Scratch
1 L L L Divisor latch (LSB)
1 L L H Divisor latch (MSB)
†The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal is controlled
by writing to this bit location (see Table 3).
Table 2. ACE Reset Functions
REGISTER/SIGNAL
RESET
RESET STATE
REGISTER/SIGNAL
RESET
CONTROL
RESET STATE
Interrupt enable register Master reset All bits low (0−3 forced and 4−7 permanent)
Interrupt identification register
Master reset
Bit 0 is high, bits 1 and 2 are low, and bits 3 −7 are
Interrupt identification register Master reset
Bit 0 is high, bits 1 and 2 are low, and bits 3 −7 are
permanently low
Line control register All bits low
Modem control register Master reset All bits low
Line status register Master reset Bits 5 and 6 are high, all other bits are low
Modem status register Master reset Bits 0−3 are low, bits 4−7 are input signals
SOUT Master reset High
INTRPT (receiver error flag) Read LSR/MR Low
INTRPT (received data available) Read RBR/MR Low
INTRPT (transmitter holding register empty)
Read IIR/Write
Low
INTRPT (transmitter holding register empty)
Read IIR/Write
THR/MR Low
INTRPT (modem status changes) Read MSR/MR Low
OUT2 Master reset High
RTS Master reset High
DTR Master reset High
OUT1 Master reset High
Scratch register Master reset No effect
Divisor latch (LSB and MSB) register Master reset No effect
Receiver buffer register Master reset No effect
Transmitter holding register Master reset No effect
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16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 3. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.
Table 3. Summary of Accessible Registers
REGISTER ADDRESS
Bit
O DLAB = 0 O DLAB = 0 1 DLAB = 0 2 3 4 5 6 7 O DLAB = 1 1
DLAB
= 0
Bit
No.
Receiver
Transmitter
Interrupt
Interrupt
Line
No.
Receiver
Buffer
Transmitter
Holding
Interrupt
Enable
Interrupt
Ident.
Line
Control
Modem
Line
Modem
Scratch
Divisor
Latch
Buffer
Register
Holding
Register
Enable
Register
Ident.
Register
Control
Register
Modem
Control
Line
Status
Modem
Status Scratch
Register
Divisor
Latch Latch
(MSB)
Register
(Read
Register
(Write
Register
IER
Register
(Read
Register
LCR
Control
Register
Status
Register
Status
Register
Register
Latch
(LSB)
(MSB)
(Read
Only)
(Write
Only)
IER
(Read
Only)
LCR
Register
Register
Register
(LSB)
RBR THR IER IIR LCR MCR LSR MSR SCR DLL DLM
Enable
Word
Enable
Received
“0” If
Word
Length
Data
Data
Delta
0
Data Bit 0*
Data Bit 0
Received
Data
“0” If
Interrupt
Length
Select
Data
Terminal Data
Ready
Delta
Clear
Bit 0
Bit 0
Bit 8
0Data Bit 0* Data Bit 0
Data
Available
Interrupt
Pending
Select
Bit 0
Terminal
Ready
Ready
(DR)
Clear
to Send Bit 0 Bit 0 Bit 8
Available
Interrupt
(ERBF)
Pending
Bit 0
(WLSO)
Ready
(DTR)
(DR)
to Send
(DCTS)
Interrupt
(ERBF)
(WLSO)
(DTR)
(DCTS)
Enable
Enable
Transmitter
Word
Delta
Transmitter
Holding
Interrupt
Word
Length
Request
Overrun
Delta
Data
1
Data Bit 1
Data Bit 1
Holding
Register
Interrupt
ID
Length
Select
Request
to Send
Overrun
Error
Data
Set
Bit 1
Bit 1
Bit 9
1
Data Bit 1
Data Bit 1
Register
Empty
ID
Bit (0)
Select
Bit 1
to Send
(RTS)
Error
(OE)
Set
Ready
Bit 1
Bit 1
Bit 9
Empty
Interrupt
(ETBE)
Bit (0)
Bit 1
(WLS1)
(RTS)
(OE)
Ready
(DDSR)
Interrupt
(ETBE)
(WLS1)
(DDSR)
Enable
Trailing
Enable
Receiver
Interrupt
Number of
Parity
Trailing
EdgeRing
2
Data Bit 2
Data Bit 2
Receiver
Line Status
Interrupt
ID
Number of
Stop Bits
Out 1
Parity
Error
EdgeRing
Indicator
Bit 2
Bit 2
Bit 10
2
Data Bit 2
Data Bit 2
Line Status
Interrupt
ID
Bit (1)
Stop Bits
(STB)
Out 1
Error
(PE)
Indicator
(TERI)
Bit 2
Bit 2
Bit 10
Interrupt
(ELSI)
Bit (1)
(STB)
(PE)
(TERI)
Enable
Delta
Enable
Modem
Parity
Framing
Delta
Data
3
Data Bit 3
Data Bit 3
Modem
Status
0
Parity
Enable
Out 2
Framing
Error
Data
Carrier
Bit 3
Bit 3
Bit 11
3
Data Bit 3
Data Bit 3
Status
Interrupt
0
Enable
(PEN)
Out 2
Error
(FE)
Carrier
Detect
Bit 3
Bit 3
Bit 11
Interrupt
(EDSSI)
(PEN)
(FE)
Detect
(DDCD)
Even
Break
Clear
4
Data Bit 4
Data Bit 4
0
0
Even
Parity
Loop
Break
Interrupt
Clear
to Send
Bit 4
Bit 4
Bit 12
4 Data Bit 4 Data Bit 4 0 0
Parity
Select
Loop
Interrupt
(BI)
to Send
(CTS)
Bit 4 Bit 4 Bit 12
Select
(EPS)
(BI)
(CTS)
Transmitter
Data
5
Data Bit 5
Data Bit 5
0
0
Stick
0
Transmitter
Holding
Data
Set
Bit 5
Bit 5
Bit 13
5Data Bit 5 Data Bit 5 0 0
Stick
Parity 0
Holding
Register
Set
Ready Bit 5 Bit 5 Bit 13
Parity
Register
(THRE)
Ready
(DSR)
Set
Transmitter
Ring
6Data Bit 6 Data Bit 6 0 0 Set
Break
0
Transmitter
Empty
Ring
Indicator Bit 6 Bit 6 Bit 14
6
Data Bit 6
Data Bit 6
0
0
Break
0
Empty
(TEMT)
Indicator
(RI)
Bit 6
Bit 6
Bit 14
Divisor
Latch
Data
7
Data Bit 7
Data Bit 7
0
0
Divisor
Latch
Access
0
0
Data
Carrier
Bit 7
Bit 7
Bit 15
7
Data Bit 7
Data Bit 7
0
0
Access
Bit
0
0
Carrier
Detect
(DCD)
Bit 7
Bit 7
Bit 15
Bit
(DLAB) (DCD)
*Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
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PRINCIPLES OF OPERATION
interrupt enable register (IER)
The IER enables each of the four types of interrupts (refer to Table 4) and the INTRPT output signal in response
to an interrupt generation. By clearing bits 0 − 3, the IER can also disable the interrupt system. The contents
of this register are summarized in Table 3 and are described in the following bulleted list.
DBit 0: This bit, when set, enables the received data available interrupt.
DBit 1: This bit, when set, enables the THRE interrupt.
DBit 2: This bit, when set, enables the receiver line status interrupt.
DBit 3: This bit, when set, enables the modem status interrupt.
DBits 4 − 7: These bits in the IER are not used and are always cleared.
interrupt identification register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
most microprocessors.
The ACE provides four prioritized levels of interrupts:
DPriority 1−Receiver line status (highest priority)
DPriority 2−Receiver data ready or receiver character time out
DPriority 3−Transmitter holding register empty
DPriority 4−Modem status (lowest priority)
When an interrupt is generated, the IIR indicates that an interrupt is pending and the type of interrupt in its three
least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and described
in Table 4.
DBit 0: This bit can be used either in a hardwire prioritized or polled interrupt system. When bit 0 is cleared,
an interrupt is pending. When bit 0 is set, no interrupt is pending.
DBits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 4.
DBits 3 − 7: These bits in the IIR are not used and are always clear.
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PRINCIPLES OF OPERATION
interrupt identification register (IIR) (continued)
Table 4. Interrupt Control Functions
INTERRUPT
INTERRUPT
IDENTIFICATION
REGISTER
PRIORITY
INTERRUPT TYPE
INTERRUPT SOURCE
INTERRUPT RESET
IDENTIFICATION
REGISTER
PRIORITY
LEVEL
INTERRUPT TYPE
INTERRUPT SOURCE
INTERRUPT RESET
METHOD
BIT 2 BIT 1 BIT 0
LEVEL
METHOD
0 0 1 None None None −
Overrun error, parity error,
Reading the line status
1 1 0 1 Receiver line status
Overrun error, parity error,
framing error or break Reading the line status
register
framing error or break
interrupt
register
1
0
0
2
Received data available
Receiver data available
Reading the receiver buffer
1
0
0
2
Received data available
Receiver data available
Buffer register
Reading the interrupt
Transmitter holding register
Transmitter holding register
Reading the interrupt
identification register (if
0 1 0 3 Transmitter holding register
empty
Transmitter holding register
empty
identification register (if
source of interrupt) or writing
into the transmitter holding
empty
empty
source of interrupt) or writing
into the transmitter holding
register
into the transmitter holding
register
Clear to send, data set
Reading the modem status
0 0 0 4 Modem status
Clear to send, data set
ready, ring indicator, or data
carrier detect
Reading the modem status
register
ready, ring indicator, or data
carrier detect
register
line control register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 3 and are described in the following bulleted list.
DBits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.
These bits are encoded as shown in Table 5.
Table 5. Serial Character Word Length
Bit 1 Bit 0 Word Length
0 0 5 Bits
0 1 6 Bits
1 0 7 Bits
1 1 8 Bits
DBit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When
bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated
is dependent on the word length selected with bits 0 and 1. The receiver checks the first stop bit only,
regardless of the number of stop bits selected. The number of stop bits generated, in relation to word length
and bit 2, is shown in Table 6.
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PRINCIPLES OF OPERATION
line control register (LCR) (continued)
Table 6. Number of Stop Bits Generated
Bit 2
Word Length Selected
Number of Stop
Bit 2
Word Length Selected
by Bits 1 and 2
Number of Stop
Bits Generated
0Any word length 1
15 bits 1 1/2
16 bits 2
17 bits 2
18 bits 2
DBit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between
the last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is
cleared, no parity is generated or checked.
DBit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity
(an even number of logic 1s is in the data and parity bits) is selected. When parity is enabled (bit 3 is set)
and bit 4 is clear, odd parity (an odd number of logic 1s) is selected.
DBit 5: This is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as
cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set.
DBit 6: This bit is the break control bit. Bit 6 is set to force a break condition, i.e, a condition where the serial
output terminal (SOUT) is forced to the spacing (cleared) state. When bit 6 is cleared, the break condition
is disabled. The break condition has no affect on the transmitter logic, it only affects the serial output.
DBit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the
baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver
buffer, the THR, or the IER.
line status register (LSR)†
The LSR provides information to the CPU concerning the status of data transfers. The contents of this register
are summarized in Table 3 and are described in the following bulleted list.
DBit 0: This bit is the data ready (DR) indicator for the receiver. Bit 0 is set whenever a complete incoming
character has been received and transferred into the RBR and is cleared by reading the RBR.
DBit 1‡: This bit is the overrun error (OE) indicator. When bit 1 is set, it indicates that before the character
in the RBR was read, it was overwritten by the next character transferred into the register . The OE indicator
is cleared every time the CPU reads the contents of the LSR.
DBit 2‡: This bit is the parity error (PE) indicator. When bit 2 is set, it indicates that the parity of the received
data character does not match the parity selected in the LCR (bit 4). The PE bit is cleared every time the
CPU reads the contents of the LSR.
DBit 3‡: This bit is the framing error (FE) indicator. When bit 3 is set, it indicates that the received character
does not have a valid (set) stop bit. The FE bit is cleared every time the CPU reads the contents of the LSR.
DBit4‡: This bit is the break interrupt (BI) indicator. When bit 4 is set, it indicates that the received data input
was held clear for longer than a full-word transmission time. A full-word transmission time is defined as the
total time of the start, data, parity, and stop bits. The BI bit is cleared every time the CPU reads the contents
of the LSR.
†The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.
‡Bits 1 through 4 are the error conditions that produce a receiver line-status interrupt.
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PRINCIPLES OF OPERATION
line status register (LSR)† (continued)
DBit 5: This bit is the THRE indicator. Bit 5 is set when the THR is empty, indicating that the ACE is ready
to accept a new character. If the THRE interrupt is enabled when the THRE bit is set, then an interrupt is
generated. THRE is set when the contents of the THR are transferred to the transmitted shift register. This
bit is cleared concurrent with the loading of the THR by the CPU.
DBit 6: This bit is the transmitter empty (TEMT) indicator. Bit 6 is set when the THR and the transmitter shift
register are both empty. When either the THR or the transmitter shift register contains a data character , the
TEMT bit is cleared.
DBit 7: This bit is always clear.
modem control register (MCR)
The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is
emulating a modem. The contents of this register are summarized in Table 3 and are described in the following
bulleted list.
DBit 0: This bit (DTR) controls the data terminal ready (DTR) output. Setting bit 0 forces the DTR output to
its active state (low). When bit 0 is clear, DTR goes high.
DBit 1: This bit (RTS) controls the request to send (RTS) output in a manner identical to bit 0’s control over
the DTR output.
DBit 2: This bit (OUT1) controls the output 1 (OUT1) signal, a user designated output signal, in a manner
identical to bit 0’s control over the DTR output.
DBit 3: This bit (OUT2) controls the output 2 (OUT2) signal, a user designated output signal, in a manner
identical to bit 0’s control over the DTR output.
DBit 4: This bit provides a local loopback feature for diagnostic testing of the ACE. When bit 4 is set, the
following occurs:
1. The SOUT is asserted high.
2. The SIN is disconnected.
3. The output of the transmitter shift register is looped back into the RSR input.
4. The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected.
5. The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four
modem control inputs.
6. The four modem control output terminals are forced to their inactive states (high).
In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify
the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational.
The modem control interrupts are also operational but the modem control interrupt sources are now the
lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the
IER.
DBits 5 through 7: These bits are clear.
†The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.
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PRINCIPLES OF OPERATION
modem status register (MSR)
The MSR is an 8-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provides change
information; when a control input from the modem changes state the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are
described in the following bulleted list.
DBit 0: This bit is the delta clear to send (DCTS) indicator. Bit 0 indicates that the CTS input has changed
states since the last time it was read by the CPU. When this bit is set and the modem status interrupt is
enabled, a modem status interrupt is generated.
DBit 1: This bit is the delta data set ready (DDSR) indicator. Bit 1 indicates that the DSR input has changed
states since the last time it was read by the CPU. When this bit is set and the modem status interrupt is
enabled, a modem status interrupt is generated.
DBit 2: This bit is the trailing edge of ring indicator (TERI) detector. Bit 2 indicates that the RI input to the chip
has changed from a low to a high state. When this bit is set and the modem status interrupt is enabled, a
modem status interrupt is generated.
DBit 3: This bit is the delta data carrier detect (DDCD) indicator. Bit 3 indicates that the DCD input to the chip
has changed state since the last time it was read by the CPU. When this bit is set and the modem status
interrupt is enabled, a modem status interrupt is generated.
DBit 4: This bit is the complement of the clear to send (CTS) input. When bit 4 (loop) of the MCR is set, this
bit is equivalent to the MCR bit 1 (RTS).
DBit 5: This bit is the complement of the data set ready (DSR) input. When bit 4 (loop) of the MCR is set,
this bit is equivalent to the MCR bit 0 (DTR).
DBit 6: This bit is the complement of the ring indicator (RI) input. When bit 4 (loop) of the MCR is set, this
bit is equivalent to the MCRs bit 2 (OUT1).
DBit 7: This bit is the complement of the data carrier detect (DCD) input. When bit 4 (loop) of the MCR is set,
this bit is equivalent to the MCRs bit 3 (OUT2).
programmable baud generator
The ACE contains a programmable baud generator that takes a clock input in the range between dc and 9 MHz
and divides it by a divisor in the range between 1 and (216 −1). The output frequency of the baud generator is
sixteen times (16×) the baud rate. The formula for the divisor is:
divisor # = XTAL1 frequency input B (desired baud rate ×16)
Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either
of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Tables 7 and 8 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072 MHz,
respectively. For baud rates of 38.4 kilobits per second and below, the error obtained is very small. The accuracy
of the selected baud rate is dependent on the selected crystal frequency.
Refer to Figure 10 for examples of typical clock circuits.
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22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Table 7. Baud Rates Using a 1.8432-MHz Crystal
DESIRED
DIVISOR USED
PERCENT ERROR
DESIRED
BAUD RATE
DIVISOR USED
TO GENERATE
16 CLOCK
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
BAUD RATE
TO GENERATE
16×CLOCK
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
50 2304
75 1536
110 1047 0.026
134.5 857 0.058
150 768
300 384
600 192
1200 96
1800 64
2000 58 0.69
2400 48
3600 32
4800 24
7200 16
9600 12
19200 6
38400 3
56000 2 2.86
Table 8. Baud Rates Using a 3.072-MHz Crystal
DESIRED
DIVISOR USED
PERCENT ERROR
DESIRED
BAUD RATE
DIVISOR USED
TO GENERATE
16 CLOCK
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
BAUD RATE
TO GENERATE
16×CLOCK
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
50 3840
75 2560
110 1745 0.026
134.5 1428 0.034
150 1280
300 640
600 320
1200 160
1800 107 0.312
2000 96
2400 80
3600 53 0.628
4800 40
7200 27 1.23
9600 20
19200 10
38400 5
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PRINCIPLES OF OPERATION
XTAL1
Oscillator Clock
to Baud
Generator
Logic
VCC
XTAL2
External
Clock
Optional
Clock
Output
Driver
Optional
XTAL1
VCC
XTAL2
RX2
C1
RPCrystal
C2
Oscillator Clock
to Baud
Generator
Logic
TYPICAL CRYSTAL OSCILLATOR NETWORK
CRYSTAL RPRX2 C1 C2
3.1 MHz 1 MΩ1.5 kΩ10−30 pF 40−60 pF
1.8 MHz 1 MΩ1.5 kΩ10−30 pF 40−60 pF
Figure 10. Typical Clock Circuits
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24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
receiver buffer register (RBR)
The ACE receiver section consists of a receiver shift register and a RBR. T iming is supplied by the 16×receiver
clock (RCLK). Receiver section control is a function of the ACE line control register.
The ACE receiver shift register receives serial data from the serial input (SIN) terminal. The receiver shift
register then converts the data to a parallel form and loads it into the RBR. When a character is placed in the
RBR and the received data available interrupt is enabled, an interrupt is generated. This interrupt is cleared
when the data is read out of the RBR.
scratch register
The scratch register is an 8-bit register that is intended for programmer use as a scratchpad, in the sense that
it temporarily holds programmer data without affecting any other ACE operation.
transmitter holding register (THR)
The ACE transmitter section consists of a THR and a transmitter shift register. Timing is supplied by the baud
out (BAUDOUT) clock signal. Transmitter section control is a function of the ACE line control register.
The ACE THR receives data from the internal data bus and, when the shift register is idle, moves it into the
transmitter shift register. The transmitter shift register serializes the data and outputs it at the serial output
(SOUT). If the THR is empty and the transmitter holding register empty (THRE) interrupt is enabled, an interrupt
is generated. This interrupt is cleared when a character is loaded into the register.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TL16C450FN ACTIVE PLCC FN 44 26 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16C450FNG4 ACTIVE PLCC FN 44 26 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16C450FNR ACTIVE PLCC FN 44 500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16C450FNRG4 ACTIVE PLCC FN 44 500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16C450N OBSOLETE PDIP N 40 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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information may not be available for release.
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to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Jul-2009
Addendum-Page 1
MECHANICAL DATA
MPLC004A – OCTOBER 1994
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER
4040005/B 03/95
20 PIN SHOWN
0.026 (0,66)
0.032 (0,81)
D2/E2
0.020 (0,51) MIN
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D2/E2
0.013 (0,33)
0.021 (0,53)
Seating Plane
MAX
D2/E2
0.219 (5,56)
0.169 (4,29)
0.319 (8,10)
0.469 (11,91)
0.569 (14,45)
0.369 (9,37)
MAX
0.356 (9,04)
0.456 (11,58)
0.656 (16,66)
0.008 (0,20) NOM
1.158 (29,41)
0.958 (24,33)
0.756 (19,20)
0.191 (4,85)
0.141 (3,58)
MIN
0.441 (11,20)
0.541 (13,74)
0.291 (7,39)
0.341 (8,66)
18
19
14
13
D
D1
13
9
E1E
4
8
MINMAXMIN
PINS
**
20
28
44
0.385 (9,78)
0.485 (12,32)
0.685 (17,40)
52
68
84 1.185 (30,10)
0.985 (25,02)
0.785 (19,94)
D/E
0.395 (10,03)
0.495 (12,57)
1.195 (30,35)
0.995 (25,27)
0.695 (17,65)
0.795 (20,19)
NO. OF D1/E1
0.350 (8,89)
0.450 (11,43)
1.150 (29,21)
0.950 (24,13)
0.650 (16,51)
0.750 (19,05)
0.004 (0,10)
M
0.007 (0,18)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
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