August 1996 M B 86 6 87 A Version 2.0 Adaptation Layer Controller (ALC) Product Flyer FML/NPD/ALC/FL/1 205 The Fujitsu MB86687A is an ATM protocol controller which autonomously terminates ATM Adaptation Layer standards} PLASTIC PACKAGE Type 3/4 and Type 5. Simultaneous segmentation and reassembly can be achieved at up to 155Mbps. | SQFP-208 Communication with the host system is through a high speed} bus interface. ; VBR and CBR ATM traffic classes are implemented in this} device. Traffic management to ATM Forum TM 3.1 is } supported on up to 1024 virtual circuits (VCs) without local SRAM. Flexible bus configuration allows optimised system design. ; The device is ideally suited to many customer premises equipment applications including ATM switches, access units} and adaptor cards and multi-protocol hubs, bridges and } routers. PRR, r FEATURES * Supports Broadband ISDN Adaptation Layer standards Type 3/4 and Type 5 * Supports simultaneous segmentation and reassembly on up to 1024 VCs with on-chip cache * Supports up to 12 peak segmentation rates with leaky bucket averaging on a per VC basis with optional bucket fill before segmentation continue. * Programmable peak and average rates and leaky bucket averaging on total ALC cell stream output. * Support for scatter / gather mode * Transparent ATM cell and cell payload modes including support for OAM and Resource Management cells * UTOPIA Level 1 v2.01 functionally compatible cell stream interface with optional HEC checking on receive * Flexible routing tag append/remove mode for direct ATM Switch connection * Supports buffer chaining, streaming and ageing time-out * Separate 32 bit data and 16 bit control ports with optimized DMA interface * JTAG pins compliant to IEEE1149.1 are provided * Fabricated in 0.8 micron CMOS technology with CMOS/TTL compatible I/O and single +5V power supply Copyright 1996 Fujitsu Microelectronics Limited Page f of 6August 1996 Version 2.0 FML/NPD/ALG/FLA 205 MB86687A Adaptation Layer Controller (ALC) oS FUI TSU Transmit Segmentation & ATM Hee! = Buffer =--m-| Convergence LI Cell 7 (3 Cells} Sub-layer Transmitter } Cell Stream Traffic Management Interface c aon <i $$ Controller pee Leal ] Memory Interface Receive Reassembly and ATM @ Buffer pa| Convergence cell [* (2 Cells) Sub-layer Receiver VCI Status/ a | Descriptor Table ALC Internal Regisiers Cell Stream Interface JTAG t O D JTAG Interface Processor Interface Fig. 1 - ALC Block Diagram General The ALC simultaneously supports autonomous segmentation and reassembly Adaptation Support of user data packets on up to 1024 virtual circuits (VCs). User data packets are transferred to and from shared data structure memory using a high speed intelligent DMA controller with a 32 bit data bus. Shared data structures are stored in SAR (Segmentation and Reassembly) memory which can be either dual port memory or a partition of system memory. The ALG autonomously terminates the protocols involved in segmenting and reassembling data streams conforming to Adaptation Layer Types 3/4 and 5. AAL 3/4 and AAL 5 traffic can be handled simultaneously. Streaming and Message Modes as defined for AAL 3/4 and AALS are supported. Copyright 1996 Fujitsu Microelectronics Limited Page 2 of 6FML/NPD/ALG/FLA 205 August 1996 Version 2.0 oO MB86687A Adaptation Layer Controller (ALC) FUJITSU Traffic Shaping Cell Stream DMA Interface Microprocessor Transmit Operation Receive Operation JTAG The Traffic Manager initiates periodic packet segmentation from one of 12 Peak Rate Queues at programmable intervals. The queues are grouped into three priority classes: high, medium and low, with 4 queues in each priority class. It also manages total ALC peak transmission rate. If the total peak transmission rate exceeds a specified threshold, the traffic management controller will service the queues according to their priority until the total peak rate falls below the threshold. This mechanism ensures that the ALC will not exceed the negotiated quality of service for the overall link connection. The average rate shaping of transmit traffic on a per virtual circuit basis uses the leaky bucket algorithm. The leaky bucket algorithm also controls the total ALC transmission. The Cell Stream Interface transmits and receives an asynchronous stream of ATM cells in 8-bit parallel form with separate synchronisation signals used to identify the start of a cell. The ALC Cell Stream Interface operates in one of two environments; either in a Switch Device or a Termination Device. The ALC has a 32-bit data and a 24-bit address DMA interface that may be programmed for either big or little endian formats. It supports standard and extended Intel/Motorola bus cycles. Intel and Motorola bus negotiations are also supported. A 16-bit control/status port is used to configure the device. This includes the setting up of receive circuits. The maintenance of the queue structures and monitoring of cell and packet loss are also achieved using this interface. An interrupt mechanism is implemented to indicate queue updates and exception conditions. Transmit operation is implemented using a simple queue structure. A buffer containing part or all of a packet's data is scheduled by placing a Transmit Descriptor identifier on a Pending Queue. The ALG links queued descriptors for the same VC into a list. Data is then assembled under the control of the traffic scheduler into packets. A data pointer is contained in the transmit descriptor as is a pointer to a table containing circuit traffic parameters. When a buffer is exhausted, it is returned to the host by putting the transmit descriptor identifier on a Release Queue. Receive operation is implemented using a simple queue structure. At the start of reassembly for each new packet the ALC finds a new Receive Deseriptor (RD) by reading a Buffer Free Queue. Each RD contains a pointer to a receive buffer. The RD also contains fields to support receive buffer chaining and the received VCI or MID fields as well as receive buffer ageing timeout. After reception is complete, the ALC passes the receive descriptor to the host using a Buffer Ready Queue. Each entry in the queue contains a pointer to the appropriate RD and the status of the associated buffer. The ALC provides boundary scan test circuitry fully compliant with IEEE 1149.1. The ALCs JTAG circuitry permits easier board level testing to be carried out by allowing the signal pins on the device to forma serial scan chain around the device. JTAG test modes are controlled by accessing an internal test access Copyright 1996 Fujitsu Microelectronics Limited Page 3 of 6August 1996 Version 2.0 FML/NPD/ALG/FLA 205 MB86687A Adaptation Layer Controller (ALC) oS FUJI Dual Port Memory -SAR data and control parameters stored in shared dual port memory Rrra ree ee eee eae aa ee Syst 4 SAR PHY ; ysiem ost Memor i Memory CPU nae ony wee ALC eee ; c Switch ; ontrol) Shared Memory - SAR data and control parameters stored in : system memory System PHY Memory Host ALC or (Data and CPU TP) switch 3 Control) Hybrid - SAR data stored in system memory and SAR control parameters stored in shared pual port memory System SAR PHY : Memary Host egepe| Memory ALC +H or ; (Data) CPU (Control) Switch Pn nn nn EE EE EE ETRE EEE REI RETREATED EAS NRTA TR ETERS STRATES ARN RATERS RAREST EES SEE EEE ETE ETRE : Fig. 2- ALC Possible Configurations Copyright 1996 Fujitsu Microelectronics Limited Page 4 of 6August 1996 Version 2.0 FML/NPD/ALG/FLA 205 MB86687A Adaptation Layer Controller (ALC) FUJI Q | ewes SRDO-SRD31 ieee, 1M Ape me JTAG Test Port eR, TDO TDI TCK TMS TIN | a we a al Microprocessor Fig. 3 - MB86687A I/O Block Diagram Sennen ; } i ; | ; : ; | ; | ; | 4 | ; | ; : ; | ; | 4 | ; : ; : ; | ; | ; 4 | ; | ; : ; | ; | 4 | ; | } : ; | ; | ; 4 | ; : ; | ; 2 ; : } : ; 2 ; | ; : ; | ; 2 r= ; | PR T PR T ; t | : ; | 0 3 oO t - : i 3 Y : ; 3 | t i T | J T t ; : ; ; . ; 3 - | } } : : ; ; : t ; 2 ; i | ; ; | : : : t ; ; | ; _Tocs | } : : t | t ; _ : ; ; | ; 1 _T DCS | : : 2 t : ; t ; ; : ; _ ~_ | ; t ; | t : ; | : : ll : | Ce : t : : | ; / . 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However, i i to high static voltages or elec i i ins circul tthe inputs against damage due | ted voltages to iis. vised thal non val preeaulrons be taken to avoid application of any voltage higher than maximum ral itis advised that norm Copyright 1996 Fujitsu Microelectronics Limited Page 5 of 6August 1996 Version 2.0 FML/NPD/ALG/FLA 205 MB86687A Adaptation Layer Controller (ALC) oS FUJI Worldwide Headquarters Japan Fujitsu Limited Tek +81 44 754 3753 1015 Kamiodanaka Fax: 181 44 754 3332 Nakaharaku Kawasaki 211 Japan hito-//www. fujitsu.co_jp/ USA Tel: +1 4089229000 Fujitsu Microelectronics Inc Fax: +1 4089229779 3545 North First Street San Jose CA 95134-1804 USA Tek +1800 866 8608 Customer Response Center Fax: +1 4089229179 Mon-Fri: 7am-5pm (PST) hito//www. fujitsumicro.com/ Asia Fujitsu Microelectronics Asia PTE Limited Tel +65 336 1600 No. 51 Bras Basah Road Fax: +65 336 1609 Plaza by the Park #06-04/07 Singapore 0718 http://www. fsi.com.sg/ Europe Tel: +49 6103 6900 Fujitsu Mikroelektronik GmbH Fax: +49 6103 6901 22 Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany hitp//www. fujitsu.ede.com/ assumes no responsibility for inaccuracies. This document is proprietary to Fujitsu. No part of this document may be copied or reproduced in any form or by any means, or disclosed or transferred to any third party without written prior consent of Fujitsu. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu The information contained in this document does not convey any title or licence under the copyright, patent rights or trade marks claimed and owned by Fujitsu or its licensors. Fujitsu reserves the right to change specifications without notice. FML/NPD/ALC/FLA 205 - 2.0 Copyright 1996 Fujitsu Microelectronics Limited Page 6 of 6