HUF76107P3 - Fairchild Semiconductor

HUF76107P3

20A, 30V, 0.052 Ohm, N-Channel, Logic

Level UltraFET Power MOSFETs

These N- C hann el power

MOSFETs are manuf actured using

the innovative UltraFET™ process.

This advanced process technology

achiev es the lowest possible on-resistance per silicon area,

resulting in outstan ding per formance. This device is

capable of withstanding high energy in the av alanche mode

and the diode exhibits very low r everse recover y time and

stored charge. It was designed fo r use in app lications

where power efficiency is important, such as switching

regulator s, switchi ng converter s, motor dr ivers, relay

drivers, low-volt age bus switches, and power manag eme nt

in por t able and batt ery-operat ed produ cts.

Formerly deve lopmental ty pe TA76 107.

Features

• Logic Level Gate Driv e

• 20A, 30V

•Ultr a Low On-Resi stance, rDS(ON) = 0.052Ω

• Tem peratur e Com pensating PSPI CE® Model

• Tem peratur e Com pensating SABER© Model

• Thermal Impedanc e SPICE Model

• Thermal Impedanc e SABER Model

• Peak Current vs Pulse Widt h Curve

• UIS Rating Curve

• Related Literature

- TB334, “G uidelines for Soldering Surface Mount

Components to PC Boards”

Symbol

Packaging

Ordering Information

PART NUMBER PACKAGE BRAND

HUF76107P3 TO-220AB 76107P

JEDEC TO-220AB

DRAIN

SOURCE

GATE

DRAIN

(FLANGE)

Data Sheet Januar y 2003

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specif ied UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 30 V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 30 V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V

Drain Current

Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID

Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID

Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM

10.5

Figu re 4

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Figur es 6, 17, 18

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

0.30 W

W/oC

Oper ating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -40 to 150 oC

Maximu m Temperature for S oldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300

260

CAUT ION: St ress es above those list ed in “Abs olute Maximum Rati ngs” may cause per mane nt damage to the device. This is a str ess only rating and operati on of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. TJ = 25oC to 150oC.

Electrical Speci fications TA = 25oC, Unless Otherwise Specified

PARAMETE R SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Dr ain t o Sou rce Breakdown Voltag e BVDSS ID = 25 0µA, VGS = 0V (Fig ure 1 2) 30 - - V

Z ero Gat e V ol tag e D rain C urrent IDSS VDS = 25V, VGS = 0V - - 1 µA

VDS = 25V, VGS = 0V, TC = 1 50 oC--250µA

Ga te t o Sour c e Le ak ag e C urr e nt IGSS VGS = ±20V - - ±100 nA

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 11) 1 - 3 V

Drain t o Source On Resistance rDS(ON) ID = 20A , VGS = 10V (Figure 9, 10) - 0.042 0.052 Ω

ID = 10.5A, VGS = 5V (Figure 9) - 0.058 0.080 Ω

ID = 10A, VGS = 4.5V (Figure 9) - 0.065 0.085 Ω

THERMAL SPECIFICATIONS

T her m al Res ista nc e Ju ncti on to Case R θJC (F i gu re 3) - - 3. 3 oC/W

Thermal Resistance Junction to Ambient RθJA TO-220 62 oC/W

SWITCHING SPECIFICATIONS (VGS = 4.5V)

Turn -On Time tON VDD = 15V, ID ≅ 10A, RL = 1. 50Ω,

VGS =4.5V, RGS = 33Ω

(Figure s 15, 21 , 22)

--120ns

Turn-O n Delay Time td(ON) -14-ns

Rise Time tr-66-ns

Turn-O ff Delay Time td(OFF) -16-ns

Fa ll Time tf-22-ns

Turn -Off Time tOFF --57ns

HUF76107P3

SWITCHING SPECIFICATIONS (VGS = 1 0V )

Turn -On Time tON VDD = 15V, ID ≅ 20A, RL =0.75 Ω,

VGS =10V, RGS = 3 3Ω

(Figure s 16, 21 , 22)

--75ns

Turn-O n Delay Time td(ON) -18-ns

Rise Time tr-30-ns

Turn-O ff Delay Time td(OFF) -62-ns

Fa ll Time tf-20 -ns

Turn -Off Time tOFF --125ns

GATE CHARGE SPECIFICATIONS

T otal G ate Charg e Qg(TOT) VGS = 0 V to 10V VDD = 15V, ID ≅

10.5A,

RL = 1.4 3Ω

Ig(REF) = 1.0mA

(Figures 14, 19 , 20)

- 8.6 10.3 nC

Gat e Charg e at 5V Qg(5) VGS = 0 V to 5V - 4.7 5. 7 nC

T hresh ol d G at e Ch arg e Qg(TH) VGS = 0V to 1V - 0.35 0 .42 nC

Ga te to Sourc e Gate Charg e Qgs -1.00- nC

Ga te t o Drai n “M iller” Charge Qgd -2.40- nC

CAPACITANCE SPECIFICATIONS

Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz

(Fi gu r e 13 ) -315- pF

Output Capacitance COSS -170- pF

Reverse Transfer Capacitance CRSS -30-pF

Electrical Speci fications TA = 25oC, Unless Otherwise Specified

PARAMETE R SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Specific ations

PARAMETER SYM BOL TEST CONDITIONS M IN TYP MAX UNITS

Source to Drain Diode Volta ge VSD ISD = 10.5A - - 1.25 V

Reverse Recovery Time trr ISD = 10.5A, dISD/dt = 100A/µs--39ns

Reverse Recovered Charge QRR ISD = 10.5A, dISD/dt = 100A/µs--49nC

Typical Performance Curves U nl es s oth erw is e sp ec ifi ed

FIGURE 1. NORMALIZED PO WER DISSIPATI ON vs CASE

TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPER ATURE

TA, AMBIENT TEMPERATURE (oC)

POWER DISSIPATION MULTIPLIER

00 25 50 75 100 150

0.2

0.4

0.6

0.8

1.0

1.2

125

025 50 75 100 125

ID, DRAIN CURRENT (A)

TC, CASE TEMPERATURE (oC)

150

VGS=4.5V

VGS=10V

HUF76107P3

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

FIGURE 4. PEAK CURRENT CAPABILITY

FIGURE 5. FORWARD BIAS SAFE OPERATI NG AREA

NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING

CAPABILITY

Typical Performance Curves U nl es s oth erw is e sp ec ifi ed (Continued)

t, RECTANGULAR PULSE DURATION (s)

10-5 10-1 100

0.1

10-2

ZθJC, NORMALIZED

THERMAL IMPEDANCE

0.01 10-4 10-3

SINGLE PULSE

NOTES:

DUTY FACTOR: D = t1/t2

PEAK TJ = PDM x ZθJC x RθJC + TC

PDM

t1t2

101

DUTY CYCLE - DESCENDING ORDER

0.5

0.2

0.1

0.05

0.01

0.02

TC = 25oC

I = I25 150 - TC

125

FOR TEMPERATURES

ABOVE 25oC DERATE PEAK

CURRENT AS FOLLOWS:

VGS = 10V

TRANSCONDUCTANCE

MAY LIMIT CURRENT

IN THIS REGION

IDM, PEAK CURRENT (A)

500

10-5 10-4 10-3 10-2 10-1 100101

t, PULSE WIDTH (s)

100

VGS = 5V

TJ = MAX RATED

TC = 25oC

10ms

1ms

BVDSS MAX = 30VLIMITED BY rDS(ON)

AREA MAY BE

OPERATION IN THIS

1001VDS, DRAIN TO SOURCE VOLTAGE (V)

100

200

ID, DRAIN CURRENT (A)

100µs

1 10 100

100

0.01

200

IAS, AVALANCHE CURRENT (A)

tAV, TIME IN AVALANCHE (ms)

tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)

If R = 0

If R ≠ 0

tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]

STARTING TJ = 25oC

STARTING TJ = 150oC

0.1

0.001

HUF76107P3

FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS

FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT FIGURE 10. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

FIGURE 11. NORMALIZED GATE THRESHOL D V OLTA GE v s

JUNCTION TEMPERATURE FIGURE 12. NORMALIZED DRAIN T O S OURCE BREAKDOW N

VOLTAGE vs JUNCTION TEMPERATURE

Typical Performance Curves U nl es s oth erw is e sp ec ifi ed (Continued)

012 6

ID, DRAIN CURRENT (A)

VGS, GATE T O SOURCE VOLTAGE (V)

150oC

-40oC

25oC

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VDD = 15 V

453

5VGS = 3.5V

VGS = 4V

01 3456

ID, DRAIN CURRENT (A)

VDS, DRAIN T O SOURCE VOLTAGE (V)

VGS = 5V

VGS = 10V

VGS = 3V

VGS = 4.5V

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

30 4

VGS, GATE TO SOURCE V OLTAGE (V)

26108

ID = 20A

ID = 12A

ID = 5A

rDS(ON), DRAIN TO SOURCE

ON RESISTANCE (mΩ)

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

0.50

0.75

1.00

1.25

1.75

-60 0 60 120

NORMALIZED DRAIN TO SOURCE

TJ, JUNCTION TEMPERATURE (oC)

ON RESISTANCE

180

1.50

2.00

120

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VGS = 10V, ID = 20A

-60 0 60 120

0.6

0.8

0.9

1.1

1.2

NORMALIZED GATE

TJ, JUNCTION TEMPERATURE (oC)

THRESHOLD VOLTAGE

VGS = VDS, ID = 250µA

180

1.0

0.7

0.6

1.15

1.10

1.00

0.95

0.90

-60 0 60 120

TJ, JUNCTION TEMPERATURE (oC)

NORMALIZED DRAIN TO SOURCE

BREAKDOWN VOLTAGE

ID = 250µA

180

1.05

HUF76107P3

FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.

FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT

GATE CURRENT

FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE

Test Circuits and Waveforms

FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS

Typical Performance Curves U nl es s oth erw is e sp ec ifi ed (Continued)

COSS

600

400

00 5 15 25

C, CAPACITANCE (pF)

300

VDS, DRAIN TO SOURCE VOLTA GE (V)

200

100

CISS

CRSS

10 20

500

VGS = 0V, f = 1MHz

CISS = CGS + CGD

CRSS = CGD

COSS ≈ CDS + CGD

VGS, GATE TO SOURCE VOLTAGE (V)

VDD = 15V

8100

Qg, GATE CHARGE (nC)

ID = 20A

ID = 12A

ID = 5A

WAVEFORMS IN

DESCENDING ORDER:

20 30 40 500

100

010

SWITCHING TIME (ns)

RGS, GATE TO SOURCE RESISTANCE (Ω)

td(OFF)

td(ON)

VGS = 4.5V, VDD = 15V, ID = 10A, RL= 1.50Ω

20 30 40 500

100

010

SWITCHING TIME (ns)

RGS, GATE TO SOURCE RESISTANCE (Ω)

td(OFF)

td(ON)

VGS = 1 0V, VDD = 15V, ID = 20A, RL= 0.75Ω

VGS

0.01Ω

IAS

VDS

VDD

DUT

VARY tP TO OBTAIN

REQUIRED PEAK IAS

VDD

VDS

BVDSS

IAS

tAV

HUF76107P3

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

FIGURE 21. SWI TCHING TIME TEST CIRCUI T FIGURE 22. SWITCHING TIME WAVEFORMS

Test Circuits and Waveforms (Continued)

VGS +

VDS

VDD

DUT

Ig(REF)

VDD

Qg(TH)

VGS = 1V

Qg(5)

VGS = 5V

Qg(TOT)

VGS = 10

VDS

VGS

Ig(REF)

VGS

RGS DUT

-VDD

VDS

VGS

tON

td(ON)

90%

10%

VDS 90%

10%

td(OFF)

tOFF

90%

50%50%

10% PULSE WIDTH

VGS

HUF76107P3

PSPICE Electrical Mode l

SUBCKT HUF76107 2 1 3 ; REV June 1998

C A 12 8 4. 2e- 10

CB 15 14 4. 9e-10

CIN 6 8 2.85e- 10

D BODY 7 5 DBODYM O D

DBREAK 5 11 DBREAKMOD

DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 35.7

EDS 14 8 5 8 1

EGS 13 8 6 8 1

ESG 6 10 6 8 1

EVTH RES 6 21 19 8 1

EVTEM P 20 6 18 22 1

IT 8 1 7 1

LDRAIN 2 5 1e-9

LGATE 1 9 3.61e-9

LSOU RCE 3 7 3.61e-9

MMED 16 6 8 8 M M EDMOD

MSTR O 16 6 8 8 M ST ROMOD

MWEAK 16 21 8 8 M WE A KMOD

RBREAK 17 18 RBREAKMOD 1

RDRAIN 50 16 RDRAINMOD 3.7e-3

R G A T E 9 20 3.39

RL DRAIN 2 5 10

RLGATE 1 9 36.1

RLSOURCE 3 7 36.1

RSLC1 5 51 RSLCMOD 1e-6

RSLC2 5 50 1e 3

RSOURCE 8 7 RSOURCEMOD 30e-3

RVT HRES 22 8 RVTHRESMOD 1

RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1A M OD

S1B 13 12 13 8 S1BMO D

S2A 6 15 14 13 S2AMO D

S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*50),7))}

.MO DE L DB ODYM OD D (IS = 2.8 e-13 IKF = 5 RS = 1.37e- 2 TRS 1 = 2e-4 TRS 2 = 2e-6 CJO = 4.9e- 10 TT = 2.8 8e-8 M = 3.9e-1 XTI = 4. 75 )

.MO DE L DB REAKMOD D (RS = 2.5e- 1 TRS 1 = 9.94e -4 TRS 2 = 9.12 e-7)

.MODEL DPLCAPMOD D (CJO = 3.2e-10 IS = 1e-30 N = 10 M = 7.4e-1)

.MODEL MMEDMOD NMOS (VTO = 2.07 KP = 1.25 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.39)

.MODE L M STROMOD NMOS (VTO = 2.4 KP = 19.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)

.MODEL MWEAKMOD NMOS (VTO = 1.8 KP =1e-1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33.9 RS=.1)

.MO DE L RB REAKMOD RE S (TC1 = 9.94e-4 TC 2 = 9.84e-8)

.MODEL RDRAINMOD RES (TC1 = 3.9e-2 TC2 = 5.5e-5)

.MO DE L RS LCMOD RES (TC1 = 1e-4 T C2 = 3.2e-6)

.MODEL RSOURCEMOD RES (TC1 = 1e-12 TC2 = 6e-6)

.MODEL RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -5.96e-6)

.MO DEL RVT EMP M O D RES (TC1 = -1.4e-3 T C2 = 1e-10)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.2 VOFF= -0.5)

.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= -4.2)

.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.8 VOFF= 0.0)

.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.0 VOFF= -0.8)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperat ure O ptions; IEEE Power Electronics Specialist Conf e rence Records, 1991, written by William J. Hepp and C. Frank Wheatley.

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK DBODY

RSOURCE

SOURCE

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ESLC

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

HUF76107P3

SABER Electrical Model

nom tem p=25 deg c 30v LL Ultrafet

REV Junel 1998

templ ate hu f76107 n2,n1,n3

electrical n2,n1,n3

{

var i iscl

d..model dbodym od = (i s=2.8e-13, xt i =4.75, cjo=4. 9e-10 ,t t =2.88e -8, m=3. 9e-1)

d..model dbreakmod = ()

d..model dplcap m od = (cjo=3.2e-10, i s =1e-30, n=10, m =7.4e-1)

m..model mmedmod = (type=_n,vto=2.07,kp=1.25,is=1e-30, tox=1)

m..model mstrongmod = (type=_n,vto=2.4,kp=19.5,is=1e-30, tox=1)

m..model mweakmod = (type=_n,vto=1.8,kp=1e-1,is=1e-30, tox=1)

sw_v cs p..mo del s1amod = (ron= 1e-5,roff=0.1,von=-4.2,vof f = -0.5)

sw_v cs p..mo del s1bmod = (ron= 1e-5,roff=0.1,von=-0.5,vof f = -4.2)

sw_v cs p..mo del s2amod = (ron= 1e-5,roff=0.1,vo n=-0. 8, vof f=0.0)

sw_v cs p..mo del s2bmod = (ron= 1e-5,roff=0.1,vo n=0.0 ,v of f=-0.8)

c . ca n1 2 n8 = 4.2e -10

c.cb n15 n14 = 4. 9e-10

c.cin n6 n8 = 2.85 e-10

d.dbody n7 n71 = model=dbodymod

d.dbreak n72 n11 = model=dbreak m od

d.dplcap n10 n5 = m odel=dplcapmod

i.it n8 n17 = 1

l.ldrain n2 n5 = 1e-9

l.lg ate n1 n9 = 3.61e-9

l.lsource n3 n7 = 3.61e -9

m.mmed n16 n6 n8 n8 = m odel=m m edmod, l=1u, w=1u

m.ms t rong n16 n6 n8 n8 = mod el =m strongmod, l=1u, w=1u

m.mw eak n16 n21 n8 n8 = model=m wea kmod, l=1u, w=1u

res. rbreak n17 n18 = 1, tc1=9.94e-4,tc2= -9.84e-8

res. rdbody n71 n5 =1. 37e-2, tc 1=2e-4 , t c2=2e -6

res. rdbreak n72 n5 =2. 5e-1, tc 1=9.94e-4, tc 2=9.1 2e-7

res. rdrain n50 n16 = 3.7e-3, tc 1=3. 9e-2, tc2=5.5e -5

res.rgate n9 n20 = 3.39

res. rl drain n2 n5 = 10

res. rl gate n1 n9 = 36. 1

res. rl sour ce n3 n7 = 36.1

res. rslc1 n5 n51 = 1e-6, tc1 =1e-4, t c2=3. 2e-6

res. rslc2 n5 n50 = 1e3

res.rsource n8 n7 = 30e-3, tc1=1e-12,tc2=6e-6

res.rvtemp n18 n19 = 1, tc1=-1.4e-3,tc2=1e-10

res. rvthres n22 n8 = 1, tc1=-1. 9e-3,tc 2=-5. 96e-6

spe. ebreak n11 n7 n17 n1 8 = 35.7

spe. eds n14 n8 n5 n8 = 1

spe. egs n13 n8 n6 n8 = 1

spe. esg n6 n10 n6 n8 = 1

spe. evtemp n20 n6 n18 n2 2 = 1

spe.evthres n6 n21 n19 n8 = 1

sw_v cs p.s1a n6 n12 n13 n8 = mo del =s1a m od

sw_v cs p.s1b n13 n12 n13 n8 = model=s1 bm od

sw_v cs p.s2a n6 n15 n14 n13 = model=s2 am od

sw_v cs p.s2b n13 n15 n14 n13 = mod el= s2bmod

v.vbat n22 n19 = dc=1

equations {

i (n51->n50) +=iscl

iscl : v (n51, n50) = ((v(n5, n51)/ (1e-9+a bs(v(n5,n 51)))) * ((abs(v(n5 ,n51) *1e6/ 50))**7 ))

}

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK DBODY

RSOURCE

SOURCE

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ISCL

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

RDBODY

RDBREAK

HUF76107P3

SPICE Thermal Model

REV June1998

HUF76107

CTHERM1 th 6 5.0e-5

CTHERM2 6 5 9.0e -4

CTHERM3 5 4 1.3e -3

CTHERM4 4 3 1.3e -3

CTHERM5 3 2 2.2e -2

CTHERM6 2 tl 7.9e-3

RTHERM1 th 6 2.0e-4

RTHERM2 6 5 6.0e -3

RTHERM3 5 4 3.5e -2

RTHERM4 4 3 8.5e -1

RTHERM5 3 2 5.1e -1

RTHERM6 2 tl 1

SABER Thermal Mod el

SABER thermal model HUF76107

template thermal_model th tl

thermal_c th, tl

{

c therm.ctherm1 th 6 = 5.0e-5

c therm.cther m2 6 5 = 9.0e-4

c therm.cther m3 5 4 = 1.3e-3

c therm.cther m4 4 3 = 1.3e-3

c therm.cther m5 3 2 = 2.2e-2

ctherm.ctherm6 2 tl = 7.9e-3

rtherm.rtherm1 th 6 = 2 .0e-4

rtherm.rtherm2 6 5 = 6.0e-3

rtherm.rtherm3 5 4 = 3.5e-2

rtherm.rtherm4 4 3 = 8.5e-1

rtherm.rtherm5 3 2 = 5.1e-1

rtherm.rtherm6 2 tl = 1

}

RTHERM4

RTHERM6

RTHERM5

RTHERM3

RTHERM2

RTHERM1

CTHERM4

CTHERM6

CTHERM5

CTHERM3

CTHERM2

CTHERM1

th JUNCTION

CASE

HUF76107P3

Rev. I2

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PRODUCT STATUS DEFINITIONS

Defini ti on of Terms

ACEx™

ActiveArray™

Bottomless™

CoolFET™

CROSSVOLT™

DOME™

EcoSPARK™

E2CMOS™

EnSigna™

FACT™

FACT Quiet Series™

FAST®

FASTr™

FRFET™

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SPM™

Stealth™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

SyncFET™

TinyLogic®

TruTranslation™

UHC™

UltraFET®

VCX™

A cross the board. Around the world.™

T he Power Franchi se™

P rogramma ble Acti ve Droop™

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Advance Information Format ive or In

Design This datasheet contains the design specificat ions for

product development. Specifications ma y change in

any manner without notice.

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supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any t ime without notice in order to impr ove

design.

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