April 2008 Rev 2 1/29
29
ST6G3240
Dual supply level translator for dual memory cards
(mini SD/micro SD + managed NAND)
Features
High speed: tPD (A to B) = 5 ns at TA = 85 °C
with VCCA = 1.8 V, VCCBn = 3.0 V
Low power dissipation: ICCA = ICCBn = 5 µA
(max.) at TA =85 °C
Balanced propagation delays: tPLH tPHL
Operating voltage range:
–V
CCA (opr) = 1.4 to 3.6 V
–V
CCBn (opr) = 1.4 to 3.6 V
B-side power supplies (VCCB1 and VCCB2) can
be different and separately controlled
Interchangeable voltage levels:
VCCA can either be greater than or less than
VCCBn
Low power mode:
when VCCBn is grounded or floating, there is
very low quiescent current on VCCA
Power down detection:
when either one of the B-side power supplies
(VCCB1 and VCCB2) is grounded or floating, the
corresponding port-n goes into high-Z state
automatically
Latch-up performance exceeds 500 mA
(JESD17)
ESD protection: 2 kV HBM
Integrated pull-up resistor and level translator
on the MS_Insert pin
Integrated pull-up resistor for card-detect pin
Description
The ST6G3240 is a dual supply low voltage
CMOS level translator supporting the dual
function of mini SD/micro SD card and managed
NAND memories. It is designed for use as an
interface between three systems using 3.3, 2.5
and 1.8 V respectively.
The ST6G3240 is capable of achieving high
speed operation and at the same time maintaining
low power dissipation.
While the A port is designed to track VCCA, the Bn
port (nCMD, nDAT, nCLK) is designed to track
VCCBn.
The device is intended for a two-way
asynchronous communication between data
buses.
μTFBGA 36
Table 1. Device summary
Order code Package Packing
ST6G3240TBR μTFBGA36 (3.6 x 3.6 mm) Tape and reel
www.st.com
Contents ST6G3240
2/29
Contents
1 ST6G3240 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ST6G3240 ST6G3240 general description
3/29
1 ST6G3240 general description
The ST6G3240 is a dual supply low voltage CMOS level translator supporting the dual
function of mini SD/micro SD card and managed NAND memories. It is designed for use as
an interface between three systems using 3.3, 2.5 and 1.8 V respectively.
The ST6G3240 is capable of achieving high speed operation and at the same time
maintaining low power dissipation.
While the A port is designed to track VCCA, the Bn port (nCMD, nDAT, nCLK) is designed to
track VCCBn.
The device is intended for a two-way asynchronous communication between data buses.
The direction of data transmission is determined by CMD-dir/DATA0-dir/DAT123-dir inputs.
In the typical application the Bn-port interfaces with the 3 V bus and the A-port with the 1.8V
bus.
With interchangeable voltage levels, there is no restriction on the voltage settings for each
supply. VCCA can be less than or greater than VCCB1 or VCCB2. For example, VCCA = 2.5 V,
VCCB1 = 3.6 V, VCCB2 = 1.8 V.
Full low power mode
This device can be entered into 'full lower power mode' by setting all the INn pins to low or
high, which will disable the device completely.
Partial low power mode
Alternatively, the device can be set into 'partial low power mode' by grounding or floating one
of the VCCBn power supplies. This will set all the corresponding output Port-n to High-Z.
However, it is important to note that VCCA power supply must not be grounded or floating
whenever VCCBn is connected to a power supply as this will lead to significant current
consumption increase.
Pin settings ST6G3240
4/29
2 Pin settings
2.1 Pin connection
Figure 1. Pin connection (top through view)
Note: It is required that VCC supply and ground pins are in close proximity, so as to allow for easy
capacitive coupling in application.
Table 2. Pin mapping
123456
AVCCA GND IN1 CD GND VCCB1
BCMD.h CMD-dir IN2 1CMD 1DAT0 2DAT0
CDAT0.h DAT0-dir GND 2CMD 1DAT1 2DAT1
DDAT1.h DAT123-dir GND GND 1DAT2 2DAT2
EDAT2.h CLK-f 2CLK 1CLK 1DAT3 2DAT3
FDAT3.h CLK-h MS_Insert MS_InsertB
1GND VCCB2
12345 6
A
B
C
D
E
F
μTFBGA36
ST6G3240 Pin settings
5/29
2.2 Pin description
Table 3. Pin description
Pin Type Side Symbol Name and function
A1 - A VCCA A-side power supply
A2 - - GND Ground (0 V)
A3 I A IN1
Output enable pin. Functions together
with IN2 pin. Refer to truth table for more
information on the settings
A4 - A CD Card detect pin with 100 kΩ internal pull-
up resistor on the A-side
A5 - - GND Ground (0 V)
A6 - B1 VCCB1 B1-side power supply
B1 I/O A CMD.h Command pin for A-side
B2 I A CMD-dir
Command direction pin
HIGH => CMD.h input, nCMD output
LOW => CMD.h output, nCMD input
B3 I A IN2
Output enable pin. Functions together
with IN1 pin. Refer to truth table for more
information on the settings
B4 I/O B1 1CMD Command pin for B1-side
B5 I/O B1 1DAT0 Data0 pin for B1-side
B6 I/O B2 2DAT0 Data0 pin for B2-side
C1 I/O A DAT0.h Data0 pin for A-side
C2 I A DAT0-dir
Data direction pin for DAT0
HIGH => DAT0.h input, nDAT0 output
LOW => DAT0.h output, nDAT0 input
C3 - - GND Ground (0 V)
C4 I/O B2 2CMD Command pin for B2-side
C5 I/O B1 1DAT1 Data1 pin for B1-side
C6 I/O B2 2DAT1 Data1 pin for B2-side
D1 I/O A DAT1.h Data1 pin for A-side
D2 I A DAT123-dir
Data direction pin for DAT1-DAT3
HIGH => DAT123.h input, nDAT123
output
LOW => DAT123.h output, nDAT123
input
D3 - - GND Ground (0 V)
D4 - GND Ground (0 V)
D5 I/O B1 1DAT2 Data2 pin for B1-side
Pin settings ST6G3240
6/29
CMD
Command pin is a bidirectional line. The host and card drivers are operating in push-pull
configuration.
DAT0-3
All data lines are bi-directional lines. Host and card drivers operate in push-pull mode.
CLK
Clock is a host to card signal. CLK operates in push-pull mode.
Feedback (return) clock is a feedback clock signal from level shifter to the host for controlling
delays.
CD
Card detect with internal pull up resistor. Pin will be pulled to VCCA when it is in high state.
IN1, IN2
Selection pins. When IN1 and IN2 are set to disabled state, all the data bus will be in high-
impedance. When enabled, all the data bus will be working as a level translator between
port A and port Bn (refer to the truth table for possible pin configuration).
Pin Type Side Symbol Name and function
D6 I/O B2 2DAT2 Data2 pin for B2-side
E1 I/O A DAT2.h Data2 pin for A-side
E2 O A CLK-f Feedback clock pin on A-side
E3 O B2 2CLK Clock Output pin for B2-side
E4 O B1 1CLK Clock Output pin for B1-side
E5 I/O B1 1DAT3 Data3 pin for B1-side
E6 I/O B2 2DAT3 Data3 pin for B2-side
F1 I/O A DAT3.h Data3 pin for A-side
F2 I A CLK.h Clock input pin for A-side
F3 - A MS_Insert MS_Insert pin with 100 kΩ internal pull-
up resistor on A-side
F4 O B1 MS_InsertB1 MS_Insert pin on B1-side
F5 - - GND Ground (0V)
F6 - B2 VCCB2 B2-side power supply
Table 3. Pin description (continued)
ST6G3240 Logic diagram
7/29
3 Logic diagram
Figure 2. ST6G3240 logic block diagram
VCCB1
DAT123-dir
DAT1.h
DAT2.h
DAT3.h
CLK.h
CLK-f
DATA0-dir
DAT0.h
CMD.h
GND
1C L K
2D A T 0
1D A T 1
1D A T 2
1D A T 3
1C M D
IN1
CD
100k
Ω
V
CCA
2C L K
1D A T 0
2D A T 1
2D A T 2
2D A T 3
2C M D
IN2
MS_ InsertB1
VCCB2
MS_
Insert
VCCB1
100k
Ω
VCCA
CMD-dir
CS00091
Logic diagram ST6G3240
8/29
Figure 3. Input and output equivalent circuit
H - Z: high impedance
Table 4. Truth table
IN1 IN2 CMD-dir
CMD.h
DAT0-dir
DAT0.h
DAT123-
dir
DAT1.h
DAT2.h
DAT3.h
CLK.h
CLK-f.h
1CMD
1DAT0
1DAT1
1DAT2
1DAT3
1CLK
2CMD
2DAT0
2DAT1
2DAT2
2DAT3
2CLK
H H H-Z H-Z H-Z H-Z H-Z H-Z
L H Active Active Active Active Active H-Z
H L Active Active Active Active H-Z Active
L L H-Z H-Z H-Z H-Z H-Z H-Z
Table 5. MS_Insert truth table
MS_Insert (referenced to VCCA) MS_InsertB1 (referenced to VCCB1)
HH
LL
ST6G3240 Maximum rating
9/29
4 Maximum rating
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 6. Absolute maximum ratings
Symbol Parameter Value Unit
VCCA Supply voltage -0.5 to 4.6 V
VCCB1 Supply voltage -0.5 to 4.6 V
VCCB2 Supply voltage -0.5 to 4.6 V
VIDC input voltage -0.5 to 4.6 V
VI/OA DC I/O voltage (output disabled) -0.5 to 4.6 V
VI/OBn DC I/O voltage (output disabled) -0.5 to 4.6 V
VOA DC output voltage -0.5 to VCCA +0.5 V
VOBn DC output voltage -0.5 to VCCBn +0.5 V
IIK DC input diode current - 20 mA
IOK DC output diode current - 50 mA
IOA DC output current ± 50 mA
IOBn DC output current ± 50 mA
ICCA DC VCCA or ground current ± 100 mA
ICCBn DC VCCBn or ground current ± 100 mA
PDPower dissipation at TA=7C
(1)
1. Derate above 70ºC by 18.5 mW/C
400 mW
Tstg Storage temperature -65 to 150 °C
TLLead temperature (10 sec) 260 °C
Table 7. Recommended operating conditions
Symbol Parameter Value Unit
VCCA Supply voltage 1.4 to 3.6 V
VCCB1 Supply voltage 1.4 to 3.6 V
VCCB2 Supply voltage 1.4 to 3.6 V
VI
Input voltage
(/IN1, /IN2, CMD-dir, DAT0-dir, DAT123-dir) 0 to VCCA V
VI/OA I/O voltage 0 to VCCA V
VI/OBn I/O voltage 0 to VCCBn V
Maximum rating ST6G3240
10/29
Symbol Parameter Value Unit
Top Operating temperature -40 to 85 °C
dt/dv Input rise and fall time 0 to 10 ns/V
Table 7. Recommended operating conditions (continued)
ST6G3240 Electrical characteristics
11/29
5 Electrical characteristics
Table 8. DC specifications for VCCA
Symbol Parameter
Test conditions Value
Unit
VCCA
(V)
VCCB
(V)
TA = 25 °C -40 to 85 °C
Min Max Min Max
VIH
High level
input voltage
1.4 1.95
1.4 3.6
0.65
VCCA
0.65
VCCA
V
1.95 2.7 1.7 1.7
2.7 3.6 2.0 2.0
VIL
Low level
input voltage
1.4 1.95
1.4 3.6
0.35
VCCA
0.35
VCCA
V
1.95 2.7 0.7 0.7
2.7 3.6 0.8 0.8
VOH
High level
output
voltage
1.4 3.6
1.4 3.6
IOH = -100 µA VCCA-0.1 VCCA-0.1
V
1.4 IOH = -1 mA 1.20 1.20
1.65 IOH = -2 mA 1.40 1.40
2.7 IOH = -4 mA 2.30 2.30
3I
OH = -8 mA 2.45 2.45
3.6 IOH = -8 mA 3.05 3.05
VOL
Low level
output
voltage
1.4 3.6
1.4 3.6
IOL = 100µA 0.10 0.10
V
1.4 IOL = 1 mA 0.20 0.20
1.65 IOL = 2 mA 0.25 0.25
2.7 IOL = 4 mA 0.40 0.40
3I
OL = 8 mA 0.55 0.55
3.6 IOL = 8 mA 0.55 0.55
IIA
Input
leakage
current per
input channel
1.4 3.6 1.4 3.6 VIA =V
CCA or
GND ±0.5 ±5 µA
IDIR
Input
leakage
current per
control input
(DIR)
1.4 3.6 1.4 3.6 VDIR = VCCA
or GND ±0.1 ±2 µA
Electrical characteristics ST6G3240
12/29
1 All A-ports I/Os and control inputs are powered by VCCA.
2 All Bn-ports I/Os are powered by VCCBn.
3 There is no restriction on VCCA or VCCBn, either one can be greater than the other.
Symbol Parameter
Test conditions Value
Unit
VCCA
(V)
VCCB
(V)
TA = 25 °C -40 to 85 °C
Min Max Min Max
IOZA
High
impedance
output
leakage
current
1.4-3.6 1.4 3.6
VIA = GND to
3.6 V
VIBn = GND
to 3.6 V
IN1, IN2 =
VCCA or IN1,
IN2 = GND
±1.0 ±10 µA
IOFF
Power off
A-side I/O
leakage
current
00
VIA= 0 to
3.6 V
INn = 0,
DIR=0
±1.0 ±10 µA
ICD
CD pin input
leakage
current
3.6 1.4 3.6 VCD = 0 50 500 µA
IMS
MS pin input
leakage
current
3.6 1.4 3.6 VMS = 0 50 500 µA
Table 8. DC specifications for VCCA (continued)
ST6G3240 Electrical characteristics
13/29
Table 9. DC specification for VCCBn
Symbol Parameter
Test conditions Value
Unit
VCCA
(V)
VCCBn
(V)
TA = 25 °C -40 to 85 °C
Min Max Min Max
VIH
High level input
voltage 1.4 – 3.6
1.4 – 1.95 0.65
VCCBn
0.65
VCCBn
V
1.95 – 2.7 1.7 1.7
2.7 – 3.6 2.0 2.0
VIL
Low level input
voltage 1.4 – 3.6
1.4 – 1.95 0.35
VCCBn
0.35
VCCBn
V
1.95 – 2.7 0.7 0.7
2.7 – 3.6 0.8 0.8
VOH High level
output voltage 1.4 – 3.6
1.4 – 3.6 IOH = -100 µA VCCBn-
0.1
VCCBn-
0.1
V
1.4 IOH = -1 mA 1.10 1.10
1.65 IOH = -2 mA 1.20 1.20
2.7 IOH = -4 mA 2.20 2.20
3.0 IOH = -8 mA 2.30 2.30
3.6 IOH = -8 mA 3.00 3.00
VOL Low level
output voltage 1.4 – 3.6
1.4 – 3.6 IOL = 100 µA 0.20 0.20
V
1.4 IOL = 1 mA 0.35 0.35
1.65 IOL = 2 mA 0.45 0.45
2.7 IOL = 4 mA 0.55 0.55
3.0 IOL = 8 mA 0.70 0.70
3.6 IOL = 8 mA 0.70 0.70
IIBn
Input leakage
current per
input channel
1.4 – 3.6 1.4 – 3.6 VIBn =V
CCBn or
GND ±0.5 ±5 µA
IOZBn
High
impedance
output leakage
current
3.6 3.6
VIA = GND to
3.6 V
VIBn = GND to
3.6
IN1,IN2 = VCCA
or
IN1,IN2 = GND
±1.0 ±10 µA
IOFF
Power off B-
side I/O
leakage current
00
VIBn=0 to 3.6V
INn= 0,
DIR =0
±1.0 ±10 µA
Electrical characteristics ST6G3240
14/29
Table 10. DC quiescent current
Symbol Parameter
Test conditions Value Unit
VCCA
(V)
VCCB1
(V)
VCCB2
(V)
TA = 25 °C -40 to 85 °C
Min Max Min Max
ICCA
Quiescent
supply
current for
A-side
1.4 – 3.6 1.4 – 3.6 1.4 – 3.6 VIA =V
CCA or
GND
VIBn =V
CCBn or
GND
VCD =V
MS =V
CCA
15
μA
1.4 – 3.6 0 1.4 – 3.6 1 5
1.4 – 3.6 1.4-3.6 0 1 5
1.4 – 3.6 0 0 1 5
ICCBn Quiescent
supply
current for
Bn-side
1.4 – 3.6 1.4 – 3.6 1.4 – 3.6
VIA =VCCA or GND
VIBn =VCCBn or
GND
VCD =V
MS =V
CCA
15μA
ICCAZ
High
impedence
quiescent
supply
current for A-
side
1.4 – 3.6 1.4 – 3.6 1.4 – 3.6 IN1 = GND/VCCA
IN2 = GND/VCCA
0.2 1
μA1.4 – 3.6 1.4 – 3.6 1.4 – 3.6 IN1 = VCCA and
IN2 = GND 0.5 2
1.4 – 3.6 1.4 – 3.6 1.4 – 3.6 IN1 = GND and
IN2 = VCCA
0.5 2
ST6G3240 Electrical characteristics
15/29
Table 11. AC electrical characteristics (f = 10 MHz, 50% duty cycle(1))
VCCA = 1.5 V ±0.1 V
Paramete
r
From
(input)
To
(output)
VCCBn=1.8 V
± 0.15 V
VCCBn=2.5
V ± 0.2 V
VCCBn =3.0
± 0.3 V
VCCBn=3.3 V
± 0.3 V Unit
Min Max Min Max Min Max Min Max
tPLHAB,
tPHLAB
Propagation
delay time from
A to B
(CL= 15 pF,
RL=2k)
CMD.h nCMD 9 6 5.5 5.5
ns
CLK.h nCLK 9 6 5.5 5.5
CLK.h CLK-f 18 12 11 11
DATx.h nDATx 9 6 5.5 5.5
tPLHBA,
tPHLBA
Propagation
delay time from
B to A
(CL=7pF,
RL=2k)
nCMDCMD.h9999
ns
nDATxDATx.h9999
tPZL, tPZH
Output enable
time
(CL=7 pF,
RL=2k)
INn A 22 22 22 22
ns
Output enable
time
(CL=15pF,
RL=2k)
INnBn 22222222
tPLZ, tPHZ
Output disable
time (CL=7 pF,
RL=2k )
INn A 33 33 33 33
ns
Output disable
time (CL=15pF,
RL=2k)
INnBn 33333333
tDIR, enable
DIRA 8888
ns
DIRB 9999
tDIR,
disable
DIRA 7777
ns
DIRB 8888
tOSLH,tOS
HL
Output to output
skew time(2) 1111ns
tCDLH,tCD
HL
Clock and data
skew time 1111ns
fmax
Clock ABn 52525252
MHz
BnA 52525252
Data A Bn 104 104 104 104 Mbps
Bn A 104 104 104 104
1. Refer to figure 4.
2. Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the
same device switching in the same direction, either High or Low ( tOSLH = | tPLHm - tPLHn |, tOSHL = | tPHLm – tPHLn | )
Electrical characteristics ST6G3240
16/29
Table 12. VCCA = 1.8 V ± 0.15 V
Parameter From
(input)
To
(output)
VCCBn =1.8
V ± 0.15 V
VCCBn=2.5V
± 0.2V
VCCBn=3.0
± 0.3 V
VCCBn =3.3
V ± 0.3V Unit
Min Max Min Max Min Max Min Max
tPLHAB,
tPHLAB
Propagation
delay time from
A to B
(CL=15pF,
RL=2k)
CMD.h nCMD 8.5 5.5 5 5
ns
CLK.h nCLK 8.5 5.5 5 5
CLK.h CLK-f 17 11 10 10
DATx.h nDATx 8.5 5.5 5 5
tPLHBA,
tPHLBA
Propagation
delay time from
B to A (CL=7 pF,
RL=2k )
nCMDCMD.h7777
ns
n DAT x DAT x . h 7 7 7 7
tPZL, tPZH
Output enable
time (CL=7pF,
RL=2 k )
INn A 15 15 15 15
ns
Output enable
time (CL=15pF,
RL=2 k )
INnBn 15151515
tPLZ, tPHZ
Output disable
time (CL=7pF,
RL=2k )
INn A 22 22 22 22
ns
Output disable
time (CL=15pF,
RL=2k )
INnBn 22222222
tDIR, enable
DIRA 7777
ns
DIRB 8888
tDIR, disable
DIRA 5555
ns
DIRB 6666
tOSLH,tOSH
L
Output to output
skew time(1) 1111ns
tCDLH,tCDH
L
Clock and data
skew time 1111ns
fmax
Clock ABn 52525252
MHz
BnA 52525252
Data A Bn 104 104 104 104 Mbp
s
Bn A 104 104 104 104
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the
same device switching in the same direction, either HIGH or LOW ( tOSLH = | tPLHm - tPLHn |, tOSHL = | tPHLm – tPHLn | )
ST6G3240 Electrical characteristics
17/29
Table 13. VCCA = 2.5 ± 0.2 V
Parameter From
(input)
To
(output)
VCCBn=1.8V
± 0.15V
VCCBn=2.5V
± 0.2V
VCCBn=3.0 ±
0.3V
VCCBn=3.3V
± 0.3V Unit
Min Max Min Max Min Max Min Max
tPLHAB,
tPHLAB
Propagation
delay time
from A to B
( CL=15pF,
RL= 2 kΩ)
CMD.h nCMD 7.5 5 4.5 4.5
ns
CLK.h nCLK 7.5 5 4.5 4.5
CLK.h CLK-f 15 10 9 9
DATx.h nDATx 7.5 5 4.5 4.5
tPLHBA,
tPHLBA
Propagation
delay time
from B to A
(CL=7pF,
RL=2k)
nCMDCMD.h5555
ns
n DAT x DAT x.h 5 5 5 5
tPZL, tPZH
Output
enable time
(CL=7pF,
RL=2k )
INn A 11 11 11 11
ns
Output
enable time
(CL=15 pF,
RL=2k)
INnBn 11111111
tPLZ, tPHZ
Output
disable time
(CL=7 pF,
RL=2 k )
INn A 21 21 21 21 ns
Output
disable time
(CL=15pF,
RL=2 k)
INnBn 21212121ns
tDIR, enable
DIRA 5555
ns
DIRB 6666
tDIR, disable
DIRA 5555
ns
DIRB 6666
tOSLH,tOSHL
Output to
output skew
time(1)
1111ns
tCDLH,tCDHL Clock and
data skew
time
1111ns
fmax Clock ABn 52525252
MHz
BnA 52525252
Data A Bn 104 104 104 104 Mbps
Bn A 104 104 104 104
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the
same device switching in the same direction, either HIGH or LOW ( tOSLH = | tPLHm - tPLHn |, tOSHL = | tPHLm – tPHLn | )
Electrical characteristics ST6G3240
18/29
Table 14. VCCA = 3.3 V ± 0.3 V
Parameter From To
VCCBn =
1.8 V ±
0.15 V
VCCBn =
2.5 V ± 0.2 V
VCCBn =
3.0 ± 0.3 V
VCCBn =
3.3 V ± 0.3 V Unit
MinMaxMinMaxMinMaxMinMax
tPLHAB,
tPHLAB
Propagation
delay time from
A to B
(CL=15pF,
RL=2k)
CMD.h nCMD 7 4.5 4.3 4.3
ns
CLK.h nCLK 7 4.5 4.3 4.3
CLK.h CLK-f 14 9 8.6 8.6
DATx.h nDATx 7 4.5 4.3 4.3
tPLHBA,
tPHLBA
Propagation
delay time from
B to A
(CL=7pF,
RL=2k )
nCMDCMD.h4444
ns
nDATxDATx.h4444
tPZL, tPZH
Output enable
time (CL=7pF,
RL=2k )
INnA 9999
ns
Output enable
time
(CL=15pF,
RL=2k)
INnBn9999
tPLZ, tPHZ
Output disable
time (CL=7pF,
RL=2 k)
INn A 20 20 20 20
ns
Output disable
time
(CL=15pF,
RL=2 k)
INnBn 20202020
tDIR, enable
DIRA 4444
ns
DIRB 5555
tDIR, disable
DIRA 4444
ns
DIRB 5555
tOSLH,tOSH
L
Output to
output skew
time(1)
1111ns
tCDLH,tCDH
L
Clock and data
skew time 1111ns
fmax
Clock ABn 52525252
MHz
BnA 52525252
Data A Bn 104 104 104 104 Mbp
s
Bn A 104 104 104 104
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the
same device switching in the same direction, either HIGH or LOW ( tOSLH = | tPLHm - tPLHn |, tOSHL = | tPHLm – tPHLn | )
ST6G3240 Electrical characteristics
19/29
Table 15. Output slew rate (f = 1 MHz, 50% duty cycle, CL=15 pF on Bn-side; CL=7 pF on A-side)
Symbol Parameter From To
Test condition TA = -40 to 85 °C
Unit
VCCA = 1.8 V ± 0.15V
VCCBn = 3.0 V ± 0.3V
Min Max
trRise time 10% 90% 3.5 ns
tfFall time 10% 90% 3.5 ns
Table 16. Capacitance characteristics
Symbol Parameter
Test condition Value
Unit
VCCA
(V)
VCCBn
(V)
TA = 25 °C -40 to 85 °C
Min Typ Max Min Max
CINBn Input capacitance Open Open 9 pF
CI/OA
Input/output
capacitance for
A-side
1.8 3.0
f=1MHz
VBIAS = 250 mV
VPP =500mV
5pF
CI/OBn
Input/output
capacitance for
Bn-side
1.8 3.0
f=1MHz
VBIAS =250mV
VPP =500mV
11 pF
CPD
Power dissipation
capacitance
2.5 3.3 f=10MHz 29 pF
1.8 3.3 29
Test circuit ST6G3240
20/29
6 Test circuit
Figure 4. Test circuit
RT is the Zout of the pulse generator, typically 50.
Table 17. Test circuit switches
Test CL
(pF)
RL/R1
(kΩ)Switch
A-side B-side
tPLH, tPHL 7 15 2 Open
tPZL, tPLZ 715 2 2V
CC
tPZH, tPHZ 715 2 GND
Table 18. Waveform symbol value
Symbol
VCC
3.0 to 3.6 V 2.3 to 2.7 V 1.65 to 1.95 V
VIH VCC VCC VCC
VM1.5 V VCC/2 VCC/2
VXVOL + 0.3 V VOL + 0.15 V VOL + 0.15 V
VYVOH - 0.3 V VOH - 0.15 V VOH - 0.15 V
ST6G3240 Test circuit
21/29
Figure 5. Waveform - propagation delay (f = 1 MHz, 50% duty cycle)
Figure 6. Waveform - output enable/disable (f = 1 MHz, 50% duty cycle)
IN 1, IN2
Test circuit ST6G3240
22/29
Figure 7. Application block diagram
10
6
6
DAT0
DAT1
DAT2
DAT3
DAT0 DIR
DAT123 D IR
CMD
CMD DIR
CLK
CLK-f
IN1
IN2
2D A T0
2D A T1
2D A T2
2D A T3
2C M D
2CL K
10
01
1D A T0
1D A T1
1D AT 2
1D AT 3
1CM D
1CL K
CD
R R
. . .
M S_Insert
MS_Insert
(1)
ST6G 3240
R
C om bocard holder
(
MicroSD + M2
)
VCCA VCCB2
VCCB1
C a rd Dete c tio n
exte rn a l s witch
100k
V
CCA
CD
Base Band
100k
G PIO option
A uto short to ground via the M 2 card internal circuitry
w hen card is inserted.
MS_InsertB1
ST6G3240 Package mechanical data
23/29
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 8. μTFBGA package outline
Package mechanical data ST6G3240
24/29
Figure 9. Recommended footprint
Table 19. μTFBGA 36 mechanical data
Symbol
Millimeters
Min Typ Max
A11.11.16
A1 0.25
A2 0.78 0.86
b 0.25 0.30 0.35
D 3.50 3.60 3.70
D1 2.50
E 3.50 3.60 3.70
E1 2.50
e0.50
F0.55
ST6G3240 Package mechanical data
25/29
Figure 10. Carrier tape information
Package mechanical data ST6G3240
26/29
Figure 11. Reel dimensions
Table 20. Reel dimensions
Tape width N W1 W2 max C
12 178 ± 5 mm 12.4 (+2,-0) 18.4 13 ± 0.25
ST6G3240 Package mechanical data
27/29
Figure 12. Reel information
Revision history ST6G3240
28/29
8 Revision history
Table 21. Document revision history
Date Revision Changes
27-Mar-2008 1 Initial release.
18-Apr-2008 2 Minor text changes.
Modified fmax values in Ta b l e 1 1 , Ta bl e 1 2 , Ta b l e 1 3 and Ta b l e 1 4 .
ST6G3240
29/29
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