SPICE Device Model Si4800BDY Vishay Siliconix N-Channel Reduced Qg, Fast Switching MOSFET CHARACTERISTICS * N-Channel Vertical DMOS * Macro Model (Model Subcircuit) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit mode is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-to-10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 72258 29-Apr-03 www.vishay.com 1 SPICE Device Model Si4800BDY Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Simulated Data Measured Data Symbol Test Conditions VGS(th) VDS = VGS, ID = 250A ID(on) VDS 5V, VGS = 10V 281 VGS = 10V, ID = 9A 0.0152 0.0155 VGS = 4.5V, ID = 7A 0.023 0.023 Unit Static Gate Threshold Voltage On-State Drain Current a Drain-Source On-State Resistancea Forward Transconductance a Forward Voltagea rDS(on) 1 V A gfs VDS = 15V, ID = 9A 20 16 VSD IS = 2.3A, VGS = 0 V 0.81 0.75 8.1 8.7 1.5 1.5 V b Dynamic Total Gate Charge Gate-Source Charge Qg Qgs VDS = 15V, VGS = 5V, ID = 9A Gate-Drain Charge Qgd 3.5 3.5 Turn-On Delay Time td(on) 8 7 10 12 47 32 10 14 22 30 Rise Time Turn-Off Delay Time tr td(off) Fall Time tf Source-Drain Reverse Recovery Time trr VDD = 15V, RL = 15 ID 1A, VGEN = 10V, RG = 6 IF = 2.3A, di/dt = 100 A/s nC ns Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 72258 29-Apr-03 SPICE Device Model Si4800BDY Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 72258 29-Apr-03 www.vishay.com 3