SPICE Device Model Si4800BDY
Vishay Siliconix
N-Channel Reduced Qg, Fast Switching MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Model Subcircuit)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
mode is extracted and optimized over the −55 to 125°C temperature
ranges under the pulsed 0-to-10V gate drive. The saturated output
impedance is best fit at the gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network is used to
model the gate charge characteristics while avoiding convergence
difficulties of the switched Cgd model. All model parameter values
are optimized to provide a best fit to the measured electrical data
and are not intended as an exact physical interpretation of the
device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 72258 www.vishay.com
29-Apr-03 1
SPICE Device Model Si4800BDY
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter Symbol Test Conditions
Simulated
Data
Measured
Data Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250µA 1 V
On-State Drain Currenta ID(on) VDS ≥ 5V, VGS = 10V 281 A
VGS = 10V, ID = 9A 0.0152 0.0155
Drain-Source On-State Resistancea r
DS(on)
VGS = 4.5V, ID = 7A 0.023 0.023
Forward Transconductancea g
fs V
DS = 15V, ID = 9A 20 16
Ω
Forward Voltagea V
SD I
S = 2.3A, VGS = 0 V 0.81 0.75 V
Dynamicb
Total Gate Charge Qg 8.1 8.7
Gate-Source Charge Qgs 1.5 1.5
Gate-Drain Charge Qgd
VDS = 15V, VGS = 5V, ID = 9A
3.5 3.5
nC
Turn-On Delay Time td(on) 8 7
Rise Time tr 10 12
Turn-Off Delay Time td(off) 47 32
Fall Time tf
VDD = 15V, RL = 15Ω
ID ≅ 1A, VGEN = 10V, RG = 6Ω
10 14
Source-Drain Reverse Recovery Time trr IF = 2.3A, di/dt = 100 A/µs 22 30
ns
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
www.vishay.com Document Number: 72258
2 29-Apr-03
SPICE Device Model Si4800BDY
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 72258 www.vishay.com
29-Apr-03 3
