PIC18FXX2 PIC18FXX2 Rev. C1 Silicon/Data Sheet Errata The PIC18FXX2 Rev. C1 parts you have received conform functionally to the Device Data Sheet (DS39564B), except for the anomalies described below. All the issues listed here will be addressed in future revisions of the PIC18FXX2 silicon. The following silicon errata apply only to PIC18FXX2 devices with these Device/Revision IDs: 2. Module: Data EEPROM When reading the data EEPROM, the contents of the EEDATA register may be corrupted if the RD bit (EECON1<0>) is set immediately following a write to the address byte (EEADR). The actual contents of the data EEPROM remain unaffected. Work around Do not set EEADR immediately before the execution of a read. Write to EEADR at least one instruction cycle before setting the RD bit. The instruction between the write to EEADR and the read can be any valid instruction, including a NOP. Part Number Device ID Revision ID PIC18F242 00 0100 100 00111 PIC18F252 00 0100 000 00111 PIC18F442 00 0100 101 00111 Date Codes that pertain to this issue: PIC18F452 00 0100 001 00111 All engineering and production devices. The Device IDs (DEVID1 and DEVID2) are located at addresses 3FFFFEh:3FFFFFh in the device's configuration space. They are shown in hexadecimal in the format "DEVID2 DEVID1". 1. Module: Core (Program Memory Space) Performing table read operations above the user program memory space (addresses over 1FFFFFh) may yield erroneous results at the extreme low end of the device's rated temperature range (-40C). This applies specifically to addresses above 1FFFFFh, including the user ID locations (200000h-200007h), the configuration bytes (300000h-30000Dh) and the device ID locations (3FFFFEh and 3FFFFFh). User program memory is unaffected. Work around Three possible work arounds are presented. Other solutions may exist. 1. Do not perform table read operations on areas above the user memory space at -40C. 2. Insert NOP instructions (specifically, literal FFFFh) around any table read instructions. The suggested optimal number is 4 instructions before and 8 instructions after each table read. This may vary depending upon the particular application and should be optimized by the user. Date Codes that pertain to this issue: All engineering and production devices. (c) 2005 Microchip Technology Inc. DS80245A-page 1 PIC18FXX2 3. Module: MSSP (All I2CTM and SPITM Modes) The Buffer Full (BF) flag bit of the SSPSTAT register (SSPSTAT<0>) may be inadvertently cleared even when the SSPBUF register has not been read. This will occur only when the following two conditions occur simultaneously: * The four Least Significant bits of the BSR register are equal to 0Fh (BSR<3:0> = 1111) and * Any instruction that contains C9h in its 8 Least Significant bits (i.e., register file addresses, literal data, address offsets, etc.) is executed. Work around All work arounds will involve setting the contents of BSR<3:0> to some value other than 0Fh. In addition to those proposed below, other solutions may exist. 1. When developing or modifying code, keep these guidelines in mind: * Assign 12-bit addresses to all variables. This allows the assembler to know when access banking can be used. * Do not set the BSR to point to Bank 15 (BSR = 0Fh). * Allow the assembler to manipulate the access bit present in most instructions. Accessing the SFRs in Bank 15 will be done through the Access Bank. Continue to use the BSR to select all GPR Banks. 2. If accessing a part of Bank 15 is required and the use of access banking is not possible, consider using indirect addressing. 3. If pointing the BSR to Bank 15 is unavoidable, review the absolute file listing. Verify that no instructions contain C9h in the 8 Least Significant bits while the BSR points to Bank 15 (BSR = 0Fh). Date Codes that pertain to this issue: All engineering and production devices. DS80245A-page 2 4. Module: Core (Instruction Set) The Decimal Adjust W register instruction, DAW, may improperly clear the Carry bit (STATUS<0>) when executed. Work around Test the Carry bit state before executing the DAW instruction. If the Carry bit is set, increment the next higher byte to be added using an instruction such as INCFSZ (this instruction does not affect any Status flags and will not overflow a BCD nibble). After the DAW instruction has been executed, process the Carry bit normally (see Example 1). EXAMPLE 1: PROCESSING THE CARRY BIT DURING BCD ADDITIONS MOVLW ADDLW 0x80 0x80 ; .80 (BCD) ; .80 (BCD) BTFSC INCFSZ DAW BTFSC INCFSZ STATUS,C byte2 ; test C ; inc next higher LSB STATUS,C byte2 ; test C ; inc next higher LSB This is repeated for each DAW instruction. 5. Module: Reset It has been observed that in certain Reset conditions, including power-up, the first GOTO instruction at address 0x0000 may not be executed. This occurrence is rare and affects very few applications. To determine if your system is affected, test a statistically significant number of applications across the operating temperature, voltage and frequency ranges of the application. Affected systems will repeatably fail normal testing. Systems not affected will continue to not be affected over time. Work around Insert a NOP instruction at address 0x0000. Date Codes that pertain to this issue: All engineering and production devices. (c) 2005 Microchip Technology Inc. PIC18FXX2 6. Module: Program Memory A very small number of applications are experiencing a low failure rate when using selfwrite through code types of applications. The most common of these are bootloader operations. This failure mechanism is characterized by a few bytes in program memory not being written as expected. If this failure is going to occur, it will occur during a self-write operation. If a failure is not immediately observed, then there will be no data retention issues. The failure does not occur when using an external programmer through In-Circuit Serial ProgrammingTM (ICSPTM). This failure mechanism is dependent on the sequence of instructions executed after selfwrites. Good power supply decoupling minimizes this issue. It is recommended that you use a 0.1 F decoupling capacitor with each power pin pair. The decoupling capacitor should be placed very close to the power pins. It is recommended that you perform statistically significant testing within your application's operating range (i.e., temperature and voltage) with devices from multiple lots. * If writing to an address within the same memory panel that you are executing from (0x0000 to 0x3FFF and 0x4000 to 0x7FFF), then jump to the opposite memory panel. If the bootloader resides between location 0x0000 to 0x3FFF, and writing to an address between 0x0000 to 0x3FFF, then jump to another instantiation of the code located between 0x4000 to 0x7FFF and vice versa. * Always load holding latches (loading of TABLAT and then TBLWT*) from the opposite panel. This will require duplicate code in each panel to load data. * Always initiate write from the opposite panel. This will require duplicate code in each panel for the unlock sequence and setting up the write bit. * At the end of the successful write, code can return to the primary panel to get the next data. 2. Use a similar device from the PIC18F4520 family. Work around 1. This work around only applies to PIC18F252 and PIC18F452 devices. The program memory is divided into discrete panels and the failure has only been observed when a table write is executed from the same panel it is programming. The table write (selfwrite) within the same memory panel (0x0000 to 0x3FFF and 0x4000 to 0x7FFF) initiates a condition that can cause a failure. The firmware work around is to duplicate the partial bootloader (two instantiations of write functions) in two panels and ensure that the bootloader code always programs a different panel from where it resides. To accomplish this, do the following: * Receive data from communication channel (normal operation for the bootloader). * Identify address to be written. (c) 2005 Microchip Technology Inc. DS80245A-page 3 PIC18FXX2 Clarifications/Corrections to the Data Sheet: In the Device Data Sheet (DS39564B), the following clarifications and corrections should be noted. 1. Module: DC Characteristics The values for parameters, D005, D010A, D022A and D022B, shown in Section 22.1 "DC Characteristics" of the Device Data Sheet have changed (modified text is shown in bold): 22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) PIC18LFXX2 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18FXX2 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Symbol VBOR D005 D005 D005 Characteristic Min Typ Max Units Conditions Brown-out Reset Voltage PIC18LFXX2 BORV1:BORV0 = 11 1.96 2.06 2.16 V BORV1:BORV0 = 10 2.64 2.78 2.92 V BORV1:BORV0 = 01 4.11 4.33 4.55 V BORV1:BORV0 = 00 4.41 4.64 4.87 V 85C T 25C PIC18FXX2 BORV1:BORV0 = 1x N.A. -- N.A. V BORV1:BORV0 = 01 4.16 BORV1:BORV0 = 00 4.45 -- 4.5 V -- 4.83 V BORV1:BORV0 = 1x N.A. -- N.A. V BORV1:BORV0 = 01 4.07 -- 4.59 V BORV1:BORV0 = 00 4.36 -- 4.92 V Not in operating voltage range of device PIC18FXX2 Extended devices operating at 125C Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR,...). 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. DS80245A-page 4 (c) 2005 Microchip Technology Inc. PIC18FXX2 22.1 DC Characteristics: PIC18FXX2 (Industrial, Extended) PIC18LFXX2 (Industrial) (Continued) PIC18LFXX2 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18FXX2 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Symbol IDD Characteristic Min Typ Max Units Conditions -- 14 30 A LP osc, FOSC = 32 kHz, WDT disabled VDD = 2.0V, -40C to +85C -- -- 60 60 150 180 A A LP osc, FOSC = 32 kHz, WDT disabled VDD = 4.2V, -40C to +85C VDD = 4.2V, -40C to +125C Supply Current(2,4) D010A PIC18LFXX2 D010A PIC18FXX2 Module Differential Current D022A IBOR D022A D022B D022B ILVD Brown-out Reset PIC18LFXX2 -- -- -- 29 29 33 40 45 50 A A A VDD = 2.0V, +25C VDD = 2.0V, -40C to +85C VDD = 4.2V, -40C to +85C Brown-out Reset PIC18FXX2 -- -- -- 36 36 36 45 50 65 A A A VDD = 4.2V, +25C VDD = 4.2V, -40C to +85C VDD = 4.2V, -40C to +125C Low-Voltage Detect PIC18LFXX2 -- -- -- 29 29 33 40 45 50 A A A VDD = 2.0V, +25C VDD = 2.0V, -40C to +85C VDD = 4.2V, -40C to +85C Low-Voltage Detect PIC18FXX2 -- -- -- 33 33 33 45 50 65 A A A VDD = 4.2V, +25C VDD = 4.2V, -40C to +85C VDD = 4.2V, -40C to +125C Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR,...). 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. (c) 2005 Microchip Technology Inc. DS80245A-page 5 PIC18FXX2 2. Module: Low-Voltage Detect Characteristics Some of the values for parameter D420 in Table 22-1 of the Device Data Sheet have been updated (modified text is shown in bold). TABLE 22-1: LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param Symbol No. D420 VLVD DS80245A-page 6 Characteristic LVD Voltage on VDD transition high-to-low Min Typ Max Units Conditions LVV = 0001 1.96 2.06 2.16 V T 25C LVV = 0010 2.16 2.27 2.38 V T 25C LVV = 0011 2.35 2.47 2.59 V T 25C LVV = 0100 2.43 2.56 2.69 V LVV = 0101 2.64 2.78 2.92 V LVV = 0110 2.75 2.89 3.03 V LVV = 0111 2.95 3.1 3.26 V LVV = 1000 3.24 3.41 3.58 V LVV = 1001 3.43 3.61 3.79 V LVV = 1010 3.53 3.72 3.91 V LVV = 1011 3.72 3.92 4.12 V LVV = 1100 3.92 4.13 4.34 V LVV = 1101 4.11 4.33 4.55 V LVV = 1110 4.41 4.64 4.87 V (c) 2005 Microchip Technology Inc. PIC18FXX2 3. Module: Packaging (Pinout and Product Identification) PIC18F442 and PICF452 devices are now offered in 44-pin, near chip scale micro lead frame packages (commonly known as "QFN"). This packaging type has been added to the product line since the latest revision of the Device Data Sheet. The addition of this option requires the following additions to the Device Data Sheet (DS39564B). The referenced figures and tables follow this text. 1. The "Pin Diagrams" on pages 2-3 of the Data Sheet are amended with the addition of the 44-pin QFN pinout, shown in Figure 1. 2. Table 1-3 of Section 1.0 "Device Overview" is replaced with an updated version which adds a column for QFN pin assignments. A row is also added for previously unlisted NC pins. All new information is indicated in bold. FIGURE 1: 3. Section 24.1 "Package Marking Information" is amended to include a marking template and example for 44-pin QFN devices. These are shown in Figure 2. 4. Section 24.2 "Package Details" is amended to include the mechanical drawing of the 44-pin QFN package, shown in Figure 3. 5. In the "PIC18FXX2 Product Identification System" (page 329), the "Package" options are amended to include the new line item: ML = QFN 6. For the sake of completeness, it is also noted that the package designation "MLF" is now replaced by "QFN" in all occurrences throughout the Device Data Sheet. "MLF" should be considered an obsoleted term. PINOUT DIAGRAM FOR PIC18F442/452, 44-PIN QFN PACKAGE 1 2 3 4 5 6 7 8 9 10 11 PIC18F442 PIC18F452 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD VDD RB0/INT0 RB1/INT1 RB2/INT2 44 43 42 41 40 39 38 37 36 35 34 RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2* RC0/T1OSO/T1CKI QFN OSC2/CLKO/RA6 OSC1/CLKI VSS VSS VDD VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS/LVDIN RA4/T0CKI RA3/AN3/VREF+ RA2/AN2/VREFRA1/AN1 RA0/AN0 MCLR/VPP RB7/PGD RB6/PGC RB5/PGM RB4 NC RB3/CCP2* *RB3 is the alternate pin for the CCP2 pin multiplexing. FIGURE 2: PACKAGE MARKING TEMPLATE FOR PIC18F442/452, 44-PIN QFN 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN (c) 2005 Microchip Technology Inc. Example PIC18F442 -I/ML 0510017 DS80245A-page 7 PIC18FXX2 TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS Pin Number Pin Name Pin Buffer DIP PLCC QFN TQFP Type Type 1 MCLR/VPP 2 18 18 MCLR VPP NC -- OSC1/CLKI OSC1 13 32 14 33 I ST I ST Master Clear (input) or high-voltage ICSPTM programming enable pin. Master Clear (Reset) input. This pin is an active low Reset to the device. High-voltage ICSP programming enable pin. -- -- These pins should be left unconnected. 30 I CLKI I OSC2/CLKO/RA6 OSC2 14 15 Description Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) ST 31 O -- CLKO O -- RA6 I/O TTL Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 2 RA1/AN1 RA1 AN1 3 RA2/AN2/VREFRA2 AN2 VREF- 4 RA3/AN3/VREF+ RA3 AN3 VREF+ 5 RA4/T0CKI RA4 T0CKI 6 RA5/AN4/SS/LVDIN RA5 AN4 SS LVDIN 7 3 4 5 6 7 8 19 20 21 22 23 24 19 I/O I TTL Analog Digital I/O. Analog input 0. I/O I TTL Analog Digital I/O. Analog input 1. I/O I I TTL Analog Analog Digital I/O. Analog input 2. A/D Reference Voltage (Low) input. I/O I I TTL Analog Analog Digital I/O. Analog input 3. A/D Reference Voltage (High) input. I/O I ST/OD ST Digital I/O. Open-drain when configured as output. Timer0 external clock input. I/O I I I TTL Analog ST Analog Digital I/O. Analog input 4. SPITM Slave Select input. Low-Voltage Detect input. 20 21 22 23 24 RA6 Legend: (See the OSC2/CLKO/RA6 pin.) TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-Drain (no P diode to VDD) DS80245A-page 8 CMOS = CMOS compatible input or output I = Input P = Power (c) 2005 Microchip Technology Inc. PIC18FXX2 TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer Type Type DIP PLCC QFN TQFP Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0 RB0 INT0 33 RB1/INT1 RB1 INT1 34 RB2/INT2 RB2 INT2 35 RB3/CCP2 RB3 CCP2 36 RB4 37 41 14 14 RB5/PGM RB5 PGM 38 42 15 15 RB6/PGC RB6 PGC 39 RB7/PGD RB7 PGD 40 Legend: 36 37 38 39 43 44 9 10 11 12 16 17 8 I/O I TTL ST Digital I/O. External Interrupt 0. I/O I TTL ST Digital I/O. External Interrupt 1. I/O I TTL ST Digital I/O. External Interrupt 2. I/O I/O TTL ST Digital I/O. Capture2 input, Compare2 output, PWM2 output. I/O TTL Digital I/O. Interrupt-on-change pin. I/O I/O TTL ST Digital I/O. Interrupt-on-change pin. Low-voltage ICSPTM programming enable pin. I/O I/O TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin. I/O I/O TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. 9 10 11 16 17 TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-Drain (no P diode to VDD) (c) 2005 Microchip Technology Inc. CMOS = CMOS compatible input or output I = Input P = Power DS80245A-page 9 PIC18FXX2 TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer Type Type DIP PLCC QFN TQFP Description PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI RC0 T1OSO T1CKI 15 RC1/T1OSI/CCP2 RC1 T1OSI CCP2 16 RC2/CCP1 RC2 CCP1 17 RC3/SCK/SCL RC3 SCK 18 16 18 19 20 34 35 36 37 32 23 RC5/SDO RC5 SDO 24 RC6/TX/CK RC6 TX CK 25 RC7/RX/DT RC7 RX DT 26 Legend: 25 26 27 29 42 43 44 1 ST -- ST Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. I/O I I/O ST CMOS ST Digital I/O. Timer1 oscillator input. Capture2 input, Compare2 output, PWM2 output. I/O I/O ST ST Digital I/O. Capture1 input/Compare1 output/ PWM1 output. I/O I/O ST ST I/O ST Digital I/O. Synchronous serial clock input/output for SPITM mode. Synchronous serial clock input/output for I2CTM mode. I/O I I/O ST ST ST Digital I/O. SPI Data In. I2C Data I/O. I/O O ST -- Digital I/O. SPI Data Out. I/O O I/O ST -- ST Digital I/O. USART Asynchronous Transmit. USART Synchronous Clock (see related RX/DT). I/O I I/O ST ST ST Digital I/O. USART Asynchronous Receive. USART Synchronous Data (see related TX/CK). 35 36 37 SCL RC4/SDI/SDA RC4 SDI SDA I/O O I 42 43 44 1 TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-Drain (no P diode to VDD) DS80245A-page 10 CMOS = CMOS compatible input or output I = Input P = Power (c) 2005 Microchip Technology Inc. PIC18FXX2 TABLE 1-3: PIC18F4X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer Type Type DIP PLCC QFN TQFP Description PORTD is a bidirectional I/O port, or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when the PSP module is enabled. RD0/PSP0 19 21 38 38 I/O ST TTL Digital I/O. Parallel Slave Port Data. RD1/PSP1 20 22 39 39 I/O ST TTL Digital I/O. Parallel Slave Port Data. RD2/PSP2 21 23 40 40 I/O ST TTL Digital I/O. Parallel Slave Port Data. RD3/PSP3 22 24 41 41 I/O ST TTL Digital I/O. Parallel Slave Port Data. RD4/PSP4 27 30 2 2 I/O ST TTL Digital I/O. Parallel Slave Port Data. RD5/PSP5 28 31 3 3 I/O ST TTL Digital I/O. Parallel Slave Port Data. RD6/PSP6 29 32 4 4 I/O ST TTL Digital I/O. Parallel Slave Port Data. RD7/PSP7 30 33 5 5 I/O ST TTL Digital I/O. Parallel Slave Port Data. RE0/RD/AN5 RE0 RD 8 9 25 25 I/O PORTE is a bidirectional I/O port. ST TTL AN5 Analog RE1/WR/AN6 RE1 WR 9 10 26 26 I/O ST TTL AN6 Analog RE2/CS/AN7 RE2 CS 10 11 27 27 Digital I/O. Read control for parallel slave port (see also WR and CS pins). Analog input 5. Digital I/O. Write control for parallel slave port (see CS and RD pins). Analog input 6. I/O ST TTL AN7 Analog Digital I/O. Chip Select control for parallel slave port (see related RD and WR). Analog input 7. VSS 12, 31 13, 34 6, 30, 31 6, 29 P -- Ground reference for logic and I/O pins. VDD 11, 32 12, 35 7, 8, 7, 28 28, 29 P -- Positive supply for logic and I/O pins. NC -- 1, 17, 28 -- -- These pins are not internally connected. They should be left unconnected. Legend: 13 12, 13, 33, 34 TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-Drain (no P diode to VDD) (c) 2005 Microchip Technology Inc. CMOS = CMOS compatible input or output I = Input P = Power DS80245A-page 11 PIC18FXX2 FIGURE 3: 44-PIN QFN PACKAGE 44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN) EXPOSED METAL PAD E p D D2 2 1 B n PIN 1 INDEX ON EXPOSED PAD (PROFILE MAY VARY) OPTIONAL PIN 1 INDEX ON TOP MARKING E2 L TOP VIEW BOTTOM VIEW DETAIL: CONTACT VARIANTS A A1 A3 Units Dimension Limits n Number of Contacts p Pitch Overall Height Standoff Base Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Contact Width Contact Length A A1 A3 E E2 D D2 B L MIN .031 .000 .309 .236 .309 .236 .008 .014 INCHES NOM 44 .026 BSC .035 .001 .010 REF .315 .258 .315 .258 .013 .016 MAX 1 .039 .002 2 .321 .260 .321 .260 .013 .019 MILLIMETERS* NOM 44 0.65 BSC 1 0.90 0.80 0.02 0 0.25 REF 2 8.00 7.85 6.55 5.99 7.85 8.00 6.55 5.99 0.20 0.33 0.40 0.35 MIN MAX 1.00 0.05 8.15 6.60 8.15 6.60 0.35 0.48 *Controlling Parameter Notes: 1. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M 2. REF: Reference Dimension, usually without tolerance, for information purposes only. See ASME Y14.5M Exposed pad varies according to die attach paddle size. JEDEC equivalent: M0-220 Drawing No. C04-103, Revised 05-05-05 DS80245A-page 12 (c) 2005 Microchip Technology Inc. PIC18FXX2 REVISION HISTORY Rev A Document (08/2005) First revision of this document. Listed silicon issues 1 (Core - Program Memory Space), 2 (Data EEPROM), 3 (MSSP), 4 (Core - Instruction Set), 5 (Reset) and 6 (Program Memory), and data sheet clarification issues 1 (DC Characteristics), 2 (Low-Voltage Detect Characteristics) and 3 (Packaging - Pinout and Product Identification). (c) 2005 Microchip Technology Inc. DS80245A-page 13 PIC18FXX2 NOTES: DS80245A-page 14 (c) 2005 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2005 Microchip Technology Inc. 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